tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc_ex.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f4xx_hal_rcc_ex.h
   4   * @author  MCD Application Team
   5   * @version V1.1.0
   6   * @date    19-June-2014
   7   * @brief   Header file of RCC HAL Extension module.
   8   ******************************************************************************
   9   * @attention
  10   *
  11   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
  12   *
  13   * Redistribution and use in source and binary forms, with or without modification,
  14   * are permitted provided that the following conditions are met:
  15   *   1. Redistributions of source code must retain the above copyright notice,
  16   *      this list of conditions and the following disclaimer.
  17   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18   *      this list of conditions and the following disclaimer in the documentation
  19   *      and/or other materials provided with the distribution.
  20   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21   *      may be used to endorse or promote products derived from this software
  22   *      without specific prior written permission.
  23   *
  24   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34   *
  35   ******************************************************************************
  36   */
  37
  38 /* Define to prevent recursive inclusion -------------------------------------*/
  39 #ifndef __STM32F4xx_HAL_RCC_EX_H
  40 #define __STM32F4xx_HAL_RCC_EX_H
  41
  42 #ifdef __cplusplus
  43  extern "C" {
  44 #endif
  45
  46 /* Includes ------------------------------------------------------------------*/
  47 #include "stm32f4xx_hal_def.h"
  48
  49 /** @addtogroup STM32F4xx_HAL_Driver
  50   * @{
  51   */
  52
  53 /** @addtogroup RCCEx
  54   * @{
  55   */
  56
  57 /* Exported types ------------------------------------------------------------*/
  58 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
  59 /**
  60   * @brief  PLLI2S Clock structure definition
  61   */
  62 typedef struct
  63 {
  64   uint32_t PLLI2SN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
  65                             This parameter must be a number between Min_Data = 192 and Max_Data = 432.
  66                             This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
  67
  68   uint32_t PLLI2SR;    /*!< Specifies the division factor for I2S clock.
  69                             This parameter must be a number between Min_Data = 2 and Max_Data = 7.
  70                             This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
  71
  72   uint32_t PLLI2SQ;    /*!< Specifies the division factor for SAI1 clock.
  73                             This parameter must be a number between Min_Data = 2 and Max_Data = 15.
  74                             This parameter will be used only when PLLI2S is selected as Clock Source SAI */
  75 }RCC_PLLI2SInitTypeDef;
  76
  77 /**
  78   * @brief  PLLSAI Clock structure definition
  79   */
  80 typedef struct
  81 {
  82   uint32_t PLLSAIN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
  83                             This parameter must be a number between Min_Data = 192 and Max_Data = 432.
  84                             This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
  85
  86   uint32_t PLLSAIQ;    /*!< Specifies the division factor for SAI1 clock.
  87                             This parameter must be a number between Min_Data = 2 and Max_Data = 15.
  88                             This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
  89
  90   uint32_t PLLSAIR;    /*!< specifies the division factor for LTDC clock
  91                             This parameter must be a number between Min_Data = 2 and Max_Data = 7.
  92                             This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
  93
  94 }RCC_PLLSAIInitTypeDef;
  95 /**
  96   * @brief  RCC extended clocks structure definition
  97   */
  98 typedef struct
  99 {
 100   uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
 101                                       This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
 102
 103   RCC_PLLI2SInitTypeDef PLLI2S;  /*!< PLL I2S structure parameters.
 104                                       This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
 105
 106   RCC_PLLSAIInitTypeDef PLLSAI;  /*!< PLL SAI structure parameters.
 107                                       This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
 108
 109   uint32_t PLLI2SDivQ;           /*!< Specifies the PLLI2S division factor for SAI1 clock.
 110                                       This parameter must be a number between Min_Data = 1 and Max_Data = 32
 111                                       This parameter will be used only when PLLI2S is selected as Clock Source SAI */
 112
 113   uint32_t PLLSAIDivQ;           /*!< Specifies the PLLI2S division factor for SAI1 clock.
 114                                       This parameter must be a number between Min_Data = 1 and Max_Data = 32
 115                                       This parameter will be used only when PLLSAI is selected as Clock Source SAI */
 116
 117   uint32_t PLLSAIDivR;           /*!< Specifies the PLLSAI division factor for LTDC clock.
 118                                       This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
 119
 120   uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Prescalers Selection.
 121                                       This parameter can be a value of @ref RCC_RTC_Clock_Source */
 122
 123   uint8_t TIMPresSelection;      /*!< Specifies TIM Clock Prescalers Selection.
 124                                       This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
 125
 126 }RCC_PeriphCLKInitTypeDef;
 127 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
 128
 129 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\
 130     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
 131 /**
 132   * @brief  PLLI2S Clock structure definition
 133   */
 134 typedef struct
 135 {
 136 #if defined(STM32F411xE)
 137   uint32_t PLLI2SM;    /*!< PLLM: Division factor for PLLI2S VCO input clock.
 138                             This parameter must be a number between Min_Data = 2 and Max_Data = 62  */
 139 #endif /* STM32F411xE */
 140
 141   uint32_t PLLI2SN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
 142                             This parameter must be a number between Min_Data = 192 and Max_Data = 432
 143                             This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
 144
 145   uint32_t PLLI2SR;    /*!< Specifies the division factor for I2S clock.
 146                             This parameter must be a number between Min_Data = 2 and Max_Data = 7.
 147                             This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
 148
 149 }RCC_PLLI2SInitTypeDef;
 150
 151
 152 /**
 153   * @brief  RCC extended clocks structure definition
 154   */
 155 typedef struct
 156 {
 157   uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
 158                                       This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
 159
 160   RCC_PLLI2SInitTypeDef PLLI2S;  /*!< PLL I2S structure parameters.
 161                                       This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
 162
 163   uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Prescalers Selection.
 164                                        This parameter can be a value of @ref RCC_RTC_Clock_Source */
 165
 166 }RCC_PeriphCLKInitTypeDef;
 167 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
 168 /* Exported constants --------------------------------------------------------*/
 169 /** @defgroup RCCEx_Exported_Constants
 170   * @{
 171   */
 172
 173 /** @defgroup RCCEx_Periph_Clock_Selection
 174   * @{
 175   */
 176 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
 177 #define RCC_PERIPHCLK_I2S             ((uint32_t)0x00000001)
 178 #define RCC_PERIPHCLK_SAI_PLLI2S      ((uint32_t)0x00000002)
 179 #define RCC_PERIPHCLK_SAI_PLLSAI      ((uint32_t)0x00000004)
 180 #define RCC_PERIPHCLK_LTDC            ((uint32_t)0x00000008)
 181 #define RCC_PERIPHCLK_TIM             ((uint32_t)0x00000010)
 182 #define RCC_PERIPHCLK_RTC             ((uint32_t)0x00000020)
 183 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000002F))
 184 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
 185
 186 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\
 187     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
 188 #define RCC_PERIPHCLK_I2S             ((uint32_t)0x00000001)
 189 #define RCC_PERIPHCLK_RTC             ((uint32_t)0x00000002)
 190 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x00000003))
 191 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
 192
 193 /**
 194   * @}
 195   */
 196
 197 /** @defgroup RCCEx_BitAddress_AliasRegion
 198   * @brief RCC registers bit address in the alias region
 199   * @{
 200   */
 201 /* --- CR Register ---*/
 202 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
 203 /* Alias word address of PLLSAION bit */
 204 #define PLLSAION_BitNumber        0x1C
 205 #define CR_PLLSAION_BB            (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (PLLSAION_BitNumber * 4))
 206
 207 /* --- DCKCFGR Register ---*/
 208 /* Alias word address of TIMPRE bit */
 209 #define RCC_DCKCFGR_OFFSET        (RCC_OFFSET + 0x8C)
 210 #define TIMPRE_BitNumber          0x18
 211 #define DCKCFGR_TIMPRE_BB         (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32) + (TIMPRE_BitNumber * 4))
 212 /**
 213   * @}
 214   */
 215
 216 /** @defgroup RCCEx_PLLI2S_Clock_Source
 217   * @{
 218   */
 219 #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
 220 /**
 221   * @}
 222   */
 223
 224 /** @defgroup RCCEx_PLLSAI_Clock_Source
 225   * @{
 226   */
 227 #define IS_RCC_PLLSAIN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
 228 #define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
 229 #define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
 230 /**
 231   * @}
 232   */
 233
 234 /** @defgroup RCCEx_PLLSAI_DIVQ
 235   * @{
 236   */
 237 #define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
 238 /**
 239   * @}
 240   */
 241
 242 /** @defgroup RCCEx_PLLI2S_DIVQ
 243   * @{
 244   */
 245 #define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
 246
 247 /**
 248   * @}
 249   */
 250
 251 /** @defgroup RCCEx_PLLSAI_DIVR
 252   * @{
 253   */
 254 #define RCC_PLLSAIDIVR_2                ((uint32_t)0x00000000)
 255 #define RCC_PLLSAIDIVR_4                ((uint32_t)0x00010000)
 256 #define RCC_PLLSAIDIVR_8                ((uint32_t)0x00020000)
 257 #define RCC_PLLSAIDIVR_16               ((uint32_t)0x00030000)
 258 #define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\
 259                                          ((VALUE) == RCC_PLLSAIDIVR_4)  ||\
 260                                          ((VALUE) == RCC_PLLSAIDIVR_8)  ||\
 261                                          ((VALUE) == RCC_PLLSAIDIVR_16))
 262
 263 /**
 264   * @}
 265   */
 266
 267 /** @defgroup RCCEx_SAI_BlockA_Clock_Source
 268   * @{
 269   */
 270 #define RCC_SAIACLKSOURCE_PLLSAI             ((uint32_t)0x00000000)
 271 #define RCC_SAIACLKSOURCE_PLLI2S             ((uint32_t)0x00100000)
 272 #define RCC_SAIACLKSOURCE_EXT                ((uint32_t)0x00200000)
 273 /**
 274   * @}
 275   */
 276
 277 /** @defgroup RCCEx_SAI_BlockB_Clock_Source
 278   * @{
 279   */
 280 #define RCC_SAIBCLKSOURCE_PLLSAI             ((uint32_t)0x00000000)
 281 #define RCC_SAIBCLKSOURCE_PLLI2S             ((uint32_t)0x00400000)
 282 #define RCC_SAIBCLKSOURCE_EXT                ((uint32_t)0x00800000)
 283 /**
 284   * @}
 285   */
 286
 287 /** @defgroup RCCEx_TIM_PRescaler_Selection
 288   * @{
 289   */
 290 #define RCC_TIMPRES_DESACTIVATED        ((uint8_t)0x00)
 291 #define RCC_TIMPRES_ACTIVATED           ((uint8_t)0x01)
 292 /**
 293   * @}
 294   */
 295 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
 296
 297 #if defined(STM32F411xE)
 298 /** @defgroup RCCEx_PLLI2S_PLLI2SM
 299   * @{
 300   */
 301 #define IS_RCC_PLLI2SM_VALUE(VALUE) ((VALUE) <= 63)
 302 /**
 303   * @}
 304   */
 305
 306 /** @defgroup RCCEx_LSE_Dual_Mode_Selection
 307   * @{
 308   */
 309 #define RCC_LSE_LOWPOWER_MODE           ((uint8_t)0x00)
 310 #define RCC_LSE_HIGHDRIVE_MODE          ((uint8_t)0x01)
 311 #define IS_RCC_LSE_MODE(MODE)           (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\
 312                                          ((MODE) == RCC_LSE_HIGHDRIVE_MODE))
 313 /**
 314   * @}
 315   */
 316
 317 #endif /* STM32F411xE */
 318 /**
 319   * @}
 320   */
 321
 322 /* Exported macro ------------------------------------------------------------*/
 323
 324 /*----------------------------------- STM32F42xxx/STM32F43xxx----------------------------------*/
 325 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
 326 /** @brief  Enables or disables the AHB1 peripheral clock.
 327   * @note   After reset, the peripheral clock (used for registers read/write access)
 328   *         is disabled and the application software has to enable this clock before
 329   *         using it.
 330   */
 331 #define __GPIOI_CLK_ENABLE()            (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOIEN))
 332 #define __GPIOF_CLK_ENABLE()            (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOFEN))
 333 #define __GPIOG_CLK_ENABLE()            (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOGEN))
 334 #define __GPIOJ_CLK_ENABLE()            (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOJEN))
 335 #define __GPIOK_CLK_ENABLE()            (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOKEN))
 336 #define __DMA2D_CLK_ENABLE()            (RCC->AHB1ENR |= (RCC_AHB1ENR_DMA2DEN))
 337 #define __ETHMAC_CLK_ENABLE()           (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACEN))
 338 #define __ETHMACTX_CLK_ENABLE()         (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACTXEN))
 339 #define __ETHMACRX_CLK_ENABLE()         (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACRXEN))
 340 #define __ETHMACPTP_CLK_ENABLE()        (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACPTPEN))
 341 #define __USB_OTG_HS_CLK_ENABLE()       (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSEN))
 342 #define __USB_OTG_HS_ULPI_CLK_ENABLE()  (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSULPIEN))
 343
 344 #define __GPIOF_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
 345 #define __GPIOG_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
 346 #define __GPIOI_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
 347 #define __GPIOJ_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
 348 #define __GPIOK_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
 349 #define __DMA2D_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
 350 #define __ETHMAC_CLK_DISABLE()          (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
 351 #define __ETHMACTX_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
 352 #define __ETHMACRX_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
 353 #define __ETHMACPTP_CLK_DISABLE()       (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
 354 #define __USB_OTG_HS_CLK_DISABLE()      (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
 355 #define __USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
 356
 357 /**
 358   * @brief  Enable ETHERNET clock.
 359   */
 360 #define __ETH_CLK_ENABLE()       do {                            \
 361                                      __ETHMAC_CLK_ENABLE();      \
 362                                      __ETHMACTX_CLK_ENABLE();    \
 363                                      __ETHMACRX_CLK_ENABLE();    \
 364                                     } while(0)
 365 /**
 366   * @brief  Disable ETHERNET clock.
 367   */
 368 #define __ETH_CLK_DISABLE()       do {                             \
 369                                       __ETHMACTX_CLK_DISABLE();    \
 370                                       __ETHMACRX_CLK_DISABLE();    \
 371                                       __ETHMAC_CLK_DISABLE();      \
 372                                      } while(0)
 373
 374 /** @brief  Enable or disable the AHB2 peripheral clock.
 375   * @note   After reset, the peripheral clock (used for registers read/write access)
 376   *         is disabled and the application software has to enable this clock before
 377   *         using it.
 378   */
 379
 380 #define __DCMI_CLK_ENABLE()   (RCC->AHB2ENR |= (RCC_AHB2ENR_DCMIEN))
 381 #define __DCMI_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
 382
 383 #if defined(STM32F437xx)|| defined(STM32F439xx)
 384 #define __CRYP_CLK_ENABLE()   (RCC->AHB2ENR |= (RCC_AHB2ENR_CRYPEN))
 385 #define __HASH_CLK_ENABLE()   (RCC->AHB2ENR |= (RCC_AHB2ENR_HASHEN))
 386
 387 #define __CRYP_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
 388 #define __HASH_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
 389 #endif /* STM32F437xx || STM32F439xx */
 390
 391 /** @brief  Enables or disables the AHB3 peripheral clock.
 392   * @note   After reset, the peripheral clock (used for registers read/write access)
 393   *         is disabled and the application software has to enable this clock before
 394   *         using it.
 395   */
 396 #define __FMC_CLK_ENABLE()   (RCC->AHB3ENR |= (RCC_AHB3ENR_FMCEN))
 397 #define __FMC_CLK_DISABLE()  (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
 398
 399 /** @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
 400   * @note   After reset, the peripheral clock (used for registers read/write access)
 401   *         is disabled and the application software has to enable this clock before
 402   *         using it.
 403   */
 404 #define __TIM6_CLK_ENABLE()    (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN))
 405 #define __TIM7_CLK_ENABLE()    (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN))
 406 #define __TIM12_CLK_ENABLE()   (RCC->APB1ENR |= (RCC_APB1ENR_TIM12EN))
 407 #define __TIM13_CLK_ENABLE()   (RCC->APB1ENR |= (RCC_APB1ENR_TIM13EN))
 408 #define __TIM14_CLK_ENABLE()   (RCC->APB1ENR |= (RCC_APB1ENR_TIM14EN))
 409 #define __WWDG_CLK_ENABLE()    (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN))
 410 #define __USART3_CLK_ENABLE()  (RCC->APB1ENR |= (RCC_APB1ENR_USART3EN))
 411 #define __UART4_CLK_ENABLE()   (RCC->APB1ENR |= (RCC_APB1ENR_UART4EN))
 412 #define __UART5_CLK_ENABLE()   (RCC->APB1ENR |= (RCC_APB1ENR_UART5EN))
 413 #define __CAN1_CLK_ENABLE()    (RCC->APB1ENR |= (RCC_APB1ENR_CAN1EN))
 414 #define __CAN2_CLK_ENABLE()    (RCC->APB1ENR |= (RCC_APB1ENR_CAN2EN))
 415 #define __DAC_CLK_ENABLE()     (RCC->APB1ENR |= (RCC_APB1ENR_DACEN))
 416 #define __UART7_CLK_ENABLE()   (RCC->APB1ENR |= (RCC_APB1ENR_UART7EN))
 417 #define __UART8_CLK_ENABLE()   (RCC->APB1ENR |= (RCC_APB1ENR_UART8EN))
 418
 419 #define __TIM6_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
 420 #define __TIM7_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
 421 #define __TIM12_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
 422 #define __TIM13_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
 423 #define __TIM14_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
 424 #define __WWDG_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
 425 #define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
 426 #define __UART4_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
 427 #define __UART5_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
 428 #define __CAN1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
 429 #define __CAN2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
 430 #define __DAC_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
 431 #define __UART7_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
 432 #define __UART8_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
 433
 434 /** @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
 435   * @note   After reset, the peripheral clock (used for registers read/write access)
 436   *         is disabled and the application software has to enable this clock before
 437   *         using it.
 438   */
 439 #define __TIM8_CLK_ENABLE()  (RCC->APB2ENR |= (RCC_APB2ENR_TIM8EN))
 440 #define __ADC2_CLK_ENABLE()  (RCC->APB2ENR |= (RCC_APB2ENR_ADC2EN))
 441 #define __ADC3_CLK_ENABLE()  (RCC->APB2ENR |= (RCC_APB2ENR_ADC3EN))
 442 #define __SPI5_CLK_ENABLE()  (RCC->APB2ENR |= (RCC_APB2ENR_SPI5EN))
 443 #define __SPI6_CLK_ENABLE()  (RCC->APB2ENR |= (RCC_APB2ENR_SPI6EN))
 444 #define __SAI1_CLK_ENABLE()  (RCC->APB2ENR |= (RCC_APB2ENR_SAI1EN))
 445
 446 #define __TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
 447 #define __ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
 448 #define __ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
 449 #define __SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
 450 #define __SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
 451 #define __SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
 452
 453 #if defined(STM32F429xx)|| defined(STM32F439xx)
 454 #define __LTDC_CLK_ENABLE()  (RCC->APB2ENR |= (RCC_APB2ENR_LTDCEN))
 455
 456 #define __LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
 457 #endif /* STM32F429xx || STM32F439xx */
 458
 459 /** @brief  Force or release AHB1 peripheral reset.
 460   */
 461 #define __GPIOF_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
 462 #define __GPIOG_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
 463 #define __GPIOI_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
 464 #define __ETHMAC_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
 465 #define __OTGHS_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
 466 #define __GPIOJ_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST))
 467 #define __GPIOK_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST))
 468 #define __DMA2D_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST))
 469
 470 #define __GPIOF_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
 471 #define __GPIOG_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
 472 #define __GPIOI_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
 473 #define __ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
 474 #define __OTGHS_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
 475 #define __GPIOJ_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
 476 #define __GPIOK_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
 477 #define __DMA2D_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
 478
 479 /** @brief  Force or release AHB2 peripheral reset.
 480   */
 481 #define __DCMI_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
 482 #define __DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
 483
 484 #if defined(STM32F437xx)|| defined(STM32F439xx)
 485 #define __CRYP_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
 486 #define __HASH_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
 487
 488 #define __CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
 489 #define __HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
 490 #endif /* STM32F437xx || STM32F439xx */
 491
 492 /** @brief  Force or release AHB3 peripheral reset
 493   */
 494 #define __FMC_FORCE_RESET()    (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
 495 #define __FMC_RELEASE_RESET()  (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
 496
 497 /** @brief  Force or release APB1 peripheral reset.
 498   */
 499 #define __TIM6_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
 500 #define __TIM7_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
 501 #define __TIM12_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
 502 #define __TIM13_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
 503 #define __TIM14_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
 504 #define __USART3_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
 505 #define __UART4_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
 506 #define __UART5_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
 507 #define __CAN1_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
 508 #define __CAN2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
 509 #define __DAC_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
 510 #define __UART7_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))
 511 #define __UART8_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))
 512
 513 #define __TIM6_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
 514 #define __TIM7_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
 515 #define __TIM12_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
 516 #define __TIM13_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
 517 #define __TIM14_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
 518 #define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
 519 #define __UART4_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
 520 #define __UART5_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
 521 #define __CAN1_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
 522 #define __CAN2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
 523 #define __DAC_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
 524 #define __UART7_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
 525 #define __UART8_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
 526
 527 /** @brief  Force or release APB2 peripheral reset.
 528   */
 529 #define __TIM8_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
 530 #define __SPI5_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
 531 #define __SPI6_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST))
 532 #define __SAI1_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
 533
 534 #define __TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
 535 #define __SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
 536 #define __SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
 537 #define __SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
 538
 539 #if defined(STM32F429xx)|| defined(STM32F439xx)
 540 #define __LTDC_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST))
 541 #define __LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
 542 #endif /* STM32F429xx|| STM32F439xx */
 543
 544 /** @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
 545   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
 546   *         power consumption.
 547   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
 548   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
 549   */
 550 #define __GPIOF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
 551 #define __GPIOG_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
 552 #define __GPIOI_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
 553 #define __SRAM2_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
 554 #define __ETHMAC_CLK_SLEEP_ENABLE()     (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
 555 #define __ETHMACTX_CLK_SLEEP_ENABLE()   (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
 556 #define __ETHMACRX_CLK_SLEEP_ENABLE()   (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
 557 #define __ETHMACPTP_CLK_SLEEP_ENABLE()  (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
 558 #define __OTGHS_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
 559 #define __OTGHSULPI_CLK_SLEEP_ENABLE()  (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
 560 #define __GPIOJ_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN))
 561 #define __GPIOK_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN))
 562 #define __SRAM3_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM3LPEN))
 563 #define __DMA2D_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN))
 564
 565 #define __GPIOF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
 566 #define __GPIOG_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
 567 #define __GPIOI_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
 568 #define __SRAM2_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
 569 #define __ETHMAC_CLK_SLEEP_DISABLE()    (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
 570 #define __ETHMACTX_CLK_SLEEP_DISABLE()  (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
 571 #define __ETHMACRX_CLK_SLEEP_DISABLE()  (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
 572 #define __ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
 573 #define __OTGHS_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
 574 #define __OTGHSULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
 575 #define __GPIOJ_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
 576 #define __GPIOK_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
 577 #define __DMA2D_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
 578
 579 /** @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
 580   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
 581   *         power consumption.
 582   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
 583   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
 584   */
 585 #define __DCMI_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
 586 #define __DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
 587
 588 #if defined(STM32F437xx)|| defined(STM32F439xx)
 589 #define __CRYP_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
 590 #define __HASH_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
 591
 592 #define __CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
 593 #define __HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
 594 #endif /* STM32F437xx || STM32F439xx */
 595
 596 /** @brief  Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
 597   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
 598   *         power consumption.
 599   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
 600   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
 601   */
 602 #define __FMC_CLK_SLEEP_ENABLE()  (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
 603 #define __FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
 604
 605 /** @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
 606   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
 607   *         power consumption.
 608   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
 609   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
 610   */
 611 #define __TIM6_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
 612 #define __TIM7_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
 613 #define __TIM12_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
 614 #define __TIM13_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
 615 #define __TIM14_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
 616 #define __USART3_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
 617 #define __UART4_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
 618 #define __UART5_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
 619 #define __CAN1_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
 620 #define __CAN2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
 621 #define __DAC_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
 622 #define __UART7_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))
 623 #define __UART8_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))
 624
 625 #define __TIM6_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
 626 #define __TIM7_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
 627 #define __TIM12_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
 628 #define __TIM13_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
 629 #define __TIM14_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
 630 #define __USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
 631 #define __UART4_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
 632 #define __UART5_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
 633 #define __CAN1_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
 634 #define __CAN2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
 635 #define __DAC_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
 636 #define __UART7_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
 637 #define __UART8_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
 638
 639 /** @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
 640   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
 641   *         power consumption.
 642   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
 643   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
 644   */
 645 #define __TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
 646 #define __ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
 647 #define __ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
 648 #define __SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
 649 #define __SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN))
 650 #define __SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
 651
 652 #define __TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
 653 #define __ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
 654 #define __ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
 655 #define __SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
 656 #define __SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
 657 #define __SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
 658
 659 #if defined(STM32F429xx)|| defined(STM32F439xx)
 660 #define __LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN))
 661
 662 #define __LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
 663 #endif /* STM32F429xx || STM32F439xx */
 664 #endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
 665 /*---------------------------------------------------------------------------------------------*/
 666
 667 /*----------------------------------- STM32F40xxx/STM32F41xxx----------------------------------*/
 668 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
 669 /** @brief  Enables or disables the AHB1 peripheral clock.
 670   * @note   After reset, the peripheral clock (used for registers read/write access)
 671   *         is disabled and the application software has to enable this clock before
 672   *         using it.
 673   */
 674 #define __GPIOI_CLK_ENABLE()            (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOIEN))
 675 #define __GPIOF_CLK_ENABLE()            (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOFEN))
 676 #define __GPIOG_CLK_ENABLE()            (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOGEN))
 677 #define __USB_OTG_HS_CLK_ENABLE()       (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSEN))
 678 #define __USB_OTG_HS_ULPI_CLK_ENABLE()  (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSULPIEN))
 679
 680 #define __GPIOF_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
 681 #define __GPIOG_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
 682 #define __GPIOI_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
 683 #define __USB_OTG_HS_CLK_DISABLE()      (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
 684 #define __USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
 685
 686 #if defined(STM32F407xx)|| defined(STM32F417xx)
 687 /**
 688   * @brief  Enable ETHERNET clock.
 689   */
 690 #define __ETHMAC_CLK_ENABLE()     (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACEN))
 691 #define __ETHMACTX_CLK_ENABLE()   (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACTXEN))
 692 #define __ETHMACRX_CLK_ENABLE()   (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACRXEN))
 693 #define __ETHMACPTP_CLK_ENABLE()  (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACPTPEN))
 694 #define __ETH_CLK_ENABLE()       do {                            \
 695                                      __ETHMAC_CLK_ENABLE();      \
 696                                      __ETHMACTX_CLK_ENABLE();    \
 697                                      __ETHMACRX_CLK_ENABLE();    \
 698                                     } while(0)
 699
 700 /**
 701   * @brief  Disable ETHERNET clock.
 702   */
 703 #define __ETHMAC_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
 704 #define __ETHMACTX_CLK_DISABLE()  (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
 705 #define __ETHMACRX_CLK_DISABLE()  (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
 706 #define __ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
 707 #define __ETH_CLK_DISABLE()       do {                             \
 708                                       __ETHMACTX_CLK_DISABLE();    \
 709                                       __ETHMACRX_CLK_DISABLE();    \
 710                                       __ETHMAC_CLK_DISABLE();      \
 711                                      } while(0)
 712 #endif /* STM32F407xx || STM32F417xx */
 713
 714 /** @brief  Enable or disable the AHB2 peripheral clock.
 715   * @note   After reset, the peripheral clock (used for registers read/write access)
 716   *         is disabled and the application software has to enable this clock before
 717   *         using it.
 718   */
 719 #if defined(STM32F407xx)|| defined(STM32F417xx)
 720 #define __DCMI_CLK_ENABLE()   (RCC->AHB2ENR |= (RCC_AHB2ENR_DCMIEN))
 721 #define __DCMI_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
 722 #endif /* STM32F407xx || STM32F417xx */
 723
 724 #if defined(STM32F415xx) || defined(STM32F417xx)
 725 #define __CRYP_CLK_ENABLE()   (RCC->AHB2ENR |= (RCC_AHB2ENR_CRYPEN))
 726 #define __HASH_CLK_ENABLE()   (RCC->AHB2ENR |= (RCC_AHB2ENR_HASHEN))
 727
 728 #define __CRYP_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
 729 #define __HASH_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
 730 #endif /* STM32F415xx || STM32F417xx */
 731
 732 /** @brief  Enables or disables the AHB3 peripheral clock.
 733   * @note   After reset, the peripheral clock (used for registers read/write access)
 734   *         is disabled and the application software has to enable this clock before
 735   *         using it.
 736   */
 737 #define __FSMC_CLK_ENABLE()  (RCC->AHB3ENR |= (RCC_AHB3ENR_FSMCEN))
 738 #define __FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
 739
 740 /** @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
 741   * @note   After reset, the peripheral clock (used for registers read/write access)
 742   *         is disabled and the application software has to enable this clock before
 743   *         using it.
 744   */
 745 #define __TIM6_CLK_ENABLE()    (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN))
 746 #define __TIM7_CLK_ENABLE()    (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN))
 747 #define __TIM12_CLK_ENABLE()   (RCC->APB1ENR |= (RCC_APB1ENR_TIM12EN))
 748 #define __TIM13_CLK_ENABLE()   (RCC->APB1ENR |= (RCC_APB1ENR_TIM13EN))
 749 #define __TIM14_CLK_ENABLE()   (RCC->APB1ENR |= (RCC_APB1ENR_TIM14EN))
 750 #define __WWDG_CLK_ENABLE()    (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN))
 751 #define __USART3_CLK_ENABLE()  (RCC->APB1ENR |= (RCC_APB1ENR_USART3EN))
 752 #define __UART4_CLK_ENABLE()   (RCC->APB1ENR |= (RCC_APB1ENR_UART4EN))
 753 #define __UART5_CLK_ENABLE()   (RCC->APB1ENR |= (RCC_APB1ENR_UART5EN))
 754 #define __CAN1_CLK_ENABLE()    (RCC->APB1ENR |= (RCC_APB1ENR_CAN1EN))
 755 #define __CAN2_CLK_ENABLE()    (RCC->APB1ENR |= (RCC_APB1ENR_CAN2EN))
 756 #define __DAC_CLK_ENABLE()     (RCC->APB1ENR |= (RCC_APB1ENR_DACEN))
 757
 758 #define __TIM6_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
 759 #define __TIM7_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
 760 #define __TIM12_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
 761 #define __TIM13_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
 762 #define __TIM14_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
 763 #define __WWDG_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
 764 #define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
 765 #define __UART4_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
 766 #define __UART5_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
 767 #define __CAN1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
 768 #define __CAN2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
 769 #define __DAC_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
 770
 771 /** @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
 772   * @note   After reset, the peripheral clock (used for registers read/write access)
 773   *         is disabled and the application software has to enable this clock before
 774   *         using it.
 775   */
 776 #define __TIM8_CLK_ENABLE()  (RCC->APB2ENR |= (RCC_APB2ENR_TIM8EN))
 777 #define __ADC2_CLK_ENABLE()  (RCC->APB2ENR |= (RCC_APB2ENR_ADC2EN))
 778 #define __ADC3_CLK_ENABLE()  (RCC->APB2ENR |= (RCC_APB2ENR_ADC3EN))
 779
 780 #define __TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
 781 #define __ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
 782 #define __ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
 783
 784 /** @brief  Force or release AHB1 peripheral reset.
 785   */
 786 #define __GPIOF_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
 787 #define __GPIOG_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
 788 #define __GPIOI_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
 789 #define __ETHMAC_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
 790 #define __OTGHS_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
 791
 792 #define __GPIOF_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
 793 #define __GPIOG_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
 794 #define __GPIOI_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
 795 #define __ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
 796 #define __OTGHS_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
 797
 798 /** @brief  Force or release AHB2 peripheral reset.
 799   */
 800 #if defined(STM32F407xx)|| defined(STM32F417xx)
 801 #define __DCMI_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
 802 #define __DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
 803 #endif /* STM32F407xx || STM32F417xx */
 804
 805 #if defined(STM32F415xx) || defined(STM32F417xx)
 806 #define __CRYP_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
 807 #define __HASH_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
 808
 809 #define __CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
 810 #define __HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
 811
 812 #endif /* STM32F415xx || STM32F417xx */
 813
 814 /** @brief  Force or release AHB3 peripheral reset
 815   */
 816 #define __FSMC_FORCE_RESET()   (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST))
 817 #define __FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
 818
 819 /** @brief  Force or release APB1 peripheral reset.
 820   */
 821 #define __TIM6_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
 822 #define __TIM7_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
 823 #define __TIM12_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
 824 #define __TIM13_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
 825 #define __TIM14_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
 826 #define __USART3_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
 827 #define __UART4_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
 828 #define __UART5_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
 829 #define __CAN1_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
 830 #define __CAN2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
 831 #define __DAC_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
 832
 833 #define __TIM6_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
 834 #define __TIM7_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
 835 #define __TIM12_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
 836 #define __TIM13_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
 837 #define __TIM14_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
 838 #define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
 839 #define __UART4_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
 840 #define __UART5_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
 841 #define __CAN1_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
 842 #define __CAN2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
 843 #define __DAC_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
 844
 845 /** @brief  Force or release APB2 peripheral reset.
 846   */
 847 #define __TIM8_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
 848 #define __TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
 849
 850 /** @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
 851   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
 852   *         power consumption.
 853   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
 854   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
 855   */
 856 #define __GPIOF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
 857 #define __GPIOG_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
 858 #define __GPIOI_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
 859 #define __SRAM2_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
 860 #define __ETHMAC_CLK_SLEEP_ENABLE()     (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
 861 #define __ETHMACTX_CLK_SLEEP_ENABLE()   (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
 862 #define __ETHMACRX_CLK_SLEEP_ENABLE()   (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
 863 #define __ETHMACPTP_CLK_SLEEP_ENABLE()  (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
 864 #define __OTGHS_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
 865 #define __OTGHSULPI_CLK_SLEEP_ENABLE()  (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
 866
 867 #define __GPIOF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
 868 #define __GPIOG_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
 869 #define __GPIOI_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
 870 #define __SRAM2_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
 871 #define __ETHMAC_CLK_SLEEP_DISABLE()    (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
 872 #define __ETHMACTX_CLK_SLEEP_DISABLE()  (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
 873 #define __ETHMACRX_CLK_SLEEP_DISABLE()  (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
 874 #define __ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
 875 #define __OTGHS_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
 876 #define __OTGHSULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
 877
 878 /** @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
 879   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
 880   *         power consumption.
 881   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
 882   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
 883   */
 884 #if defined(STM32F407xx)|| defined(STM32F417xx)
 885 #define __DCMI_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
 886 #define __DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
 887 #endif /* STM32F407xx || STM32F417xx */
 888
 889 #if defined(STM32F415xx) || defined(STM32F417xx)
 890 #define __CRYP_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
 891 #define __HASH_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
 892
 893 #define __CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
 894 #define __HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
 895 #endif /* STM32F415xx || STM32F417xx */
 896
 897 /** @brief  Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
 898   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
 899   *         power consumption.
 900   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
 901   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
 902   */
 903 #define __FSMC_CLK_SLEEP_ENABLE()  (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN))
 904 #define __FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
 905
 906 /** @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
 907   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
 908   *         power consumption.
 909   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
 910   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
 911   */
 912 #define __TIM6_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
 913 #define __TIM7_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
 914 #define __TIM12_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
 915 #define __TIM13_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
 916 #define __TIM14_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
 917 #define __USART3_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
 918 #define __UART4_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
 919 #define __UART5_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
 920 #define __CAN1_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
 921 #define __CAN2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
 922 #define __DAC_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
 923
 924 #define __TIM6_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
 925 #define __TIM7_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
 926 #define __TIM12_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
 927 #define __TIM13_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
 928 #define __TIM14_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
 929 #define __USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
 930 #define __UART4_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
 931 #define __UART5_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
 932 #define __CAN1_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
 933 #define __CAN2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
 934 #define __DAC_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
 935
 936 /** @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
 937   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
 938   *         power consumption.
 939   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
 940   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
 941   */
 942 #define __TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
 943 #define __ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
 944 #define __ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
 945
 946 #define __TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
 947 #define __ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
 948 #define __ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
 949 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
 950 /*---------------------------------------------------------------------------------------------*/
 951
 952 /*------------------------------------------ STM32F411xx --------------------------------------*/
 953 #if defined(STM32F411xE)
 954 /** @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
 955   */
 956 #define __SPI5_CLK_ENABLE()  (RCC->APB2ENR |= (RCC_APB2ENR_SPI5EN))
 957 #define __SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
 958
 959 /** @brief  Force or release APB2 peripheral reset.
 960   */
 961 #define __SPI5_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
 962 #define __SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
 963
 964 /** @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
 965   */
 966 #define __SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
 967 #define __SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
 968
 969 #endif /* STM32F411xE */
 970 /*---------------------------------------------------------------------------------------------*/
 971
 972 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
 973     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
 974
 975 /** @brief  Macro to configure the Timers clocks prescalers
 976   * @note   This feature is only available with STM32F429x/439x Devices.
 977   * @param  __PRESC__ : specifies the Timers clocks prescalers selection
 978   *         This parameter can be one of the following values:
 979   *            @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
 980   *                 equal to HPRE if PPREx is corresponding to division by 1 or 2,
 981   *                 else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
 982   *                 division by 4 or more.
 983   *            @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
 984   *                 equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
 985   *                 else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
 986   *                 to division by 8 or more.
 987   */
 988 #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) (*(__IO uint32_t *) DCKCFGR_TIMPRE_BB = (__PRESC__))
 989
 990 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx) || STM32F401xC || STM32F401xE || STM32F411xE */
 991
 992 #if defined(STM32F411xE)
 993
 994 /** @brief  Macro to configure the PLLI2S clock multiplication and division factors .
 995   * @note   This macro must be used only when the PLLI2S is disabled.
 996   * @note   This macro must be used only when the PLLI2S is disabled.
 997   * @note   PLLI2S clock source is common with the main PLL (configured in
 998   *         HAL_RCC_ClockConfig() API).
 999   * @param  __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock
1000   *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.
1001   * @note   You have to set the PLLI2SM parameter correctly to ensure that the VCO input
1002   *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
1003   *         of 2 MHz to limit PLLI2S jitter.
1004   * @param  __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
1005   *         This parameter must be a number between Min_Data = 192 and Max_Data = 432.
1006   * @note   You have to set the PLLI2SN parameter correctly to ensure that the VCO
1007   *         output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
1008   * @param  __PLLI2SR__: specifies the division factor for I2S clock
1009   *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
1010   * @note   You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
1011   *         on the I2S clock frequency.
1012   */
1013 #define __HAL_RCC_PLLI2S_I2SCLK_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\
1014                                                                                     ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)) | (__PLLI2SM__))
1015 #endif /* STM32F411xE */
1016
1017
1018 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
1019
1020 /** @brief Macros to Enable or Disable the PLLISAI.
1021   * @note  The PLLSAI is only available with STM32F429x/439x Devices.
1022   * @note  The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
1023   */
1024 #define __HAL_RCC_PLLSAI_ENABLE() (*(__IO uint32_t *) CR_PLLSAION_BB = ENABLE)
1025 #define __HAL_RCC_PLLSAI_DISABLE() (*(__IO uint32_t *) CR_PLLSAION_BB = DISABLE)
1026
1027 /** @brief  Macro to configure the PLLSAI clock multiplication and division factors.
1028   * @note   The PLLSAI is only available with STM32F429x/439x Devices.
1029   * @note   This function must be used only when the PLLSAI is disabled.
1030   * @note   PLLSAI clock source is common with the main PLL (configured in
1031   *         RCC_PLLConfig function )
1032   * @param  __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
1033   *         This parameter must be a number between Min_Data = 192 and Max_Data = 432.
1034   * @note   You have to set the PLLSAIN parameter correctly to ensure that the VCO
1035   *         output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
1036   * @param  __PLLSAIQ__: specifies the division factor for SAI1 clock
1037   *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
1038   * @param  __PLLSAIR__: specifies the division factor for LTDC clock
1039   *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
1040   */
1041 #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) (RCC->PLLSAICFGR = ((__PLLSAIN__) << 6) | ((__PLLSAIQ__) << 24) | ((__PLLSAIR__) << 28))
1042
1043 /** @brief  Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors.
1044   * @note   This macro must be used only when the PLLI2S is disabled.
1045   * @note   PLLI2S clock source is common with the main PLL (configured in
1046   *         HAL_RCC_ClockConfig() API)
1047   * @param  __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
1048   *         This parameter must be a number between Min_Data = 192 and Max_Data = 432.
1049   * @note   You have to set the PLLI2SN parameter correctly to ensure that the VCO
1050   *         output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
1051   * @param  __PLLI2SQ__: specifies the division factor for SAI1 clock.
1052   *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
1053   * @note   the PLLI2SQ parameter is only available with STM32F429x/439x Devices
1054   *         and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro
1055   * @param  __PLLI2SR__: specifies the division factor for I2S clock
1056   *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
1057   * @note   You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
1058   *         on the I2S clock frequency.
1059   */
1060 #define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6) | ((__PLLI2SQ__) << 24) | ((__PLLI2SR__) << 28))
1061
1062 /** @brief  Macro to configure the SAI clock Divider coming from PLLI2S.
1063   * @note   The SAI peripheral is only available with STM32F429x/439x Devices.
1064   * @note   This function must be called before enabling the PLLI2S.
1065   * @param  __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock .
1066   *          This parameter must be a number between 1 and 32.
1067   *          SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
1068   */
1069 #define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))
1070
1071 /** @brief  Macro to configure the SAI clock Divider coming from PLLSAI.
1072   * @note   The SAI peripheral is only available with STM32F429x/439x Devices.
1073   * @note   This function must be called before enabling the PLLSAI.
1074   * @param  __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock .
1075   *         This parameter must be a number between Min_Data = 1 and Max_Data = 32.
1076   *         SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
1077   */
1078 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))
1079
1080 /** @brief  Macro to configure the LTDC clock Divider coming from PLLSAI.
1081   *
1082   * @note   The LTDC peripheral is only available with STM32F429x/439x Devices.
1083   * @note   This function must be called before enabling the PLLSAI.
1084   * @param  __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .
1085   *          This parameter must be a number between Min_Data = 2 and Max_Data = 16.
1086   *          LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
1087   */
1088 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__)))
1089
1090 /** @brief  Macro to configure SAI1BlockA clock source selection.
1091   * @note   The SAI peripheral is only available with STM32F429x/439x Devices.
1092   * @note   This function must be called before enabling PLLSAI, PLLI2S and
1093   *         the SAI clock.
1094   * @param  __SOURCE__: specifies the SAI Block A clock source.
1095   *         This parameter can be one of the following values:
1096   *            @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
1097   *                                           as SAI1 Block A clock.
1098   *            @arg RCC_SAIACLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
1099   *                                           as SAI1 Block A clock.
1100   *            @arg RCC_SAIACLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
1101   *                                        used as SAI1 Block A clock.
1102   */
1103 #define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
1104
1105 /** @brief  Macro to configure SAI1BlockB clock source selection.
1106   * @note   The SAI peripheral is only available with STM32F429x/439x Devices.
1107   * @note   This function must be called before enabling PLLSAI, PLLI2S and
1108   *         the SAI clock.
1109   * @param  __SOURCE__: specifies the SAI Block B clock source.
1110   *         This parameter can be one of the following values:
1111   *            @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
1112   *                                           as SAI1 Block B clock.
1113   *            @arg RCC_SAIBCLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
1114   *                                           as SAI1 Block B clock.
1115   *            @arg RCC_SAIBCLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
1116   *                                        used as SAI1 Block B clock.
1117   */
1118 #define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
1119
1120 /** @brief Enable PLLSAI_RDY interrupt.
1121   */
1122 #define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE))
1123
1124 /** @brief Disable PLLSAI_RDY interrupt.
1125   */
1126 #define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
1127
1128 /** @brief Clear the PLLSAI RDY interrupt pending bits.
1129   */
1130 #define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF))
1131
1132 /** @brief Check the PLLSAI RDY interrupt has occurred or not.
1133   * @retval The new state (TRUE or FALSE).
1134   */
1135 #define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
1136
1137 /** @brief  Check PLLSAI RDY flag is set or not.
1138   * @retval The new state (TRUE or FALSE).
1139   */
1140 #define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
1141
1142 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
1143
1144 /* Exported functions --------------------------------------------------------*/
1145 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
1146 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
1147
1148 #if defined(STM32F411xE)
1149 void HAL_RCCEx_SelectLSEMode(uint8_t Mode);
1150 #endif /* STM32F411xE */
1151 /**
1152   * @}
1153   */
1154
1155 /**
1156   * @}
1157   */
1158
1159 #ifdef __cplusplus
1160 }
1161 #endif
1162
1163 #endif /* __STM32F4xx_HAL_RCC_EX_H */
1164
1165 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/