tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sdram.c

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f4xx_hal_sdram.c
   4   * @author  MCD Application Team
   5   * @version V1.1.0
   6   * @date    19-June-2014
   7   * @brief   SDRAM HAL module driver.
   8   *          This file provides a generic firmware to drive SDRAM memories mounted
   9   *          as external device.
  10   *
  11   @verbatim
  12   ==============================================================================
  13                        ##### How to use this driver #####
  14   ==============================================================================
  15   [..]
  16     This driver is a generic layered driver which contains a set of APIs used to
  17     control SDRAM memories. It uses the FMC layer functions to interface
  18     with SDRAM devices.
  19     The following sequence should be followed to configure the FMC to interface
  20     with SDRAM memories:
  21
  22    (#) Declare a SDRAM_HandleTypeDef handle structure, for example:
  23           SDRAM_HandleTypeDef  hdsram
  24
  25        (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed
  26             values of the structure member.
  27
  28        (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined
  29             base register instance for NOR or SDRAM device
  30
  31    (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example:
  32           FMC_SDRAM_TimingTypeDef  Timing;
  33       and fill its fields with the allowed values of the structure member.
  34
  35    (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function
  36        performs the following sequence:
  37
  38        (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit()
  39        (##) Control register configuration using the FMC SDRAM interface function
  40             FMC_SDRAM_Init()
  41        (##) Timing register configuration using the FMC SDRAM interface function
  42             FMC_SDRAM_Timing_Init()
  43        (##) Program the SDRAM external device by applying its initialization sequence
  44             according to the device plugged in your hardware. This step is mandatory
  45             for accessing the SDRAM device.
  46
  47    (#) At this stage you can perform read/write accesses from/to the memory connected
  48        to the SDRAM Bank. You can perform either polling or DMA transfer using the
  49        following APIs:
  50        (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access
  51        (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer
  52
  53    (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/
  54        HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or
  55        the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM
  56        device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef
  57        structure.
  58
  59    (#) You can continuously monitor the SDRAM device HAL state by calling the function
  60        HAL_SDRAM_GetState()
  61
  62   @endverbatim
  63   ******************************************************************************
  64   * @attention
  65   *
  66   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
  67   *
  68   * Redistribution and use in source and binary forms, with or without modification,
  69   * are permitted provided that the following conditions are met:
  70   *   1. Redistributions of source code must retain the above copyright notice,
  71   *      this list of conditions and the following disclaimer.
  72   *   2. Redistributions in binary form must reproduce the above copyright notice,
  73   *      this list of conditions and the following disclaimer in the documentation
  74   *      and/or other materials provided with the distribution.
  75   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  76   *      may be used to endorse or promote products derived from this software
  77   *      without specific prior written permission.
  78   *
  79   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  80   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  81   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  82   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  83   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  84   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  85   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  86   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  87   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  88   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  89   *
  90   ******************************************************************************
  91   */
  92
  93 /* Includes ------------------------------------------------------------------*/
  94 #include "stm32f4xx_hal.h"
  95
  96 /** @addtogroup STM32F4xx_HAL_Driver
  97   * @{
  98   */
  99
 100 /** @defgroup SDRAM
 101   * @brief SDRAM driver modules
 102   * @{
 103   */
 104 #ifdef HAL_SDRAM_MODULE_ENABLED
 105 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
 106
 107 /* Private typedef -----------------------------------------------------------*/
 108 /* Private define ------------------------------------------------------------*/
 109 /* Private macro -------------------------------------------------------------*/
 110 /* Private variables ---------------------------------------------------------*/
 111 /* Private function prototypes -----------------------------------------------*/
 112
 113 /* Private functions ---------------------------------------------------------*/
 114
 115 /** @defgroup SDRAM_Private_Functions
 116   * @{
 117   */
 118
 119 /** @defgroup SDRAM_Group1 Initialization and de-initialization functions
 120   * @brief    Initialization and Configuration functions
 121   *
 122   @verbatim
 123   ==============================================================================
 124            ##### SDRAM Initialization and de_initialization functions #####
 125   ==============================================================================
 126   [..]
 127     This section provides functions allowing to initialize/de-initialize
 128     the SDRAM memory
 129
 130 @endverbatim
 131   * @{
 132   */
 133
 134 /**
 135   * @brief  Performs the SDRAM device initialization sequence.
 136   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
 137   *                the configuration information for SDRAM module.
 138   * @param  Timing: Pointer to SDRAM control timing structure
 139   * @retval HAL status
 140   */
 141 HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
 142 {
 143   /* Check the SDRAM handle parameter */
 144   if(hsdram == HAL_NULL)
 145   {
 146     return HAL_ERROR;
 147   }
 148
 149   if(hsdram->State == HAL_SDRAM_STATE_RESET)
 150   {
 151     /* Initialize the low level hardware (MSP) */
 152     HAL_SDRAM_MspInit(hsdram);
 153   }
 154
 155   /* Initialize the SDRAM controller state */
 156   hsdram->State = HAL_SDRAM_STATE_BUSY;
 157
 158   /* Initialize SDRAM control Interface */
 159   FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init));
 160
 161   /* Initialize SDRAM timing Interface */
 162   FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank);
 163
 164   /* Update the SDRAM controller state */
 165   hsdram->State = HAL_SDRAM_STATE_READY;
 166
 167   return HAL_OK;
 168 }
 169
 170 /**
 171   * @brief  Perform the SDRAM device initialization sequence.
 172   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
 173   *                the configuration information for SDRAM module.
 174   * @retval HAL status
 175   */
 176 HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram)
 177 {
 178   /* Initialize the low level hardware (MSP) */
 179   HAL_SDRAM_MspDeInit(hsdram);
 180
 181   /* Configure the SDRAM registers with their reset values */
 182   FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank);
 183
 184   /* Reset the SDRAM controller state */
 185   hsdram->State = HAL_SDRAM_STATE_RESET;
 186
 187   /* Release Lock */
 188   __HAL_UNLOCK(hsdram);
 189
 190   return HAL_OK;
 191 }
 192
 193 /**
 194   * @brief  SDRAM MSP Init.
 195   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
 196   *                the configuration information for SDRAM module.
 197   * @retval None
 198   */
 199 __weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram)
 200 {
 201   /* NOTE: This function Should not be modified, when the callback is needed,
 202             the HAL_SDRAM_MspInit could be implemented in the user file
 203    */
 204 }
 205
 206 /**
 207   * @brief  SDRAM MSP DeInit.
 208   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
 209   *                the configuration information for SDRAM module.
 210   * @retval None
 211   */
 212 __weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram)
 213 {
 214   /* NOTE: This function Should not be modified, when the callback is needed,
 215             the HAL_SDRAM_MspDeInit could be implemented in the user file
 216    */
 217 }
 218
 219 /**
 220   * @brief  This function handles SDRAM refresh error interrupt request.
 221   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
 222   *                the configuration information for SDRAM module.
 223   * @retval HAL status
 224 */
 225 void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram)
 226 {
 227   /* Check SDRAM interrupt Rising edge flag */
 228   if(__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT))
 229   {
 230     /* SDRAM refresh error interrupt callback */
 231     HAL_SDRAM_RefreshErrorCallback(hsdram);
 232
 233     /* Clear SDRAM refresh error interrupt pending bit */
 234     __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR);
 235   }
 236 }
 237
 238 /**
 239   * @brief  SDRAM Refresh error callback.
 240   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
 241   *                the configuration information for SDRAM module.
 242   * @retval None
 243   */
 244 __weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram)
 245 {
 246   /* NOTE: This function Should not be modified, when the callback is needed,
 247             the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file
 248    */
 249 }
 250
 251 /**
 252   * @brief  DMA transfer complete callback.
 253   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
 254   *                the configuration information for the specified DMA module.
 255   * @retval None
 256   */
 257 __weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
 258 {
 259   /* NOTE: This function Should not be modified, when the callback is needed,
 260             the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file
 261    */
 262 }
 263
 264 /**
 265   * @brief  DMA transfer complete error callback.
 266   * @param  hdma: DMA handle
 267   * @retval None
 268   */
 269 __weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
 270 {
 271   /* NOTE: This function Should not be modified, when the callback is needed,
 272             the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file
 273    */
 274 }
 275
 276 /**
 277   * @}
 278   */
 279
 280 /** @defgroup SDRAM_Group2 Input and Output functions
 281   * @brief    Input Output and memory control functions
 282   *
 283   @verbatim
 284   ==============================================================================
 285                     ##### SDRAM Input and Output functions #####
 286   ==============================================================================
 287   [..]
 288     This section provides functions allowing to use and control the SDRAM memory
 289
 290 @endverbatim
 291   * @{
 292   */
 293
 294 /**
 295   * @brief  Reads 8-bit data buffer from the SDRAM memory.
 296   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
 297   *                the configuration information for SDRAM module.
 298   * @param  pAddress: Pointer to read start address
 299   * @param  pDstBuffer: Pointer to destination buffer
 300   * @param  BufferSize: Size of the buffer to read from memory
 301   * @retval HAL status
 302   */
 303 HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
 304 {
 305   __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
 306
 307   /* Process Locked */
 308   __HAL_LOCK(hsdram);
 309
 310   /* Check the SDRAM controller state */
 311   if(hsdram->State == HAL_SDRAM_STATE_BUSY)
 312   {
 313     return HAL_BUSY;
 314   }
 315   else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
 316   {
 317     return  HAL_ERROR;
 318   }
 319
 320   /* Read data from source */
 321   for(; BufferSize != 0; BufferSize--)
 322   {
 323     *pDstBuffer = *(__IO uint8_t *)pSdramAddress;
 324     pDstBuffer++;
 325     pSdramAddress++;
 326   }
 327
 328   /* Process Unlocked */
 329   __HAL_UNLOCK(hsdram);
 330
 331   return HAL_OK;
 332 }
 333
 334
 335 /**
 336   * @brief  Writes 8-bit data buffer to SDRAM memory.
 337   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
 338   *                the configuration information for SDRAM module.
 339   * @param  pAddress: Pointer to write start address
 340   * @param  pSrcBuffer: Pointer to source buffer to write
 341   * @param  BufferSize: Size of the buffer to write to memory
 342   * @retval HAL status
 343   */
 344 HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
 345 {
 346   __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
 347   uint32_t tmp = 0;
 348
 349   /* Process Locked */
 350   __HAL_LOCK(hsdram);
 351
 352   /* Check the SDRAM controller state */
 353   tmp = hsdram->State;
 354
 355   if(tmp == HAL_SDRAM_STATE_BUSY)
 356   {
 357     return HAL_BUSY;
 358   }
 359   else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
 360   {
 361     return  HAL_ERROR;
 362   }
 363
 364   /* Write data to memory */
 365   for(; BufferSize != 0; BufferSize--)
 366   {
 367     *(__IO uint8_t *)pSdramAddress = *pSrcBuffer;
 368     pSrcBuffer++;
 369     pSdramAddress++;
 370   }
 371
 372   /* Process Unlocked */
 373   __HAL_UNLOCK(hsdram);
 374
 375   return HAL_OK;
 376 }
 377
 378
 379 /**
 380   * @brief  Reads 16-bit data buffer from the SDRAM memory.
 381   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
 382   *                the configuration information for SDRAM module.
 383   * @param  pAddress: Pointer to read start address
 384   * @param  pDstBuffer: Pointer to destination buffer
 385   * @param  BufferSize: Size of the buffer to read from memory
 386   * @retval HAL status
 387   */
 388 HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
 389 {
 390   __IO uint16_t *pSdramAddress = (uint16_t *)pAddress;
 391
 392   /* Process Locked */
 393   __HAL_LOCK(hsdram);
 394
 395   /* Check the SDRAM controller state */
 396   if(hsdram->State == HAL_SDRAM_STATE_BUSY)
 397   {
 398     return HAL_BUSY;
 399   }
 400   else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
 401   {
 402     return  HAL_ERROR;
 403   }
 404
 405   /* Read data from source */
 406   for(; BufferSize != 0; BufferSize--)
 407   {
 408     *pDstBuffer = *(__IO uint16_t *)pSdramAddress;
 409     pDstBuffer++;
 410     pSdramAddress++;
 411   }
 412
 413   /* Process Unlocked */
 414   __HAL_UNLOCK(hsdram);
 415
 416   return HAL_OK;
 417 }
 418
 419 /**
 420   * @brief  Writes 16-bit data buffer to SDRAM memory.
 421   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
 422   *                the configuration information for SDRAM module.
 423   * @param  pAddress: Pointer to write start address
 424   * @param  pSrcBuffer: Pointer to source buffer to write
 425   * @param  BufferSize: Size of the buffer to write to memory
 426   * @retval HAL status
 427   */
 428 HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
 429 {
 430   __IO uint16_t *pSdramAddress = (uint16_t *)pAddress;
 431   uint32_t tmp = 0;
 432
 433   /* Process Locked */
 434   __HAL_LOCK(hsdram);
 435
 436   /* Check the SDRAM controller state */
 437   tmp = hsdram->State;
 438
 439   if(tmp == HAL_SDRAM_STATE_BUSY)
 440   {
 441     return HAL_BUSY;
 442   }
 443   else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
 444   {
 445     return  HAL_ERROR;
 446   }
 447
 448   /* Write data to memory */
 449   for(; BufferSize != 0; BufferSize--)
 450   {
 451     *(__IO uint16_t *)pSdramAddress = *pSrcBuffer;
 452     pSrcBuffer++;
 453     pSdramAddress++;
 454   }
 455
 456   /* Process Unlocked */
 457   __HAL_UNLOCK(hsdram);
 458
 459   return HAL_OK;
 460 }
 461
 462 /**
 463   * @brief  Reads 32-bit data buffer from the SDRAM memory.
 464   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
 465   *                the configuration information for SDRAM module.
 466   * @param  pAddress: Pointer to read start address
 467   * @param  pDstBuffer: Pointer to destination buffer
 468   * @param  BufferSize: Size of the buffer to read from memory
 469   * @retval HAL status
 470   */
 471 HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
 472 {
 473   __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
 474
 475   /* Process Locked */
 476   __HAL_LOCK(hsdram);
 477
 478   /* Check the SDRAM controller state */
 479   if(hsdram->State == HAL_SDRAM_STATE_BUSY)
 480   {
 481     return HAL_BUSY;
 482   }
 483   else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
 484   {
 485     return  HAL_ERROR;
 486   }
 487
 488   /* Read data from source */
 489   for(; BufferSize != 0; BufferSize--)
 490   {
 491     *pDstBuffer = *(__IO uint32_t *)pSdramAddress;
 492     pDstBuffer++;
 493     pSdramAddress++;
 494   }
 495
 496   /* Process Unlocked */
 497   __HAL_UNLOCK(hsdram);
 498
 499   return HAL_OK;
 500 }
 501
 502 /**
 503   * @brief  Writes 32-bit data buffer to SDRAM memory.
 504   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
 505   *                the configuration information for SDRAM module.
 506   * @param  pAddress: Pointer to write start address
 507   * @param  pSrcBuffer: Pointer to source buffer to write
 508   * @param  BufferSize: Size of the buffer to write to memory
 509   * @retval HAL status
 510   */
 511 HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
 512 {
 513   __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
 514   uint32_t tmp = 0;
 515
 516   /* Process Locked */
 517   __HAL_LOCK(hsdram);
 518
 519   /* Check the SDRAM controller state */
 520   tmp = hsdram->State;
 521
 522   if(tmp == HAL_SDRAM_STATE_BUSY)
 523   {
 524     return HAL_BUSY;
 525   }
 526   else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
 527   {
 528     return  HAL_ERROR;
 529   }
 530
 531   /* Write data to memory */
 532   for(; BufferSize != 0; BufferSize--)
 533   {
 534     *(__IO uint32_t *)pSdramAddress = *pSrcBuffer;
 535     pSrcBuffer++;
 536     pSdramAddress++;
 537   }
 538
 539   /* Process Unlocked */
 540   __HAL_UNLOCK(hsdram);
 541
 542   return HAL_OK;
 543 }
 544
 545 /**
 546   * @brief  Reads a Words data from the SDRAM memory using DMA transfer.
 547   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
 548   *                the configuration information for SDRAM module.
 549   * @param  pAddress: Pointer to read start address
 550   * @param  pDstBuffer: Pointer to destination buffer
 551   * @param  BufferSize: Size of the buffer to read from memory
 552   * @retval HAL status
 553   */
 554 HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
 555 {
 556   uint32_t tmp = 0;
 557
 558   /* Process Locked */
 559   __HAL_LOCK(hsdram);
 560
 561   /* Check the SDRAM controller state */
 562   tmp = hsdram->State;
 563
 564   if(tmp == HAL_SDRAM_STATE_BUSY)
 565   {
 566     return HAL_BUSY;
 567   }
 568   else if(tmp == HAL_SDRAM_STATE_PRECHARGED)
 569   {
 570     return  HAL_ERROR;
 571   }
 572
 573   /* Configure DMA user callbacks */
 574   hsdram->hdma->XferCpltCallback  = HAL_SDRAM_DMA_XferCpltCallback;
 575   hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
 576
 577   /* Enable the DMA Stream */
 578   HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
 579
 580   /* Process Unlocked */
 581   __HAL_UNLOCK(hsdram);
 582
 583   return HAL_OK;
 584 }
 585
 586 /**
 587   * @brief  Writes a Words data buffer to SDRAM memory using DMA transfer.
 588   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
 589   *                the configuration information for SDRAM module.
 590   * @param  pAddress: Pointer to write start address
 591   * @param  pSrcBuffer: Pointer to source buffer to write
 592   * @param  BufferSize: Size of the buffer to write to memory
 593   * @retval HAL status
 594   */
 595 HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
 596 {
 597   uint32_t tmp = 0;
 598
 599   /* Process Locked */
 600   __HAL_LOCK(hsdram);
 601
 602   /* Check the SDRAM controller state */
 603   tmp = hsdram->State;
 604
 605   if(tmp == HAL_SDRAM_STATE_BUSY)
 606   {
 607     return HAL_BUSY;
 608   }
 609   else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
 610   {
 611     return  HAL_ERROR;
 612   }
 613
 614   /* Configure DMA user callbacks */
 615   hsdram->hdma->XferCpltCallback  = HAL_SDRAM_DMA_XferCpltCallback;
 616   hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
 617
 618   /* Enable the DMA Stream */
 619   HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
 620
 621   /* Process Unlocked */
 622   __HAL_UNLOCK(hsdram);
 623
 624   return HAL_OK;
 625 }
 626
 627 /**
 628   * @}
 629   */
 630
 631 /** @defgroup SDRAM_Group3 Control functions
 632  *  @brief   management functions
 633  *
 634 @verbatim
 635   ==============================================================================
 636                          ##### SDRAM Control functions #####
 637   ==============================================================================
 638   [..]
 639     This subsection provides a set of functions allowing to control dynamically
 640     the SDRAM interface.
 641
 642 @endverbatim
 643   * @{
 644   */
 645
 646 /**
 647   * @brief  Enables dynamically SDRAM write protection.
 648   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
 649   *                the configuration information for SDRAM module.
 650   * @retval HAL status
 651   */
 652 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram)
 653 {
 654   /* Check the SDRAM controller state */
 655   if(hsdram->State == HAL_SDRAM_STATE_BUSY)
 656   {
 657     return HAL_BUSY;
 658   }
 659
 660   /* Update the SDRAM state */
 661   hsdram->State = HAL_SDRAM_STATE_BUSY;
 662
 663   /* Enable write protection */
 664   FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank);
 665
 666   /* Update the SDRAM state */
 667   hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED;
 668
 669   return HAL_OK;
 670 }
 671
 672 /**
 673   * @brief  Disables dynamically SDRAM write protection.
 674   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
 675   *                the configuration information for SDRAM module.
 676   * @retval HAL status
 677   */
 678 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram)
 679 {
 680   /* Check the SDRAM controller state */
 681   if(hsdram->State == HAL_SDRAM_STATE_BUSY)
 682   {
 683     return HAL_BUSY;
 684   }
 685
 686   /* Update the SDRAM state */
 687   hsdram->State = HAL_SDRAM_STATE_BUSY;
 688
 689   /* Disable write protection */
 690   FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank);
 691
 692   /* Update the SDRAM state */
 693   hsdram->State = HAL_SDRAM_STATE_READY;
 694
 695   return HAL_OK;
 696 }
 697
 698 /**
 699   * @brief  Sends Command to the SDRAM bank.
 700   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
 701   *                the configuration information for SDRAM module.
 702   * @param  Command: SDRAM command structure
 703   * @param  Timeout: Timeout duration
 704   * @retval HAL status
 705   */
 706 HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
 707 {
 708   /* Check the SDRAM controller state */
 709   if(hsdram->State == HAL_SDRAM_STATE_BUSY)
 710   {
 711     return HAL_BUSY;
 712   }
 713
 714   /* Update the SDRAM state */
 715   hsdram->State = HAL_SDRAM_STATE_BUSY;
 716
 717   /* Send SDRAM command */
 718   FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout);
 719
 720   /* Update the SDRAM controller state state */
 721   if(Command->CommandMode == FMC_SDRAM_CMD_PALL)
 722   {
 723     hsdram->State = HAL_SDRAM_STATE_PRECHARGED;
 724   }
 725   else
 726   {
 727     hsdram->State = HAL_SDRAM_STATE_READY;
 728   }
 729
 730   return HAL_OK;
 731 }
 732
 733 /**
 734   * @brief  Programs the SDRAM Memory Refresh rate.
 735   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
 736   *                the configuration information for SDRAM module.
 737   * @param  RefreshRate: The SDRAM refresh rate value
 738   * @retval HAL status
 739   */
 740 HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
 741 {
 742   /* Check the SDRAM controller state */
 743   if(hsdram->State == HAL_SDRAM_STATE_BUSY)
 744   {
 745     return HAL_BUSY;
 746   }
 747
 748   /* Update the SDRAM state */
 749   hsdram->State = HAL_SDRAM_STATE_BUSY;
 750
 751   /* Program the refresh rate */
 752   FMC_SDRAM_ProgramRefreshRate(hsdram->Instance ,RefreshRate);
 753
 754   /* Update the SDRAM state */
 755   hsdram->State = HAL_SDRAM_STATE_READY;
 756
 757   return HAL_OK;
 758 }
 759
 760 /**
 761   * @brief  Sets the Number of consecutive SDRAM Memory auto Refresh commands.
 762   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
 763   *                the configuration information for SDRAM module.
 764   * @param  AutoRefreshNumber: The SDRAM auto Refresh number
 765   * @retval HAL status
 766   */
 767 HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber)
 768 {
 769   /* Check the SDRAM controller state */
 770   if(hsdram->State == HAL_SDRAM_STATE_BUSY)
 771   {
 772     return HAL_BUSY;
 773   }
 774
 775   /* Update the SDRAM state */
 776   hsdram->State = HAL_SDRAM_STATE_BUSY;
 777
 778   /* Set the Auto-Refresh number */
 779   FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance ,AutoRefreshNumber);
 780
 781   /* Update the SDRAM state */
 782   hsdram->State = HAL_SDRAM_STATE_READY;
 783
 784   return HAL_OK;
 785 }
 786
 787 /**
 788   * @brief  Returns the SDRAM memory current mode.
 789   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
 790   *                the configuration information for SDRAM module.
 791   * @retval The SDRAM memory mode.
 792   */
 793 uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram)
 794 {
 795   /* Return the SDRAM memory current mode */
 796   return(FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank));
 797 }
 798
 799 /**
 800   * @}
 801   */
 802
 803 /** @defgroup SDRAM_Group4 State functions
 804  *  @brief   Peripheral State functions
 805  *
 806 @verbatim
 807   ==============================================================================
 808                       ##### SDRAM State functions #####
 809   ==============================================================================
 810   [..]
 811     This subsection permits to get in run-time the status of the SDRAM controller
 812     and the data flow.
 813
 814 @endverbatim
 815   * @{
 816   */
 817
 818 /**
 819   * @brief  Returns the SDRAM state.
 820   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
 821   *                the configuration information for SDRAM module.
 822   * @retval HAL state
 823   */
 824 HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram)
 825 {
 826   return hsdram->State;
 827 }
 828
 829 /**
 830   * @}
 831   */
 832
 833 /**
 834   * @}
 835   */
 836 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
 837 #endif /* HAL_SDRAM_MODULE_ENABLED */
 838 /**
 839   * @}
 840   */
 841
 842 /**
 843   * @}
 844   */
 845
 846 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/