tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fsmc.c

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f4xx_ll_fsmc.c
   4   * @author  MCD Application Team
   5   * @version V1.1.0
   6   * @date    19-June-2014
   7   * @brief   FSMC Low Layer HAL module driver.
   8   *
   9   *          This file provides firmware functions to manage the following
  10   *          functionalities of the Flexible Static Memory Controller (FSMC) peripheral memories:
  11   *           + Initialization/de-initialization functions
  12   *           + Peripheral Control functions
  13   *           + Peripheral State functions
  14   *
  15   @verbatim
  16   ==============================================================================
  17                         ##### FSMC peripheral features #####
  18   ==============================================================================
  19     [..] The Flexible static memory controller (FSMC) includes two memory controllers:
  20          (+) The NOR/PSRAM memory controller
  21          (+) The NAND/PC Card memory controller
  22
  23     [..] The FSMC functional block makes the interface with synchronous and asynchronous static
  24          memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are:
  25          (+) to translate AHB transactions into the appropriate external device protocol.
  26          (+) to meet the access time requirements of the external memory devices.
  27
  28     [..] All external memories share the addresses, data and control signals with the controller.
  29          Each external device is accessed by means of a unique Chip Select. The FSMC performs
  30          only one access at a time to an external device.
  31          The main features of the FSMC controller are the following:
  32           (+) Interface with static-memory mapped devices including:
  33              (++) Static random access memory (SRAM).
  34              (++) Read-only memory (ROM).
  35              (++) NOR Flash memory/OneNAND Flash memory.
  36              (++) PSRAM (4 memory banks).
  37              (++) 16-bit PC Card compatible devices.
  38              (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
  39                   data.
  40           (+) Independent Chip Select control for each memory bank.
  41           (+) Independent configuration for each memory bank.
  42
  43   @endverbatim
  44   ******************************************************************************
  45   * @attention
  46   *
  47   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
  48   *
  49   * Redistribution and use in source and binary forms, with or without modification,
  50   * are permitted provided that the following conditions are met:
  51   *   1. Redistributions of source code must retain the above copyright notice,
  52   *      this list of conditions and the following disclaimer.
  53   *   2. Redistributions in binary form must reproduce the above copyright notice,
  54   *      this list of conditions and the following disclaimer in the documentation
  55   *      and/or other materials provided with the distribution.
  56   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  57   *      may be used to endorse or promote products derived from this software
  58   *      without specific prior written permission.
  59   *
  60   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  61   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  62   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  63   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  64   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  65   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  66   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  67   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  68   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  69   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  70   *
  71   ******************************************************************************
  72   */
  73
  74 /* Includes ------------------------------------------------------------------*/
  75 #include "stm32f4xx_hal.h"
  76
  77 /** @addtogroup STM32F4xx_HAL_Driver
  78   * @{
  79   */
  80
  81 /** @defgroup FSMC
  82   * @brief FSMC driver modules
  83   * @{
  84   */
  85
  86 #if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED)
  87
  88 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
  89
  90 /* Private typedef -----------------------------------------------------------*/
  91 /* Private define ------------------------------------------------------------*/
  92 /* Private macro -------------------------------------------------------------*/
  93 /* Private variables ---------------------------------------------------------*/
  94 /* Private function prototypes -----------------------------------------------*/
  95 /* Private functions ---------------------------------------------------------*/
  96
  97 /** @defgroup FSMC_Private_Functions
  98   * @{
  99   */
 100
 101 /** @defgroup FSMC_NORSRAM Controller functions
 102   * @brief    NORSRAM Controller functions
 103   *
 104   @verbatim
 105   ==============================================================================
 106                    ##### How to use NORSRAM device driver #####
 107   ==============================================================================
 108
 109   [..]
 110     This driver contains a set of APIs to interface with the FSMC NORSRAM banks in order
 111     to run the NORSRAM external devices.
 112
 113     (+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit()
 114     (+) FSMC NORSRAM bank control configuration using the function FSMC_NORSRAM_Init()
 115     (+) FSMC NORSRAM bank timing configuration using the function FSMC_NORSRAM_Timing_Init()
 116     (+) FSMC NORSRAM bank extended timing configuration using the function
 117         FSMC_NORSRAM_Extended_Timing_Init()
 118     (+) FSMC NORSRAM bank enable/disable write operation using the functions
 119         FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable()
 120
 121 @endverbatim
 122   * @{
 123   */
 124
 125 /** @defgroup HAL_FSMC_NORSRAM_Group1 Initialization/de-initialization functions
 126   * @brief    Initialization and Configuration functions
 127   *
 128   @verbatim
 129   ==============================================================================
 130               ##### Initialization and de_initialization functions #####
 131   ==============================================================================
 132   [..]
 133     This section provides functions allowing to:
 134     (+) Initialize and configure the FSMC NORSRAM interface
 135     (+) De-initialize the FSMC NORSRAM interface
 136     (+) Configure the FSMC clock and associated GPIOs
 137
 138 @endverbatim
 139   * @{
 140   */
 141
 142 /**
 143   * @brief  Initialize the FSMC_NORSRAM device according to the specified
 144   *         control parameters in the FSMC_NORSRAM_InitTypeDef
 145   * @param  Device: Pointer to NORSRAM device instance
 146   * @param  Init: Pointer to NORSRAM Initialization structure
 147   * @retval HAL status
 148   */
 149 HAL_StatusTypeDef  FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef* Init)
 150 {
 151   uint32_t tmpr = 0;
 152
 153   /* Check the parameters */
 154   assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank));
 155   assert_param(IS_FSMC_MUX(Init->DataAddressMux));
 156   assert_param(IS_FSMC_MEMORY(Init->MemoryType));
 157   assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
 158   assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode));
 159   assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity));
 160   assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode));
 161   assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
 162   assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation));
 163   assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal));
 164   assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode));
 165   assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait));
 166   assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst));
 167
 168   /* Set NORSRAM device control parameters */
 169   tmpr = (uint32_t)(Init->DataAddressMux       |\
 170                     Init->MemoryType           |\
 171                     Init->MemoryDataWidth      |\
 172                     Init->BurstAccessMode      |\
 173                     Init->WaitSignalPolarity   |\
 174                     Init->WrapMode             |\
 175                     Init->WaitSignalActive     |\
 176                     Init->WriteOperation       |\
 177                     Init->WaitSignal           |\
 178                     Init->ExtendedMode         |\
 179                     Init->AsynchronousWait     |\
 180                     Init->WriteBurst
 181                     );
 182
 183   if(Init->MemoryType == FSMC_MEMORY_TYPE_NOR)
 184   {
 185     tmpr |= (uint32_t)FSMC_NORSRAM_FLASH_ACCESS_ENABLE;
 186   }
 187
 188   Device->BTCR[Init->NSBank] = tmpr;
 189
 190   return HAL_OK;
 191 }
 192
 193
 194 /**
 195   * @brief  DeInitialize the FSMC_NORSRAM peripheral
 196   * @param  Device: Pointer to NORSRAM device instance
 197   * @param  ExDevice: Pointer to NORSRAM extended mode device instance
 198   * @param  Bank: NORSRAM bank number
 199   * @retval HAL status
 200   */
 201 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
 202 {
 203   /* Check the parameters */
 204   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
 205   assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
 206
 207   /* Disable the FSMC_NORSRAM device */
 208   __FSMC_NORSRAM_DISABLE(Device, Bank);
 209
 210   /* De-initialize the FSMC_NORSRAM device */
 211   /* FSMC_NORSRAM_BANK1 */
 212   if(Bank == FSMC_NORSRAM_BANK1)
 213   {
 214     Device->BTCR[Bank] = 0x000030DB;
 215   }
 216   /* FSMC_NORSRAM_BANK2, FSMC_NORSRAM_BANK3 or FSMC_NORSRAM_BANK4 */
 217   else
 218   {
 219     Device->BTCR[Bank] = 0x000030D2;
 220   }
 221
 222   Device->BTCR[Bank + 1] = 0x0FFFFFFF;
 223   ExDevice->BWTR[Bank]   = 0x0FFFFFFF;
 224
 225   return HAL_OK;
 226 }
 227
 228
 229 /**
 230   * @brief  Initialize the FSMC_NORSRAM Timing according to the specified
 231   *         parameters in the FSMC_NORSRAM_TimingTypeDef
 232   * @param  Device: Pointer to NORSRAM device instance
 233   * @param  Timing: Pointer to NORSRAM Timing structure
 234   * @param  Bank: NORSRAM bank number
 235   * @retval HAL status
 236   */
 237 HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
 238 {
 239   uint32_t tmpr = 0;
 240
 241   /* Check the parameters */
 242   assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
 243   assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
 244   assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
 245   assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
 246   assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
 247   assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
 248   assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
 249
 250   /* Set FSMC_NORSRAM device timing parameters */
 251   tmpr = (uint32_t)(Timing->AddressSetupTime                  |\
 252                    ((Timing->AddressHoldTime) << 4)          |\
 253                    ((Timing->DataSetupTime) << 8)            |\
 254                    ((Timing->BusTurnAroundDuration) << 16)   |\
 255                    (((Timing->CLKDivision)-1) << 20)         |\
 256                    (((Timing->DataLatency)-2) << 24)         |\
 257                     (Timing->AccessMode)
 258                     );
 259
 260   Device->BTCR[Bank + 1] = tmpr;
 261
 262   return HAL_OK;
 263 }
 264
 265 /**
 266   * @brief  Initialize the FSMC_NORSRAM Extended mode Timing according to the specified
 267   *         parameters in the FSMC_NORSRAM_TimingTypeDef
 268   * @param  Device: Pointer to NORSRAM device instance
 269   * @param  Timing: Pointer to NORSRAM Timing structure
 270   * @param  Bank: NORSRAM bank number
 271   * @retval HAL status
 272   */
 273 HAL_StatusTypeDef  FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
 274 {
 275   /* Set NORSRAM device timing register for write configuration, if extended mode is used */
 276   if(ExtendedMode == FSMC_EXTENDED_MODE_ENABLE)
 277   {
 278     /* Check the parameters */
 279     assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
 280     assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
 281     assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
 282     assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
 283     assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
 284     assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
 285     assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
 286
 287     Device->BWTR[Bank] = (uint32_t)(Timing->AddressSetupTime                 |\
 288                                    ((Timing->AddressHoldTime) << 4)          |\
 289                                    ((Timing->DataSetupTime) << 8)            |\
 290                                    ((Timing->BusTurnAroundDuration) << 16)   |\
 291                                    (((Timing->CLKDivision)-1) << 20)         |\
 292                                    (((Timing->DataLatency)-2) << 24)         |\
 293                                    (Timing->AccessMode));
 294   }
 295   else
 296   {
 297     Device->BWTR[Bank] = 0x0FFFFFFF;
 298   }
 299
 300   return HAL_OK;
 301 }
 302
 303
 304 /**
 305   * @}
 306   */
 307
 308
 309 /** @defgroup HAL_FSMC_NORSRAM_Group3 Control functions
 310  *  @brief   management functions
 311  *
 312 @verbatim
 313   ==============================================================================
 314                       ##### FSMC_NORSRAM Control functions #####
 315   ==============================================================================
 316   [..]
 317     This subsection provides a set of functions allowing to control dynamically
 318     the FSMC NORSRAM interface.
 319
 320 @endverbatim
 321   * @{
 322   */
 323
 324 /**
 325   * @brief  Enables dynamically FSMC_NORSRAM write operation.
 326   * @param  Device: Pointer to NORSRAM device instance
 327   * @param  Bank: NORSRAM bank number
 328   * @retval HAL status
 329   */
 330 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
 331 {
 332   /* Enable write operation */
 333   Device->BTCR[Bank] |= FSMC_WRITE_OPERATION_ENABLE;
 334
 335   return HAL_OK;
 336 }
 337
 338 /**
 339   * @brief  Disables dynamically FSMC_NORSRAM write operation.
 340   * @param  Device: Pointer to NORSRAM device instance
 341   * @param  Bank: NORSRAM bank number
 342   * @retval HAL status
 343   */
 344 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
 345 {
 346   /* Disable write operation */
 347   Device->BTCR[Bank] &= ~FSMC_WRITE_OPERATION_ENABLE;
 348
 349   return HAL_OK;
 350 }
 351
 352 /**
 353   * @}
 354   */
 355
 356 /**
 357   * @}
 358   */
 359
 360 /** @defgroup FSMC_PCCARD Controller functions
 361   * @brief    PCCARD Controller functions
 362   *
 363   @verbatim
 364   ==============================================================================
 365                     ##### How to use NAND device driver #####
 366   ==============================================================================
 367   [..]
 368     This driver contains a set of APIs to interface with the FSMC NAND banks in order
 369     to run the NAND external devices.
 370
 371     (+) FSMC NAND bank reset using the function FSMC_NAND_DeInit()
 372     (+) FSMC NAND bank control configuration using the function FSMC_NAND_Init()
 373     (+) FSMC NAND bank common space timing configuration using the function
 374         FSMC_NAND_CommonSpace_Timing_Init()
 375     (+) FSMC NAND bank attribute space timing configuration using the function
 376         FSMC_NAND_AttributeSpace_Timing_Init()
 377     (+) FSMC NAND bank enable/disable ECC correction feature using the functions
 378         FSMC_NAND_ECC_Enable()/FSMC_NAND_ECC_Disable()
 379     (+) FSMC NAND bank get ECC correction code using the function FSMC_NAND_GetECC()
 380
 381 @endverbatim
 382   * @{
 383   */
 384
 385 /** @defgroup HAL_FSMC_NAND_Group1 Initialization/de-initialization functions
 386  *  @brief    Initialization and Configuration functions
 387  *
 388 @verbatim
 389   ==============================================================================
 390               ##### Initialization and de_initialization functions #####
 391   ==============================================================================
 392   [..]
 393     This section provides functions allowing to:
 394     (+) Initialize and configure the FSMC NAND interface
 395     (+) De-initialize the FSMC NAND interface
 396     (+) Configure the FSMC clock and associated GPIOs
 397
 398 @endverbatim
 399   * @{
 400   */
 401
 402 /**
 403   * @brief  Initializes the FSMC_NAND device according to the specified
 404   *         control parameters in the FSMC_NAND_HandleTypeDef
 405   * @param  Device: Pointer to NAND device instance
 406   * @param  Init: Pointer to NAND Initialization structure
 407   * @retval HAL status
 408   */
 409 HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init)
 410 {
 411   uint32_t tmppcr  = 0;
 412
 413   /* Check the parameters */
 414   assert_param(IS_FSMC_NAND_BANK(Init->NandBank));
 415   assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
 416   assert_param(IS_FSMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
 417   assert_param(IS_FSMC_ECC_STATE(Init->EccComputation));
 418   assert_param(IS_FSMC_ECCPAGE_SIZE(Init->ECCPageSize));
 419   assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
 420   assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
 421
 422   /* Set NAND device control parameters */
 423   tmppcr = (uint32_t)(Init->Waitfeature                |\
 424                       FSMC_PCR_MEMORY_TYPE_NAND         |\
 425                       Init->MemoryDataWidth            |\
 426                       Init->EccComputation             |\
 427                       Init->ECCPageSize                |\
 428                       ((Init->TCLRSetupTime) << 9)     |\
 429                       ((Init->TARSetupTime) << 13)
 430                       );
 431
 432   if(Init->NandBank == FSMC_NAND_BANK2)
 433   {
 434     /* NAND bank 2 registers configuration */
 435     Device->PCR2  = tmppcr;
 436   }
 437   else
 438   {
 439     /* NAND bank 3 registers configuration */
 440     Device->PCR3  = tmppcr;
 441   }
 442
 443   return HAL_OK;
 444
 445 }
 446
 447 /**
 448   * @brief  Initializes the FSMC_NAND Common space Timing according to the specified
 449   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
 450   * @param  Device: Pointer to NAND device instance
 451   * @param  Timing: Pointer to NAND timing structure
 452   * @param  Bank: NAND bank number
 453   * @retval HAL status
 454   */
 455 HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
 456 {
 457   uint32_t tmppmem = 0;
 458
 459   /* Check the parameters */
 460   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
 461   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
 462   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
 463   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
 464
 465   /* Set FSMC_NAND device timing parameters */
 466   tmppmem = (uint32_t)(Timing->SetupTime                  |\
 467                        ((Timing->WaitSetupTime) << 8)     |\
 468                        ((Timing->HoldSetupTime) << 16)    |\
 469                        ((Timing->HiZSetupTime) << 24)
 470                        );
 471
 472   if(Bank == FSMC_NAND_BANK2)
 473   {
 474     /* NAND bank 2 registers configuration */
 475     Device->PMEM2 = tmppmem;
 476   }
 477   else
 478   {
 479     /* NAND bank 3 registers configuration */
 480     Device->PMEM3 = tmppmem;
 481   }
 482
 483   return HAL_OK;
 484 }
 485
 486 /**
 487   * @brief  Initializes the FSMC_NAND Attribute space Timing according to the specified
 488   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
 489   * @param  Device: Pointer to NAND device instance
 490   * @param  Timing: Pointer to NAND timing structure
 491   * @param  Bank: NAND bank number
 492   * @retval HAL status
 493   */
 494 HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
 495 {
 496   uint32_t tmppatt = 0;
 497
 498   /* Check the parameters */
 499   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
 500   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
 501   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
 502   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
 503
 504   /* Set FSMC_NAND device timing parameters */
 505   tmppatt = (uint32_t)(Timing->SetupTime                  |\
 506                        ((Timing->WaitSetupTime) << 8)     |\
 507                        ((Timing->HoldSetupTime) << 16)    |\
 508                        ((Timing->HiZSetupTime) << 24)
 509                        );
 510
 511   if(Bank == FSMC_NAND_BANK2)
 512   {
 513     /* NAND bank 2 registers configuration */
 514     Device->PATT2 = tmppatt;
 515   }
 516   else
 517   {
 518     /* NAND bank 3 registers configuration */
 519     Device->PATT3 = tmppatt;
 520   }
 521
 522   return HAL_OK;
 523 }
 524
 525
 526 /**
 527   * @brief  DeInitializes the FSMC_NAND device
 528   * @param  Device: Pointer to NAND device instance
 529   * @param  Bank: NAND bank number
 530   * @retval HAL status
 531   */
 532 HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank)
 533 {
 534   /* Disable the NAND Bank */
 535   __FSMC_NAND_DISABLE(Device, Bank);
 536
 537   /* De-initialize the NAND Bank */
 538   if(Bank == FSMC_NAND_BANK2)
 539   {
 540     /* Set the FSMC_NAND_BANK2 registers to their reset values */
 541     Device->PCR2  = 0x00000018;
 542     Device->SR2   = 0x00000040;
 543     Device->PMEM2 = 0xFCFCFCFC;
 544     Device->PATT2 = 0xFCFCFCFC;
 545   }
 546   /* FSMC_Bank3_NAND */
 547   else
 548   {
 549     /* Set the FSMC_NAND_BANK3 registers to their reset values */
 550     Device->PCR3  = 0x00000018;
 551     Device->SR3   = 0x00000040;
 552     Device->PMEM3 = 0xFCFCFCFC;
 553     Device->PATT3 = 0xFCFCFCFC;
 554   }
 555
 556   return HAL_OK;
 557 }
 558
 559 /**
 560   * @}
 561   */
 562
 563
 564 /** @defgroup HAL_FSMC_NAND_Group3 Control functions
 565  *  @brief   management functions
 566  *
 567 @verbatim
 568   ==============================================================================
 569                        ##### FSMC_NAND Control functions #####
 570   ==============================================================================
 571   [..]
 572     This subsection provides a set of functions allowing to control dynamically
 573     the FSMC NAND interface.
 574
 575 @endverbatim
 576   * @{
 577   */
 578
 579
 580 /**
 581   * @brief  Enables dynamically FSMC_NAND ECC feature.
 582   * @param  Device: Pointer to NAND device instance
 583   * @param  Bank: NAND bank number
 584   * @retval HAL status
 585   */
 586 HAL_StatusTypeDef  FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
 587 {
 588   /* Enable ECC feature */
 589   if(Bank == FSMC_NAND_BANK2)
 590   {
 591     Device->PCR2 |= FSMC_PCR2_ECCEN;
 592   }
 593   else
 594   {
 595     Device->PCR3 |= FSMC_PCR3_ECCEN;
 596   }
 597
 598   return HAL_OK;
 599 }
 600
 601
 602 /**
 603   * @brief  Disables dynamically FSMC_NAND ECC feature.
 604   * @param  Device: Pointer to NAND device instance
 605   * @param  Bank: NAND bank number
 606   * @retval HAL status
 607   */
 608 HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
 609 {
 610   /* Disable ECC feature */
 611   if(Bank == FSMC_NAND_BANK2)
 612   {
 613     Device->PCR2 &= ~FSMC_PCR2_ECCEN;
 614   }
 615   else
 616   {
 617     Device->PCR3 &= ~FSMC_PCR3_ECCEN;
 618   }
 619
 620   return HAL_OK;
 621 }
 622
 623 /**
 624   * @brief  Disables dynamically FSMC_NAND ECC feature.
 625   * @param  Device: Pointer to NAND device instance
 626   * @param  ECCval: Pointer to ECC value
 627   * @param  Bank: NAND bank number
 628   * @param  Timeout: Timeout wait value
 629   * @retval HAL status
 630   */
 631 HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
 632 {
 633   uint32_t tickstart = 0;
 634
 635   /* Check the parameters */
 636   assert_param(IS_FSMC_NAND_DEVICE(Device));
 637   assert_param(IS_FSMC_NAND_BANK(Bank));
 638
 639   /* Get tick */
 640   tickstart = HAL_GetTick();
 641
 642   /* Wait untill FIFO is empty */
 643   while(__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT))
 644   {
 645     /* Check for the Timeout */
 646     if(Timeout != HAL_MAX_DELAY)
 647     {
 648       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
 649       {
 650         return HAL_TIMEOUT;
 651       }
 652     }
 653   }
 654
 655   if(Bank == FSMC_NAND_BANK2)
 656   {
 657     /* Get the ECCR2 register value */
 658     *ECCval = (uint32_t)Device->ECCR2;
 659   }
 660   else
 661   {
 662     /* Get the ECCR3 register value */
 663     *ECCval = (uint32_t)Device->ECCR3;
 664   }
 665
 666   return HAL_OK;
 667 }
 668
 669 /**
 670   * @}
 671   */
 672
 673 /**
 674   * @}
 675   */
 676
 677 /** @defgroup FSMC_PCCARD Controller functions
 678   * @brief    PCCARD Controller functions
 679   *
 680   @verbatim
 681   ==============================================================================
 682                     ##### How to use PCCARD device driver #####
 683   ==============================================================================
 684   [..]
 685     This driver contains a set of APIs to interface with the FSMC PCCARD bank in order
 686     to run the PCCARD/compact flash external devices.
 687
 688     (+) FSMC PCCARD bank reset using the function FSMC_PCCARD_DeInit()
 689     (+) FSMC PCCARD bank control configuration using the function FSMC_PCCARD_Init()
 690     (+) FSMC PCCARD bank common space timing configuration using the function
 691         FSMC_PCCARD_CommonSpace_Timing_Init()
 692     (+) FSMC PCCARD bank attribute space timing configuration using the function
 693         FSMC_PCCARD_AttributeSpace_Timing_Init()
 694     (+) FSMC PCCARD bank IO space timing configuration using the function
 695         FSMC_PCCARD_IOSpace_Timing_Init()
 696
 697 @endverbatim
 698   * @{
 699   */
 700
 701 /** @defgroup HAL_FSMC_PCCARD_Group1 Initialization/de-initialization functions
 702  *  @brief    Initialization and Configuration functions
 703  *
 704 @verbatim
 705   ==============================================================================
 706               ##### Initialization and de_initialization functions #####
 707   ==============================================================================
 708   [..]
 709     This section provides functions allowing to:
 710     (+) Initialize and configure the FSMC PCCARD interface
 711     (+) De-initialize the FSMC PCCARD interface
 712     (+) Configure the FSMC clock and associated GPIOs
 713
 714 @endverbatim
 715   * @{
 716   */
 717
 718 /**
 719   * @brief  Initializes the FSMC_PCCARD device according to the specified
 720   *         control parameters in the FSMC_PCCARD_HandleTypeDef
 721   * @param  Device: Pointer to PCCARD device instance
 722   * @param  Init: Pointer to PCCARD Initialization structure
 723   * @retval HAL status
 724   */
 725 HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init)
 726 {
 727   /* Check the parameters */
 728   assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
 729   assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
 730   assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
 731
 732   /* Set FSMC_PCCARD device control parameters */
 733   Device->PCR4 = (uint32_t)(Init->Waitfeature               |\
 734                             FSMC_NAND_PCC_MEM_BUS_WIDTH_16   |\
 735                             (Init->TCLRSetupTime << 9)      |\
 736                             (Init->TARSetupTime << 13));
 737
 738   return HAL_OK;
 739
 740 }
 741
 742 /**
 743   * @brief  Initializes the FSMC_PCCARD Common space Timing according to the specified
 744   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
 745   * @param  Device: Pointer to PCCARD device instance
 746   * @param  Timing: Pointer to PCCARD timing structure
 747   * @retval HAL status
 748   */
 749 HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
 750 {
 751   /* Check the parameters */
 752   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
 753   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
 754   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
 755   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
 756
 757   /* Set PCCARD timing parameters */
 758   Device->PMEM4 = (uint32_t)((Timing->SetupTime                 |\
 759                              ((Timing->WaitSetupTime) << 8)     |\
 760                               (Timing->HoldSetupTime) << 16)    |\
 761                               ((Timing->HiZSetupTime) << 24)
 762                              );
 763
 764   return HAL_OK;
 765 }
 766
 767 /**
 768   * @brief  Initializes the FSMC_PCCARD Attribute space Timing according to the specified
 769   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
 770   * @param  Device: Pointer to PCCARD device instance
 771   * @param  Timing: Pointer to PCCARD timing structure
 772   * @retval HAL status
 773   */
 774 HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
 775 {
 776   /* Check the parameters */
 777   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
 778   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
 779   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
 780   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
 781
 782   /* Set PCCARD timing parameters */
 783   Device->PATT4 = (uint32_t)((Timing->SetupTime                 |\
 784                              ((Timing->WaitSetupTime) << 8)     |\
 785                               (Timing->HoldSetupTime) << 16)    |\
 786                               ((Timing->HiZSetupTime) << 24)
 787                              );
 788
 789   return HAL_OK;
 790 }
 791
 792 /**
 793   * @brief  Initializes the FSMC_PCCARD IO space Timing according to the specified
 794   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
 795   * @param  Device: Pointer to PCCARD device instance
 796   * @param  Timing: Pointer to PCCARD timing structure
 797   * @retval HAL status
 798   */
 799 HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
 800 {
 801   /* Check the parameters */
 802   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
 803   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
 804   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
 805   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
 806
 807   /* Set FSMC_PCCARD device timing parameters */
 808   Device->PIO4 = (uint32_t)((Timing->SetupTime                  |\
 809                              ((Timing->WaitSetupTime) << 8)     |\
 810                               (Timing->HoldSetupTime) << 16)    |\
 811                               ((Timing->HiZSetupTime) << 24)
 812                              );
 813
 814   return HAL_OK;
 815 }
 816
 817 /**
 818   * @brief  DeInitializes the FSMC_PCCARD device
 819   * @param  Device: Pointer to PCCARD device instance
 820   * @retval HAL status
 821   */
 822 HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device)
 823 {
 824   /* Disable the FSMC_PCCARD device */
 825   __FSMC_PCCARD_DISABLE(Device);
 826
 827   /* De-initialize the FSMC_PCCARD device */
 828   Device->PCR4    = 0x00000018;
 829   Device->SR4     = 0x00000000;
 830   Device->PMEM4   = 0xFCFCFCFC;
 831   Device->PATT4   = 0xFCFCFCFC;
 832   Device->PIO4    = 0xFCFCFCFC;
 833
 834   return HAL_OK;
 835 }
 836
 837 /**
 838   * @}
 839   */
 840
 841 /**
 842   * @}
 843   */
 844
 845 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
 846
 847 #endif /* HAL_FSMC_MODULE_ENABLED */
 848
 849 /**
 850   * @}
 851   */
 852
 853 /**
 854   * @}
 855   */
 856
 857 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/