tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_sdmmc.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f4xx_ll_sdmmc.h
   4   * @author  MCD Application Team
   5   * @version V1.1.0
   6   * @date    19-June-2014
   7   * @brief   Header file of SDMMC HAL module.
   8   ******************************************************************************
   9   * @attention
  10   *
  11   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
  12   *
  13   * Redistribution and use in source and binary forms, with or without modification,
  14   * are permitted provided that the following conditions are met:
  15   *   1. Redistributions of source code must retain the above copyright notice,
  16   *      this list of conditions and the following disclaimer.
  17   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18   *      this list of conditions and the following disclaimer in the documentation
  19   *      and/or other materials provided with the distribution.
  20   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21   *      may be used to endorse or promote products derived from this software
  22   *      without specific prior written permission.
  23   *
  24   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34   *
  35   ******************************************************************************
  36   */
  37
  38 /* Define to prevent recursive inclusion -------------------------------------*/
  39 #ifndef __STM32F4xx_LL_SDMMC_H
  40 #define __STM32F4xx_LL_SDMMC_H
  41
  42 #ifdef __cplusplus
  43  extern "C" {
  44 #endif
  45
  46 /* Includes ------------------------------------------------------------------*/
  47 #include "stm32f4xx_hal_def.h"
  48
  49 /** @addtogroup STM32F4xx_Driver
  50   * @{
  51   */
  52
  53 /** @addtogroup SDMMC
  54   * @{
  55   */
  56
  57 /* Exported types ------------------------------------------------------------*/
  58
  59 /** @defgroup SDIO_Exported_Types SDIO Exported Types
  60   * @{
  61   */
  62
  63 /**
  64   * @brief  SDMMC Configuration Structure definition
  65   */
  66 typedef struct
  67 {
  68   uint32_t ClockEdge;            /*!< Specifies the clock transition on which the bit capture is made.
  69                                       This parameter can be a value of @ref SDIO_Clock_Edge                 */
  70
  71   uint32_t ClockBypass;          /*!< Specifies whether the SDIO Clock divider bypass is
  72                                       enabled or disabled.
  73                                       This parameter can be a value of @ref SDIO_Clock_Bypass               */
  74
  75   uint32_t ClockPowerSave;       /*!< Specifies whether SDIO Clock output is enabled or
  76                                       disabled when the bus is idle.
  77                                       This parameter can be a value of @ref SDIO_Clock_Power_Save           */
  78
  79   uint32_t BusWide;              /*!< Specifies the SDIO bus width.
  80                                       This parameter can be a value of @ref SDIO_Bus_Wide                   */
  81
  82   uint32_t HardwareFlowControl;  /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
  83                                       This parameter can be a value of @ref SDIO_Hardware_Flow_Control      */
  84
  85   uint32_t ClockDiv;             /*!< Specifies the clock frequency of the SDIO controller.
  86                                       This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
  87
  88 }SDIO_InitTypeDef;
  89
  90
  91 /**
  92   * @brief  SDIO Command Control structure
  93   */
  94 typedef struct
  95 {
  96   uint32_t Argument;            /*!< Specifies the SDIO command argument which is sent
  97                                      to a card as part of a command message. If a command
  98                                      contains an argument, it must be loaded into this register
  99                                      before writing the command to the command register.              */
 100
 101   uint32_t CmdIndex;            /*!< Specifies the SDIO command index. It must be Min_Data = 0 and
 102                                      Max_Data = 64                                                    */
 103
 104   uint32_t Response;            /*!< Specifies the SDIO response type.
 105                                      This parameter can be a value of @ref SDIO_Response_Type         */
 106
 107   uint32_t WaitForInterrupt;    /*!< Specifies whether SDIO wait for interrupt request is
 108                                      enabled or disabled.
 109                                      This parameter can be a value of @ref SDIO_Wait_Interrupt_State  */
 110
 111   uint32_t CPSM;                /*!< Specifies whether SDIO Command path state machine (CPSM)
 112                                      is enabled or disabled.
 113                                      This parameter can be a value of @ref SDIO_CPSM_State            */
 114 }SDIO_CmdInitTypeDef;
 115
 116
 117 /**
 118   * @brief  SDIO Data Control structure
 119   */
 120 typedef struct
 121 {
 122   uint32_t DataTimeOut;         /*!< Specifies the data timeout period in card bus clock periods.  */
 123
 124   uint32_t DataLength;          /*!< Specifies the number of data bytes to be transferred.         */
 125
 126   uint32_t DataBlockSize;       /*!< Specifies the data block size for block transfer.
 127                                      This parameter can be a value of @ref SDIO_Data_Block_Size    */
 128
 129   uint32_t TransferDir;         /*!< Specifies the data transfer direction, whether the transfer
 130                                      is a read or write.
 131                                      This parameter can be a value of @ref SDIO_Transfer_Direction */
 132
 133   uint32_t TransferMode;        /*!< Specifies whether data transfer is in stream or block mode.
 134                                      This parameter can be a value of @ref SDIO_Transfer_Type      */
 135
 136   uint32_t DPSM;                /*!< Specifies whether SDIO Data path state machine (DPSM)
 137                                      is enabled or disabled.
 138                                      This parameter can be a value of @ref SDIO_DPSM_State         */
 139 }SDIO_DataInitTypeDef;
 140
 141 /**
 142   * @}
 143   */
 144
 145 /* Exported constants --------------------------------------------------------*/
 146
 147 /** @defgroup SDIO_Exported_Constants
 148   * @{
 149   */
 150
 151 /** @defgroup SDIO_Clock_Edge
 152   * @{
 153   */
 154 #define SDIO_CLOCK_EDGE_RISING               ((uint32_t)0x00000000)
 155 #define SDIO_CLOCK_EDGE_FALLING              SDIO_CLKCR_NEGEDGE
 156
 157 #define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \
 158                                   ((EDGE) == SDIO_CLOCK_EDGE_FALLING))
 159 /**
 160   * @}
 161   */
 162
 163 /** @defgroup SDIO_Clock_Bypass
 164   * @{
 165   */
 166 #define SDIO_CLOCK_BYPASS_DISABLE             ((uint32_t)0x00000000)
 167 #define SDIO_CLOCK_BYPASS_ENABLE              SDIO_CLKCR_BYPASS
 168
 169 #define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \
 170                                       ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE))
 171 /**
 172   * @}
 173   */
 174
 175 /** @defgroup SDIO_Clock_Power_Save
 176   * @{
 177   */
 178 #define SDIO_CLOCK_POWER_SAVE_DISABLE         ((uint32_t)0x00000000)
 179 #define SDIO_CLOCK_POWER_SAVE_ENABLE          SDIO_CLKCR_PWRSAV
 180
 181 #define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \
 182                                         ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))
 183 /**
 184   * @}
 185   */
 186
 187 /** @defgroup SDIO_Bus_Wide
 188   * @{
 189   */
 190 #define SDIO_BUS_WIDE_1B                      ((uint32_t)0x00000000)
 191 #define SDIO_BUS_WIDE_4B                      SDIO_CLKCR_WIDBUS_0
 192 #define SDIO_BUS_WIDE_8B                      SDIO_CLKCR_WIDBUS_1
 193
 194 #define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \
 195                                 ((WIDE) == SDIO_BUS_WIDE_4B) || \
 196                                 ((WIDE) == SDIO_BUS_WIDE_8B))
 197 /**
 198   * @}
 199   */
 200
 201 /** @defgroup SDIO_Hardware_Flow_Control
 202   * @{
 203   */
 204 #define SDIO_HARDWARE_FLOW_CONTROL_DISABLE    ((uint32_t)0x00000000)
 205 #define SDIO_HARDWARE_FLOW_CONTROL_ENABLE     SDIO_CLKCR_HWFC_EN
 206
 207 #define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \
 208                                                 ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))
 209 /**
 210   * @}
 211   */
 212
 213 /** @defgroup SDIO_Clock_Division
 214   * @{
 215   */
 216 #define IS_SDIO_CLKDIV(DIV)   ((DIV) <= 0xFF)
 217 /**
 218   * @}
 219   */
 220
 221 /** @defgroup SDIO_Command_Index
 222   * @{
 223   */
 224 #define IS_SDIO_CMD_INDEX(INDEX)            ((INDEX) < 0x40)
 225 /**
 226   * @}
 227   */
 228
 229 /** @defgroup SDIO_Response_Type
 230   * @{
 231   */
 232 #define SDIO_RESPONSE_NO                    ((uint32_t)0x00000000)
 233 #define SDIO_RESPONSE_SHORT                 SDIO_CMD_WAITRESP_0
 234 #define SDIO_RESPONSE_LONG                  SDIO_CMD_WAITRESP
 235
 236 #define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO)    || \
 237                                     ((RESPONSE) == SDIO_RESPONSE_SHORT) || \
 238                                     ((RESPONSE) == SDIO_RESPONSE_LONG))
 239 /**
 240   * @}
 241   */
 242
 243 /** @defgroup SDIO_Wait_Interrupt_State
 244   * @{
 245   */
 246 #define SDIO_WAIT_NO                        ((uint32_t)0x00000000)
 247 #define SDIO_WAIT_IT                        SDIO_CMD_WAITINT
 248 #define SDIO_WAIT_PEND                      SDIO_CMD_WAITPEND
 249
 250 #define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \
 251                             ((WAIT) == SDIO_WAIT_IT) || \
 252                             ((WAIT) == SDIO_WAIT_PEND))
 253 /**
 254   * @}
 255   */
 256
 257 /** @defgroup SDIO_CPSM_State
 258   * @{
 259   */
 260 #define SDIO_CPSM_DISABLE                   ((uint32_t)0x00000000)
 261 #define SDIO_CPSM_ENABLE                    SDIO_CMD_CPSMEN
 262
 263 #define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \
 264                             ((CPSM) == SDIO_CPSM_ENABLE))
 265 /**
 266   * @}
 267   */
 268
 269 /** @defgroup SDIO_Response_Registers
 270   * @{
 271   */
 272 #define SDIO_RESP1                          ((uint32_t)0x00000000)
 273 #define SDIO_RESP2                          ((uint32_t)0x00000004)
 274 #define SDIO_RESP3                          ((uint32_t)0x00000008)
 275 #define SDIO_RESP4                          ((uint32_t)0x0000000C)
 276
 277 #define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \
 278                             ((RESP) == SDIO_RESP2) || \
 279                             ((RESP) == SDIO_RESP3) || \
 280                             ((RESP) == SDIO_RESP4))
 281 /**
 282   * @}
 283   */
 284
 285 /** @defgroup SDIO_Data_Length
 286   * @{
 287   */
 288 #define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
 289 /**
 290   * @}
 291   */
 292
 293 /** @defgroup SDIO_Data_Block_Size
 294   * @{
 295   */
 296 #define SDIO_DATABLOCK_SIZE_1B               ((uint32_t)0x00000000)
 297 #define SDIO_DATABLOCK_SIZE_2B               SDIO_DCTRL_DBLOCKSIZE_0
 298 #define SDIO_DATABLOCK_SIZE_4B               SDIO_DCTRL_DBLOCKSIZE_1
 299 #define SDIO_DATABLOCK_SIZE_8B               ((uint32_t)0x00000030)
 300 #define SDIO_DATABLOCK_SIZE_16B              SDIO_DCTRL_DBLOCKSIZE_2
 301 #define SDIO_DATABLOCK_SIZE_32B              ((uint32_t)0x00000050)
 302 #define SDIO_DATABLOCK_SIZE_64B              ((uint32_t)0x00000060)
 303 #define SDIO_DATABLOCK_SIZE_128B             ((uint32_t)0x00000070)
 304 #define SDIO_DATABLOCK_SIZE_256B             SDIO_DCTRL_DBLOCKSIZE_3
 305 #define SDIO_DATABLOCK_SIZE_512B             ((uint32_t)0x00000090)
 306 #define SDIO_DATABLOCK_SIZE_1024B            ((uint32_t)0x000000A0)
 307 #define SDIO_DATABLOCK_SIZE_2048B            ((uint32_t)0x000000B0)
 308 #define SDIO_DATABLOCK_SIZE_4096B            ((uint32_t)0x000000C0)
 309 #define SDIO_DATABLOCK_SIZE_8192B            ((uint32_t)0x000000D0)
 310 #define SDIO_DATABLOCK_SIZE_16384B           ((uint32_t)0x000000E0)
 311
 312 #define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B)    || \
 313                                   ((SIZE) == SDIO_DATABLOCK_SIZE_2B)    || \
 314                                   ((SIZE) == SDIO_DATABLOCK_SIZE_4B)    || \
 315                                   ((SIZE) == SDIO_DATABLOCK_SIZE_8B)    || \
 316                                   ((SIZE) == SDIO_DATABLOCK_SIZE_16B)   || \
 317                                   ((SIZE) == SDIO_DATABLOCK_SIZE_32B)   || \
 318                                   ((SIZE) == SDIO_DATABLOCK_SIZE_64B)   || \
 319                                   ((SIZE) == SDIO_DATABLOCK_SIZE_128B)  || \
 320                                   ((SIZE) == SDIO_DATABLOCK_SIZE_256B)  || \
 321                                   ((SIZE) == SDIO_DATABLOCK_SIZE_512B)  || \
 322                                   ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \
 323                                   ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \
 324                                   ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \
 325                                   ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \
 326                                   ((SIZE) == SDIO_DATABLOCK_SIZE_16384B))
 327 /**
 328   * @}
 329   */
 330
 331 /** @defgroup SDIO_Transfer_Direction
 332   * @{
 333   */
 334 #define SDIO_TRANSFER_DIR_TO_CARD            ((uint32_t)0x00000000)
 335 #define SDIO_TRANSFER_DIR_TO_SDIO            SDIO_DCTRL_DTDIR
 336
 337 #define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \
 338                                    ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))
 339 /**
 340   * @}
 341   */
 342
 343 /** @defgroup SDIO_Transfer_Type
 344   * @{
 345   */
 346 #define SDIO_TRANSFER_MODE_BLOCK             ((uint32_t)0x00000000)
 347 #define SDIO_TRANSFER_MODE_STREAM            SDIO_DCTRL_DTMODE
 348
 349 #define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \
 350                                      ((MODE) == SDIO_TRANSFER_MODE_STREAM))
 351 /**
 352   * @}
 353   */
 354
 355 /** @defgroup SDIO_DPSM_State
 356   * @{
 357   */
 358 #define SDIO_DPSM_DISABLE                    ((uint32_t)0x00000000)
 359 #define SDIO_DPSM_ENABLE                     SDIO_DCTRL_DTEN
 360
 361 #define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\
 362                             ((DPSM) == SDIO_DPSM_ENABLE))
 363 /**
 364   * @}
 365   */
 366
 367 /** @defgroup SDIO_Read_Wait_Mode
 368   * @{
 369   */
 370 #define SDIO_READ_WAIT_MODE_CLK               ((uint32_t)0x00000000)
 371 #define SDIO_READ_WAIT_MODE_DATA2             ((uint32_t)0x00000001)
 372
 373 #define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \
 374                                      ((MODE) == SDIO_READ_WAIT_MODE_DATA2))
 375 /**
 376   * @}
 377   */
 378
 379 /** @defgroup SDIO_Interrupt_sources
 380   * @{
 381   */
 382 #define SDIO_IT_CCRCFAIL                    SDIO_STA_CCRCFAIL
 383 #define SDIO_IT_DCRCFAIL                    SDIO_STA_DCRCFAIL
 384 #define SDIO_IT_CTIMEOUT                    SDIO_STA_CTIMEOUT
 385 #define SDIO_IT_DTIMEOUT                    SDIO_STA_DTIMEOUT
 386 #define SDIO_IT_TXUNDERR                    SDIO_STA_TXUNDERR
 387 #define SDIO_IT_RXOVERR                     SDIO_STA_RXOVERR
 388 #define SDIO_IT_CMDREND                     SDIO_STA_CMDREND
 389 #define SDIO_IT_CMDSENT                     SDIO_STA_CMDSENT
 390 #define SDIO_IT_DATAEND                     SDIO_STA_DATAEND
 391 #define SDIO_IT_STBITERR                    SDIO_STA_STBITERR
 392 #define SDIO_IT_DBCKEND                     SDIO_STA_DBCKEND
 393 #define SDIO_IT_CMDACT                      SDIO_STA_CMDACT
 394 #define SDIO_IT_TXACT                       SDIO_STA_TXACT
 395 #define SDIO_IT_RXACT                       SDIO_STA_RXACT
 396 #define SDIO_IT_TXFIFOHE                    SDIO_STA_TXFIFOHE
 397 #define SDIO_IT_RXFIFOHF                    SDIO_STA_RXFIFOHF
 398 #define SDIO_IT_TXFIFOF                     SDIO_STA_TXFIFOF
 399 #define SDIO_IT_RXFIFOF                     SDIO_STA_RXFIFOF
 400 #define SDIO_IT_TXFIFOE                     SDIO_STA_TXFIFOE
 401 #define SDIO_IT_RXFIFOE                     SDIO_STA_RXFIFOE
 402 #define SDIO_IT_TXDAVL                      SDIO_STA_TXDAVL
 403 #define SDIO_IT_RXDAVL                      SDIO_STA_RXDAVL
 404 #define SDIO_IT_SDIOIT                      SDIO_STA_SDIOIT
 405 #define SDIO_IT_CEATAEND                    SDIO_STA_CEATAEND
 406
 407 #define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
 408 /**
 409   * @}
 410   */
 411
 412 /** @defgroup SDIO_Flags
 413   * @{
 414   */
 415 #define SDIO_FLAG_CCRCFAIL                  SDIO_STA_CCRCFAIL
 416 #define SDIO_FLAG_DCRCFAIL                  SDIO_STA_DCRCFAIL
 417 #define SDIO_FLAG_CTIMEOUT                  SDIO_STA_CTIMEOUT
 418 #define SDIO_FLAG_DTIMEOUT                  SDIO_STA_DTIMEOUT
 419 #define SDIO_FLAG_TXUNDERR                  SDIO_STA_TXUNDERR
 420 #define SDIO_FLAG_RXOVERR                   SDIO_STA_RXOVERR
 421 #define SDIO_FLAG_CMDREND                   SDIO_STA_CMDREND
 422 #define SDIO_FLAG_CMDSENT                   SDIO_STA_CMDSENT
 423 #define SDIO_FLAG_DATAEND                   SDIO_STA_DATAEND
 424 #define SDIO_FLAG_STBITERR                  SDIO_STA_STBITERR
 425 #define SDIO_FLAG_DBCKEND                   SDIO_STA_DBCKEND
 426 #define SDIO_FLAG_CMDACT                    SDIO_STA_CMDACT
 427 #define SDIO_FLAG_TXACT                     SDIO_STA_TXACT
 428 #define SDIO_FLAG_RXACT                     SDIO_STA_RXACT
 429 #define SDIO_FLAG_TXFIFOHE                  SDIO_STA_TXFIFOHE
 430 #define SDIO_FLAG_RXFIFOHF                  SDIO_STA_RXFIFOHF
 431 #define SDIO_FLAG_TXFIFOF                   SDIO_STA_TXFIFOF
 432 #define SDIO_FLAG_RXFIFOF                   SDIO_STA_RXFIFOF
 433 #define SDIO_FLAG_TXFIFOE                   SDIO_STA_TXFIFOE
 434 #define SDIO_FLAG_RXFIFOE                   SDIO_STA_RXFIFOE
 435 #define SDIO_FLAG_TXDAVL                    SDIO_STA_TXDAVL
 436 #define SDIO_FLAG_RXDAVL                    SDIO_STA_RXDAVL
 437 #define SDIO_FLAG_SDIOIT                    SDIO_STA_SDIOIT
 438 #define SDIO_FLAG_CEATAEND                  SDIO_STA_CEATAEND
 439
 440 #define IS_SDIO_FLAG(FLAG) (((FLAG)  == SDIO_FLAG_CCRCFAIL) || \
 441                             ((FLAG)  == SDIO_FLAG_DCRCFAIL) || \
 442                             ((FLAG)  == SDIO_FLAG_CTIMEOUT) || \
 443                             ((FLAG)  == SDIO_FLAG_DTIMEOUT) || \
 444                             ((FLAG)  == SDIO_FLAG_TXUNDERR) || \
 445                             ((FLAG)  == SDIO_FLAG_RXOVERR)  || \
 446                             ((FLAG)  == SDIO_FLAG_CMDREND)  || \
 447                             ((FLAG)  == SDIO_FLAG_CMDSENT)  || \
 448                             ((FLAG)  == SDIO_FLAG_DATAEND)  || \
 449                             ((FLAG)  == SDIO_FLAG_STBITERR) || \
 450                             ((FLAG)  == SDIO_FLAG_DBCKEND)  || \
 451                             ((FLAG)  == SDIO_FLAG_CMDACT)   || \
 452                             ((FLAG)  == SDIO_FLAG_TXACT)    || \
 453                             ((FLAG)  == SDIO_FLAG_RXACT)    || \
 454                             ((FLAG)  == SDIO_FLAG_TXFIFOHE) || \
 455                             ((FLAG)  == SDIO_FLAG_RXFIFOHF) || \
 456                             ((FLAG)  == SDIO_FLAG_TXFIFOF)  || \
 457                             ((FLAG)  == SDIO_FLAG_RXFIFOF)  || \
 458                             ((FLAG)  == SDIO_FLAG_TXFIFOE)  || \
 459                             ((FLAG)  == SDIO_FLAG_RXFIFOE)  || \
 460                             ((FLAG)  == SDIO_FLAG_TXDAVL)   || \
 461                             ((FLAG)  == SDIO_FLAG_RXDAVL)   || \
 462                             ((FLAG)  == SDIO_FLAG_SDIOIT)   || \
 463                             ((FLAG)  == SDIO_FLAG_CEATAEND))
 464
 465 #define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
 466
 467 #define IS_SDIO_GET_IT(IT) (((IT)  == SDIO_IT_CCRCFAIL) || \
 468                             ((IT)  == SDIO_IT_DCRCFAIL) || \
 469                             ((IT)  == SDIO_IT_CTIMEOUT) || \
 470                             ((IT)  == SDIO_IT_DTIMEOUT) || \
 471                             ((IT)  == SDIO_IT_TXUNDERR) || \
 472                             ((IT)  == SDIO_IT_RXOVERR)  || \
 473                             ((IT)  == SDIO_IT_CMDREND)  || \
 474                             ((IT)  == SDIO_IT_CMDSENT)  || \
 475                             ((IT)  == SDIO_IT_DATAEND)  || \
 476                             ((IT)  == SDIO_IT_STBITERR) || \
 477                             ((IT)  == SDIO_IT_DBCKEND)  || \
 478                             ((IT)  == SDIO_IT_CMDACT)   || \
 479                             ((IT)  == SDIO_IT_TXACT)    || \
 480                             ((IT)  == SDIO_IT_RXACT)    || \
 481                             ((IT)  == SDIO_IT_TXFIFOHE) || \
 482                             ((IT)  == SDIO_IT_RXFIFOHF) || \
 483                             ((IT)  == SDIO_IT_TXFIFOF)  || \
 484                             ((IT)  == SDIO_IT_RXFIFOF)  || \
 485                             ((IT)  == SDIO_IT_TXFIFOE)  || \
 486                             ((IT)  == SDIO_IT_RXFIFOE)  || \
 487                             ((IT)  == SDIO_IT_TXDAVL)   || \
 488                             ((IT)  == SDIO_IT_RXDAVL)   || \
 489                             ((IT)  == SDIO_IT_SDIOIT)   || \
 490                             ((IT)  == SDIO_IT_CEATAEND))
 491
 492 #define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
 493
 494 /**
 495   * @}
 496   */
 497
 498
 499 /** @defgroup SDIO_Instance_definition
 500   * @{
 501   */
 502 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
 503
 504 /**
 505   * @}
 506   */
 507
 508 /* Exported macro ------------------------------------------------------------*/
 509 /* ------------ SDIO registers bit address in the alias region -------------- */
 510 #define SDIO_OFFSET               (SDIO_BASE - PERIPH_BASE)
 511
 512 /* --- CLKCR Register ---*/
 513 /* Alias word address of CLKEN bit */
 514 #define CLKCR_OFFSET              (SDIO_OFFSET + 0x04)
 515 #define CLKEN_BitNumber           0x08
 516 #define CLKCR_CLKEN_BB            (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))
 517
 518 /* --- CMD Register ---*/
 519 /* Alias word address of SDIOSUSPEND bit */
 520 #define CMD_OFFSET                (SDIO_OFFSET + 0x0C)
 521 #define SDIOSUSPEND_BitNumber     0x0B
 522 #define CMD_SDIOSUSPEND_BB        (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))
 523
 524 /* Alias word address of ENCMDCOMPL bit */
 525 #define ENCMDCOMPL_BitNumber      0x0C
 526 #define CMD_ENCMDCOMPL_BB         (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))
 527
 528 /* Alias word address of NIEN bit */
 529 #define NIEN_BitNumber            0x0D
 530 #define CMD_NIEN_BB               (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))
 531
 532 /* Alias word address of ATACMD bit */
 533 #define ATACMD_BitNumber          0x0E
 534 #define CMD_ATACMD_BB             (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
 535
 536 /* --- DCTRL Register ---*/
 537 /* Alias word address of DMAEN bit */
 538 #define DCTRL_OFFSET              (SDIO_OFFSET + 0x2C)
 539 #define DMAEN_BitNumber           0x03
 540 #define DCTRL_DMAEN_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
 541
 542 /* Alias word address of RWSTART bit */
 543 #define RWSTART_BitNumber         0x08
 544 #define DCTRL_RWSTART_BB          (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))
 545
 546 /* Alias word address of RWSTOP bit */
 547 #define RWSTOP_BitNumber          0x09
 548 #define DCTRL_RWSTOP_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
 549
 550 /* Alias word address of RWMOD bit */
 551 #define RWMOD_BitNumber           0x0A
 552 #define DCTRL_RWMOD_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))
 553
 554 /* Alias word address of SDIOEN bit */
 555 #define SDIOEN_BitNumber          0x0B
 556 #define DCTRL_SDIOEN_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))
 557
 558 /* ---------------------- SDIO registers bit mask --------------------------- */
 559 /* --- CLKCR Register ---*/
 560 /* CLKCR register clear mask */
 561 #define CLKCR_CLEAR_MASK         ((uint32_t)(SDIO_CLKCR_CLKDIV  | SDIO_CLKCR_PWRSAV |\
 562                                              SDIO_CLKCR_BYPASS  | SDIO_CLKCR_WIDBUS |\
 563                                              SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN))
 564
 565 /* --- PWRCTRL Register ---*/
 566 /* --- DCTRL Register ---*/
 567 /* SDIO DCTRL Clear Mask */
 568 #define DCTRL_CLEAR_MASK         ((uint32_t)(SDIO_DCTRL_DTEN    | SDIO_DCTRL_DTDIR |\
 569                                              SDIO_DCTRL_DTMODE  | SDIO_DCTRL_DBLOCKSIZE))
 570
 571 /* --- CMD Register ---*/
 572 /* CMD Register clear mask */
 573 #define CMD_CLEAR_MASK           ((uint32_t)(SDIO_CMD_CMDINDEX | SDIO_CMD_WAITRESP |\
 574                                              SDIO_CMD_WAITINT  | SDIO_CMD_WAITPEND |\
 575                                              SDIO_CMD_CPSMEN   | SDIO_CMD_SDIOSUSPEND))
 576
 577 /* SDIO RESP Registers Address */
 578 #define SDIO_RESP_ADDR           ((uint32_t)(SDIO_BASE + 0x14))
 579
 580 /* SDIO Intialization Frequency (400KHz max) */
 581 #define SDIO_INIT_CLK_DIV ((uint8_t)0x76)
 582
 583 /* SDIO Data Transfer Frequency (25MHz max) */
 584 #define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x0)
 585
 586 /** @defgroup SDIO_Interrupt_Clock
 587  *  @brief macros to handle interrupts and specific clock configurations
 588  * @{
 589  */
 590
 591 /**
 592   * @brief  Enable the SDIO device.
 593   * @param  None
 594   * @retval None
 595   */
 596 #define __SDIO_ENABLE()   (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE)
 597
 598 /**
 599   * @brief  Disable the SDIO device.
 600   * @param  None
 601   * @retval None
 602   */
 603 #define __SDIO_DISABLE()   (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE)
 604
 605 /**
 606   * @brief  Enable the SDIO DMA transfer.
 607   * @param  None
 608   * @retval None
 609   */
 610 #define __SDIO_DMA_ENABLE()   (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE)
 611
 612 /**
 613   * @brief  Disable the SDIO DMA transfer.
 614   * @param  None
 615   * @retval None
 616   */
 617 #define __SDIO_DMA_DISABLE()   (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE)
 618
 619 /**
 620   * @brief  Enable the SDIO device interrupt.
 621   * @param  __INSTANCE__ : Pointer to SDIO register base
 622   * @param  __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled.
 623   *         This parameter can be one or a combination of the following values:
 624   *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
 625   *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
 626   *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
 627   *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
 628   *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
 629   *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
 630   *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
 631   *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
 632   *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
 633   *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
 634   *                                   bus mode interrupt
 635   *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
 636   *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
 637   *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
 638   *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
 639   *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
 640   *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
 641   *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
 642   *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
 643   *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
 644   *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
 645   *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
 646   *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
 647   *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
 648   *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
 649   * @retval None
 650   */
 651 #define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->MASK |= (__INTERRUPT__))
 652
 653 /**
 654   * @brief  Disable the SDIO device interrupt.
 655   * @param  __INSTANCE__ : Pointer to SDIO register base
 656   * @param  __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled.
 657   *          This parameter can be one or a combination of the following values:
 658   *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
 659   *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
 660   *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
 661   *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
 662   *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
 663   *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
 664   *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
 665   *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
 666   *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
 667   *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
 668   *                                   bus mode interrupt
 669   *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
 670   *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
 671   *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
 672   *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
 673   *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
 674   *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
 675   *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
 676   *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
 677   *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
 678   *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
 679   *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
 680   *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
 681   *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
 682   *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
 683   * @retval None
 684   */
 685 #define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
 686
 687 /**
 688   * @brief  Checks whether the specified SDIO flag is set or not.
 689   * @param  __INSTANCE__ : Pointer to SDIO register base
 690   * @param  __FLAG__: specifies the flag to check.
 691   *          This parameter can be one of the following values:
 692   *            @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
 693   *            @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
 694   *            @arg SDIO_FLAG_CTIMEOUT: Command response timeout
 695   *            @arg SDIO_FLAG_DTIMEOUT: Data timeout
 696   *            @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
 697   *            @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
 698   *            @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
 699   *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
 700   *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
 701   *            @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
 702   *            @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
 703   *            @arg SDIO_FLAG_CMDACT:   Command transfer in progress
 704   *            @arg SDIO_FLAG_TXACT:    Data transmit in progress
 705   *            @arg SDIO_FLAG_RXACT:    Data receive in progress
 706   *            @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
 707   *            @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
 708   *            @arg SDIO_FLAG_TXFIFOF:  Transmit FIFO full
 709   *            @arg SDIO_FLAG_RXFIFOF:  Receive FIFO full
 710   *            @arg SDIO_FLAG_TXFIFOE:  Transmit FIFO empty
 711   *            @arg SDIO_FLAG_RXFIFOE:  Receive FIFO empty
 712   *            @arg SDIO_FLAG_TXDAVL:   Data available in transmit FIFO
 713   *            @arg SDIO_FLAG_RXDAVL:   Data available in receive FIFO
 714   *            @arg SDIO_FLAG_SDIOIT:   SD I/O interrupt received
 715   *            @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
 716   * @retval The new state of SDIO_FLAG (SET or RESET).
 717   */
 718 #define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__)   (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
 719
 720
 721 /**
 722   * @brief  Clears the SDIO pending flags.
 723   * @param  __INSTANCE__ : Pointer to SDIO register base
 724   * @param  __FLAG__: specifies the flag to clear.
 725   *          This parameter can be one or a combination of the following values:
 726   *            @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
 727   *            @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
 728   *            @arg SDIO_FLAG_CTIMEOUT: Command response timeout
 729   *            @arg SDIO_FLAG_DTIMEOUT: Data timeout
 730   *            @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
 731   *            @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
 732   *            @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
 733   *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
 734   *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
 735   *            @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
 736   *            @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
 737   *            @arg SDIO_FLAG_SDIOIT:   SD I/O interrupt received
 738   *            @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
 739   * @retval None
 740   */
 741 #define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__)   ((__INSTANCE__)->ICR = (__FLAG__))
 742
 743 /**
 744   * @brief  Checks whether the specified SDIO interrupt has occurred or not.
 745   * @param  __INSTANCE__ : Pointer to SDIO register base
 746   * @param  __INTERRUPT__: specifies the SDIO interrupt source to check.
 747   *          This parameter can be one of the following values:
 748   *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
 749   *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
 750   *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
 751   *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
 752   *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
 753   *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
 754   *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
 755   *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
 756   *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
 757   *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
 758   *                                   bus mode interrupt
 759   *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
 760   *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
 761   *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
 762   *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
 763   *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
 764   *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
 765   *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
 766   *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
 767   *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
 768   *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
 769   *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
 770   *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
 771   *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
 772   *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
 773   * @retval The new state of SDIO_IT (SET or RESET).
 774   */
 775 #define __SDIO_GET_IT  (__INSTANCE__, __INTERRUPT__)   (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
 776
 777 /**
 778   * @brief  Clears the SDIO's interrupt pending bits.
 779   * @param  __INSTANCE__ : Pointer to SDIO register base
 780   * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
 781   *          This parameter can be one or a combination of the following values:
 782   *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
 783   *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
 784   *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
 785   *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
 786   *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
 787   *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
 788   *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
 789   *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
 790   *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIO_DCOUNT, is zero) interrupt
 791   *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
 792   *                                   bus mode interrupt
 793   *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
 794   *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
 795   * @retval None
 796   */
 797 #define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__)   ((__INSTANCE__)->ICR = (__INTERRUPT__))
 798
 799 /**
 800   * @brief  Enable Start the SD I/O Read Wait operation.
 801   * @param  None
 802   * @retval None
 803   */
 804 #define __SDIO_START_READWAIT_ENABLE()   (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE)
 805
 806 /**
 807   * @brief  Disable Start the SD I/O Read Wait operations.
 808   * @param  None
 809   * @retval None
 810   */
 811 #define __SDIO_START_READWAIT_DISABLE()   (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE)
 812
 813 /**
 814   * @brief  Enable Start the SD I/O Read Wait operation.
 815   * @param  None
 816   * @retval None
 817   */
 818 #define __SDIO_STOP_READWAIT_ENABLE()   (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE)
 819
 820 /**
 821   * @brief  Disable Stop the SD I/O Read Wait operations.
 822   * @param  None
 823   * @retval None
 824   */
 825 #define __SDIO_STOP_READWAIT_DISABLE()   (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE)
 826
 827 /**
 828   * @brief  Enable the SD I/O Mode Operation.
 829   * @param  None
 830   * @retval None
 831   */
 832 #define __SDIO_OPERATION_ENABLE()   (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE)
 833
 834 /**
 835   * @brief  Disable the SD I/O Mode Operation.
 836   * @param  None
 837   * @retval None
 838   */
 839 #define __SDIO_OPERATION_DISABLE()   (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE)
 840
 841 /**
 842   * @brief  Enable the SD I/O Suspend command sending.
 843   * @param  None
 844   * @retval None
 845   */
 846 #define __SDIO_SUSPEND_CMD_ENABLE()   (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE)
 847
 848 /**
 849   * @brief  Disable the SD I/O Suspend command sending.
 850   * @param  None
 851   * @retval None
 852   */
 853 #define __SDIO_SUSPEND_CMD_DISABLE()   (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE)
 854
 855 /**
 856   * @brief  Enable the command completion signal.
 857   * @param  None
 858   * @retval None
 859   */
 860 #define __SDIO_CEATA_CMD_COMPLETION_ENABLE()   (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE)
 861
 862 /**
 863   * @brief  Disable the command completion signal.
 864   * @param  None
 865   * @retval None
 866   */
 867 #define __SDIO_CEATA_CMD_COMPLETION_DISABLE()   (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = DISABLE)
 868
 869 /**
 870   * @brief  Enable the CE-ATA interrupt.
 871   * @param  None
 872   * @retval None
 873   */
 874 #define __SDIO_CEATA_ENABLE_IT()   (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)0)
 875
 876 /**
 877   * @brief  Disable the CE-ATA interrupt.
 878   * @param  None
 879   * @retval None
 880   */
 881 #define __SDIO_CEATA_DISABLE_IT()   (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)1)
 882
 883 /**
 884   * @brief  Enable send CE-ATA command (CMD61).
 885   * @param  None
 886   * @retval None
 887   */
 888 #define __SDIO_CEATA_SENDCMD_ENABLE()   (*(__IO uint32_t *) CMD_ATACMD_BB = ENABLE)
 889
 890 /**
 891   * @brief  Disable send CE-ATA command (CMD61).
 892   * @param  None
 893   * @retval None
 894   */
 895 #define __SDIO_CEATA_SENDCMD_DISABLE()   (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE)
 896
 897 /**
 898   * @}
 899   */
 900
 901 /**
 902   * @}
 903   */
 904
 905 /* Exported functions --------------------------------------------------------*/
 906 /** @addtogroup SDIO_Exported_Functions
 907   * @{
 908   */
 909
 910 /* Initialization/de-initialization functions  **********************************/
 911 /** @addtogroup HAL_SDIO_Group1
 912   * @{
 913   */
 914 HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init);
 915 /**
 916   * @}
 917   */
 918
 919 /* I/O operation functions  *****************************************************/
 920 /** @addtogroup HAL_SDIO_Group2
 921   * @{
 922   */
 923 /* Blocking mode: Polling */
 924 uint32_t          SDIO_ReadFIFO(SDIO_TypeDef *SDIOx);
 925 HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData);
 926 /**
 927   * @}
 928   */
 929
 930 /* Peripheral Control functions  ************************************************/
 931 /** @addtogroup HAL_SDIO_Group3
 932   * @{
 933   */
 934 HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx);
 935 HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx);
 936 uint32_t          SDIO_GetPowerState(SDIO_TypeDef *SDIOx);
 937
 938 /* Command path state machine (CPSM) management functions */
 939 HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
 940 uint8_t           SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx);
 941 uint32_t          SDIO_GetResponse(uint32_t SDIO_RESP);
 942
 943 /* Data path state machine (DPSM) management functions */
 944 HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* SDIO_DataInitStruct);
 945 uint32_t          SDIO_GetDataCounter(SDIO_TypeDef *SDIOx);
 946 uint32_t          SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx);
 947
 948 /* SDIO IO Cards mode management functions */
 949 HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
 950
 951 /**
 952   * @}
 953   */
 954
 955 /**
 956   * @}
 957   */
 958
 959 /**
 960   * @}
 961   */
 962
 963 /**
 964   * @}
 965   */
 966
 967 #ifdef __cplusplus
 968 }
 969 #endif
 970
 971 #endif /* __STM32F4xx_LL_SDMMC_H */
 972
 973 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/