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[tmk_keyboard.git] / tool / mbed / mbed-sdk / libraries / mbed / targets / cmsis / TARGET_STM / TARGET_STM32L0 / TARGET_NUCLEO_L053R8 / TOOLCHAIN_GCC_ARM / startup_stm32l053xx.s
1 /**
2 ******************************************************************************
3 * @file startup_stm32l053xx.s
4 * @author MCD Application Team
5 * @version V1.2.0
6 * @date 06-February-2015
7 * @brief STM32L053xx Devices vector table for Atollic TrueSTUDIO toolchain.
8 * This module performs:
9 * - Set the initial SP
10 * - Set the initial PC == Reset_Handler,
11 * - Set the vector table entries with the exceptions ISR address
12 * - Branches to main in the C library (which eventually
13 * calls main()).
14 * After Reset the Cortex-M0+ processor is in Thread mode,
15 * priority is Privileged, and the Stack is set to Main.
16 ******************************************************************************
17 *
18 * Redistribution and use in source and binary forms, with or without modification,
19 * are permitted provided that the following conditions are met:
20 * 1. Redistributions of source code must retain the above copyright notice,
21 * this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright notice,
23 * this list of conditions and the following disclaimer in the documentation
24 * and/or other materials provided with the distribution.
25 * 3. Neither the name of STMicroelectronics nor the names of its contributors
26 * may be used to endorse or promote products derived from this software
27 * without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
30 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
32 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
33 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
35 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
36 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
37 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 ******************************************************************************
41 */
42
43 .syntax unified
44 .cpu cortex-m0plus
45 .fpu softvfp
46 .thumb
47
48 .global g_pfnVectors
49 .global Default_Handler
50
51 /* start address for the initialization values of the .data section.
52 defined in linker script */
53 .word _sidata
54 /* start address for the .data section. defined in linker script */
55 .word _sdata
56 /* end address for the .data section. defined in linker script */
57 .word _edata
58 /* start address for the .bss section. defined in linker script */
59 .word _sbss
60 /* end address for the .bss section. defined in linker script */
61 .word _ebss
62
63 .section .text.Reset_Handler
64 .weak Reset_Handler
65 .type Reset_Handler, %function
66 Reset_Handler:
67 ldr r0, =_estack
68 mov sp, r0 /* set stack pointer */
69
70 /* Copy the data segment initializers from flash to SRAM */
71 movs r1, #0
72 b LoopCopyDataInit
73
74 CopyDataInit:
75 ldr r3, =_sidata
76 ldr r3, [r3, r1]
77 str r3, [r0, r1]
78 adds r1, r1, #4
79
80 LoopCopyDataInit:
81 ldr r0, =_sdata
82 ldr r3, =_edata
83 adds r2, r0, r1
84 cmp r2, r3
85 bcc CopyDataInit
86 ldr r2, =_sbss
87 b LoopFillZerobss
88 /* Zero fill the bss segment. */
89 FillZerobss:
90 movs r3, #0
91 str r3, [r2]
92 adds r2, r2, #4
93
94
95 LoopFillZerobss:
96 ldr r3, = _ebss
97 cmp r2, r3
98 bcc FillZerobss
99
100 /* Call the clock system intitialization function.*/
101 bl SystemInit
102 /* Call static constructors */
103 //bl __libc_init_array
104 /* Call the application's entry point.*/
105 //bl main
106 bl _start
107
108 LoopForever:
109 b LoopForever
110
111
112 .size Reset_Handler, .-Reset_Handler
113
114 /**
115 * @brief This is the code that gets called when the processor receives an
116 * unexpected interrupt. This simply enters an infinite loop, preserving
117 * the system state for examination by a debugger.
118 *
119 * @param None
120 * @retval : None
121 */
122 .section .text.Default_Handler,"ax",%progbits
123 Default_Handler:
124 Infinite_Loop:
125 b Infinite_Loop
126 .size Default_Handler, .-Default_Handler
127 /******************************************************************************
128 *
129 * The minimal vector table for a Cortex M0. Note that the proper constructs
130 * must be placed on this to ensure that it ends up at physical address
131 * 0x0000.0000.
132 *
133 ******************************************************************************/
134 .section .isr_vector,"a",%progbits
135 .type g_pfnVectors, %object
136 .size g_pfnVectors, .-g_pfnVectors
137
138
139 g_pfnVectors:
140 .word _estack
141 .word Reset_Handler
142 .word NMI_Handler
143 .word HardFault_Handler
144 .word 0
145 .word 0
146 .word 0
147 .word 0
148 .word 0
149 .word 0
150 .word 0
151 .word SVC_Handler
152 .word DebugMon_Handler
153 .word 0
154 .word PendSV_Handler
155 .word SysTick_Handler
156 .word WWDG_IRQHandler /* Window WatchDog */
157 .word PVD_IRQHandler /* PVD through EXTI Line detection */
158 .word RTC_IRQHandler /* RTC through the EXTI line */
159 .word FLASH_IRQHandler /* FLASH */
160 .word RCC_CRS_IRQHandler /* RCC and CRS */
161 .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */
162 .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */
163 .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */
164 .word TSC_IRQHandler /* TSC */
165 .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
166 .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */
167 .word DMA1_Channel4_5_6_7_IRQHandler /* DMA1 Channel 4, Channel 5, Channel 6 and Channel 7*/
168 .word ADC1_COMP_IRQHandler /* ADC1, COMP1 and COMP2 */
169 .word LPTIM1_IRQHandler /* LPTIM1 */
170 .word 0 /* Reserved */
171 .word TIM2_IRQHandler /* TIM2 */
172 .word 0 /* Reserved */
173 .word TIM6_DAC_IRQHandler /* TIM6 and DAC */
174 .word 0 /* Reserved */
175 .word 0 /* Reserved */
176 .word TIM21_IRQHandler /* TIM21 */
177 .word 0 /* Reserved */
178 .word TIM22_IRQHandler /* TIM22 */
179 .word I2C1_IRQHandler /* I2C1 */
180 .word I2C2_IRQHandler /* I2C2 */
181 .word SPI1_IRQHandler /* SPI1 */
182 .word SPI2_IRQHandler /* SPI2 */
183 .word USART1_IRQHandler /* USART1 */
184 .word USART2_IRQHandler /* USART2 */
185 .word RNG_LPUART1_IRQHandler /* RNG and LPUART1 */
186 .word LCD_IRQHandler /* LCD */
187 .word USB_IRQHandler /* USB */
188
189 /*******************************************************************************
190 *
191 * Provide weak aliases for each Exception handler to the Default_Handler.
192 * As they are weak aliases, any function with the same name will override
193 * this definition.
194 *
195 *******************************************************************************/
196
197 .weak NMI_Handler
198 .thumb_set NMI_Handler,Default_Handler
199
200 .weak HardFault_Handler
201 .thumb_set HardFault_Handler,Default_Handler
202
203 .weak SVC_Handler
204 .thumb_set SVC_Handler,Default_Handler
205
206 .weak DebugMon_Handler
207 .thumb_set DebugMon_Handler,Default_Handler
208
209 .weak PendSV_Handler
210 .thumb_set PendSV_Handler,Default_Handler
211
212 .weak SysTick_Handler
213 .thumb_set SysTick_Handler,Default_Handler
214
215 .weak WWDG_IRQHandler
216 .thumb_set WWDG_IRQHandler,Default_Handler
217
218 .weak PVD_IRQHandler
219 .thumb_set PVD_IRQHandler,Default_Handler
220
221 .weak RTC_IRQHandler
222 .thumb_set RTC_IRQHandler,Default_Handler
223
224 .weak FLASH_IRQHandler
225 .thumb_set FLASH_IRQHandler,Default_Handler
226
227 .weak RCC_CRS_IRQHandler
228 .thumb_set RCC_CRS_IRQHandler,Default_Handler
229
230 .weak EXTI0_1_IRQHandler
231 .thumb_set EXTI0_1_IRQHandler,Default_Handler
232
233 .weak EXTI2_3_IRQHandler
234 .thumb_set EXTI2_3_IRQHandler,Default_Handler
235
236 .weak EXTI4_15_IRQHandler
237 .thumb_set EXTI4_15_IRQHandler,Default_Handler
238
239 .weak TSC_IRQHandler
240 .thumb_set TSC_IRQHandler,Default_Handler
241
242 .weak DMA1_Channel1_IRQHandler
243 .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
244
245 .weak DMA1_Channel2_3_IRQHandler
246 .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
247
248 .weak DMA1_Channel4_5_6_7_IRQHandler
249 .thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler
250
251 .weak ADC1_COMP_IRQHandler
252 .thumb_set ADC1_COMP_IRQHandler,Default_Handler
253
254 .weak LPTIM1_IRQHandler
255 .thumb_set LPTIM1_IRQHandler,Default_Handler
256
257 .weak TIM2_IRQHandler
258 .thumb_set TIM2_IRQHandler,Default_Handler
259
260 .weak TIM6_DAC_IRQHandler
261 .thumb_set TIM6_DAC_IRQHandler,Default_Handler
262
263 .weak TIM21_IRQHandler
264 .thumb_set TIM21_IRQHandler,Default_Handler
265
266 .weak TIM22_IRQHandler
267 .thumb_set TIM22_IRQHandler,Default_Handler
268
269 .weak I2C1_IRQHandler
270 .thumb_set I2C1_IRQHandler,Default_Handler
271
272 .weak I2C2_IRQHandler
273 .thumb_set I2C2_IRQHandler,Default_Handler
274
275 .weak SPI1_IRQHandler
276 .thumb_set SPI1_IRQHandler,Default_Handler
277
278 .weak SPI2_IRQHandler
279 .thumb_set SPI2_IRQHandler,Default_Handler
280
281 .weak USART1_IRQHandler
282 .thumb_set USART1_IRQHandler,Default_Handler
283
284 .weak USART2_IRQHandler
285 .thumb_set USART2_IRQHandler,Default_Handler
286
287 .weak RNG_LPUART1_IRQHandler
288 .thumb_set RNG_LPUART1_IRQHandler,Default_Handler
289
290 .weak LCD_IRQHandler
291 .thumb_set LCD_IRQHandler,Default_Handler
292
293 .weak USB_IRQHandler
294 .thumb_set USB_IRQHandler,Default_Handler
295
296
297
298 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
299
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