2 ******************************************************************************
3 * @file startup_stm32l053xx.s
4 * @author MCD Application Team
6 * @date 06-February-2015
7 * @brief STM32L053xx Devices vector table for Atollic TrueSTUDIO toolchain.
8 * This module performs:
10 * - Set the initial PC == Reset_Handler,
11 * - Set the vector table entries with the exceptions ISR address
12 * - Branches to main in the C library (which eventually
14 * After Reset the Cortex-M0+ processor is in Thread mode,
15 * priority is Privileged, and the Stack is set to Main.
16 ******************************************************************************
18 * Redistribution and use in source and binary forms, with or without modification,
19 * are permitted provided that the following conditions are met:
20 * 1. Redistributions of source code must retain the above copyright notice,
21 * this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright notice,
23 * this list of conditions and the following disclaimer in the documentation
24 * and/or other materials provided with the distribution.
25 * 3. Neither the name of STMicroelectronics nor the names of its contributors
26 * may be used to endorse or promote products derived from this software
27 * without specific prior written permission.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
30 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
32 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
33 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
35 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
36 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
37 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 ******************************************************************************
49 .global Default_Handler
51 /* start address for the initialization values of the .data section.
52 defined in linker script */
54 /* start address for the .data section. defined in linker script */
56 /* end address for the .data section. defined in linker script */
58 /* start address for the .bss section. defined in linker script */
60 /* end address for the .bss section. defined in linker script */
63 .section .text.Reset_Handler
65 .type Reset_Handler, %function
68 mov sp, r0 /* set stack pointer */
70 /* Copy the data segment initializers from flash to SRAM */
88 /* Zero fill the bss segment. */
100 /* Call the clock system intitialization function.*/
102 /* Call static constructors */
103 //bl __libc_init_array
104 /* Call the application's entry point.*/
112 .size Reset_Handler, .-Reset_Handler
115 * @brief This is the code that gets called when the processor receives an
116 * unexpected interrupt. This simply enters an infinite loop, preserving
117 * the system state for examination by a debugger.
122 .section .text.Default_Handler,"ax",%progbits
126 .size Default_Handler, .-Default_Handler
127 /******************************************************************************
129 * The minimal vector table for a Cortex M0. Note that the proper constructs
130 * must be placed on this to ensure that it ends up at physical address
133 ******************************************************************************/
134 .section .isr_vector,"a",%progbits
135 .type g_pfnVectors, %object
136 .size g_pfnVectors, .-g_pfnVectors
143 .word HardFault_Handler
152 .word DebugMon_Handler
155 .word SysTick_Handler
156 .word WWDG_IRQHandler /* Window WatchDog */
157 .word PVD_IRQHandler /* PVD through EXTI Line detection */
158 .word RTC_IRQHandler /* RTC through the EXTI line */
159 .word FLASH_IRQHandler /* FLASH */
160 .word RCC_CRS_IRQHandler /* RCC and CRS */
161 .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */
162 .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */
163 .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */
164 .word TSC_IRQHandler /* TSC */
165 .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
166 .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */
167 .word DMA1_Channel4_5_6_7_IRQHandler /* DMA1 Channel 4, Channel 5, Channel 6 and Channel 7*/
168 .word ADC1_COMP_IRQHandler /* ADC1, COMP1 and COMP2 */
169 .word LPTIM1_IRQHandler /* LPTIM1 */
170 .word 0 /* Reserved */
171 .word TIM2_IRQHandler /* TIM2 */
172 .word 0 /* Reserved */
173 .word TIM6_DAC_IRQHandler /* TIM6 and DAC */
174 .word 0 /* Reserved */
175 .word 0 /* Reserved */
176 .word TIM21_IRQHandler /* TIM21 */
177 .word 0 /* Reserved */
178 .word TIM22_IRQHandler /* TIM22 */
179 .word I2C1_IRQHandler /* I2C1 */
180 .word I2C2_IRQHandler /* I2C2 */
181 .word SPI1_IRQHandler /* SPI1 */
182 .word SPI2_IRQHandler /* SPI2 */
183 .word USART1_IRQHandler /* USART1 */
184 .word USART2_IRQHandler /* USART2 */
185 .word RNG_LPUART1_IRQHandler /* RNG and LPUART1 */
186 .word LCD_IRQHandler /* LCD */
187 .word USB_IRQHandler /* USB */
189 /*******************************************************************************
191 * Provide weak aliases for each Exception handler to the Default_Handler.
192 * As they are weak aliases, any function with the same name will override
195 *******************************************************************************/
198 .thumb_set NMI_Handler,Default_Handler
200 .weak HardFault_Handler
201 .thumb_set HardFault_Handler,Default_Handler
204 .thumb_set SVC_Handler,Default_Handler
206 .weak DebugMon_Handler
207 .thumb_set DebugMon_Handler,Default_Handler
210 .thumb_set PendSV_Handler,Default_Handler
212 .weak SysTick_Handler
213 .thumb_set SysTick_Handler,Default_Handler
215 .weak WWDG_IRQHandler
216 .thumb_set WWDG_IRQHandler,Default_Handler
219 .thumb_set PVD_IRQHandler,Default_Handler
222 .thumb_set RTC_IRQHandler,Default_Handler
224 .weak FLASH_IRQHandler
225 .thumb_set FLASH_IRQHandler,Default_Handler
227 .weak RCC_CRS_IRQHandler
228 .thumb_set RCC_CRS_IRQHandler,Default_Handler
230 .weak EXTI0_1_IRQHandler
231 .thumb_set EXTI0_1_IRQHandler,Default_Handler
233 .weak EXTI2_3_IRQHandler
234 .thumb_set EXTI2_3_IRQHandler,Default_Handler
236 .weak EXTI4_15_IRQHandler
237 .thumb_set EXTI4_15_IRQHandler,Default_Handler
240 .thumb_set TSC_IRQHandler,Default_Handler
242 .weak DMA1_Channel1_IRQHandler
243 .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
245 .weak DMA1_Channel2_3_IRQHandler
246 .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
248 .weak DMA1_Channel4_5_6_7_IRQHandler
249 .thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler
251 .weak ADC1_COMP_IRQHandler
252 .thumb_set ADC1_COMP_IRQHandler,Default_Handler
254 .weak LPTIM1_IRQHandler
255 .thumb_set LPTIM1_IRQHandler,Default_Handler
257 .weak TIM2_IRQHandler
258 .thumb_set TIM2_IRQHandler,Default_Handler
260 .weak TIM6_DAC_IRQHandler
261 .thumb_set TIM6_DAC_IRQHandler,Default_Handler
263 .weak TIM21_IRQHandler
264 .thumb_set TIM21_IRQHandler,Default_Handler
266 .weak TIM22_IRQHandler
267 .thumb_set TIM22_IRQHandler,Default_Handler
269 .weak I2C1_IRQHandler
270 .thumb_set I2C1_IRQHandler,Default_Handler
272 .weak I2C2_IRQHandler
273 .thumb_set I2C2_IRQHandler,Default_Handler
275 .weak SPI1_IRQHandler
276 .thumb_set SPI1_IRQHandler,Default_Handler
278 .weak SPI2_IRQHandler
279 .thumb_set SPI2_IRQHandler,Default_Handler
281 .weak USART1_IRQHandler
282 .thumb_set USART1_IRQHandler,Default_Handler
284 .weak USART2_IRQHandler
285 .thumb_set USART2_IRQHandler,Default_Handler
287 .weak RNG_LPUART1_IRQHandler
288 .thumb_set RNG_LPUART1_IRQHandler,Default_Handler
291 .thumb_set LCD_IRQHandler,Default_Handler
294 .thumb_set USB_IRQHandler,Default_Handler
298 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/