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[tmk_keyboard.git] / tool / mbed / mbed-sdk / libraries / mbed / targets / cmsis / TARGET_STM / TARGET_STM32L0 / TARGET_NUCLEO_L073RZ / stm32l073xx.h
1 /**
2 ******************************************************************************
3 * @file stm32l073xx.h
4 * @author MCD Application Team
5 * @version V1.2.0
6 * @date 06-February-2015
7 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
8 * This file contains all the peripheral register's definitions, bits
9 * definitions and memory mapping for stm32l073xx devices.
10 *
11 * This file contains:
12 * - Data structures and the address mapping for all peripherals
13 * - Peripheral's registers declarations and bits definition
14 * - Macros to access peripheral's registers hardware
15 *
16 ******************************************************************************
17 * @attention
18 *
19 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
20 *
21 * Redistribution and use in source and binary forms, with or without modification,
22 * are permitted provided that the following conditions are met:
23 * 1. Redistributions of source code must retain the above copyright notice,
24 * this list of conditions and the following disclaimer.
25 * 2. Redistributions in binary form must reproduce the above copyright notice,
26 * this list of conditions and the following disclaimer in the documentation
27 * and/or other materials provided with the distribution.
28 * 3. Neither the name of STMicroelectronics nor the names of its contributors
29 * may be used to endorse or promote products derived from this software
30 * without specific prior written permission.
31 *
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
33 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
38 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
39 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
40 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 *
43 ******************************************************************************
44 */
45
46 /** @addtogroup CMSIS
47 * @{
48 */
49
50 /** @addtogroup stm32l073xx
51 * @{
52 */
53
54 #ifndef __STM32L073xx_H
55 #define __STM32L073xx_H
56
57 #ifdef __cplusplus
58 extern "C" {
59 #endif
60
61
62 /** @addtogroup Configuration_section_for_CMSIS
63 * @{
64 */
65 /**
66 * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals
67 */
68 #define __CM0PLUS_REV 0 /*!< Core Revision r0p0 */
69 #define __MPU_PRESENT 1 /*!< STM32L0xx provides an MPU */
70 #define __VTOR_PRESENT 1 /*!< Vector Table Register supported */
71 #define __NVIC_PRIO_BITS 2 /*!< STM32L0xx uses 2 Bits for the Priority Levels */
72 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
73
74 /**
75 * @}
76 */
77
78 /** @addtogroup Peripheral_interrupt_number_definition
79 * @{
80 */
81
82 /**
83 * @brief stm32l073xx Interrupt Number Definition, according to the selected device
84 * in @ref Library_configuration_section
85 */
86
87 /*!< Interrupt Number Definition */
88 typedef enum
89 {
90 /****** Cortex-M0 Processor Exceptions Numbers ******************************************************/
91 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
92 HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */
93 SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */
94 PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */
95 SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */
96
97 /****** STM32L-0 specific Interrupt Numbers *********************************************************/
98 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
99 PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */
100 RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
101 FLASH_IRQn = 3, /*!< FLASH Interrupt */
102 RCC_CRS_IRQn = 4, /*!< RCC and CRS Interrupts */
103 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
104 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
105 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
106 TSC_IRQn = 8, /*!< TSC Interrupt */
107 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
108 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
109 DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
110 ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */
111 LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */
112 USART4_5_IRQn = 14, /*!< USART4 and USART5 Interrupt */
113 TIM2_IRQn = 15, /*!< TIM2 Interrupt */
114 TIM3_IRQn = 16, /*!< TIM3 Interrupt */
115 TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */
116 TIM7_IRQn = 18, /*!< TIM7 Interrupt */
117 TIM21_IRQn = 20, /*!< TIM21 Interrupt */
118 I2C3_IRQn = 21, /*!< I2C3 Interrupt */
119 TIM22_IRQn = 22, /*!< TIM22 Interrupt */
120 I2C1_IRQn = 23, /*!< I2C1 Interrupt */
121 I2C2_IRQn = 24, /*!< I2C2 Interrupt */
122 SPI1_IRQn = 25, /*!< SPI1 Interrupt */
123 SPI2_IRQn = 26, /*!< SPI2 Interrupt */
124 USART1_IRQn = 27, /*!< USART1 Interrupt */
125 USART2_IRQn = 28, /*!< USART2 Interrupt */
126 RNG_LPUART1_IRQn = 29, /*!< RNG and LPUART1 Interrupts */
127 LCD_IRQn = 30, /*!< LCD Interrupt */
128 USB_IRQn = 31, /*!< USB global Interrupt */
129 } IRQn_Type;
130
131 /**
132 * @}
133 */
134
135 #include "core_cm0plus.h"
136 #include "system_stm32l0xx.h"
137 #include <stdint.h>
138
139 /** @addtogroup Peripheral_registers_structures
140 * @{
141 */
142
143 /**
144 * @brief Analog to Digital Converter
145 */
146
147 typedef struct
148 {
149 __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
150 __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
151 __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
152 __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
153 __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
154 __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
155 uint32_t RESERVED1; /*!< Reserved, 0x18 */
156 uint32_t RESERVED2; /*!< Reserved, 0x1C */
157 __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
158 uint32_t RESERVED3; /*!< Reserved, 0x24 */
159 __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
160 uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
161 __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
162 uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */
163 __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */
164 } ADC_TypeDef;
165
166 typedef struct
167 {
168 __IO uint32_t CCR;
169 } ADC_Common_TypeDef;
170
171
172 /**
173 * @brief Comparator
174 */
175
176 typedef struct
177 {
178 __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */
179 } COMP_TypeDef;
180
181
182 /**
183 * @brief CRC calculation unit
184 */
185
186 typedef struct
187 {
188 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
189 __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
190 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
191 uint32_t RESERVED2; /*!< Reserved, 0x0C */
192 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
193 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
194 } CRC_TypeDef;
195
196 /**
197 * @brief Clock Recovery System
198 */
199
200 typedef struct
201 {
202 __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
203 __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
204 __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
205 __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
206 } CRS_TypeDef;
207
208 /**
209 * @brief Digital to Analog Converter
210 */
211
212 typedef struct
213 {
214 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
215 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
216 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
217 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
218 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
219 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
220 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
221 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
222 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
223 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
224 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
225 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
226 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
227 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
228 } DAC_TypeDef;
229
230 /**
231 * @brief Debug MCU
232 */
233
234 typedef struct
235 {
236 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
237 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
238 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
239 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
240 }DBGMCU_TypeDef;
241
242 /**
243 * @brief DMA Controller
244 */
245
246 typedef struct
247 {
248 __IO uint32_t CCR; /*!< DMA channel x configuration register */
249 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
250 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
251 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
252 } DMA_Channel_TypeDef;
253
254 typedef struct
255 {
256 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
257 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
258 } DMA_TypeDef;
259
260 typedef struct
261 {
262 __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */
263 } DMA_Request_TypeDef;
264
265 /**
266 * @brief External Interrupt/Event Controller
267 */
268
269 typedef struct
270 {
271 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
272 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
273 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
274 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
275 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
276 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
277 }EXTI_TypeDef;
278
279 /**
280 * @brief FLASH Registers
281 */
282 typedef struct
283 {
284 __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */
285 __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */
286 __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */
287 __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */
288 __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */
289 __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */
290 __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */
291 __IO uint32_t OPTR; /*!< Option byte register, Address offset: 0x1c */
292 __IO uint32_t WRPR; /*!< Write protection register, Address offset: 0x20 */
293 __IO uint32_t RESERVED1[23]; /*!< Reserved1, Address offset: 0x24 */
294 __IO uint32_t WRPR2; /*!< Write protection register 2, Address offset: 0x80 */
295 } FLASH_TypeDef;
296
297
298 /**
299 * @brief Option Bytes Registers
300 */
301 typedef struct
302 {
303 __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */
304 __IO uint32_t USER; /*!< user register, Address offset: 0x04 */
305 __IO uint32_t WRP01; /*!< write protection Bytes 0 and 1 Address offset: 0x08 */
306 __IO uint32_t WRP23; /*!< write protection Bytes 2 and 3 Address offset: 0x0C */
307 __IO uint32_t WRP45; /*!< write protection Bytes 4 and 5 Address offset: 0x10 */
308 } OB_TypeDef;
309
310
311 /**
312 * @brief General Purpose IO
313 */
314
315 typedef struct
316 {
317 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
318 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
319 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
320 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
321 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
322 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
323 __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */
324 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
325 __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */
326 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
327 }GPIO_TypeDef;
328
329 /**
330 * @brief LPTIMIMER
331 */
332 typedef struct
333 {
334 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
335 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
336 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
337 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
338 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
339 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
340 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
341 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
342 } LPTIM_TypeDef;
343
344 /**
345 * @brief SysTem Configuration
346 */
347
348 typedef struct
349 {
350 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
351 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x04 */
352 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
353 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
354 __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x20 */
355 } SYSCFG_TypeDef;
356
357
358
359 /**
360 * @brief Inter-integrated Circuit Interface
361 */
362
363 typedef struct
364 {
365 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
366 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
367 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
368 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
369 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
370 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
371 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
372 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
373 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
374 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
375 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
376 }I2C_TypeDef;
377
378
379 /**
380 * @brief Independent WATCHDOG
381 */
382 typedef struct
383 {
384 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
385 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
386 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
387 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
388 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
389 } IWDG_TypeDef;
390
391 /**
392 * @brief LCD
393 */
394
395 typedef struct
396 {
397 __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */
398 __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */
399 __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */
400 __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */
401 uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */
402 __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */
403 } LCD_TypeDef;
404
405 /**
406 * @brief MIFARE Firewall
407 */
408
409 typedef struct
410 {
411 __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */
412 __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */
413 __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */
414 __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */
415 __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */
416 __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */
417 __IO uint32_t LSSA ; /*!< Library Segment Start Address register, Address offset: 0x18 */
418 __IO uint32_t LSL ; /*!< Library Segment Length register, Address offset: 0x1C */
419 __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */
420
421 } FW_TypeDef;
422
423 /**
424 * @brief Power Control
425 */
426
427 typedef struct
428 {
429 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
430 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
431 } PWR_TypeDef;
432
433 /**
434 * @brief Reset and Clock Control
435 */
436 typedef struct
437 {
438 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
439 __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */
440 __IO uint32_t CRRCR; /*!< RCC Clock recovery RC register, Address offset: 0x08 */
441 __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x0C */
442 __IO uint32_t CIER; /*!< RCC Clock interrupt enable register, Address offset: 0x10 */
443 __IO uint32_t CIFR; /*!< RCC Clock interrupt flag register, Address offset: 0x14 */
444 __IO uint32_t CICR; /*!< RCC Clock interrupt clear register, Address offset: 0x18 */
445 __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x1C */
446 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x20 */
447 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
448 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x28 */
449 __IO uint32_t IOPENR; /*!< RCC Clock IO port enable register, Address offset: 0x2C */
450 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x30 */
451 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral enable register, Address offset: 0x34 */
452 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral enable register, Address offset: 0x38 */
453 __IO uint32_t IOPSMENR; /*!< RCC IO port clock enable in sleep mode register, Address offset: 0x3C */
454 __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clock enable in sleep mode register, Address offset: 0x40 */
455 __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clock enable in sleep mode register, Address offset: 0x44 */
456 __IO uint32_t APB1SMENR; /*!< RCC APB1 peripheral clock enable in sleep mode register, Address offset: 0x48 */
457 __IO uint32_t CCIPR; /*!< RCC clock configuration register, Address offset: 0x4C */
458 __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x50 */
459 } RCC_TypeDef;
460
461 /**
462 * @brief Random numbers generator
463 */
464 typedef struct
465 {
466 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
467 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
468 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
469 } RNG_TypeDef;
470
471 /**
472 * @brief Real-Time Clock
473 */
474 typedef struct
475 {
476 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
477 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
478 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
479 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
480 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
481 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
482 uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
483 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
484 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
485 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
486 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
487 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
488 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
489 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
490 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
491 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
492 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
493 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
494 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
495 __IO uint32_t OR; /*!< RTC option register, Address offset 0x4C */
496 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
497 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
498 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
499 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
500 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
501 } RTC_TypeDef;
502
503
504 /**
505 * @brief Serial Peripheral Interface
506 */
507
508 typedef struct
509 {
510 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
511 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
512 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
513 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
514 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
515 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
516 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
517 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
518 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
519 } SPI_TypeDef;
520
521 /**
522 * @brief TIM
523 */
524 typedef struct
525 {
526 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
527 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
528 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
529 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
530 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
531 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
532 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
533 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
534 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
535 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
536 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
537 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
538 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
539 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
540 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
541 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
542 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
543 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
544 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
545 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
546 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
547 } TIM_TypeDef;
548
549 /**
550 * @brief Touch Sensing Controller (TSC)
551 */
552 typedef struct
553 {
554 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
555 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
556 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
557 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
558 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
559 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
560 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
561 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
562 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
563 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
564 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
565 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
566 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
567 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
568 } TSC_TypeDef;
569
570 /**
571 * @brief Universal Synchronous Asynchronous Receiver Transmitter
572 */
573
574 typedef struct
575 {
576 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
577 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
578 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
579 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
580 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
581 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
582 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
583 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
584 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
585 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
586 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
587 } USART_TypeDef;
588
589 /**
590 * @brief Window WATCHDOG
591 */
592 typedef struct
593 {
594 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
595 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
596 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
597 } WWDG_TypeDef;
598
599 /**
600 * @brief Universal Serial Bus Full Speed Device
601 */
602
603 typedef struct
604 {
605 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
606 __IO uint16_t RESERVED0; /*!< Reserved */
607 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
608 __IO uint16_t RESERVED1; /*!< Reserved */
609 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
610 __IO uint16_t RESERVED2; /*!< Reserved */
611 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
612 __IO uint16_t RESERVED3; /*!< Reserved */
613 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
614 __IO uint16_t RESERVED4; /*!< Reserved */
615 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
616 __IO uint16_t RESERVED5; /*!< Reserved */
617 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
618 __IO uint16_t RESERVED6; /*!< Reserved */
619 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
620 __IO uint16_t RESERVED7[17]; /*!< Reserved */
621 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
622 __IO uint16_t RESERVED8; /*!< Reserved */
623 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
624 __IO uint16_t RESERVED9; /*!< Reserved */
625 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
626 __IO uint16_t RESERVEDA; /*!< Reserved */
627 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
628 __IO uint16_t RESERVEDB; /*!< Reserved */
629 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
630 __IO uint16_t RESERVEDC; /*!< Reserved */
631 __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
632 __IO uint16_t RESERVEDD; /*!< Reserved */
633 __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */
634 __IO uint16_t RESERVEDE; /*!< Reserved */
635 } USB_TypeDef;
636
637 /**
638 * @}
639 */
640
641 /** @addtogroup Peripheral_memory_map
642 * @{
643 */
644
645 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
646 #define FLASH_BANK2_BASE ((uint32_t)0x08018000) /*!< FLASH BANK2 base address in the alias region */
647 #define FLASH_BANK1_END ((uint32_t)0x08017FFF) /*!< Program end FLASH BANK1 address */
648 #define FLASH_BANK2_END ((uint32_t)0x0802FFFF) /*!< Program end FLASH BANK2 address */
649 #define DATA_EEPROM_BASE ((uint32_t)0x08080000) /*!< DATA_EEPROM base address in the alias region */
650 #define DATA_EEPROM_BANK2_BASE ((uint32_t)0x08080C00) /*!< DATA EEPROM BANK2 base address in the alias region */
651 #define DATA_EEPROM_BANK1_END ((uint32_t)0x08080BFF) /*!< Program end DATA EEPROM BANK1 address */
652 #define DATA_EEPROM_BANK2_END ((uint32_t)0x080817FF) /*!< Program end DATA EEPROM BANK2 address */
653 #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
654 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
655
656 /*!< Peripheral memory map */
657 #define APBPERIPH_BASE PERIPH_BASE
658 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
659 #define IOPPERIPH_BASE (PERIPH_BASE + 0x10000000)
660
661 #define TIM2_BASE (APBPERIPH_BASE + 0x00000000)
662 #define TIM3_BASE (APBPERIPH_BASE + 0x00000400)
663 #define TIM6_BASE (APBPERIPH_BASE + 0x00001000)
664 #define TIM7_BASE (APBPERIPH_BASE + 0x00001400)
665 #define LCD_BASE (APBPERIPH_BASE + 0x00002400)
666 #define RTC_BASE (APBPERIPH_BASE + 0x00002800)
667 #define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)
668 #define IWDG_BASE (APBPERIPH_BASE + 0x00003000)
669 #define SPI2_BASE (APBPERIPH_BASE + 0x00003800)
670 #define USART2_BASE (APBPERIPH_BASE + 0x00004400)
671 #define LPUART1_BASE (APBPERIPH_BASE + 0x00004800)
672 #define USART4_BASE (APBPERIPH_BASE + 0x00004C00)
673 #define USART5_BASE (APBPERIPH_BASE + 0x00005000)
674 #define I2C1_BASE (APBPERIPH_BASE + 0x00005400)
675 #define I2C2_BASE (APBPERIPH_BASE + 0x00005800)
676 #define CRS_BASE (APBPERIPH_BASE + 0x00006C00)
677 #define PWR_BASE (APBPERIPH_BASE + 0x00007000)
678 #define DAC_BASE (APBPERIPH_BASE + 0x00007400)
679 #define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00)
680 #define I2C3_BASE (APBPERIPH_BASE + 0x00007800)
681
682 #define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
683 #define COMP1_BASE (APBPERIPH_BASE + 0x00010018)
684 #define COMP2_BASE (APBPERIPH_BASE + 0x0001001C)
685 #define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
686 #define TIM21_BASE (APBPERIPH_BASE + 0x00010800)
687 #define TIM22_BASE (APBPERIPH_BASE + 0x00011400)
688 #define FW_BASE (APBPERIPH_BASE + 0x00011C00)
689 #define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
690 #define ADC_BASE (APBPERIPH_BASE + 0x00012708)
691 #define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
692 #define USART1_BASE (APBPERIPH_BASE + 0x00013800)
693 #define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)
694
695 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)
696 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
697 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
698 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
699 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
700 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
701 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006C)
702 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080)
703 #define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8)
704
705
706 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
707 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
708 #define OB_BASE ((uint32_t)0x1FF80000) /*!< FLASH Option Bytes base address */
709 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
710 #define TSC_BASE (AHBPERIPH_BASE + 0x00004000)
711 #define RNG_BASE (AHBPERIPH_BASE + 0x00005000)
712
713 #define GPIOA_BASE (IOPPERIPH_BASE + 0x00000000)
714 #define GPIOB_BASE (IOPPERIPH_BASE + 0x00000400)
715 #define GPIOC_BASE (IOPPERIPH_BASE + 0x00000800)
716 #define GPIOD_BASE (IOPPERIPH_BASE + 0x00000C00)
717 #define GPIOE_BASE (IOPPERIPH_BASE + 0x00001000)
718 #define GPIOH_BASE (IOPPERIPH_BASE + 0x00001C00)
719
720 /**
721 * @}
722 */
723
724 /** @addtogroup Peripheral_declaration
725 * @{
726 */
727
728 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
729 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
730 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
731 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
732 #define RTC ((RTC_TypeDef *) RTC_BASE)
733 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
734 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
735 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
736 #define USART2 ((USART_TypeDef *) USART2_BASE)
737 #define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
738 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
739 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
740 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
741 #define CRS ((CRS_TypeDef *) CRS_BASE)
742 #define PWR ((PWR_TypeDef *) PWR_BASE)
743 #define DAC ((DAC_TypeDef *) DAC_BASE)
744 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
745 #define LCD ((LCD_TypeDef *) LCD_BASE)
746 #define USART4 ((USART_TypeDef *) USART4_BASE)
747 #define USART5 ((USART_TypeDef *) USART5_BASE)
748
749 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
750 #define COMP1 ((COMP_TypeDef *) COMP1_BASE)
751 #define COMP2 ((COMP_TypeDef *) COMP2_BASE)
752 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
753 #define TIM21 ((TIM_TypeDef *) TIM21_BASE)
754 #define TIM22 ((TIM_TypeDef *) TIM22_BASE)
755 #define FW ((FW_TypeDef *) FW_BASE)
756 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
757 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
758 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
759 #define USART1 ((USART_TypeDef *) USART1_BASE)
760 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
761
762 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
763 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
764 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
765 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
766 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
767 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
768 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
769 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
770 #define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
771
772
773 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
774 #define OB ((OB_TypeDef *) OB_BASE)
775 #define RCC ((RCC_TypeDef *) RCC_BASE)
776 #define CRC ((CRC_TypeDef *) CRC_BASE)
777 #define TSC ((TSC_TypeDef *) TSC_BASE)
778 #define RNG ((RNG_TypeDef *) RNG_BASE)
779
780 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
781 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
782 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
783 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
784 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
785 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
786
787 #define USB ((USB_TypeDef *) USB_BASE)
788
789 /**
790 * @}
791 */
792
793 /** @addtogroup Exported_constants
794 * @{
795 */
796
797 /** @addtogroup Peripheral_Registers_Bits_Definition
798 * @{
799 */
800
801 /******************************************************************************/
802 /* Peripheral Registers Bits Definition */
803 /******************************************************************************/
804 /******************************************************************************/
805 /* */
806 /* Analog to Digital Converter (ADC) */
807 /* */
808 /******************************************************************************/
809 /******************** Bits definition for ADC_ISR register ******************/
810 #define ADC_ISR_EOCAL ((uint32_t)0x00000800) /*!< End of calibration flag */
811 #define ADC_ISR_AWD ((uint32_t)0x00000080) /*!< Analog watchdog flag */
812 #define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< Overrun flag */
813 #define ADC_ISR_EOSEQ ((uint32_t)0x00000008) /*!< End of Sequence flag */
814 #define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< End of Conversion */
815 #define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< End of sampling flag */
816 #define ADC_ISR_ADRDY ((uint32_t)0x00000001) /*!< ADC Ready */
817
818 /* Old EOSEQ bit definition, maintained for legacy purpose */
819 #define ADC_ISR_EOS ADC_ISR_EOSEQ
820
821 /******************** Bits definition for ADC_IER register ******************/
822 #define ADC_IER_EOCALIE ((uint32_t)0x00000800) /*!< Enf Of Calibration interrupt enable */
823 #define ADC_IER_AWDIE ((uint32_t)0x00000080) /*!< Analog Watchdog interrupt enable */
824 #define ADC_IER_OVRIE ((uint32_t)0x00000010) /*!< Overrun interrupt enable */
825 #define ADC_IER_EOSEQIE ((uint32_t)0x00000008) /*!< End of Sequence of conversion interrupt enable */
826 #define ADC_IER_EOCIE ((uint32_t)0x00000004) /*!< End of Conversion interrupt enable */
827 #define ADC_IER_EOSMPIE ((uint32_t)0x00000002) /*!< End of sampling interrupt enable */
828 #define ADC_IER_ADRDYIE ((uint32_t)0x00000001) /*!< ADC Ready interrupt enable */
829
830 /* Old EOSEQIE bit definition, maintained for legacy purpose */
831 #define ADC_IER_EOSIE ADC_IER_EOSEQIE
832
833 /******************** Bits definition for ADC_CR register *******************/
834 #define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC calibration */
835 #define ADC_CR_ADVREGEN ((uint32_t)0x10000000) /*!< ADC Voltage Regulator Enable */
836 #define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC stop of conversion command */
837 #define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC start of conversion */
838 #define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC disable command */
839 #define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC enable control */ /*#### TBV */
840
841 /******************* Bits definition for ADC_CFGR1 register *****************/
842 #define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
843 #define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000) /*!< Bit 0 */
844 #define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000) /*!< Bit 1 */
845 #define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000) /*!< Bit 2 */
846 #define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000) /*!< Bit 3 */
847 #define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000) /*!< Bit 4 */
848 #define ADC_CFGR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
849 #define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000) /*!< Enable the watchdog on a single channel or on all channels */
850 #define ADC_CFGR1_DISCEN ((uint32_t)0x00010000) /*!< Discontinuous mode on regular channels */
851 #define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000) /*!< ADC auto power off */
852 #define ADC_CFGR1_WAIT ((uint32_t)0x00004000) /*!< ADC wait conversion mode */
853 #define ADC_CFGR1_CONT ((uint32_t)0x00002000) /*!< Continuous Conversion */
854 #define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000) /*!< Overrun mode */
855 #define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
856 #define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400) /*!< Bit 0 */
857 #define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800) /*!< Bit 1 */
858 #define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
859 #define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040) /*!< Bit 0 */
860 #define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080) /*!< Bit 1 */
861 #define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100) /*!< Bit 2 */
862 #define ADC_CFGR1_ALIGN ((uint32_t)0x00000020) /*!< Data Alignment */
863 #define ADC_CFGR1_RES ((uint32_t)0x00000018) /*!< RES[1:0] bits (Resolution) */
864 #define ADC_CFGR1_RES_0 ((uint32_t)0x00000008) /*!< Bit 0 */
865 #define ADC_CFGR1_RES_1 ((uint32_t)0x00000010) /*!< Bit 1 */
866 #define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004) /*!< Sequence scan direction */
867 #define ADC_CFGR1_DMACFG ((uint32_t)0x00000002) /*!< Direct memory access configuration */
868 #define ADC_CFGR1_DMAEN ((uint32_t)0x00000001) /*!< Direct memory access enable */
869
870 /* Old WAIT bit definition, maintained for legacy purpose */
871 #define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
872
873 /******************* Bits definition for ADC_CFGR2 register *****************/
874 #define ADC_CFGR2_TOVS ((uint32_t)0x80000200) /*!< Triggered Oversampling */
875 #define ADC_CFGR2_OVSS ((uint32_t)0x000001E0) /*!< OVSS [3:0] bits (Oversampling shift) */
876 #define ADC_CFGR2_OVSS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
877 #define ADC_CFGR2_OVSS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
878 #define ADC_CFGR2_OVSS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
879 #define ADC_CFGR2_OVSS_3 ((uint32_t)0x00000100) /*!< Bit 3 */
880 #define ADC_CFGR2_OVSR ((uint32_t)0x0000001C) /*!< OVSR [2:0] bits (Oversampling ratio) */
881 #define ADC_CFGR2_OVSR_0 ((uint32_t)0x00000004) /*!< Bit 0 */
882 #define ADC_CFGR2_OVSR_1 ((uint32_t)0x00000008) /*!< Bit 1 */
883 #define ADC_CFGR2_OVSR_2 ((uint32_t)0x00000010) /*!< Bit 2 */
884 #define ADC_CFGR2_OVSE ((uint32_t)0x00000001) /*!< Oversampler Enable */
885 #define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000) /*!< CKMODE [1:0] bits (ADC clock mode) */
886 #define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000) /*!< Bit 0 */
887 #define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000) /*!< Bit 1 */
888
889
890 /****************** Bit definition for ADC_SMPR register ********************/
891 #define ADC_SMPR_SMP ((uint32_t)0x00000007) /*!< SMPR[2:0] bits (Sampling time selection) */
892 #define ADC_SMPR_SMP_0 ((uint32_t)0x00000001) /*!< Bit 0 */
893 #define ADC_SMPR_SMP_1 ((uint32_t)0x00000002) /*!< Bit 1 */
894 #define ADC_SMPR_SMP_2 ((uint32_t)0x00000004) /*!< Bit 2 */
895
896 /* Bit names aliases maintained for legacy */
897 #define ADC_SMPR_SMPR ADC_SMPR_SMP
898 #define ADC_SMPR_SMPR_0 ADC_SMPR_SMP_0
899 #define ADC_SMPR_SMPR_1 ADC_SMPR_SMP_1
900 #define ADC_SMPR_SMPR_2 ADC_SMPR_SMP_2
901
902 /******************* Bit definition for ADC_TR register ********************/
903 #define ADC_TR_HT ((uint32_t)0x0FFF0000) /*!< Analog watchdog high threshold */
904 #define ADC_TR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
905
906 /****************** Bit definition for ADC_CHSELR register ******************/
907 #define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000) /*!< Channel 18 selection */
908 #define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000) /*!< Channel 17 selection */
909 #define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000) /*!< Channel 16 selection */
910 #define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000) /*!< Channel 15 selection */
911 #define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000) /*!< Channel 14 selection */
912 #define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000) /*!< Channel 13 selection */
913 #define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000) /*!< Channel 12 selection */
914 #define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800) /*!< Channel 11 selection */
915 #define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400) /*!< Channel 10 selection */
916 #define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200) /*!< Channel 9 selection */
917 #define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100) /*!< Channel 8 selection */
918 #define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080) /*!< Channel 7 selection */
919 #define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040) /*!< Channel 6 selection */
920 #define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020) /*!< Channel 5 selection */
921 #define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010) /*!< Channel 4 selection */
922 #define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008) /*!< Channel 3 selection */
923 #define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004) /*!< Channel 2 selection */
924 #define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002) /*!< Channel 1 selection */
925 #define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001) /*!< Channel 0 selection */
926
927 /******************** Bit definition for ADC_DR register ********************/
928 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
929
930 /******************** Bit definition for ADC_CALFACT register ********************/
931 #define ADC_CALFACT_CALFACT ((uint32_t)0x0000007F) /*!< Calibration factor */
932
933 /******************* Bit definition for ADC_CCR register ********************/
934 #define ADC_CCR_LFMEN ((uint32_t)0x02000000) /*!< Low Frequency Mode enable */
935 #define ADC_CCR_VLCDEN ((uint32_t)0x01000000) /*!< Voltage battery enable */
936 #define ADC_CCR_TSEN ((uint32_t)0x00800000) /*!< Temperature sensore enable */
937 #define ADC_CCR_VREFEN ((uint32_t)0x00400000) /*!< Vrefint enable */
938 #define ADC_CCR_PRESC ((uint32_t)0x003C0000) /*!< PRESC [3:0] bits (ADC prescaler) */
939 #define ADC_CCR_PRESC_0 ((uint32_t)0x00040000) /*!< Bit 0 */
940 #define ADC_CCR_PRESC_1 ((uint32_t)0x00080000) /*!< Bit 1 */
941 #define ADC_CCR_PRESC_2 ((uint32_t)0x00100000) /*!< Bit 2 */
942 #define ADC_CCR_PRESC_3 ((uint32_t)0x00200000) /*!< Bit 3 */
943
944 /******************************************************************************/
945 /* */
946 /* Analog Comparators (COMP) */
947 /* */
948 /******************************************************************************/
949 /************* Bit definition for COMP_CSR register (COMP1 and COMP2) **************/
950 /* COMP1 bits definition */
951 #define COMP_CSR_COMP1EN ((uint32_t)0x00000001) /*!< COMP1 enable */
952 #define COMP_CSR_COMP1INNSEL ((uint32_t)0x00000030) /*!< COMP1 inverting input select */
953 #define COMP_CSR_COMP1INNSEL_0 ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */
954 #define COMP_CSR_COMP1INNSEL_1 ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */
955 #define COMP_CSR_COMP1WM ((uint32_t)0x00000100) /*!< Comparators window mode enable */
956 #define COMP_CSR_COMP1LPTIM1IN1 ((uint32_t)0x00001000) /*!< COMP1 LPTIM1 IN1 connection */
957 #define COMP_CSR_COMP1POLARITY ((uint32_t)0x00008000) /*!< COMP1 output polarity */
958 #define COMP_CSR_COMP1VALUE ((uint32_t)0x40000000) /*!< COMP1 output level */
959 #define COMP_CSR_COMP1LOCK ((uint32_t)0x80000000) /*!< COMP1 lock */
960 /* COMP2 bits definition */
961 #define COMP_CSR_COMP2EN ((uint32_t)0x00000001) /*!< COMP2 enable */
962 #define COMP_CSR_COMP2SPEED ((uint32_t)0x000C0008) /*!< COMP2 power mode */
963 #define COMP_CSR_COMP2INNSEL ((uint32_t)0x00100070) /*!< COMP2 inverting input select */
964 #define COMP_CSR_COMP2INNSEL_0 ((uint32_t)0x00100010) /*!< COMP2 inverting input select bit 0 */
965 #define COMP_CSR_COMP2INNSEL_1 ((uint32_t)0x00200020) /*!< COMP2 inverting input select bit 1 */
966 #define COMP_CSR_COMP2INNSEL_2 ((uint32_t)0x00400040) /*!< COMP2 inverting input select bit 2 */
967 #define COMP_CSR_COMP2INPSEL ((uint32_t)0x00000700) /*!< COMPx non inverting input select */
968 #define COMP_CSR_COMP2INPSEL_0 ((uint32_t)0x00000100) /*!< COMPx non inverting input select */
969 #define COMP_CSR_COMP2INPSEL_1 ((uint32_t)0x00000200) /*!< COMPx non inverting input select */
970 #define COMP_CSR_COMP2INPSEL_2 ((uint32_t)0x00000400) /*!< COMPx non inverting input select */
971 #define COMP_CSR_COMP2LPTIM1IN2 ((uint32_t)0x00001000) /*!< COMP2 LPTIM1 IN2 connection */
972 #define COMP_CSR_COMP2POLARITY ((uint32_t)0x00008000) /*!< COMP2 output polarity */
973 #define COMP_CSR_COMP2VALUE ((uint32_t)0x40000000) /*!< COMP2 output level */
974 #define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */
975
976 /********************** Bit definition for COMP_CSR register common ****************/
977 #define COMP_CSR_COMPxEN ((uint32_t)0x00000001) /*!< COMPx enable */
978 #define COMP_CSR_COMPxPOLARITY ((uint32_t)0x00008000) /*!< COMPx output polarity */
979 #define COMP_CSR_COMPxOUTVALUE ((uint32_t)0x40000000) /*!< COMPx output level */
980 #define COMP_CSR_COMPxLOCK ((uint32_t)0x80000000) /*!< COMPx lock */
981
982
983 /******************************************************************************/
984 /* */
985 /* CRC calculation unit (CRC) */
986 /* */
987 /******************************************************************************/
988 /******************* Bit definition for CRC_DR register *********************/
989 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
990
991 /******************* Bit definition for CRC_IDR register ********************/
992 #define CRC_IDR_IDR ((uint32_t)0x000000FF) /*!< General-purpose 8-bit data register bits */
993
994 /******************** Bit definition for CRC_CR register ********************/
995 #define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
996 #define CRC_CR_POLYSIZE ((uint32_t)0x00000018) /*!< Polynomial size bits */
997 #define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008) /*!< Polynomial size bit 0 */
998 #define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010) /*!< Polynomial size bit 1 */
999 #define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
1000 #define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< Bit 0 */
1001 #define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< Bit 1 */
1002 #define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
1003
1004 /******************* Bit definition for CRC_INIT register *******************/
1005 #define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
1006
1007 /******************* Bit definition for CRC_POL register ********************/
1008 #define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */
1009
1010 /******************************************************************************/
1011 /* */
1012 /* CRS Clock Recovery System */
1013 /* */
1014 /******************************************************************************/
1015
1016 /******************* Bit definition for CRS_CR register *********************/
1017 #define CRS_CR_SYNCOKIE ((uint32_t)0x00000001) /* SYNC event OK interrupt enable */
1018 #define CRS_CR_SYNCWARNIE ((uint32_t)0x00000002) /* SYNC warning interrupt enable */
1019 #define CRS_CR_ERRIE ((uint32_t)0x00000004) /* SYNC error interrupt enable */
1020 #define CRS_CR_ESYNCIE ((uint32_t)0x00000008) /* Expected SYNC(ESYNCF) interrupt Enable*/
1021 #define CRS_CR_CEN ((uint32_t)0x00000020) /* Frequency error counter enable */
1022 #define CRS_CR_AUTOTRIMEN ((uint32_t)0x00000040) /* Automatic trimming enable */
1023 #define CRS_CR_SWSYNC ((uint32_t)0x00000080) /* A Software SYNC event is generated */
1024 #define CRS_CR_TRIM ((uint32_t)0x00003F00) /* HSI48 oscillator smooth trimming */
1025
1026 /******************* Bit definition for CRS_CFGR register *********************/
1027 #define CRS_CFGR_RELOAD ((uint32_t)0x0000FFFF) /* Counter reload value */
1028 #define CRS_CFGR_FELIM ((uint32_t)0x00FF0000) /* Frequency error limit */
1029
1030 #define CRS_CFGR_SYNCDIV ((uint32_t)0x07000000) /* SYNC divider */
1031 #define CRS_CFGR_SYNCDIV_0 ((uint32_t)0x01000000) /* Bit 0 */
1032 #define CRS_CFGR_SYNCDIV_1 ((uint32_t)0x02000000) /* Bit 1 */
1033 #define CRS_CFGR_SYNCDIV_2 ((uint32_t)0x04000000) /* Bit 2 */
1034
1035 #define CRS_CFGR_SYNCSRC ((uint32_t)0x30000000) /* SYNC signal source selection */
1036 #define CRS_CFGR_SYNCSRC_0 ((uint32_t)0x10000000) /* Bit 0 */
1037 #define CRS_CFGR_SYNCSRC_1 ((uint32_t)0x20000000) /* Bit 1 */
1038
1039 #define CRS_CFGR_SYNCPOL ((uint32_t)0x80000000) /* SYNC polarity selection */
1040
1041 /******************* Bit definition for CRS_ISR register *********************/
1042 #define CRS_ISR_SYNCOKF ((uint32_t)0x00000001) /* SYNC event OK flag */
1043 #define CRS_ISR_SYNCWARNF ((uint32_t)0x00000002) /* SYNC warning */
1044 #define CRS_ISR_ERRF ((uint32_t)0x00000004) /* SYNC error flag */
1045 #define CRS_ISR_ESYNCF ((uint32_t)0x00000008) /* Expected SYNC flag */
1046 #define CRS_ISR_SYNCERR ((uint32_t)0x00000100) /* SYNC error */
1047 #define CRS_ISR_SYNCMISS ((uint32_t)0x00000200) /* SYNC missed */
1048 #define CRS_ISR_TRIMOVF ((uint32_t)0x00000400) /* Trimming overflow or underflow */
1049 #define CRS_ISR_FEDIR ((uint32_t)0x00008000) /* Frequency error direction */
1050 #define CRS_ISR_FECAP ((uint32_t)0xFFFF0000) /* Frequency error capture */
1051
1052 /******************* Bit definition for CRS_ICR register *********************/
1053 #define CRS_ICR_SYNCOKC ((uint32_t)0x00000001) /* SYNC event OK clear flag */
1054 #define CRS_ICR_SYNCWARNC ((uint32_t)0x00000002) /* SYNC warning clear flag */
1055 #define CRS_ICR_ERRC ((uint32_t)0x00000004) /* Error clear flag */
1056 #define CRS_ICR_ESYNCC ((uint32_t)0x00000008) /* Expected SYNC clear flag */
1057
1058 /******************************************************************************/
1059 /* */
1060 /* Digital to Analog Converter (DAC) */
1061 /* */
1062 /******************************************************************************/
1063 /******************** Bit definition for DAC_CR register ********************/
1064 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */
1065 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */
1066 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */
1067
1068 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
1069 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
1070 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
1071 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
1072
1073 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
1074 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
1075 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
1076
1077 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
1078 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
1079 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
1080 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
1081 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */
1082
1083 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
1084 #define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA Underrun interrupt enable */
1085
1086 #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */
1087 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */
1088 #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */
1089
1090 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
1091 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */
1092 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */
1093 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */
1094
1095 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
1096 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */
1097 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */
1098
1099 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
1100 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */
1101 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */
1102 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */
1103 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */
1104
1105 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */
1106 #define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!< DAC channel12DMA Underrun interrupt enable */
1107
1108 /***************** Bit definition for DAC_SWTRIGR register ******************/
1109 #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!< DAC channel1 software trigger */
1110 #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) /*!< DAC channel2 software trigger */
1111
1112 /***************** Bit definition for DAC_DHR12R1 register ******************/
1113 #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
1114
1115 /***************** Bit definition for DAC_DHR12L1 register ******************/
1116 #define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
1117
1118 /****************** Bit definition for DAC_DHR8R1 register ******************/
1119 #define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
1120
1121 /***************** Bit definition for DAC_DHR12R2 register ******************/
1122 #define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFF) /*!< DAC channel2 12-bit Right aligned data */
1123
1124 /***************** Bit definition for DAC_DHR12L2 register ******************/
1125 #define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0) /*!< DAC channel2 12-bit Left aligned data */
1126
1127 /****************** Bit definition for DAC_DHR8R2 register ******************/
1128 #define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FF) /*!< DAC channel2 8-bit Right aligned data */
1129
1130 /***************** Bit definition for DAC_DHR12RD register ******************/
1131 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
1132 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */
1133
1134 /***************** Bit definition for DAC_DHR12LD register ******************/
1135 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
1136 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */
1137
1138 /****************** Bit definition for DAC_DHR8RD register ******************/
1139 #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
1140 #define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00) /*!< DAC channel2 8-bit Right aligned data */
1141
1142 /******************* Bit definition for DAC_DOR1 register *******************/
1143 #define DAC_DOR1_DACC1DOR ((uint16_t)0x00000FFF) /*!< DAC channel1 data output */
1144
1145 /******************* Bit definition for DAC_DOR2 register *******************/
1146 #define DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFF) /*!< DAC channel2 data output */
1147
1148 /******************** Bit definition for DAC_SR register ********************/
1149 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */
1150 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */
1151
1152 /******************************************************************************/
1153 /* */
1154 /* Debug MCU (DBGMCU) */
1155 /* */
1156 /******************************************************************************/
1157
1158 /**************** Bit definition for DBGMCU_IDCODE register *****************/
1159 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
1160
1161 #define DBGMCU_IDCODE_DIV_ID ((uint32_t)0x0000F000) /*!< Division Identifier */
1162 #define DBGMCU_IDCODE_MCD_DIV_ID ((uint32_t)0x00006000) /*!< MCD divsion ID is 6 */
1163 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
1164 #define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
1165 #define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
1166 #define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
1167 #define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
1168 #define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
1169 #define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
1170 #define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
1171 #define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
1172 #define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
1173 #define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
1174 #define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
1175 #define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
1176 #define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
1177 #define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
1178 #define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
1179 #define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
1180
1181 /****************** Bit definition for DBGMCU_CR register *******************/
1182 #define DBGMCU_CR_DBG ((uint32_t)0x00000007) /*!< Debug mode mask */
1183 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */
1184 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
1185 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
1186
1187 /****************** Bit definition for DBGMCU_APB1_FZ register **************/
1188 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /*!< TIM2 counter stopped when core is halted */
1189 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
1190 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /*!< TIM6 counter stopped when core is halted */
1191 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
1192 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /*!< RTC Calendar frozen when core is halted */
1193 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /*!< Debug Window Watchdog stopped when Core is halted */
1194 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /*!< Debug Independent Watchdog stopped when Core is halted */
1195 #define DBGMCU_APB1_FZ_DBG_I2C1_STOP ((uint32_t)0x00200000) /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
1196 #define DBGMCU_APB1_FZ_DBG_I2C2_STOP ((uint32_t)0x00400000) /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
1197 #define DBGMCU_APB1_FZ_DBG_I2C3_STOP ((uint32_t)0x00800000) /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
1198 #define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP ((uint32_t)0x80000000) /*!< LPTIM1 counter stopped when core is halted */
1199 /****************** Bit definition for DBGMCU_APB2_FZ register **************/
1200 #define DBGMCU_APB2_FZ_DBG_TIM22_STOP ((uint32_t)0x00000020) /*!< TIM22 counter stopped when core is halted */
1201 #define DBGMCU_APB2_FZ_DBG_TIM21_STOP ((uint32_t)0x00000004) /*!< TIM21 counter stopped when core is halted */
1202
1203 /******************************************************************************/
1204 /* */
1205 /* DMA Controller (DMA) */
1206 /* */
1207 /******************************************************************************/
1208
1209 /******************* Bit definition for DMA_ISR register ********************/
1210 #define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
1211 #define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
1212 #define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
1213 #define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
1214 #define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
1215 #define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
1216 #define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
1217 #define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
1218 #define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
1219 #define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
1220 #define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
1221 #define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
1222 #define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
1223 #define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
1224 #define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
1225 #define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
1226 #define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
1227 #define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
1228 #define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
1229 #define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
1230 #define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
1231 #define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
1232 #define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
1233 #define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
1234 #define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
1235 #define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
1236 #define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
1237 #define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
1238
1239 /******************* Bit definition for DMA_IFCR register *******************/
1240 #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
1241 #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
1242 #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
1243 #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
1244 #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
1245 #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
1246 #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
1247 #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
1248 #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
1249 #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
1250 #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
1251 #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
1252 #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
1253 #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
1254 #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
1255 #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
1256 #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
1257 #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
1258 #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
1259 #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
1260 #define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
1261 #define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
1262 #define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
1263 #define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
1264 #define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
1265 #define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
1266 #define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
1267 #define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
1268
1269 /******************* Bit definition for DMA_CCR register ********************/
1270 #define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
1271 #define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
1272 #define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
1273 #define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
1274 #define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
1275 #define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
1276 #define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
1277 #define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
1278
1279 #define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
1280 #define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
1281 #define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
1282
1283 #define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
1284 #define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
1285 #define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
1286
1287 #define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/
1288 #define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
1289 #define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
1290
1291 #define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
1292
1293 /****************** Bit definition for DMA_CNDTR register *******************/
1294 #define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
1295
1296 /****************** Bit definition for DMA_CPAR register ********************/
1297 #define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
1298
1299 /****************** Bit definition for DMA_CMAR register ********************/
1300 #define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
1301
1302
1303 /******************* Bit definition for DMA_CSELR register *******************/
1304 #define DMA_CSELR_C1S ((uint32_t)0x0000000F) /*!< Channel 1 Selection */
1305 #define DMA_CSELR_C2S ((uint32_t)0x000000F0) /*!< Channel 2 Selection */
1306 #define DMA_CSELR_C3S ((uint32_t)0x00000F00) /*!< Channel 3 Selection */
1307 #define DMA_CSELR_C4S ((uint32_t)0x0000F000) /*!< Channel 4 Selection */
1308 #define DMA_CSELR_C5S ((uint32_t)0x000F0000) /*!< Channel 5 Selection */
1309 #define DMA_CSELR_C6S ((uint32_t)0x00F00000) /*!< Channel 6 Selection */
1310 #define DMA_CSELR_C7S ((uint32_t)0x0F000000) /*!< Channel 7 Selection */
1311
1312
1313 /******************************************************************************/
1314 /* */
1315 /* External Interrupt/Event Controller (EXTI) */
1316 /* */
1317 /******************************************************************************/
1318
1319 /******************* Bit definition for EXTI_IMR register *******************/
1320 #define EXTI_IMR_IM0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
1321 #define EXTI_IMR_IM1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
1322 #define EXTI_IMR_IM2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
1323 #define EXTI_IMR_IM3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
1324 #define EXTI_IMR_IM4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
1325 #define EXTI_IMR_IM5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
1326 #define EXTI_IMR_IM6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
1327 #define EXTI_IMR_IM7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
1328 #define EXTI_IMR_IM8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
1329 #define EXTI_IMR_IM9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
1330 #define EXTI_IMR_IM10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
1331 #define EXTI_IMR_IM11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
1332 #define EXTI_IMR_IM12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
1333 #define EXTI_IMR_IM13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
1334 #define EXTI_IMR_IM14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
1335 #define EXTI_IMR_IM15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
1336 #define EXTI_IMR_IM16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
1337 #define EXTI_IMR_IM17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
1338 #define EXTI_IMR_IM18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
1339 #define EXTI_IMR_IM19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
1340 #define EXTI_IMR_IM20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
1341 #define EXTI_IMR_IM21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
1342 #define EXTI_IMR_IM22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
1343 #define EXTI_IMR_IM23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
1344 #define EXTI_IMR_IM24 ((uint32_t)0x01000000) /*!< Interrupt Mask on line 24 */
1345 #define EXTI_IMR_IM25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
1346 #define EXTI_IMR_IM26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
1347 #define EXTI_IMR_IM28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */
1348 #define EXTI_IMR_IM29 ((uint32_t)0x20000000) /*!< Interrupt Mask on line 29 */
1349
1350 /****************** Bit definition for EXTI_EMR register ********************/
1351 #define EXTI_EMR_EM0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
1352 #define EXTI_EMR_EM1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
1353 #define EXTI_EMR_EM2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
1354 #define EXTI_EMR_EM3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
1355 #define EXTI_EMR_EM4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
1356 #define EXTI_EMR_EM5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
1357 #define EXTI_EMR_EM6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
1358 #define EXTI_EMR_EM7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
1359 #define EXTI_EMR_EM8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
1360 #define EXTI_EMR_EM9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
1361 #define EXTI_EMR_EM10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
1362 #define EXTI_EMR_EM11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
1363 #define EXTI_EMR_EM12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
1364 #define EXTI_EMR_EM13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
1365 #define EXTI_EMR_EM14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
1366 #define EXTI_EMR_EM15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
1367 #define EXTI_EMR_EM16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
1368 #define EXTI_EMR_EM17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
1369 #define EXTI_EMR_EM18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
1370 #define EXTI_EMR_EM19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
1371 #define EXTI_EMR_EM20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
1372 #define EXTI_EMR_EM21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
1373 #define EXTI_EMR_EM22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
1374 #define EXTI_EMR_EM23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
1375 #define EXTI_EMR_EM24 ((uint32_t)0x01000000) /*!< Event Mask on line 24 */
1376 #define EXTI_EMR_EM25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
1377 #define EXTI_EMR_EM26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
1378 #define EXTI_EMR_EM28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */
1379 #define EXTI_EMR_EM29 ((uint32_t)0x20000000) /*!< Event Mask on line 29 */
1380
1381 /******************* Bit definition for EXTI_RTSR register ******************/
1382 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
1383 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
1384 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
1385 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
1386 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
1387 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
1388 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
1389 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
1390 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
1391 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
1392 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
1393 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
1394 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
1395 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
1396 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
1397 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
1398 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
1399 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
1400 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
1401 #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
1402 #define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
1403 #define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
1404
1405 /******************* Bit definition for EXTI_FTSR register *******************/
1406 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
1407 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
1408 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
1409 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
1410 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
1411 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
1412 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
1413 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
1414 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
1415 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
1416 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
1417 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
1418 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
1419 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
1420 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
1421 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
1422 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
1423 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
1424 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
1425 #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
1426 #define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
1427 #define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
1428
1429 /******************* Bit definition for EXTI_SWIER register *******************/
1430 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
1431 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
1432 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
1433 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
1434 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
1435 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
1436 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
1437 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
1438 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
1439 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
1440 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
1441 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
1442 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
1443 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
1444 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
1445 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
1446 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
1447 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
1448 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
1449 #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
1450 #define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
1451 #define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
1452
1453 /****************** Bit definition for EXTI_PR register *********************/
1454 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */
1455 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */
1456 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */
1457 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */
1458 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */
1459 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */
1460 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */
1461 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */
1462 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */
1463 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */
1464 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */
1465 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */
1466 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */
1467 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */
1468 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */
1469 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */
1470 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */
1471 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */
1472 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */
1473 #define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit 20 */
1474 #define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit 21 */
1475 #define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit 22 */
1476
1477 /******************************************************************************/
1478 /* */
1479 /* FLASH and Option Bytes Registers */
1480 /* */
1481 /******************************************************************************/
1482
1483 /******************* Bit definition for FLASH_ACR register ******************/
1484 #define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /*!< LATENCY bit (Latency) */
1485 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000002) /*!< Prefetch Buffer Enable */
1486 #define FLASH_ACR_SLEEP_PD ((uint32_t)0x00000008) /*!< Flash mode during sleep mode */
1487 #define FLASH_ACR_RUN_PD ((uint32_t)0x00000010) /*!< Flash mode during RUN mode */
1488 #define FLASH_ACR_DISAB_BUF ((uint32_t)0x00000020) /*!< Disable Buffer */
1489 #define FLASH_ACR_PRE_READ ((uint32_t)0x00000040) /*!< Pre-read data address */
1490
1491 /******************* Bit definition for FLASH_PECR register ******************/
1492 #define FLASH_PECR_PELOCK ((uint32_t)0x00000001) /*!< FLASH_PECR and Flash data Lock */
1493 #define FLASH_PECR_PRGLOCK ((uint32_t)0x00000002) /*!< Program matrix Lock */
1494 #define FLASH_PECR_OPTLOCK ((uint32_t)0x00000004) /*!< Option byte matrix Lock */
1495 #define FLASH_PECR_PROG ((uint32_t)0x00000008) /*!< Program matrix selection */
1496 #define FLASH_PECR_DATA ((uint32_t)0x00000010) /*!< Data matrix selection */
1497 #define FLASH_PECR_FIX ((uint32_t)0x00000100) /*!< Fixed Time Data write for Word/Half Word/Byte programming */
1498 #define FLASH_PECR_ERASE ((uint32_t)0x00000200) /*!< Page erasing mode */
1499 #define FLASH_PECR_FPRG ((uint32_t)0x00000400) /*!< Fast Page/Half Page programming mode */
1500 #define FLASH_PECR_PARALLBANK ((uint32_t)0x00008000) /*!< Parallel Bank mode */
1501 #define FLASH_PECR_EOPIE ((uint32_t)0x00010000) /*!< End of programming interrupt */
1502 #define FLASH_PECR_ERRIE ((uint32_t)0x00020000) /*!< Error interrupt */
1503 #define FLASH_PECR_OBL_LAUNCH ((uint32_t)0x00040000) /*!< Launch the option byte loading */
1504 #define FLASH_PECR_HALF_ARRAY ((uint32_t)0x00080000) /*!< Half array mode */
1505 #define FLASH_PECR_NZDISABLE ((uint32_t)0x00400000) /*!< Non-Zero check disable */
1506
1507 /****************** Bit definition for FLASH_PDKEYR register ******************/
1508 #define FLASH_PDKEYR_PDKEYR ((uint32_t)0xFFFFFFFF) /*!< FLASH_PEC and data matrix Key */
1509
1510 /****************** Bit definition for FLASH_PEKEYR register ******************/
1511 #define FLASH_PEKEYR_PEKEYR ((uint32_t)0xFFFFFFFF) /*!< FLASH_PEC and data matrix Key */
1512
1513 /****************** Bit definition for FLASH_PRGKEYR register ******************/
1514 #define FLASH_PRGKEYR_PRGKEYR ((uint32_t)0xFFFFFFFF) /*!< Program matrix Key */
1515
1516 /****************** Bit definition for FLASH_OPTKEYR register ******************/
1517 #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option bytes matrix Key */
1518
1519 /****************** Bit definition for FLASH_SR register *******************/
1520 #define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
1521 #define FLASH_SR_EOP ((uint32_t)0x00000002) /*!< End Of Programming*/
1522 #define FLASH_SR_HVOFF ((uint32_t)0x00000004) /*!< End of high voltage */
1523 #define FLASH_SR_READY ((uint32_t)0x00000008) /*!< Flash ready after low power mode */
1524
1525 #define FLASH_SR_WRPERR ((uint32_t)0x00000100) /*!< Write protection error */
1526 #define FLASH_SR_PGAERR ((uint32_t)0x00000200) /*!< Programming Alignment Error */
1527 #define FLASH_SR_SIZERR ((uint32_t)0x00000400) /*!< Size error */
1528 #define FLASH_SR_OPTVERR ((uint32_t)0x00000800) /*!< Option Valid error */
1529 #define FLASH_SR_RDERR ((uint32_t)0x00002000) /*!< Read protected error */
1530 #define FLASH_SR_NOTZEROERR ((uint32_t)0x00010000) /*!< Not Zero error */
1531 #define FLASH_SR_FWWERR ((uint32_t)0x00020000) /*!< Write/Errase operation aborted */
1532
1533 /* alias maintained for legacy */
1534 #define FLASH_SR_FWWER FLASH_SR_FWWERR
1535 #define FLASH_SR_ENHV FLASH_SR_HVOFF
1536 #define FLASH_SR_ENDHV FLASH_SR_HVOFF
1537
1538 /****************** Bit definition for FLASH_OPTR register *******************/
1539 #define FLASH_OPTR_RDPROT ((uint32_t)0x000000FF) /*!< Read Protection */
1540 #define FLASH_OPTR_WPRMOD ((uint32_t)0x00000100) /*!< Selection of protection mode of WPR bits */
1541 #define FLASH_OPTR_BOR_LEV ((uint32_t)0x000F0000) /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
1542 #define FLASH_OPTR_IWDG_SW ((uint32_t)0x00100000) /*!< IWDG_SW */
1543 #define FLASH_OPTR_nRST_STOP ((uint32_t)0x00200000) /*!< nRST_STOP */
1544 #define FLASH_OPTR_nRST_STDBY ((uint32_t)0x00400000) /*!< nRST_STDBY */
1545 #define FLASH_OPTR_BFB2 ((uint32_t)0x00800000) /*!< BFB2 */
1546 #define FLASH_OPTR_USER ((uint32_t)0x00700000) /*!< User Option Bytes */
1547 #define FLASH_OPTR_BOOT1 ((uint32_t)0x80000000) /*!< BOOT1 */
1548
1549 /****************** Bit definition for FLASH_WRPR register ******************/
1550 #define FLASH_WRPR_WRP ((uint32_t)0x0000FFFF) /*!< Write Protection bits */
1551
1552 /******************************************************************************/
1553 /* */
1554 /* General Purpose IOs (GPIO) */
1555 /* */
1556 /******************************************************************************/
1557 /******************* Bit definition for GPIO_MODER register *****************/
1558 #define GPIO_MODER_MODE0 ((uint32_t)0x00000003)
1559 #define GPIO_MODER_MODE0_0 ((uint32_t)0x00000001)
1560 #define GPIO_MODER_MODE0_1 ((uint32_t)0x00000002)
1561 #define GPIO_MODER_MODE1 ((uint32_t)0x0000000C)
1562 #define GPIO_MODER_MODE1_0 ((uint32_t)0x00000004)
1563 #define GPIO_MODER_MODE1_1 ((uint32_t)0x00000008)
1564 #define GPIO_MODER_MODE2 ((uint32_t)0x00000030)
1565 #define GPIO_MODER_MODE2_0 ((uint32_t)0x00000010)
1566 #define GPIO_MODER_MODE2_1 ((uint32_t)0x00000020)
1567 #define GPIO_MODER_MODE3 ((uint32_t)0x000000C0)
1568 #define GPIO_MODER_MODE3_0 ((uint32_t)0x00000040)
1569 #define GPIO_MODER_MODE3_1 ((uint32_t)0x00000080)
1570 #define GPIO_MODER_MODE4 ((uint32_t)0x00000300)
1571 #define GPIO_MODER_MODE4_0 ((uint32_t)0x00000100)
1572 #define GPIO_MODER_MODE4_1 ((uint32_t)0x00000200)
1573 #define GPIO_MODER_MODE5 ((uint32_t)0x00000C00)
1574 #define GPIO_MODER_MODE5_0 ((uint32_t)0x00000400)
1575 #define GPIO_MODER_MODE5_1 ((uint32_t)0x00000800)
1576 #define GPIO_MODER_MODE6 ((uint32_t)0x00003000)
1577 #define GPIO_MODER_MODE6_0 ((uint32_t)0x00001000)
1578 #define GPIO_MODER_MODE6_1 ((uint32_t)0x00002000)
1579 #define GPIO_MODER_MODE7 ((uint32_t)0x0000C000)
1580 #define GPIO_MODER_MODE7_0 ((uint32_t)0x00004000)
1581 #define GPIO_MODER_MODE7_1 ((uint32_t)0x00008000)
1582 #define GPIO_MODER_MODE8 ((uint32_t)0x00030000)
1583 #define GPIO_MODER_MODE8_0 ((uint32_t)0x00010000)
1584 #define GPIO_MODER_MODE8_1 ((uint32_t)0x00020000)
1585 #define GPIO_MODER_MODE9 ((uint32_t)0x000C0000)
1586 #define GPIO_MODER_MODE9_0 ((uint32_t)0x00040000)
1587 #define GPIO_MODER_MODE9_1 ((uint32_t)0x00080000)
1588 #define GPIO_MODER_MODE10 ((uint32_t)0x00300000)
1589 #define GPIO_MODER_MODE10_0 ((uint32_t)0x00100000)
1590 #define GPIO_MODER_MODE10_1 ((uint32_t)0x00200000)
1591 #define GPIO_MODER_MODE11 ((uint32_t)0x00C00000)
1592 #define GPIO_MODER_MODE11_0 ((uint32_t)0x00400000)
1593 #define GPIO_MODER_MODE11_1 ((uint32_t)0x00800000)
1594 #define GPIO_MODER_MODE12 ((uint32_t)0x03000000)
1595 #define GPIO_MODER_MODE12_0 ((uint32_t)0x01000000)
1596 #define GPIO_MODER_MODE12_1 ((uint32_t)0x02000000)
1597 #define GPIO_MODER_MODE13 ((uint32_t)0x0C000000)
1598 #define GPIO_MODER_MODE13_0 ((uint32_t)0x04000000)
1599 #define GPIO_MODER_MODE13_1 ((uint32_t)0x08000000)
1600 #define GPIO_MODER_MODE14 ((uint32_t)0x30000000)
1601 #define GPIO_MODER_MODE14_0 ((uint32_t)0x10000000)
1602 #define GPIO_MODER_MODE14_1 ((uint32_t)0x20000000)
1603 #define GPIO_MODER_MODE15 ((uint32_t)0xC0000000)
1604 #define GPIO_MODER_MODE15_0 ((uint32_t)0x40000000)
1605 #define GPIO_MODER_MODE15_1 ((uint32_t)0x80000000)
1606
1607 /****************** Bit definition for GPIO_OTYPER register *****************/
1608 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
1609 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
1610 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
1611 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
1612 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
1613 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
1614 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
1615 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
1616 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
1617 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
1618 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
1619 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
1620 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
1621 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
1622 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
1623 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
1624
1625 /**************** Bit definition for GPIO_OSPEEDR register ******************/
1626 #define GPIO_OSPEEDER_OSPEED0 ((uint32_t)0x00000003)
1627 #define GPIO_OSPEEDER_OSPEED0_0 ((uint32_t)0x00000001)
1628 #define GPIO_OSPEEDER_OSPEED0_1 ((uint32_t)0x00000002)
1629 #define GPIO_OSPEEDER_OSPEED1 ((uint32_t)0x0000000C)
1630 #define GPIO_OSPEEDER_OSPEED1_0 ((uint32_t)0x00000004)
1631 #define GPIO_OSPEEDER_OSPEED1_1 ((uint32_t)0x00000008)
1632 #define GPIO_OSPEEDER_OSPEED2 ((uint32_t)0x00000030)
1633 #define GPIO_OSPEEDER_OSPEED2_0 ((uint32_t)0x00000010)
1634 #define GPIO_OSPEEDER_OSPEED2_1 ((uint32_t)0x00000020)
1635 #define GPIO_OSPEEDER_OSPEED3 ((uint32_t)0x000000C0)
1636 #define GPIO_OSPEEDER_OSPEED3_0 ((uint32_t)0x00000040)
1637 #define GPIO_OSPEEDER_OSPEED3_1 ((uint32_t)0x00000080)
1638 #define GPIO_OSPEEDER_OSPEED4 ((uint32_t)0x00000300)
1639 #define GPIO_OSPEEDER_OSPEED4_0 ((uint32_t)0x00000100)
1640 #define GPIO_OSPEEDER_OSPEED4_1 ((uint32_t)0x00000200)
1641 #define GPIO_OSPEEDER_OSPEED5 ((uint32_t)0x00000C00)
1642 #define GPIO_OSPEEDER_OSPEED5_0 ((uint32_t)0x00000400)
1643 #define GPIO_OSPEEDER_OSPEED5_1 ((uint32_t)0x00000800)
1644 #define GPIO_OSPEEDER_OSPEED6 ((uint32_t)0x00003000)
1645 #define GPIO_OSPEEDER_OSPEED6_0 ((uint32_t)0x00001000)
1646 #define GPIO_OSPEEDER_OSPEED6_1 ((uint32_t)0x00002000)
1647 #define GPIO_OSPEEDER_OSPEED7 ((uint32_t)0x0000C000)
1648 #define GPIO_OSPEEDER_OSPEED7_0 ((uint32_t)0x00004000)
1649 #define GPIO_OSPEEDER_OSPEED7_1 ((uint32_t)0x00008000)
1650 #define GPIO_OSPEEDER_OSPEED8 ((uint32_t)0x00030000)
1651 #define GPIO_OSPEEDER_OSPEED8_0 ((uint32_t)0x00010000)
1652 #define GPIO_OSPEEDER_OSPEED8_1 ((uint32_t)0x00020000)
1653 #define GPIO_OSPEEDER_OSPEED9 ((uint32_t)0x000C0000)
1654 #define GPIO_OSPEEDER_OSPEED9_0 ((uint32_t)0x00040000)
1655 #define GPIO_OSPEEDER_OSPEED9_1 ((uint32_t)0x00080000)
1656 #define GPIO_OSPEEDER_OSPEED10 ((uint32_t)0x00300000)
1657 #define GPIO_OSPEEDER_OSPEED10_0 ((uint32_t)0x00100000)
1658 #define GPIO_OSPEEDER_OSPEED10_1 ((uint32_t)0x00200000)
1659 #define GPIO_OSPEEDER_OSPEED11 ((uint32_t)0x00C00000)
1660 #define GPIO_OSPEEDER_OSPEED11_0 ((uint32_t)0x00400000)
1661 #define GPIO_OSPEEDER_OSPEED11_1 ((uint32_t)0x00800000)
1662 #define GPIO_OSPEEDER_OSPEED12 ((uint32_t)0x03000000)
1663 #define GPIO_OSPEEDER_OSPEED12_0 ((uint32_t)0x01000000)
1664 #define GPIO_OSPEEDER_OSPEED12_1 ((uint32_t)0x02000000)
1665 #define GPIO_OSPEEDER_OSPEED13 ((uint32_t)0x0C000000)
1666 #define GPIO_OSPEEDER_OSPEED13_0 ((uint32_t)0x04000000)
1667 #define GPIO_OSPEEDER_OSPEED13_1 ((uint32_t)0x08000000)
1668 #define GPIO_OSPEEDER_OSPEED14 ((uint32_t)0x30000000)
1669 #define GPIO_OSPEEDER_OSPEED14_0 ((uint32_t)0x10000000)
1670 #define GPIO_OSPEEDER_OSPEED14_1 ((uint32_t)0x20000000)
1671 #define GPIO_OSPEEDER_OSPEED15 ((uint32_t)0xC0000000)
1672 #define GPIO_OSPEEDER_OSPEED15_0 ((uint32_t)0x40000000)
1673 #define GPIO_OSPEEDER_OSPEED15_1 ((uint32_t)0x80000000)
1674
1675 /******************* Bit definition for GPIO_PUPDR register ******************/
1676 #define GPIO_PUPDR_PUPD0 ((uint32_t)0x00000003)
1677 #define GPIO_PUPDR_PUPD0_0 ((uint32_t)0x00000001)
1678 #define GPIO_PUPDR_PUPD0_1 ((uint32_t)0x00000002)
1679 #define GPIO_PUPDR_PUPD1 ((uint32_t)0x0000000C)
1680 #define GPIO_PUPDR_PUPD1_0 ((uint32_t)0x00000004)
1681 #define GPIO_PUPDR_PUPD1_1 ((uint32_t)0x00000008)
1682 #define GPIO_PUPDR_PUPD2 ((uint32_t)0x00000030)
1683 #define GPIO_PUPDR_PUPD2_0 ((uint32_t)0x00000010)
1684 #define GPIO_PUPDR_PUPD2_1 ((uint32_t)0x00000020)
1685 #define GPIO_PUPDR_PUPD3 ((uint32_t)0x000000C0)
1686 #define GPIO_PUPDR_PUPD3_0 ((uint32_t)0x00000040)
1687 #define GPIO_PUPDR_PUPD3_1 ((uint32_t)0x00000080)
1688 #define GPIO_PUPDR_PUPD4 ((uint32_t)0x00000300)
1689 #define GPIO_PUPDR_PUPD4_0 ((uint32_t)0x00000100)
1690 #define GPIO_PUPDR_PUPD4_1 ((uint32_t)0x00000200)
1691 #define GPIO_PUPDR_PUPD5 ((uint32_t)0x00000C00)
1692 #define GPIO_PUPDR_PUPD5_0 ((uint32_t)0x00000400)
1693 #define GPIO_PUPDR_PUPD5_1 ((uint32_t)0x00000800)
1694 #define GPIO_PUPDR_PUPD6 ((uint32_t)0x00003000)
1695 #define GPIO_PUPDR_PUPD6_0 ((uint32_t)0x00001000)
1696 #define GPIO_PUPDR_PUPD6_1 ((uint32_t)0x00002000)
1697 #define GPIO_PUPDR_PUPD7 ((uint32_t)0x0000C000)
1698 #define GPIO_PUPDR_PUPD7_0 ((uint32_t)0x00004000)
1699 #define GPIO_PUPDR_PUPD7_1 ((uint32_t)0x00008000)
1700 #define GPIO_PUPDR_PUPD8 ((uint32_t)0x00030000)
1701 #define GPIO_PUPDR_PUPD8_0 ((uint32_t)0x00010000)
1702 #define GPIO_PUPDR_PUPD8_1 ((uint32_t)0x00020000)
1703 #define GPIO_PUPDR_PUPD9 ((uint32_t)0x000C0000)
1704 #define GPIO_PUPDR_PUPD9_0 ((uint32_t)0x00040000)
1705 #define GPIO_PUPDR_PUPD9_1 ((uint32_t)0x00080000)
1706 #define GPIO_PUPDR_PUPD10 ((uint32_t)0x00300000)
1707 #define GPIO_PUPDR_PUPD10_0 ((uint32_t)0x00100000)
1708 #define GPIO_PUPDR_PUPD10_1 ((uint32_t)0x00200000)
1709 #define GPIO_PUPDR_PUPD11 ((uint32_t)0x00C00000)
1710 #define GPIO_PUPDR_PUPD11_0 ((uint32_t)0x00400000)
1711 #define GPIO_PUPDR_PUPD11_1 ((uint32_t)0x00800000)
1712 #define GPIO_PUPDR_PUPD12 ((uint32_t)0x03000000)
1713 #define GPIO_PUPDR_PUPD12_0 ((uint32_t)0x01000000)
1714 #define GPIO_PUPDR_PUPD12_1 ((uint32_t)0x02000000)
1715 #define GPIO_PUPDR_PUPD13 ((uint32_t)0x0C000000)
1716 #define GPIO_PUPDR_PUPD13_0 ((uint32_t)0x04000000)
1717 #define GPIO_PUPDR_PUPD13_1 ((uint32_t)0x08000000)
1718 #define GPIO_PUPDR_PUPD14 ((uint32_t)0x30000000)
1719 #define GPIO_PUPDR_PUPD14_0 ((uint32_t)0x10000000)
1720 #define GPIO_PUPDR_PUPD14_1 ((uint32_t)0x20000000)
1721 #define GPIO_PUPDR_PUPD15 ((uint32_t)0xC0000000)
1722 #define GPIO_PUPDR_PUPD15_0 ((uint32_t)0x40000000)
1723 #define GPIO_PUPDR_PUPD15_1 ((uint32_t)0x80000000)
1724
1725 /******************* Bit definition for GPIO_IDR register *******************/
1726 #define GPIO_IDR_ID0 ((uint32_t)0x00000001)
1727 #define GPIO_IDR_ID1 ((uint32_t)0x00000002)
1728 #define GPIO_IDR_ID2 ((uint32_t)0x00000004)
1729 #define GPIO_IDR_ID3 ((uint32_t)0x00000008)
1730 #define GPIO_IDR_ID4 ((uint32_t)0x00000010)
1731 #define GPIO_IDR_ID5 ((uint32_t)0x00000020)
1732 #define GPIO_IDR_ID6 ((uint32_t)0x00000040)
1733 #define GPIO_IDR_ID7 ((uint32_t)0x00000080)
1734 #define GPIO_IDR_ID8 ((uint32_t)0x00000100)
1735 #define GPIO_IDR_ID9 ((uint32_t)0x00000200)
1736 #define GPIO_IDR_ID10 ((uint32_t)0x00000400)
1737 #define GPIO_IDR_ID11 ((uint32_t)0x00000800)
1738 #define GPIO_IDR_ID12 ((uint32_t)0x00001000)
1739 #define GPIO_IDR_ID13 ((uint32_t)0x00002000)
1740 #define GPIO_IDR_ID14 ((uint32_t)0x00004000)
1741 #define GPIO_IDR_ID15 ((uint32_t)0x00008000)
1742
1743 /****************** Bit definition for GPIO_ODR register ********************/
1744 #define GPIO_ODR_OD0 ((uint32_t)0x00000001)
1745 #define GPIO_ODR_OD1 ((uint32_t)0x00000002)
1746 #define GPIO_ODR_OD2 ((uint32_t)0x00000004)
1747 #define GPIO_ODR_OD3 ((uint32_t)0x00000008)
1748 #define GPIO_ODR_OD4 ((uint32_t)0x00000010)
1749 #define GPIO_ODR_OD5 ((uint32_t)0x00000020)
1750 #define GPIO_ODR_OD6 ((uint32_t)0x00000040)
1751 #define GPIO_ODR_OD7 ((uint32_t)0x00000080)
1752 #define GPIO_ODR_OD8 ((uint32_t)0x00000100)
1753 #define GPIO_ODR_OD9 ((uint32_t)0x00000200)
1754 #define GPIO_ODR_OD10 ((uint32_t)0x00000400)
1755 #define GPIO_ODR_OD11 ((uint32_t)0x00000800)
1756 #define GPIO_ODR_OD12 ((uint32_t)0x00001000)
1757 #define GPIO_ODR_OD13 ((uint32_t)0x00002000)
1758 #define GPIO_ODR_OD14 ((uint32_t)0x00004000)
1759 #define GPIO_ODR_OD15 ((uint32_t)0x00008000)
1760
1761 /****************** Bit definition for GPIO_BSRR register ********************/
1762 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
1763 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
1764 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
1765 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
1766 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
1767 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
1768 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
1769 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
1770 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
1771 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
1772 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
1773 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
1774 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
1775 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
1776 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
1777 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
1778 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
1779 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
1780 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
1781 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
1782 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
1783 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
1784 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
1785 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
1786 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
1787 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
1788 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
1789 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
1790 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
1791 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
1792 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
1793 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
1794
1795 /****************** Bit definition for GPIO_LCKR register ********************/
1796 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
1797 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
1798 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
1799 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
1800 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
1801 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
1802 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
1803 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
1804 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
1805 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
1806 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
1807 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
1808 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
1809 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
1810 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
1811 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
1812 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
1813
1814 /****************** Bit definition for GPIO_BRR register *********************/
1815 #define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
1816 #define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
1817 #define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
1818 #define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
1819 #define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
1820 #define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
1821 #define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
1822 #define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
1823 #define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
1824 #define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
1825 #define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
1826 #define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
1827 #define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
1828 #define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
1829 #define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
1830 #define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
1831
1832 /******************************************************************************/
1833 /* */
1834 /* Inter-integrated Circuit Interface (I2C) */
1835 /* */
1836 /******************************************************************************/
1837
1838 /******************* Bit definition for I2C_CR1 register *******************/
1839 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
1840 #define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
1841 #define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
1842 #define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
1843 #define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
1844 #define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
1845 #define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
1846 #define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
1847 #define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
1848 #define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
1849 #define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
1850 #define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
1851 #define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
1852 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
1853 #define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
1854 #define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
1855 #define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
1856 #define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
1857 #define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
1858 #define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
1859
1860 /****************** Bit definition for I2C_CR2 register ********************/
1861 #define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
1862 #define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
1863 #define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
1864 #define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
1865 #define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
1866 #define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
1867 #define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
1868 #define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
1869 #define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
1870 #define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
1871 #define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
1872
1873 /******************* Bit definition for I2C_OAR1 register ******************/
1874 #define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
1875 #define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
1876 #define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
1877
1878 /******************* Bit definition for I2C_OAR2 register ******************/
1879 #define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
1880 #define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
1881 #define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
1882
1883 /******************* Bit definition for I2C_TIMINGR register *******************/
1884 #define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
1885 #define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
1886 #define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
1887 #define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
1888 #define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
1889
1890 /******************* Bit definition for I2C_TIMEOUTR register *******************/
1891 #define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
1892 #define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
1893 #define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
1894 #define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/
1895 #define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
1896
1897 /****************** Bit definition for I2C_ISR register *********************/
1898 #define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
1899 #define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
1900 #define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
1901 #define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/
1902 #define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
1903 #define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
1904 #define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
1905 #define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
1906 #define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
1907 #define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
1908 #define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
1909 #define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
1910 #define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
1911 #define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
1912 #define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
1913 #define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
1914 #define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
1915
1916 /****************** Bit definition for I2C_ICR register *********************/
1917 #define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
1918 #define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
1919 #define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
1920 #define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
1921 #define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
1922 #define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
1923 #define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
1924 #define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
1925 #define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
1926
1927 /****************** Bit definition for I2C_PECR register *********************/
1928 #define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
1929
1930 /****************** Bit definition for I2C_RXDR register *********************/
1931 #define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
1932
1933 /****************** Bit definition for I2C_TXDR register *********************/
1934 #define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
1935
1936 /******************************************************************************/
1937 /* */
1938 /* Independent WATCHDOG (IWDG) */
1939 /* */
1940 /******************************************************************************/
1941 /******************* Bit definition for IWDG_KR register ********************/
1942 #define IWDG_KR_KEY ((uint32_t)0x0000FFFF) /*!< Key value (write only, read 0000h) */
1943
1944 /******************* Bit definition for IWDG_PR register ********************/
1945 #define IWDG_PR_PR ((uint32_t)0x00000007) /*!< PR[2:0] (Prescaler divider) */
1946 #define IWDG_PR_PR_0 ((uint32_t)0x00000001) /*!< Bit 0 */
1947 #define IWDG_PR_PR_1 ((uint32_t)0x00000002) /*!< Bit 1 */
1948 #define IWDG_PR_PR_2 ((uint32_t)0x00000004) /*!< Bit 2 */
1949
1950 /******************* Bit definition for IWDG_RLR register *******************/
1951 #define IWDG_RLR_RL ((uint32_t)0x00000FFF) /*!< Watchdog counter reload value */
1952
1953 /******************* Bit definition for IWDG_SR register ********************/
1954 #define IWDG_SR_PVU ((uint32_t)0x00000001) /*!< Watchdog prescaler value update */
1955 #define IWDG_SR_RVU ((uint32_t)0x00000002) /*!< Watchdog counter reload value update */
1956 #define IWDG_SR_WVU ((uint32_t)0x00000004) /*!< Watchdog counter window value update */
1957
1958 /******************* Bit definition for IWDG_KR register ********************/
1959 #define IWDG_WINR_WIN ((uint32_t)0x00000FFF) /*!< Watchdog counter window value */
1960
1961 /******************************************************************************/
1962 /* */
1963 /* LCD Controller (LCD) */
1964 /* */
1965 /******************************************************************************/
1966
1967 /******************* Bit definition for LCD_CR register *********************/
1968 #define LCD_CR_LCDEN ((uint32_t)0x00000001) /*!< LCD Enable Bit */
1969 #define LCD_CR_VSEL ((uint32_t)0x00000002) /*!< Voltage source selector Bit */
1970
1971 #define LCD_CR_DUTY ((uint32_t)0x0000001C) /*!< DUTY[2:0] bits (Duty selector) */
1972 #define LCD_CR_DUTY_0 ((uint32_t)0x00000004) /*!< Duty selector Bit 0 */
1973 #define LCD_CR_DUTY_1 ((uint32_t)0x00000008) /*!< Duty selector Bit 1 */
1974 #define LCD_CR_DUTY_2 ((uint32_t)0x00000010) /*!< Duty selector Bit 2 */
1975
1976 #define LCD_CR_BIAS ((uint32_t)0x00000060) /*!< BIAS[1:0] bits (Bias selector) */
1977 #define LCD_CR_BIAS_0 ((uint32_t)0x00000020) /*!< Bias selector Bit 0 */
1978 #define LCD_CR_BIAS_1 ((uint32_t)0x00000040) /*!< Bias selector Bit 1 */
1979
1980 /******************* Bit definition for LCD_FCR register ********************/
1981 #define LCD_FCR_HD ((uint32_t)0x00000001) /*!< High Drive Enable Bit */
1982 #define LCD_FCR_SOFIE ((uint32_t)0x00000002) /*!< Start of Frame Interrupt Enable Bit */
1983 #define LCD_FCR_UDDIE ((uint32_t)0x00000008) /*!< Update Display Done Interrupt Enable Bit */
1984
1985 #define LCD_FCR_PON ((uint32_t)0x00000070) /*!< PON[2:0] bits (Puls ON Duration) */
1986 #define LCD_FCR_PON_0 ((uint32_t)0x00000010) /*!< Bit 0 */
1987 #define LCD_FCR_PON_1 ((uint32_t)0x00000020) /*!< Bit 1 */
1988 #define LCD_FCR_PON_2 ((uint32_t)0x00000040) /*!< Bit 2 */
1989
1990 #define LCD_FCR_DEAD ((uint32_t)0x00000380) /*!< DEAD[2:0] bits (DEAD Time) */
1991 #define LCD_FCR_DEAD_0 ((uint32_t)0x00000080) /*!< Bit 0 */
1992 #define LCD_FCR_DEAD_1 ((uint32_t)0x00000100) /*!< Bit 1 */
1993 #define LCD_FCR_DEAD_2 ((uint32_t)0x00000200) /*!< Bit 2 */
1994
1995 #define LCD_FCR_CC ((uint32_t)0x00001C00) /*!< CC[2:0] bits (Contrast Control) */
1996 #define LCD_FCR_CC_0 ((uint32_t)0x00000400) /*!< Bit 0 */
1997 #define LCD_FCR_CC_1 ((uint32_t)0x00000800) /*!< Bit 1 */
1998 #define LCD_FCR_CC_2 ((uint32_t)0x00001000) /*!< Bit 2 */
1999
2000 #define LCD_FCR_BLINKF ((uint32_t)0x0000E000) /*!< BLINKF[2:0] bits (Blink Frequency) */
2001 #define LCD_FCR_BLINKF_0 ((uint32_t)0x00002000) /*!< Bit 0 */
2002 #define LCD_FCR_BLINKF_1 ((uint32_t)0x00004000) /*!< Bit 1 */
2003 #define LCD_FCR_BLINKF_2 ((uint32_t)0x00008000) /*!< Bit 2 */
2004
2005 #define LCD_FCR_BLINK ((uint32_t)0x00030000) /*!< BLINK[1:0] bits (Blink Enable) */
2006 #define LCD_FCR_BLINK_0 ((uint32_t)0x00010000) /*!< Bit 0 */
2007 #define LCD_FCR_BLINK_1 ((uint32_t)0x00020000) /*!< Bit 1 */
2008
2009 #define LCD_FCR_DIV ((uint32_t)0x003C0000) /*!< DIV[3:0] bits (Divider) */
2010 #define LCD_FCR_PS ((uint32_t)0x03C00000) /*!< PS[3:0] bits (Prescaler) */
2011
2012 /******************* Bit definition for LCD_SR register *********************/
2013 #define LCD_SR_ENS ((uint32_t)0x00000001) /*!< LCD Enabled Bit */
2014 #define LCD_SR_SOF ((uint32_t)0x00000002) /*!< Start Of Frame Flag Bit */
2015 #define LCD_SR_UDR ((uint32_t)0x00000004) /*!< Update Display Request Bit */
2016 #define LCD_SR_UDD ((uint32_t)0x00000008) /*!< Update Display Done Flag Bit */
2017 #define LCD_SR_RDY ((uint32_t)0x00000010) /*!< Ready Flag Bit */
2018 #define LCD_SR_FCRSR ((uint32_t)0x00000020) /*!< LCD FCR Register Synchronization Flag Bit */
2019
2020 /******************* Bit definition for LCD_CLR register ********************/
2021 #define LCD_CLR_SOFC ((uint32_t)0x00000002) /*!< Start Of Frame Flag Clear Bit */
2022 #define LCD_CLR_UDDC ((uint32_t)0x00000008) /*!< Update Display Done Flag Clear Bit */
2023
2024 /******************* Bit definition for LCD_RAM register ********************/
2025 #define LCD_RAM_SEGMENT_DATA ((uint32_t)0xFFFFFFFF) /*!< Segment Data Bits */
2026
2027 /******************************************************************************/
2028 /* */
2029 /* Low Power Timer (LPTTIM) */
2030 /* */
2031 /******************************************************************************/
2032 /****************** Bit definition for LPTIM_ISR register *******************/
2033 #define LPTIM_ISR_CMPM ((uint32_t)0x00000001) /*!< Compare match */
2034 #define LPTIM_ISR_ARRM ((uint32_t)0x00000002) /*!< Autoreload match */
2035 #define LPTIM_ISR_EXTTRIG ((uint32_t)0x00000004) /*!< External trigger edge event */
2036 #define LPTIM_ISR_CMPOK ((uint32_t)0x00000008) /*!< Compare register update OK */
2037 #define LPTIM_ISR_ARROK ((uint32_t)0x00000010) /*!< Autoreload register update OK */
2038 #define LPTIM_ISR_UP ((uint32_t)0x00000020) /*!< Counter direction change down to up */
2039 #define LPTIM_ISR_DOWN ((uint32_t)0x00000040) /*!< Counter direction change up to down */
2040
2041 /****************** Bit definition for LPTIM_ICR register *******************/
2042 #define LPTIM_ICR_CMPMCF ((uint32_t)0x00000001) /*!< Compare match Clear Flag */
2043 #define LPTIM_ICR_ARRMCF ((uint32_t)0x00000002) /*!< Autoreload match Clear Flag */
2044 #define LPTIM_ICR_EXTTRIGCF ((uint32_t)0x00000004) /*!< External trigger edge event Clear Flag */
2045 #define LPTIM_ICR_CMPOKCF ((uint32_t)0x00000008) /*!< Compare register update OK Clear Flag */
2046 #define LPTIM_ICR_ARROKCF ((uint32_t)0x00000010) /*!< Autoreload register update OK Clear Flag */
2047 #define LPTIM_ICR_UPCF ((uint32_t)0x00000020) /*!< Counter direction change down to up Clear Flag */
2048 #define LPTIM_ICR_DOWNCF ((uint32_t)0x00000040) /*!< Counter direction change up to down Clear Flag */
2049
2050 /****************** Bit definition for LPTIM_IER register ********************/
2051 #define LPTIM_IER_CMPMIE ((uint32_t)0x00000001) /*!< Compare match Interrupt Enable */
2052 #define LPTIM_IER_ARRMIE ((uint32_t)0x00000002) /*!< Autoreload match Interrupt Enable */
2053 #define LPTIM_IER_EXTTRIGIE ((uint32_t)0x00000004) /*!< External trigger edge event Interrupt Enable */
2054 #define LPTIM_IER_CMPOKIE ((uint32_t)0x00000008) /*!< Compare register update OK Interrupt Enable */
2055 #define LPTIM_IER_ARROKIE ((uint32_t)0x00000010) /*!< Autoreload register update OK Interrupt Enable */
2056 #define LPTIM_IER_UPIE ((uint32_t)0x00000020) /*!< Counter direction change down to up Interrupt Enable */
2057 #define LPTIM_IER_DOWNIE ((uint32_t)0x00000040) /*!< Counter direction change up to down Interrupt Enable */
2058
2059 /****************** Bit definition for LPTIM_CFGR register *******************/
2060 #define LPTIM_CFGR_CKSEL ((uint32_t)0x00000001) /*!< Clock selector */
2061
2062 #define LPTIM_CFGR_CKPOL ((uint32_t)0x00000006) /*!< CKPOL[1:0] bits (Clock polarity) */
2063 #define LPTIM_CFGR_CKPOL_0 ((uint32_t)0x00000002) /*!< Bit 0 */
2064 #define LPTIM_CFGR_CKPOL_1 ((uint32_t)0x00000004) /*!< Bit 1 */
2065
2066 #define LPTIM_CFGR_CKFLT ((uint32_t)0x00000018) /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
2067 #define LPTIM_CFGR_CKFLT_0 ((uint32_t)0x00000008) /*!< Bit 0 */
2068 #define LPTIM_CFGR_CKFLT_1 ((uint32_t)0x00000010) /*!< Bit 1 */
2069
2070 #define LPTIM_CFGR_TRGFLT ((uint32_t)0x000000C0) /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
2071 #define LPTIM_CFGR_TRGFLT_0 ((uint32_t)0x00000040) /*!< Bit 0 */
2072 #define LPTIM_CFGR_TRGFLT_1 ((uint32_t)0x00000080) /*!< Bit 1 */
2073
2074 #define LPTIM_CFGR_PRESC ((uint32_t)0x00000E00) /*!< PRESC[2:0] bits (Clock prescaler) */
2075 #define LPTIM_CFGR_PRESC_0 ((uint32_t)0x00000200) /*!< Bit 0 */
2076 #define LPTIM_CFGR_PRESC_1 ((uint32_t)0x00000400) /*!< Bit 1 */
2077 #define LPTIM_CFGR_PRESC_2 ((uint32_t)0x00000800) /*!< Bit 2 */
2078
2079 #define LPTIM_CFGR_TRIGSEL ((uint32_t)0x0000E000) /*!< TRIGSEL[2:0]] bits (Trigger selector) */
2080 #define LPTIM_CFGR_TRIGSEL_0 ((uint32_t)0x00002000) /*!< Bit 0 */
2081 #define LPTIM_CFGR_TRIGSEL_1 ((uint32_t)0x00004000) /*!< Bit 1 */
2082 #define LPTIM_CFGR_TRIGSEL_2 ((uint32_t)0x00008000) /*!< Bit 2 */
2083
2084 #define LPTIM_CFGR_TRIGEN ((uint32_t)0x00060000) /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
2085 #define LPTIM_CFGR_TRIGEN_0 ((uint32_t)0x00020000) /*!< Bit 0 */
2086 #define LPTIM_CFGR_TRIGEN_1 ((uint32_t)0x00040000) /*!< Bit 1 */
2087
2088 #define LPTIM_CFGR_TIMOUT ((uint32_t)0x00080000) /*!< Timout enable */
2089 #define LPTIM_CFGR_WAVE ((uint32_t)0x00100000) /*!< Waveform shape */
2090 #define LPTIM_CFGR_WAVPOL ((uint32_t)0x00200000) /*!< Waveform shape polarity */
2091 #define LPTIM_CFGR_PRELOAD ((uint32_t)0x00400000) /*!< Reg update mode */
2092 #define LPTIM_CFGR_COUNTMODE ((uint32_t)0x00800000) /*!< Counter mode enable */
2093 #define LPTIM_CFGR_ENC ((uint32_t)0x01000000) /*!< Encoder mode enable */
2094
2095 /****************** Bit definition for LPTIM_CR register ********************/
2096 #define LPTIM_CR_ENABLE ((uint32_t)0x00000001) /*!< LPTIMer enable */
2097 #define LPTIM_CR_SNGSTRT ((uint32_t)0x00000002) /*!< Timer start in single mode */
2098 #define LPTIM_CR_CNTSTRT ((uint32_t)0x00000004) /*!< Timer start in continuous mode */
2099
2100 /****************** Bit definition for LPTIM_CMP register *******************/
2101 #define LPTIM_CMP_CMP ((uint32_t)0x0000FFFF) /*!< Compare register */
2102
2103 /****************** Bit definition for LPTIM_ARR register *******************/
2104 #define LPTIM_ARR_ARR ((uint32_t)0x0000FFFF) /*!< Auto reload register */
2105
2106 /****************** Bit definition for LPTIM_CNT register *******************/
2107 #define LPTIM_CNT_CNT ((uint32_t)0x0000FFFF) /*!< Counter register */
2108
2109 /******************************************************************************/
2110 /* */
2111 /* MIFARE Firewall */
2112 /* */
2113 /******************************************************************************/
2114
2115 /*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
2116 #define FW_CSSA_ADD ((uint32_t)0x00FFFF00) /*!< Code Segment Start Address */
2117 #define FW_CSL_LENG ((uint32_t)0x003FFF00) /*!< Code Segment Length */
2118 #define FW_NVDSSA_ADD ((uint32_t)0x00FFFF00) /*!< Non Volatile Dat Segment Start Address */
2119 #define FW_NVDSL_LENG ((uint32_t)0x003FFF00) /*!< Non Volatile Data Segment Length */
2120 #define FW_VDSSA_ADD ((uint32_t)0x0000FFC0) /*!< Volatile Data Segment Start Address */
2121 #define FW_VDSL_LENG ((uint32_t)0x0000FFC0) /*!< Volatile Data Segment Length */
2122
2123 /**************************Bit definition for CR register *********************/
2124 #define FW_CR_FPA ((uint32_t)0x00000001) /*!< Firewall Pre Arm*/
2125 #define FW_CR_VDS ((uint32_t)0x00000002) /*!< Volatile Data Sharing*/
2126 #define FW_CR_VDE ((uint32_t)0x00000004) /*!< Volatile Data Execution*/
2127
2128 /******************************************************************************/
2129 /* */
2130 /* Power Control (PWR) */
2131 /* */
2132 /******************************************************************************/
2133
2134 /******************** Bit definition for PWR_CR register ********************/
2135 #define PWR_CR_LPSDSR ((uint32_t)0x00000001) /*!< Low-power deepsleep/sleep/low power run */
2136 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
2137 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
2138 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
2139 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
2140
2141 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
2142 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
2143 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
2144 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
2145
2146 /*!< PVD level configuration */
2147 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
2148 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
2149 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
2150 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
2151 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
2152 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
2153 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
2154 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
2155
2156 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
2157 #define PWR_CR_ULP ((uint32_t)0x00000200) /*!< Ultra Low Power mode */
2158 #define PWR_CR_FWU ((uint32_t)0x00000400) /*!< Fast wakeup */
2159
2160 #define PWR_CR_VOS ((uint32_t)0x00001800) /*!< VOS[1:0] bits (Voltage scaling range selection) */
2161 #define PWR_CR_VOS_0 ((uint32_t)0x00000800) /*!< Bit 0 */
2162 #define PWR_CR_VOS_1 ((uint32_t)0x00001000) /*!< Bit 1 */
2163 #define PWR_CR_DSEEKOFF ((uint32_t)0x00002000) /*!< Deep Sleep mode with EEPROM kept Off */
2164 #define PWR_CR_LPRUN ((uint32_t)0x00004000) /*!< Low power run mode */
2165
2166 /******************* Bit definition for PWR_CSR register ********************/
2167 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
2168 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
2169 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
2170 #define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008) /*!< Internal voltage reference (VREFINT) ready flag */
2171 #define PWR_CSR_VOSF ((uint32_t)0x00000010) /*!< Voltage Scaling select flag */
2172 #define PWR_CSR_REGLPF ((uint32_t)0x00000020) /*!< Regulator LP flag */
2173
2174 #define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */
2175 #define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /*!< Enable WKUP pin 2 */
2176 #define PWR_CSR_EWUP3 ((uint32_t)0x00000400) /*!< Enable WKUP pin 3 */
2177
2178 /******************************************************************************/
2179 /* */
2180 /* Reset and Clock Control */
2181 /* */
2182 /******************************************************************************/
2183
2184 /******************** Bit definition for RCC_CR register ********************/
2185 #define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
2186 #define RCC_CR_HSIKERON ((uint32_t)0x00000002) /*!< Internal High Speed clock enable for some IPs Kernel */
2187 #define RCC_CR_HSIRDY ((uint32_t)0x00000004) /*!< Internal High Speed clock ready flag */
2188 #define RCC_CR_HSIDIVEN ((uint32_t)0x00000008) /*!< Internal High Speed clock divider enable */
2189 #define RCC_CR_HSIDIVF ((uint32_t)0x00000010) /*!< Internal High Speed clock divider flag */
2190 #define RCC_CR_HSIOUTEN ((uint32_t)0x00000020) /*!< Internal High Speed clock out enable */
2191 #define RCC_CR_MSION ((uint32_t)0x00000100) /*!< Internal Multi Speed clock enable */
2192 #define RCC_CR_MSIRDY ((uint32_t)0x00000200) /*!< Internal Multi Speed clock ready flag */
2193 #define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
2194 #define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
2195 #define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
2196 #define RCC_CR_CSSHSEON ((uint32_t)0x00080000) /*!< HSE Clock Security System enable */
2197 #define RCC_CR_RTCPRE ((uint32_t)0x00300000) /*!< RTC/LCD prescaler [1:0] bits */
2198 #define RCC_CR_RTCPRE_0 ((uint32_t)0x00100000) /*!< RTC/LCD prescaler Bit 0 */
2199 #define RCC_CR_RTCPRE_1 ((uint32_t)0x00200000) /*!< RTC/LCD prescaler Bit 1 */
2200 #define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
2201 #define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
2202
2203 /******************** Bit definition for RCC_ICSCR register *****************/
2204 #define RCC_ICSCR_HSICAL ((uint32_t)0x000000FF) /*!< Internal High Speed clock Calibration */
2205 #define RCC_ICSCR_HSITRIM ((uint32_t)0x00001F00) /*!< Internal High Speed clock trimming */
2206
2207 #define RCC_ICSCR_MSIRANGE ((uint32_t)0x0000E000) /*!< Internal Multi Speed clock Range */
2208 #define RCC_ICSCR_MSIRANGE_0 ((uint32_t)0x00000000) /*!< Internal Multi Speed clock Range 65.536 KHz */
2209 #define RCC_ICSCR_MSIRANGE_1 ((uint32_t)0x00002000) /*!< Internal Multi Speed clock Range 131.072 KHz */
2210 #define RCC_ICSCR_MSIRANGE_2 ((uint32_t)0x00004000) /*!< Internal Multi Speed clock Range 262.144 KHz */
2211 #define RCC_ICSCR_MSIRANGE_3 ((uint32_t)0x00006000) /*!< Internal Multi Speed clock Range 524.288 KHz */
2212 #define RCC_ICSCR_MSIRANGE_4 ((uint32_t)0x00008000) /*!< Internal Multi Speed clock Range 1.048 MHz */
2213 #define RCC_ICSCR_MSIRANGE_5 ((uint32_t)0x0000A000) /*!< Internal Multi Speed clock Range 2.097 MHz */
2214 #define RCC_ICSCR_MSIRANGE_6 ((uint32_t)0x0000C000) /*!< Internal Multi Speed clock Range 4.194 MHz */
2215 #define RCC_ICSCR_MSICAL ((uint32_t)0x00FF0000) /*!< Internal Multi Speed clock Calibration */
2216 #define RCC_ICSCR_MSITRIM ((uint32_t)0xFF000000) /*!< Internal Multi Speed clock trimming */
2217
2218 /******************** Bit definition for RCC_CRRCR register *****************/
2219 #define RCC_CRRCR_HSI48ON ((uint32_t)0x00000001) /*!< HSI 48MHz clock enable */
2220 #define RCC_CRRCR_HSI48RDY ((uint32_t)0x00000002) /*!< HSI 48MHz clock ready flag */
2221 #define RCC_CRRCR_HSI48DIV6OUTEN ((uint32_t)0x00000004) /*!< HSI 48MHz DIV6 out enable */
2222 #define RCC_CRRCR_HSI48CAL ((uint32_t)0x0000FF00) /*!< HSI 48MHz clock Calibration */
2223
2224 /******************* Bit definition for RCC_CFGR register *******************/
2225 /*!< SW configuration */
2226 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
2227 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
2228 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
2229
2230 #define RCC_CFGR_SW_MSI ((uint32_t)0x00000000) /*!< MSI selected as system clock */
2231 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000001) /*!< HSI selected as system clock */
2232 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000002) /*!< HSE selected as system clock */
2233 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000003) /*!< PLL selected as system clock */
2234
2235 /*!< SWS configuration */
2236 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
2237 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
2238 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
2239
2240 #define RCC_CFGR_SWS_MSI ((uint32_t)0x00000000) /*!< MSI oscillator used as system clock */
2241 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000004) /*!< HSI oscillator used as system clock */
2242 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000008) /*!< HSE oscillator used as system clock */
2243 #define RCC_CFGR_SWS_PLL ((uint32_t)0x0000000C) /*!< PLL used as system clock */
2244
2245 /*!< HPRE configuration */
2246 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
2247 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
2248 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
2249 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
2250 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
2251
2252 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
2253 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
2254 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
2255 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
2256 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
2257 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
2258 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
2259 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
2260 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
2261
2262 /*!< PPRE1 configuration */
2263 #define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */
2264 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
2265 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
2266 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
2267
2268 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
2269 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
2270 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
2271 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
2272 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
2273
2274 /*!< PPRE2 configuration */
2275 #define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */
2276 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */
2277 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */
2278 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */
2279
2280 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
2281 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
2282 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
2283 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
2284 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
2285
2286 #define RCC_CFGR_STOPWUCK ((uint32_t)0x00008000) /*!< Wake Up from Stop Clock selection */
2287
2288 /*!< PLL entry clock source*/
2289 #define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
2290
2291 #define RCC_CFGR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI as PLL entry clock source */
2292 #define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE as PLL entry clock source */
2293
2294
2295 /*!< PLLMUL configuration */
2296 #define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
2297 #define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
2298 #define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
2299 #define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
2300 #define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
2301
2302 #define RCC_CFGR_PLLMUL3 ((uint32_t)0x00000000) /*!< PLL input clock * 3 */
2303 #define RCC_CFGR_PLLMUL4 ((uint32_t)0x00040000) /*!< PLL input clock * 4 */
2304 #define RCC_CFGR_PLLMUL6 ((uint32_t)0x00080000) /*!< PLL input clock * 6 */
2305 #define RCC_CFGR_PLLMUL8 ((uint32_t)0x000C0000) /*!< PLL input clock * 8 */
2306 #define RCC_CFGR_PLLMUL12 ((uint32_t)0x00100000) /*!< PLL input clock * 12 */
2307 #define RCC_CFGR_PLLMUL16 ((uint32_t)0x00140000) /*!< PLL input clock * 16 */
2308 #define RCC_CFGR_PLLMUL24 ((uint32_t)0x00180000) /*!< PLL input clock * 24 */
2309 #define RCC_CFGR_PLLMUL32 ((uint32_t)0x001C0000) /*!< PLL input clock * 32 */
2310 #define RCC_CFGR_PLLMUL48 ((uint32_t)0x00200000) /*!< PLL input clock * 48 */
2311
2312 /*!< PLLDIV configuration */
2313 #define RCC_CFGR_PLLDIV ((uint32_t)0x00C00000) /*!< PLLDIV[1:0] bits (PLL Output Division) */
2314 #define RCC_CFGR_PLLDIV_0 ((uint32_t)0x00400000) /*!< Bit0 */
2315 #define RCC_CFGR_PLLDIV_1 ((uint32_t)0x00800000) /*!< Bit1 */
2316
2317 #define RCC_CFGR_PLLDIV2 ((uint32_t)0x00400000) /*!< PLL clock output = CKVCO / 2 */
2318 #define RCC_CFGR_PLLDIV3 ((uint32_t)0x00800000) /*!< PLL clock output = CKVCO / 3 */
2319 #define RCC_CFGR_PLLDIV4 ((uint32_t)0x00C00000) /*!< PLL clock output = CKVCO / 4 */
2320
2321 /*!< MCO configuration */
2322 #define RCC_CFGR_MCOSEL ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */
2323 #define RCC_CFGR_MCOSEL_0 ((uint32_t)0x01000000) /*!< Bit 0 */
2324 #define RCC_CFGR_MCOSEL_1 ((uint32_t)0x02000000) /*!< Bit 1 */
2325 #define RCC_CFGR_MCOSEL_2 ((uint32_t)0x04000000) /*!< Bit 2 */
2326 #define RCC_CFGR_MCOSEL_3 ((uint32_t)0x08000000) /*!< Bit 3 */
2327
2328 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
2329 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x01000000) /*!< System clock selected as MCO source */
2330 #define RCC_CFGR_MCO_HSI ((uint32_t)0x02000000) /*!< Internal 16 MHz RC oscillator clock selected */
2331 #define RCC_CFGR_MCO_MSI ((uint32_t)0x03000000) /*!< Internal Medium Speed RC oscillator clock selected */
2332 #define RCC_CFGR_MCO_HSE ((uint32_t)0x04000000) /*!< External 1-25 MHz oscillator clock selected */
2333 #define RCC_CFGR_MCO_PLL ((uint32_t)0x05000000) /*!< PLL clock divided */
2334 #define RCC_CFGR_MCO_LSI ((uint32_t)0x06000000) /*!< LSI selected */
2335 #define RCC_CFGR_MCO_LSE ((uint32_t)0x07000000) /*!< LSE selected */
2336 #define RCC_CFGR_MCO_HSI48 ((uint32_t)0x08000000) /*!< HSI48 clock selected as MCO source */
2337
2338 #define RCC_CFGR_MCO_PRE ((uint32_t)0x70000000) /*!< MCO prescaler */
2339 #define RCC_CFGR_MCO_PRE_1 ((uint32_t)0x00000000) /*!< MCO is divided by 1 */
2340 #define RCC_CFGR_MCO_PRE_2 ((uint32_t)0x10000000) /*!< MCO is divided by 2 */
2341 #define RCC_CFGR_MCO_PRE_4 ((uint32_t)0x20000000) /*!< MCO is divided by 4 */
2342 #define RCC_CFGR_MCO_PRE_8 ((uint32_t)0x30000000) /*!< MCO is divided by 8 */
2343 #define RCC_CFGR_MCO_PRE_16 ((uint32_t)0x40000000) /*!< MCO is divided by 16 */
2344
2345 /*!<****************** Bit definition for RCC_CIER register ********************/
2346 #define RCC_CIER_LSIRDYIE ((uint32_t)0x00000001) /*!< LSI Ready Interrupt Enable */
2347 #define RCC_CIER_LSERDYIE ((uint32_t)0x00000002) /*!< LSE Ready Interrupt Enable */
2348 #define RCC_CIER_HSIRDYIE ((uint32_t)0x00000004) /*!< HSI Ready Interrupt Enable */
2349 #define RCC_CIER_HSERDYIE ((uint32_t)0x00000008) /*!< HSE Ready Interrupt Enable */
2350 #define RCC_CIER_PLLRDYIE ((uint32_t)0x00000010) /*!< PLL Ready Interrupt Enable */
2351 #define RCC_CIER_MSIRDYIE ((uint32_t)0x00000020) /*!< MSI Ready Interrupt Enable */
2352 #define RCC_CIER_HSI48RDYIE ((uint32_t)0x00000040) /*!< HSI48 Ready Interrupt Enable */
2353 #define RCC_CIER_LSECSSIE ((uint32_t)0x00000080) /*!< LSE CSS Interrupt Enable */
2354
2355 /*!<****************** Bit definition for RCC_CIFR register ********************/
2356 #define RCC_CIFR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
2357 #define RCC_CIFR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
2358 #define RCC_CIFR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
2359 #define RCC_CIFR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
2360 #define RCC_CIFR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
2361 #define RCC_CIFR_MSIRDYF ((uint32_t)0x00000020) /*!< MSI Ready Interrupt flag */
2362 #define RCC_CIFR_HSI48RDYF ((uint32_t)0x00000040) /*!< HSI48 Ready Interrupt flag */
2363 #define RCC_CIFR_LSECSSF ((uint32_t)0x00000080) /*!< LSE Clock Security System Interrupt flag */
2364 #define RCC_CIFR_CSSF ((uint32_t)0x00000100) /*!< Clock Security System Interrupt flag */
2365
2366 /*!<****************** Bit definition for RCC_CICR register ********************/
2367 #define RCC_CICR_LSIRDYC ((uint32_t)0x00000001) /*!< LSI Ready Interrupt Clear */
2368 #define RCC_CICR_LSERDYC ((uint32_t)0x00000002) /*!< LSE Ready Interrupt Clear */
2369 #define RCC_CICR_HSIRDYC ((uint32_t)0x00000004) /*!< HSI Ready Interrupt Clear */
2370 #define RCC_CICR_HSERDYC ((uint32_t)0x00000008) /*!< HSE Ready Interrupt Clear */
2371 #define RCC_CICR_PLLRDYC ((uint32_t)0x00000010) /*!< PLL Ready Interrupt Clear */
2372 #define RCC_CICR_MSIRDYC ((uint32_t)0x00000020) /*!< MSI Ready Interrupt Clear */
2373 #define RCC_CICR_HSI48RDYC ((uint32_t)0x00000040) /*!< HSI48 Ready Interrupt Clear */
2374 #define RCC_CICR_LSECSSC ((uint32_t)0x00000080) /*!< LSE Clock Security System Interrupt Clear */
2375 #define RCC_CICR_CSSC ((uint32_t)0x00000100) /*!< Clock Security System Interrupt Clear */
2376
2377 /***************** Bit definition for RCC_IOPRSTR register ******************/
2378 #define RCC_IOPRSTR_GPIOARST ((uint32_t)0x00000001) /*!< GPIO port A reset */
2379 #define RCC_IOPRSTR_GPIOBRST ((uint32_t)0x00000002) /*!< GPIO port B reset */
2380 #define RCC_IOPRSTR_GPIOCRST ((uint32_t)0x00000004) /*!< GPIO port C reset */
2381 #define RCC_IOPRSTR_GPIODRST ((uint32_t)0x00000008) /*!< GPIO port D reset */
2382 #define RCC_IOPRSTR_GPIOERST ((uint32_t)0x00000010) /*!< GPIO port E reset */
2383 #define RCC_IOPRSTR_GPIOHRST ((uint32_t)0x00000080) /*!< GPIO port H reset */
2384
2385 /****************** Bit definition for RCC_AHBRST register ******************/
2386 #define RCC_AHBRSTR_DMA1RST ((uint32_t)0x00000001) /*!< DMA1 reset */
2387 #define RCC_AHBRSTR_MIFRST ((uint32_t)0x00000100) /*!< Memory interface reset reset */
2388 #define RCC_AHBRSTR_CRCRST ((uint32_t)0x00001000) /*!< CRC reset */
2389 #define RCC_AHBRSTR_TSCRST ((uint32_t)0x00010000) /*!< TSC reset */
2390 #define RCC_AHBRSTR_RNGRST ((uint32_t)0x00100000) /*!< RNG reset */
2391
2392 /***************** Bit definition for RCC_APB2RSTR register *****************/
2393 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG clock reset */
2394 #define RCC_APB2RSTR_TIM21RST ((uint32_t)0x00000004) /*!< TIM21 clock reset */
2395 #define RCC_APB2RSTR_TIM22RST ((uint32_t)0x00000020) /*!< TIM22 clock reset */
2396 #define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC1 clock reset */
2397 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 clock reset */
2398 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 clock reset */
2399 #define RCC_APB2RSTR_DBGMCURST ((uint32_t)0x00400000) /*!< DBGMCU clock reset */
2400
2401 /***************** Bit definition for RCC_APB1RSTR register *****************/
2402 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 clock reset */
2403 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 clock reset */
2404 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 clock reset */
2405 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 clock reset */
2406 #define RCC_APB1RSTR_LCDRST ((uint32_t)0x00000200) /*!< LCD clock reset */
2407 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog clock reset */
2408 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI2 clock reset */
2409 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 clock reset */
2410 #define RCC_APB1RSTR_LPUART1RST ((uint32_t)0x00040000) /*!< LPUART1 clock reset */
2411 #define RCC_APB1RSTR_USART4RST ((uint32_t)0x00080000) /*!< USART4 clock reset */
2412 #define RCC_APB1RSTR_USART5RST ((uint32_t)0x00100000) /*!< USART5 clock reset */
2413 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 clock reset */
2414 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 clock reset */
2415 #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB clock reset */
2416 #define RCC_APB1RSTR_CRSRST ((uint32_t)0x08000000) /*!< CRS clock reset */
2417 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR clock reset */
2418 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC clock reset */
2419 #define RCC_APB1RSTR_I2C3RST ((uint32_t)0x40000000) /*!< I2C 3 clock reset */
2420 #define RCC_APB1RSTR_LPTIM1RST ((uint32_t)0x80000000) /*!< LPTIM1 clock reset */
2421
2422 /***************** Bit definition for RCC_IOPENR register ******************/
2423 #define RCC_IOPENR_GPIOAEN ((uint32_t)0x00000001) /*!< GPIO port A clock enable */
2424 #define RCC_IOPENR_GPIOBEN ((uint32_t)0x00000002) /*!< GPIO port B clock enable */
2425 #define RCC_IOPENR_GPIOCEN ((uint32_t)0x00000004) /*!< GPIO port C clock enable */
2426 #define RCC_IOPENR_GPIODEN ((uint32_t)0x00000008) /*!< GPIO port D clock enable */
2427 #define RCC_IOPENR_GPIOEEN ((uint32_t)0x00000010) /*!< GPIO port E clock enable */
2428 #define RCC_IOPENR_GPIOHEN ((uint32_t)0x00000080) /*!< GPIO port H clock enable */
2429
2430 /***************** Bit definition for RCC_AHBENR register ******************/
2431 #define RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) /*!< DMA1 clock enable */
2432 #define RCC_AHBENR_MIFEN ((uint32_t)0x00000100) /*!< NVM interface clock enable bit */
2433 #define RCC_AHBENR_CRCEN ((uint32_t)0x00001000) /*!< CRC clock enable */
2434 #define RCC_AHBENR_TSCEN ((uint32_t)0x00010000) /*!< TSC clock enable */
2435 #define RCC_AHBENR_RNGEN ((uint32_t)0x00100000) /*!< RNG clock enable */
2436
2437 /***************** Bit definition for RCC_APB2ENR register ******************/
2438 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) /*!< SYSCFG clock enable */
2439 #define RCC_APB2ENR_TIM21EN ((uint32_t)0x00000004) /*!< TIM21 clock enable */
2440 #define RCC_APB2ENR_TIM22EN ((uint32_t)0x00000020) /*!< TIM22 clock enable */
2441 #define RCC_APB2ENR_MIFIEN ((uint32_t)0x00000080) /*!< MiFare Firewall clock enable */
2442 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC1 clock enable */
2443 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
2444 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
2445 #define RCC_APB2ENR_DBGMCUEN ((uint32_t)0x00400000) /*!< DBGMCU clock enable */
2446
2447 /***************** Bit definition for RCC_APB1ENR register ******************/
2448 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enable */
2449 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
2450 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
2451 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
2452 #define RCC_APB1ENR_LCDEN ((uint32_t)0x00000200) /*!< LCD clock enable */
2453 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
2454 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI2 clock enable */
2455 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART2 clock enable */
2456 #define RCC_APB1ENR_LPUART1EN ((uint32_t)0x00040000) /*!< LPUART1 clock enable */
2457 #define RCC_APB1ENR_USART4EN ((uint32_t)0x00080000) /*!< USART4 clock enable */
2458 #define RCC_APB1ENR_USART5EN ((uint32_t)0x00100000) /*!< USART5 clock enable */
2459 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C1 clock enable */
2460 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C2 clock enable */
2461 #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */
2462 #define RCC_APB1ENR_CRSEN ((uint32_t)0x08000000) /*!< CRS clock enable */
2463 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */
2464 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC clock enable */
2465 #define RCC_APB1ENR_I2C3EN ((uint32_t)0x40000000) /*!< I2C3 clock enable */
2466 #define RCC_APB1ENR_LPTIM1EN ((uint32_t)0x80000000) /*!< LPTIM1 clock enable */
2467
2468 /****************** Bit definition for RCC_IOPSMENR register ****************/
2469 #define RCC_IOPSMENR_GPIOASMEN ((uint32_t)0x00000001) /*!< GPIO port A clock enabled in sleep mode */
2470 #define RCC_IOPSMENR_GPIOBSMEN ((uint32_t)0x00000002) /*!< GPIO port B clock enabled in sleep mode */
2471 #define RCC_IOPSMENR_GPIOCSMEN ((uint32_t)0x00000004) /*!< GPIO port C clock enabled in sleep mode */
2472 #define RCC_IOPSMENR_GPIODSMEN ((uint32_t)0x00000008) /*!< GPIO port D clock enabled in sleep mode */
2473 #define RCC_IOPSMENR_GPIOESMEN ((uint32_t)0x00000010) /*!< GPIO port E clock enabled in sleep mode */
2474 #define RCC_IOPSMENR_GPIOHSMEN ((uint32_t)0x00000080) /*!< GPIO port H clock enabled in sleep mode */
2475
2476 /***************** Bit definition for RCC_AHBSMENR register ******************/
2477 #define RCC_AHBSMENR_DMA1SMEN ((uint32_t)0x00000001) /*!< DMA1 clock enabled in sleep mode */
2478 #define RCC_AHBSMENR_MIFSMEN ((uint32_t)0x00000100) /*!< NVM interface clock enable during sleep mode */
2479 #define RCC_AHBSMENR_SRAMSMEN ((uint32_t)0x00000200) /*!< SRAM clock enabled in sleep mode */
2480 #define RCC_AHBSMENR_CRCSMEN ((uint32_t)0x00001000) /*!< CRC clock enabled in sleep mode */
2481 #define RCC_AHBSMENR_TSCSMEN ((uint32_t)0x00010000) /*!< TSC clock enabled in sleep mode */
2482 #define RCC_AHBSMENR_RNGSMEN ((uint32_t)0x00100000) /*!< RNG clock enabled in sleep mode */
2483
2484 /***************** Bit definition for RCC_APB2SMENR register ******************/
2485 #define RCC_APB2SMENR_SYSCFGSMEN ((uint32_t)0x00000001) /*!< SYSCFG clock enabled in sleep mode */
2486 #define RCC_APB2SMENR_TIM21SMEN ((uint32_t)0x00000004) /*!< TIM21 clock enabled in sleep mode */
2487 #define RCC_APB2SMENR_TIM22SMEN ((uint32_t)0x00000020) /*!< TIM22 clock enabled in sleep mode */
2488 #define RCC_APB2SMENR_ADC1SMEN ((uint32_t)0x00000200) /*!< ADC1 clock enabled in sleep mode */
2489 #define RCC_APB2SMENR_SPI1SMEN ((uint32_t)0x00001000) /*!< SPI1 clock enabled in sleep mode */
2490 #define RCC_APB2SMENR_USART1SMEN ((uint32_t)0x00004000) /*!< USART1 clock enabled in sleep mode */
2491 #define RCC_APB2SMENR_DBGMCUSMEN ((uint32_t)0x00400000) /*!< DBGMCU clock enabled in sleep mode */
2492
2493 /***************** Bit definition for RCC_APB1SMENR register ******************/
2494 #define RCC_APB1SMENR_TIM2SMEN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled in sleep mode */
2495 #define RCC_APB1SMENR_TIM3SMEN ((uint32_t)0x00000002) /*!< Timer 3 clock enabled in sleep mode */
2496 #define RCC_APB1SMENR_TIM6SMEN ((uint32_t)0x00000010) /*!< Timer 6 clock enabled in sleep mode */
2497 #define RCC_APB1SMENR_TIM7SMEN ((uint32_t)0x00000020) /*!< Timer 7 clock enabled in sleep mode */
2498 #define RCC_APB1SMENR_LCDSMEN ((uint32_t)0x00000200) /*!< LCD clock enabled in sleep mode */
2499 #define RCC_APB1SMENR_WWDGSMEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enabled in sleep mode */
2500 #define RCC_APB1SMENR_SPI2SMEN ((uint32_t)0x00004000) /*!< SPI2 clock enabled in sleep mode */
2501 #define RCC_APB1SMENR_USART2SMEN ((uint32_t)0x00020000) /*!< USART2 clock enabled in sleep mode */
2502 #define RCC_APB1SMENR_LPUART1SMEN ((uint32_t)0x00040000) /*!< LPUART1 clock enabled in sleep mode */
2503 #define RCC_APB1SMENR_USART4SMEN ((uint32_t)0x00080000) /*!< USART4 clock enabled in sleep mode */
2504 #define RCC_APB1SMENR_USART5SMEN ((uint32_t)0x00100000) /*!< USART5 clock enabled in sleep mode */
2505 #define RCC_APB1SMENR_I2C1SMEN ((uint32_t)0x00200000) /*!< I2C1 clock enabled in sleep mode */
2506 #define RCC_APB1SMENR_I2C2SMEN ((uint32_t)0x00400000) /*!< I2C2 clock enabled in sleep mode */
2507 #define RCC_APB1SMENR_USBSMEN ((uint32_t)0x00800000) /*!< USB clock enabled in sleep mode */
2508 #define RCC_APB1SMENR_CRSSMEN ((uint32_t)0x08000000) /*!< CRS clock enabled in sleep mode */
2509 #define RCC_APB1SMENR_PWRSMEN ((uint32_t)0x10000000) /*!< PWR clock enabled in sleep mode */
2510 #define RCC_APB1SMENR_DACSMEN ((uint32_t)0x20000000) /*!< DAC clock enabled in sleep mode */
2511 #define RCC_APB1SMENR_I2C3SMEN ((uint32_t)0x40000000) /*!< I2C3 clock enabled in sleep mode */
2512 #define RCC_APB1SMENR_LPTIM1SMEN ((uint32_t)0x80000000) /*!< LPTIM1 clock enabled in sleep mode */
2513
2514 /******************* Bit definition for RCC_CCIPR register *******************/
2515 /*!< USART1 Clock source selection */
2516 #define RCC_CCIPR_USART1SEL ((uint32_t)0x00000003) /*!< USART1SEL[1:0] bits */
2517 #define RCC_CCIPR_USART1SEL_0 ((uint32_t)0x00000001) /*!< Bit 0 */
2518 #define RCC_CCIPR_USART1SEL_1 ((uint32_t)0x00000002) /*!< Bit 1 */
2519
2520 /*!< USART2 Clock source selection */
2521 #define RCC_CCIPR_USART2SEL ((uint32_t)0x0000000C) /*!< USART2SEL[1:0] bits */
2522 #define RCC_CCIPR_USART2SEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
2523 #define RCC_CCIPR_USART2SEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
2524
2525 /*!< LPUART1 Clock source selection */
2526 #define RCC_CCIPR_LPUART1SEL ((uint32_t)0x0000C00) /*!< LPUART1SEL[1:0] bits */
2527 #define RCC_CCIPR_LPUART1SEL_0 ((uint32_t)0x0000400) /*!< Bit 0 */
2528 #define RCC_CCIPR_LPUART1SEL_1 ((uint32_t)0x0000800) /*!< Bit 1 */
2529
2530 /*!< I2C1 Clock source selection */
2531 #define RCC_CCIPR_I2C1SEL ((uint32_t)0x00003000) /*!< I2C1SEL [1:0] bits */
2532 #define RCC_CCIPR_I2C1SEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
2533 #define RCC_CCIPR_I2C1SEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
2534
2535 /*!< I2C3 Clock source selection */
2536 #define RCC_CCIPR_I2C3SEL ((uint32_t)0x00030000) /*!< I2C3SEL [1:0] bits */
2537 #define RCC_CCIPR_I2C3SEL_0 ((uint32_t)0x00010000) /*!< Bit 0 */
2538 #define RCC_CCIPR_I2C3SEL_1 ((uint32_t)0x00020000) /*!< Bit 1 */
2539
2540 /*!< LPTIM1 Clock source selection */
2541 #define RCC_CCIPR_LPTIM1SEL ((uint32_t)0x000C0000) /*!< LPTIM1SEL [1:0] bits */
2542 #define RCC_CCIPR_LPTIM1SEL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
2543 #define RCC_CCIPR_LPTIM1SEL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
2544
2545 /*!< HSI48 Clock source selection */
2546 #define RCC_CCIPR_HSI48SEL ((uint32_t)0x04000000) /*!< HSI48 RC clock source selection bit for USB and RNG*/
2547
2548 /* Bit name alias maintained for legacy */
2549 #define RCC_CCIPR_HSI48MSEL RCC_CCIPR_HSI48SEL
2550
2551 /******************* Bit definition for RCC_CSR register *******************/
2552 #define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
2553 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
2554
2555 #define RCC_CSR_LSEON ((uint32_t)0x00000100) /*!< External Low Speed oscillator enable */
2556 #define RCC_CSR_LSERDY ((uint32_t)0x00000200) /*!< External Low Speed oscillator Ready */
2557 #define RCC_CSR_LSEBYP ((uint32_t)0x00000400) /*!< External Low Speed oscillator Bypass */
2558
2559 #define RCC_CSR_LSEDRV ((uint32_t)0x00001800) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
2560 #define RCC_CSR_LSEDRV_0 ((uint32_t)0x00000800) /*!< Bit 0 */
2561 #define RCC_CSR_LSEDRV_1 ((uint32_t)0x00001000) /*!< Bit 1 */
2562
2563 #define RCC_CSR_LSECSSON ((uint32_t)0x00002000) /*!< External Low Speed oscillator CSS Enable */
2564 #define RCC_CSR_LSECSSD ((uint32_t)0x00004000) /*!< External Low Speed oscillator CSS Detected */
2565
2566 /*!< RTC congiguration */
2567 #define RCC_CSR_RTCSEL ((uint32_t)0x00030000) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
2568 #define RCC_CSR_RTCSEL_0 ((uint32_t)0x00010000) /*!< Bit 0 */
2569 #define RCC_CSR_RTCSEL_1 ((uint32_t)0x00020000) /*!< Bit 1 */
2570
2571 #define RCC_CSR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
2572 #define RCC_CSR_RTCSEL_LSE ((uint32_t)0x00010000) /*!< LSE oscillator clock used as RTC clock */
2573 #define RCC_CSR_RTCSEL_LSI ((uint32_t)0x00020000) /*!< LSI oscillator clock used as RTC clock */
2574 #define RCC_CSR_RTCSEL_HSE ((uint32_t)0x00030000) /*!< HSE oscillator clock used as RTC clock */
2575
2576 #define RCC_CSR_RTCEN ((uint32_t)0x00040000) /*!< RTC clock enable */
2577 #define RCC_CSR_RTCRST ((uint32_t)0x00080000) /*!< RTC software reset */
2578
2579 #define RCC_CSR_RMVF ((uint32_t)0x00800000) /*!< Remove reset flag */
2580 #define RCC_CSR_FWRSTF ((uint32_t)0x01000000) /*!< Mifare Firewall reset flag */
2581 #define RCC_CSR_OBL ((uint32_t)0x02000000) /*!< OBL reset flag */
2582 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
2583 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
2584 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
2585 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
2586 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
2587 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
2588
2589 /******************************************************************************/
2590 /* */
2591 /* RNG */
2592 /* */
2593 /******************************************************************************/
2594 /******************** Bits definition for RNG_CR register *******************/
2595 #define RNG_CR_RNGEN ((uint32_t)0x00000004)
2596 #define RNG_CR_IE ((uint32_t)0x00000008)
2597
2598 /******************** Bits definition for RNG_SR register *******************/
2599 #define RNG_SR_DRDY ((uint32_t)0x00000001)
2600 #define RNG_SR_CECS ((uint32_t)0x00000002)
2601 #define RNG_SR_SECS ((uint32_t)0x00000004)
2602 #define RNG_SR_CEIS ((uint32_t)0x00000020)
2603 #define RNG_SR_SEIS ((uint32_t)0x00000040)
2604
2605 /******************************************************************************/
2606 /* */
2607 /* Real-Time Clock (RTC) */
2608 /* */
2609 /******************************************************************************/
2610 /******************** Bits definition for RTC_TR register *******************/
2611 #define RTC_TR_PM ((uint32_t)0x00400000) /*!< */
2612 #define RTC_TR_HT ((uint32_t)0x00300000) /*!< */
2613 #define RTC_TR_HT_0 ((uint32_t)0x00100000) /*!< */
2614 #define RTC_TR_HT_1 ((uint32_t)0x00200000) /*!< */
2615 #define RTC_TR_HU ((uint32_t)0x000F0000) /*!< */
2616 #define RTC_TR_HU_0 ((uint32_t)0x00010000) /*!< */
2617 #define RTC_TR_HU_1 ((uint32_t)0x00020000) /*!< */
2618 #define RTC_TR_HU_2 ((uint32_t)0x00040000) /*!< */
2619 #define RTC_TR_HU_3 ((uint32_t)0x00080000) /*!< */
2620 #define RTC_TR_MNT ((uint32_t)0x00007000) /*!< */
2621 #define RTC_TR_MNT_0 ((uint32_t)0x00001000) /*!< */
2622 #define RTC_TR_MNT_1 ((uint32_t)0x00002000) /*!< */
2623 #define RTC_TR_MNT_2 ((uint32_t)0x00004000) /*!< */
2624 #define RTC_TR_MNU ((uint32_t)0x00000F00) /*!< */
2625 #define RTC_TR_MNU_0 ((uint32_t)0x00000100) /*!< */
2626 #define RTC_TR_MNU_1 ((uint32_t)0x00000200) /*!< */
2627 #define RTC_TR_MNU_2 ((uint32_t)0x00000400) /*!< */
2628 #define RTC_TR_MNU_3 ((uint32_t)0x00000800) /*!< */
2629 #define RTC_TR_ST ((uint32_t)0x00000070) /*!< */
2630 #define RTC_TR_ST_0 ((uint32_t)0x00000010) /*!< */
2631 #define RTC_TR_ST_1 ((uint32_t)0x00000020) /*!< */
2632 #define RTC_TR_ST_2 ((uint32_t)0x00000040) /*!< */
2633 #define RTC_TR_SU ((uint32_t)0x0000000F) /*!< */
2634 #define RTC_TR_SU_0 ((uint32_t)0x00000001) /*!< */
2635 #define RTC_TR_SU_1 ((uint32_t)0x00000002) /*!< */
2636 #define RTC_TR_SU_2 ((uint32_t)0x00000004) /*!< */
2637 #define RTC_TR_SU_3 ((uint32_t)0x00000008) /*!< */
2638
2639 /******************** Bits definition for RTC_DR register *******************/
2640 #define RTC_DR_YT ((uint32_t)0x00F00000) /*!< */
2641 #define RTC_DR_YT_0 ((uint32_t)0x00100000) /*!< */
2642 #define RTC_DR_YT_1 ((uint32_t)0x00200000) /*!< */
2643 #define RTC_DR_YT_2 ((uint32_t)0x00400000) /*!< */
2644 #define RTC_DR_YT_3 ((uint32_t)0x00800000) /*!< */
2645 #define RTC_DR_YU ((uint32_t)0x000F0000) /*!< */
2646 #define RTC_DR_YU_0 ((uint32_t)0x00010000) /*!< */
2647 #define RTC_DR_YU_1 ((uint32_t)0x00020000) /*!< */
2648 #define RTC_DR_YU_2 ((uint32_t)0x00040000) /*!< */
2649 #define RTC_DR_YU_3 ((uint32_t)0x00080000) /*!< */
2650 #define RTC_DR_WDU ((uint32_t)0x0000E000) /*!< */
2651 #define RTC_DR_WDU_0 ((uint32_t)0x00002000) /*!< */
2652 #define RTC_DR_WDU_1 ((uint32_t)0x00004000) /*!< */
2653 #define RTC_DR_WDU_2 ((uint32_t)0x00008000) /*!< */
2654 #define RTC_DR_MT ((uint32_t)0x00001000) /*!< */
2655 #define RTC_DR_MU ((uint32_t)0x00000F00) /*!< */
2656 #define RTC_DR_MU_0 ((uint32_t)0x00000100) /*!< */
2657 #define RTC_DR_MU_1 ((uint32_t)0x00000200) /*!< */
2658 #define RTC_DR_MU_2 ((uint32_t)0x00000400) /*!< */
2659 #define RTC_DR_MU_3 ((uint32_t)0x00000800) /*!< */
2660 #define RTC_DR_DT ((uint32_t)0x00000030) /*!< */
2661 #define RTC_DR_DT_0 ((uint32_t)0x00000010) /*!< */
2662 #define RTC_DR_DT_1 ((uint32_t)0x00000020) /*!< */
2663 #define RTC_DR_DU ((uint32_t)0x0000000F) /*!< */
2664 #define RTC_DR_DU_0 ((uint32_t)0x00000001) /*!< */
2665 #define RTC_DR_DU_1 ((uint32_t)0x00000002) /*!< */
2666 #define RTC_DR_DU_2 ((uint32_t)0x00000004) /*!< */
2667 #define RTC_DR_DU_3 ((uint32_t)0x00000008) /*!< */
2668
2669 /******************** Bits definition for RTC_CR register *******************/
2670 #define RTC_CR_COE ((uint32_t)0x00800000) /*!< */
2671 #define RTC_CR_OSEL ((uint32_t)0x00600000) /*!< */
2672 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000) /*!< */
2673 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000) /*!< */
2674 #define RTC_CR_POL ((uint32_t)0x00100000) /*!< */
2675 #define RTC_CR_COSEL ((uint32_t)0x00080000) /*!< */
2676 #define RTC_CR_BCK ((uint32_t)0x00040000) /*!< */
2677 #define RTC_CR_SUB1H ((uint32_t)0x00020000) /*!< */
2678 #define RTC_CR_ADD1H ((uint32_t)0x00010000) /*!< */
2679 #define RTC_CR_TSIE ((uint32_t)0x00008000) /*!< */
2680 #define RTC_CR_WUTIE ((uint32_t)0x00004000) /*!< */
2681 #define RTC_CR_ALRBIE ((uint32_t)0x00002000) /*!< */
2682 #define RTC_CR_ALRAIE ((uint32_t)0x00001000) /*!< */
2683 #define RTC_CR_TSE ((uint32_t)0x00000800) /*!< */
2684 #define RTC_CR_WUTE ((uint32_t)0x00000400) /*!< */
2685 #define RTC_CR_ALRBE ((uint32_t)0x00000200) /*!< */
2686 #define RTC_CR_ALRAE ((uint32_t)0x00000100) /*!< */
2687 #define RTC_CR_FMT ((uint32_t)0x00000040) /*!< */
2688 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020) /*!< */
2689 #define RTC_CR_REFCKON ((uint32_t)0x00000010) /*!< */
2690 #define RTC_CR_TSEDGE ((uint32_t)0x00000008) /*!< */
2691 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007) /*!< */
2692 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001) /*!< */
2693 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002) /*!< */
2694 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004) /*!< */
2695
2696 /******************** Bits definition for RTC_ISR register ******************/
2697 #define RTC_ISR_RECALPF ((uint32_t)0x00010000) /*!< */
2698 #define RTC_ISR_TAMP3F ((uint32_t)0x00008000) /*!< */
2699 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000) /*!< */
2700 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000) /*!< */
2701 #define RTC_ISR_TSOVF ((uint32_t)0x00001000) /*!< */
2702 #define RTC_ISR_TSF ((uint32_t)0x00000800) /*!< */
2703 #define RTC_ISR_WUTF ((uint32_t)0x00000400) /*!< */
2704 #define RTC_ISR_ALRBF ((uint32_t)0x00000200) /*!< */
2705 #define RTC_ISR_ALRAF ((uint32_t)0x00000100) /*!< */
2706 #define RTC_ISR_INIT ((uint32_t)0x00000080) /*!< */
2707 #define RTC_ISR_INITF ((uint32_t)0x00000040) /*!< */
2708 #define RTC_ISR_RSF ((uint32_t)0x00000020) /*!< */
2709 #define RTC_ISR_INITS ((uint32_t)0x00000010) /*!< */
2710 #define RTC_ISR_SHPF ((uint32_t)0x00000008) /*!< */
2711 #define RTC_ISR_WUTWF ((uint32_t)0x00000004) /*!< */
2712 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002) /*!< */
2713 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001) /*!< */
2714
2715 /******************** Bits definition for RTC_PRER register *****************/
2716 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000) /*!< */
2717 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF) /*!< */
2718
2719 /******************** Bits definition for RTC_WUTR register *****************/
2720 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
2721
2722 /******************** Bits definition for RTC_ALRMAR register ***************/
2723 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000) /*!< */
2724 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000) /*!< */
2725 #define RTC_ALRMAR_DT ((uint32_t)0x30000000) /*!< */
2726 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000) /*!< */
2727 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000) /*!< */
2728 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000) /*!< */
2729 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000) /*!< */
2730 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000) /*!< */
2731 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000) /*!< */
2732 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000) /*!< */
2733 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000) /*!< */
2734 #define RTC_ALRMAR_PM ((uint32_t)0x00400000) /*!< */
2735 #define RTC_ALRMAR_HT ((uint32_t)0x00300000) /*!< */
2736 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000) /*!< */
2737 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000) /*!< */
2738 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000) /*!< */
2739 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000) /*!< */
2740 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000) /*!< */
2741 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000) /*!< */
2742 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000) /*!< */
2743 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000) /*!< */
2744 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000) /*!< */
2745 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000) /*!< */
2746 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000) /*!< */
2747 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000) /*!< */
2748 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00) /*!< */
2749 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100) /*!< */
2750 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200) /*!< */
2751 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400) /*!< */
2752 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800) /*!< */
2753 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080) /*!< */
2754 #define RTC_ALRMAR_ST ((uint32_t)0x00000070) /*!< */
2755 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010) /*!< */
2756 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020) /*!< */
2757 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040) /*!< */
2758 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F) /*!< */
2759 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001) /*!< */
2760 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002) /*!< */
2761 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004) /*!< */
2762 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008) /*!< */
2763
2764 /******************** Bits definition for RTC_ALRMBR register ***************/
2765 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000) /*!< */
2766 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000) /*!< */
2767 #define RTC_ALRMBR_DT ((uint32_t)0x30000000) /*!< */
2768 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000) /*!< */
2769 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000) /*!< */
2770 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000) /*!< */
2771 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000) /*!< */
2772 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000) /*!< */
2773 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000) /*!< */
2774 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000) /*!< */
2775 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000) /*!< */
2776 #define RTC_ALRMBR_PM ((uint32_t)0x00400000) /*!< */
2777 #define RTC_ALRMBR_HT ((uint32_t)0x00300000) /*!< */
2778 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000) /*!< */
2779 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000) /*!< */
2780 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000) /*!< */
2781 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000) /*!< */
2782 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000) /*!< */
2783 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000) /*!< */
2784 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000) /*!< */
2785 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000) /*!< */
2786 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000) /*!< */
2787 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000) /*!< */
2788 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000) /*!< */
2789 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000) /*!< */
2790 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00) /*!< */
2791 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100) /*!< */
2792 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200) /*!< */
2793 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400) /*!< */
2794 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800) /*!< */
2795 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080) /*!< */
2796 #define RTC_ALRMBR_ST ((uint32_t)0x00000070) /*!< */
2797 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010) /*!< */
2798 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020) /*!< */
2799 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040) /*!< */
2800 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F) /*!< */
2801 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001) /*!< */
2802 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002) /*!< */
2803 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004) /*!< */
2804 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008) /*!< */
2805
2806 /******************** Bits definition for RTC_WPR register ******************/
2807 #define RTC_WPR_KEY ((uint32_t)0x000000FF) /*!< */
2808
2809 /******************** Bits definition for RTC_SSR register ******************/
2810 #define RTC_SSR_SS ((uint32_t)0x0000FFFF) /*!< */
2811
2812 /******************** Bits definition for RTC_SHIFTR register ***************/
2813 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF) /*!< */
2814 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000) /*!< */
2815
2816 /******************** Bits definition for RTC_TSTR register *****************/
2817 #define RTC_TSTR_PM ((uint32_t)0x00400000) /*!< */
2818 #define RTC_TSTR_HT ((uint32_t)0x00300000) /*!< */
2819 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000) /*!< */
2820 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000) /*!< */
2821 #define RTC_TSTR_HU ((uint32_t)0x000F0000) /*!< */
2822 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000) /*!< */
2823 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000) /*!< */
2824 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000) /*!< */
2825 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000) /*!< */
2826 #define RTC_TSTR_MNT ((uint32_t)0x00007000) /*!< */
2827 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000) /*!< */
2828 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000) /*!< */
2829 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000) /*!< */
2830 #define RTC_TSTR_MNU ((uint32_t)0x00000F00) /*!< */
2831 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100) /*!< */
2832 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200) /*!< */
2833 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400) /*!< */
2834 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800) /*!< */
2835 #define RTC_TSTR_ST ((uint32_t)0x00000070) /*!< */
2836 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010) /*!< */
2837 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020) /*!< */
2838 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040) /*!< */
2839 #define RTC_TSTR_SU ((uint32_t)0x0000000F) /*!< */
2840 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001) /*!< */
2841 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002) /*!< */
2842 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004) /*!< */
2843 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008) /*!< */
2844
2845 /******************** Bits definition for RTC_TSDR register *****************/
2846 #define RTC_TSDR_WDU ((uint32_t)0x0000E000) /*!< */
2847 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000) /*!< */
2848 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000) /*!< */
2849 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000) /*!< */
2850 #define RTC_TSDR_MT ((uint32_t)0x00001000) /*!< */
2851 #define RTC_TSDR_MU ((uint32_t)0x00000F00) /*!< */
2852 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100) /*!< */
2853 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200) /*!< */
2854 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400) /*!< */
2855 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800) /*!< */
2856 #define RTC_TSDR_DT ((uint32_t)0x00000030) /*!< */
2857 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010) /*!< */
2858 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020) /*!< */
2859 #define RTC_TSDR_DU ((uint32_t)0x0000000F) /*!< */
2860 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001) /*!< */
2861 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002) /*!< */
2862 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004) /*!< */
2863 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008) /*!< */
2864
2865 /******************** Bits definition for RTC_TSSSR register ****************/
2866 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
2867
2868 /******************** Bits definition for RTC_CAL register *****************/
2869 #define RTC_CAL_CALP ((uint32_t)0x00008000) /*!< */
2870 #define RTC_CAL_CALW8 ((uint32_t)0x00004000) /*!< */
2871 #define RTC_CAL_CALW16 ((uint32_t)0x00002000) /*!< */
2872 #define RTC_CAL_CALM ((uint32_t)0x000001FF) /*!< */
2873 #define RTC_CAL_CALM_0 ((uint32_t)0x00000001) /*!< */
2874 #define RTC_CAL_CALM_1 ((uint32_t)0x00000002) /*!< */
2875 #define RTC_CAL_CALM_2 ((uint32_t)0x00000004) /*!< */
2876 #define RTC_CAL_CALM_3 ((uint32_t)0x00000008) /*!< */
2877 #define RTC_CAL_CALM_4 ((uint32_t)0x00000010) /*!< */
2878 #define RTC_CAL_CALM_5 ((uint32_t)0x00000020) /*!< */
2879 #define RTC_CAL_CALM_6 ((uint32_t)0x00000040) /*!< */
2880 #define RTC_CAL_CALM_7 ((uint32_t)0x00000080) /*!< */
2881 #define RTC_CAL_CALM_8 ((uint32_t)0x00000100) /*!< */
2882
2883 /******************** Bits definition for RTC_TAMPCR register ****************/
2884 #define RTC_TAMPCR_TAMP3MF ((uint32_t)0x01000000) /*!< */
2885 #define RTC_TAMPCR_TAMP3NOERASE ((uint32_t)0x00800000) /*!< */
2886 #define RTC_TAMPCR_TAMP3IE ((uint32_t)0x00400000) /*!< */
2887 #define RTC_TAMPCR_TAMP2MF ((uint32_t)0x00200000) /*!< */
2888 #define RTC_TAMPCR_TAMP2NOERASE ((uint32_t)0x00100000) /*!< */
2889 #define RTC_TAMPCR_TAMP2IE ((uint32_t)0x00080000) /*!< */
2890 #define RTC_TAMPCR_TAMP1MF ((uint32_t)0x00040000) /*!< */
2891 #define RTC_TAMPCR_TAMP1NOERASE ((uint32_t)0x00020000) /*!< */
2892 #define RTC_TAMPCR_TAMP1IE ((uint32_t)0x00010000) /*!< */
2893 #define RTC_TAMPCR_TAMPPUDIS ((uint32_t)0x00008000) /*!< */
2894 #define RTC_TAMPCR_TAMPPRCH ((uint32_t)0x00006000) /*!< */
2895 #define RTC_TAMPCR_TAMPPRCH_0 ((uint32_t)0x00002000) /*!< */
2896 #define RTC_TAMPCR_TAMPPRCH_1 ((uint32_t)0x00004000) /*!< */
2897 #define RTC_TAMPCR_TAMPFLT ((uint32_t)0x00001800) /*!< */
2898 #define RTC_TAMPCR_TAMPFLT_0 ((uint32_t)0x00000800) /*!< */
2899 #define RTC_TAMPCR_TAMPFLT_1 ((uint32_t)0x00001000) /*!< */
2900 #define RTC_TAMPCR_TAMPFREQ ((uint32_t)0x00000700) /*!< */
2901 #define RTC_TAMPCR_TAMPFREQ_0 ((uint32_t)0x00000100) /*!< */
2902 #define RTC_TAMPCR_TAMPFREQ_1 ((uint32_t)0x00000200) /*!< */
2903 #define RTC_TAMPCR_TAMPFREQ_2 ((uint32_t)0x00000400) /*!< */
2904 #define RTC_TAMPCR_TAMPTS ((uint32_t)0x00000080) /*!< */
2905 #define RTC_TAMPCR_TAMP3TRG ((uint32_t)0x00000040) /*!< */
2906 #define RTC_TAMPCR_TAMP3E ((uint32_t)0x00000020) /*!< */
2907 #define RTC_TAMPCR_TAMP2TRG ((uint32_t)0x00000010) /*!< */
2908 #define RTC_TAMPCR_TAMP2E ((uint32_t)0x00000008) /*!< */
2909 #define RTC_TAMPCR_TAMPIE ((uint32_t)0x00000004) /*!< */
2910 #define RTC_TAMPCR_TAMP1TRG ((uint32_t)0x00000002) /*!< */
2911 #define RTC_TAMPCR_TAMP1E ((uint32_t)0x00000001) /*!< */
2912
2913 /******************** Bits definition for RTC_ALRMASSR register *************/
2914 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
2915 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
2916 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
2917 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
2918 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
2919 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
2920
2921 /******************** Bits definition for RTC_ALRMBSSR register *************/
2922 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
2923 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
2924 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
2925 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
2926 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
2927 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
2928
2929 /******************** Bits definition for RTC_OR register ****************/
2930 #define RTC_OR_OUT_RMP ((uint32_t)0x00000002) /*!< */
2931 #define RTC_OR_ALARMOUTTYPE ((uint32_t)0x00000001) /*!< */
2932
2933 /* Bit names aliases maintained for legacy */
2934 #define RTC_OR_RTC_OUT_RMP RTC_OR_OUT_RMP
2935
2936 /******************** Bits definition for RTC_BKP0R register ****************/
2937 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF) /*!< */
2938
2939 /******************** Bits definition for RTC_BKP1R register ****************/
2940 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF) /*!< */
2941
2942 /******************** Bits definition for RTC_BKP2R register ****************/
2943 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF) /*!< */
2944
2945 /******************** Bits definition for RTC_BKP3R register ****************/
2946 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF) /*!< */
2947
2948 /******************** Bits definition for RTC_BKP4R register ****************/
2949 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF) /*!< */
2950
2951 /******************************************************************************/
2952 /* */
2953 /* Serial Peripheral Interface (SPI) */
2954 /* */
2955 /******************************************************************************/
2956 /******************* Bit definition for SPI_CR1 register ********************/
2957 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
2958 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
2959 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
2960 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
2961 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
2962 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
2963 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
2964 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
2965 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
2966 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
2967 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
2968 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
2969 #define SPI_CR1_DFF ((uint32_t)0x00000800) /*!< Data Frame Format */
2970 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
2971 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
2972 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
2973 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
2974
2975 /******************* Bit definition for SPI_CR2 register ********************/
2976 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
2977 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
2978 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
2979 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame Format Enable */
2980 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
2981 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
2982 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
2983
2984 /******************** Bit definition for SPI_SR register ********************/
2985 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
2986 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
2987 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */
2988 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */
2989 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
2990 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
2991 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
2992 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
2993 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!< TI frame format error */
2994
2995 /******************** Bit definition for SPI_DR register ********************/
2996 #define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!< Data Register */
2997
2998 /******************* Bit definition for SPI_CRCPR register ******************/
2999 #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!< CRC polynomial register */
3000
3001 /****************** Bit definition for SPI_RXCRCR register ******************/
3002 #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!< Rx CRC Register */
3003
3004 /****************** Bit definition for SPI_TXCRCR register ******************/
3005 #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!< Tx CRC Register */
3006
3007 /****************** Bit definition for SPI_I2SCFGR register *****************/
3008 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
3009 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
3010 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
3011 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
3012 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
3013 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
3014 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3015 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3016 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
3017 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
3018 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3019 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3020 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
3021 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
3022 #define SPI_I2SCFGR_ASTRTEN ((uint32_t)0x000001000) /*!<Asynchronous start enable */
3023 /****************** Bit definition for SPI_I2SPR register *******************/
3024 #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
3025 #define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
3026 #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
3027
3028 /******************************************************************************/
3029 /* */
3030 /* System Configuration (SYSCFG) */
3031 /* */
3032 /******************************************************************************/
3033 /***************** Bit definition for SYSCFG_CFGR1 register ****************/
3034 #define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
3035 #define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
3036 #define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
3037 #define SYSCFG_CFGR1_BOOT_MODE ((uint32_t)0x00000300) /*!< SYSCFG_Boot mode Config */
3038 #define SYSCFG_CFGR1_BOOT_MOD_0 ((uint32_t)0x00000100) /*!< SYSCFG_Boot mode Config Bit 0 */
3039 #define SYSCFG_CFGR1_BOOT_MODE_1 ((uint32_t)0x00000200) /*!< SYSCFG_Boot mode Config Bit 1 */
3040
3041 /***************** Bit definition for SYSCFG_CFGR2 register ****************/
3042 #define SYSCFG_CFGR2_FWDISEN ((uint32_t)0x00000001) /*!< Firewall disable bit */
3043 #define SYSCFG_CFGR2_CAPA ((uint32_t)0x0000003E) /*!< Connection of internal Vlcd rail to external capacitors */
3044 #define SYSCFG_CFGR2_CAPA_0 ((uint32_t)0x00000002)
3045 #define SYSCFG_CFGR2_CAPA_1 ((uint32_t)0x00000004)
3046 #define SYSCFG_CFGR2_CAPA_2 ((uint32_t)0x00000008)
3047 #define SYSCFG_CFGR2_CAPA_3 ((uint32_t)0x00000010)
3048 #define SYSCFG_CFGR2_CAPA_4 ((uint32_t)0x00000020)
3049 #define SYSCFG_CFGR2_I2C_PB6_FMP ((uint32_t)0x00000100) /*!< I2C PB6 Fast mode plus */
3050 #define SYSCFG_CFGR2_I2C_PB7_FMP ((uint32_t)0x00000200) /*!< I2C PB7 Fast mode plus */
3051 #define SYSCFG_CFGR2_I2C_PB8_FMP ((uint32_t)0x00000400) /*!< I2C PB8 Fast mode plus */
3052 #define SYSCFG_CFGR2_I2C_PB9_FMP ((uint32_t)0x00000800) /*!< I2C PB9 Fast mode plus */
3053 #define SYSCFG_CFGR2_I2C1_FMP ((uint32_t)0x00001000) /*!< I2C1 Fast mode plus */
3054 #define SYSCFG_CFGR2_I2C2_FMP ((uint32_t)0x00002000) /*!< I2C2 Fast mode plus */
3055 #define SYSCFG_CFGR2_I2C3_FMP ((uint32_t)0x00004000) /*!< I2C3 Fast mode plus */
3056
3057 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
3058 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */
3059 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */
3060 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */
3061 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */
3062
3063 /**
3064 * @brief EXTI0 configuration
3065 */
3066 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
3067 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */
3068 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */
3069 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!< PD[0] pin */
3070 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!< PE[0] pin */
3071 #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000005) /*!< PH[0] pin */
3072
3073 /**
3074 * @brief EXTI1 configuration
3075 */
3076 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
3077 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */
3078 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */
3079 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!< PD[1] pin */
3080 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!< PE[1] pin */
3081 #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000050) /*!< PH[1] pin */
3082
3083 /**
3084 * @brief EXTI2 configuration
3085 */
3086 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
3087 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */
3088 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */
3089 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */
3090 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!< PE[2] pin */
3091
3092 /**
3093 * @brief EXTI3 configuration
3094 */
3095 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
3096 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */
3097 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */
3098 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!< PD[3] pin */
3099 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!< PE[3] pin */
3100
3101 /***************** Bit definition for SYSCFG_EXTICR2 register *****************/
3102 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */
3103 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */
3104 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */
3105 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */
3106
3107 /**
3108 * @brief EXTI4 configuration
3109 */
3110 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
3111 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */
3112 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */
3113 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!< PD[4] pin */
3114 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!< PE[4] pin */
3115
3116 /**
3117 * @brief EXTI5 configuration
3118 */
3119 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
3120 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */
3121 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */
3122 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!< PD[5] pin */
3123 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!< PE[5] pin */
3124
3125 /**
3126 * @brief EXTI6 configuration
3127 */
3128 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
3129 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */
3130 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */
3131 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!< PD[6] pin */
3132 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!< PE[6] pin */
3133
3134 /**
3135 * @brief EXTI7 configuration
3136 */
3137 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
3138 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */
3139 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */
3140 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */
3141 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!< PE[7] pin */
3142
3143 /***************** Bit definition for SYSCFG_EXTICR3 register *****************/
3144 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
3145 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */
3146 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */
3147 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */
3148
3149 /**
3150 * @brief EXTI8 configuration
3151 */
3152 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
3153 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */
3154 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */
3155 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!< PD[8] pin */
3156 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!< PE[8] pin */
3157
3158 /**
3159 * @brief EXTI9 configuration
3160 */
3161 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
3162 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */
3163 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */
3164 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!< PD[9] pin */
3165 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!< PE[9] pin */
3166 #define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000050) /*!< PH[9] pin */
3167
3168 /**
3169 * @brief EXTI10 configuration
3170 */
3171 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
3172 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */
3173 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */
3174 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!< PD[10] pin */
3175 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!< PE[10] pin */
3176 #define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000500) /*!< PH[10] pin */
3177
3178 /**
3179 * @brief EXTI11 configuration
3180 */
3181 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
3182 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */
3183 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */
3184 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!< PD[11] pin */
3185 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!< PE[11] pin */
3186
3187 /***************** Bit definition for SYSCFG_EXTICR4 register *****************/
3188 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */
3189 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */
3190 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */
3191 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */
3192
3193 /**
3194 * @brief EXTI12 configuration
3195 */
3196 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
3197 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */
3198 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */
3199 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!< PD[12] pin */
3200 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!< PE[12] pin */
3201
3202 /**
3203 * @brief EXTI13 configuration
3204 */
3205 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
3206 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */
3207 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */
3208 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!< PD[13] pin */
3209 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!< PE[13] pin */
3210
3211 /**
3212 * @brief EXTI14 configuration
3213 */
3214 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
3215 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */
3216 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */
3217 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!< PD[14] pin */
3218 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!< PE[14] pin */
3219
3220 /**
3221 * @brief EXTI15 configuration
3222 */
3223 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
3224 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */
3225 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */
3226 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
3227 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
3228
3229
3230 /***************** Bit definition for SYSCFG_CFGR3 register ****************/
3231 #define SYSCFG_CFGR3_EN_VREFINT ((uint32_t)0x00000001) /*!< Vref Enable bit*/
3232 #define SYSCFG_CFGR3_VREF_OUT ((uint32_t)0x00000030) /*!< Verf_ADC connection bit */
3233 #define SYSCFG_CFGR3_VREF_OUT_0 ((uint32_t)0x00000010) /*!< Bit 0 */
3234 #define SYSCFG_CFGR3_VREF_OUT_1 ((uint32_t)0x00000020) /*!< Bit 1 */
3235 #define SYSCFG_CFGR3_ENBUF_VREFINT_ADC ((uint32_t)0x00000100) /*!< VREFINT reference for ADC enable bit */
3236 #define SYSCFG_CFGR3_ENBUF_SENSOR_ADC ((uint32_t)0x00000200) /*!< Sensor reference for ADC enable bit */
3237 #define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP ((uint32_t)0x00001000) /*!< VREFINT reference for comparator 2 enable bit */
3238 #define SYSCFG_CFGR3_ENREF_HSI48 ((uint32_t)0x00002000) /*!< VREFINT reference or 48 MHz RC oscillator enable bit */
3239 #define SYSCFG_CFGR3_REF_HSI48_RDYF ((uint32_t)0x04000000) /*!< VREFINT for 48 MHz RC oscillator ready flag */
3240 #define SYSCFG_CFGR3_SENSOR_ADC_RDYF ((uint32_t)0x08000000) /*!< Sensor for ADC ready flag */
3241 #define SYSCFG_CFGR3_VREFINT_ADC_RDYF ((uint32_t)0x10000000) /*!< VREFINT for ADC ready flag */
3242 #define SYSCFG_CFGR3_VREFINT_COMP_RDYF ((uint32_t)0x20000000) /*!< VREFINT for comparator ready flag */
3243 #define SYSCFG_CFGR3_VREFINT_RDYF ((uint32_t)0x40000000) /*!< VREFINT ready flag */
3244 #define SYSCFG_CFGR3_REF_LOCK ((uint32_t)0x80000000) /*!< CFGR3 lock bit */
3245
3246 /* Bit names aliases maintained for legacy */
3247
3248 #define SYSCFG_CFGR3_EN_BGAP SYSCFG_CFGR3_EN_VREFINT
3249 #define SYSCFG_CFGR3_ENBUF_BGAP_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC
3250 #define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
3251 #define SYSCFG_CFGR3_ENREF_RC48MHz SYSCFG_CFGR3_ENREF_HSI48
3252 #define SYSCFG_CFGR3_REF_RC48MHz_RDYF SYSCFG_CFGR3_REF_HSI48_RDYF
3253 #define SYSCFG_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_ADC_RDYF
3254
3255 /******************************************************************************/
3256 /* */
3257 /* Timers (TIM) */
3258 /* */
3259 /******************************************************************************/
3260 /******************* Bit definition for TIM_CR1 register ********************/
3261 #define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */
3262 #define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */
3263 #define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */
3264 #define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */
3265 #define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */
3266
3267 #define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
3268 #define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
3269 #define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
3270
3271 #define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */
3272
3273 #define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */
3274 #define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3275 #define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3276
3277 /******************* Bit definition for TIM_CR2 register ********************/
3278 #define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
3279 #define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
3280 #define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
3281
3282 #define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */
3283 #define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3284 #define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3285 #define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3286
3287 #define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */
3288 #define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */
3289 #define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */
3290 #define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */
3291 #define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */
3292 #define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */
3293 #define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */
3294 #define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */
3295
3296 /******************* Bit definition for TIM_SMCR register *******************/
3297 #define TIM_SMCR_SMS ((uint32_t)0x00000007) /*!<SMS[2:0] bits (Slave mode selection) */
3298 #define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3299 #define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3300 #define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3301
3302 #define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
3303
3304 #define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */
3305 #define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3306 #define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3307 #define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3308
3309 #define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */
3310
3311 #define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */
3312 #define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3313 #define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3314 #define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3315 #define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3316
3317 #define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */
3318 #define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */
3319 #define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */
3320
3321 #define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */
3322 #define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */
3323
3324 /******************* Bit definition for TIM_DIER register *******************/
3325 #define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */
3326 #define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */
3327 #define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */
3328 #define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */
3329 #define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */
3330 #define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */
3331 #define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */
3332 #define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */
3333 #define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */
3334 #define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */
3335 #define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */
3336 #define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */
3337
3338 /******************** Bit definition for TIM_SR register ********************/
3339 #define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */
3340 #define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */
3341 #define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */
3342 #define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */
3343 #define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */
3344 #define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */
3345 #define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */
3346 #define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */
3347 #define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */
3348 #define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */
3349 #define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */
3350 #define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */
3351
3352 /******************* Bit definition for TIM_EGR register ********************/
3353 #define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
3354 #define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
3355 #define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
3356 #define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
3357 #define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
3358 #define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */
3359 #define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
3360 #define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */
3361
3362 /****************** Bit definition for TIM_CCMR1 register *******************/
3363 #define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
3364 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3365 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3366
3367 #define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
3368 #define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
3369
3370 #define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
3371 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3372 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3373 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3374
3375 #define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
3376
3377 #define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
3378 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3379 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3380
3381 #define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
3382 #define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
3383
3384 #define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
3385 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
3386 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
3387 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
3388
3389 #define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
3390
3391 /*----------------------------------------------------------------------------*/
3392
3393 #define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
3394 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
3395 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
3396
3397 #define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
3398 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3399 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3400 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3401 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
3402
3403 #define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
3404 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
3405 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
3406
3407 #define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
3408 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
3409 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
3410 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
3411 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
3412
3413 /****************** Bit definition for TIM_CCMR2 register *******************/
3414 #define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
3415 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3416 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3417
3418 #define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
3419 #define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
3420
3421 #define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
3422 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3423 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3424 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3425
3426 #define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
3427
3428 #define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
3429 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3430 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3431
3432 #define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
3433 #define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
3434
3435 #define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
3436 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
3437 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
3438 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
3439
3440 #define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
3441
3442 /*----------------------------------------------------------------------------*/
3443
3444 #define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
3445 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
3446 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
3447
3448 #define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
3449 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3450 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3451 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3452 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
3453
3454 #define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
3455 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
3456 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
3457
3458 #define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
3459 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
3460 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
3461 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
3462 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
3463
3464 /******************* Bit definition for TIM_CCER register *******************/
3465 #define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
3466 #define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
3467 #define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
3468 #define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
3469 #define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
3470 #define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
3471 #define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
3472 #define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
3473 #define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
3474 #define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
3475 #define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
3476 #define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
3477 #define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
3478 #define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
3479 #define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
3480
3481 /******************* Bit definition for TIM_CNT register ********************/
3482 #define TIM_CNT_CNT ((uint32_t)0x0000FFFF) /*!<Counter Value */
3483
3484 /******************* Bit definition for TIM_PSC register ********************/
3485 #define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */
3486
3487 /******************* Bit definition for TIM_ARR register ********************/
3488 #define TIM_ARR_ARR ((uint32_t)0x0000FFFF) /*!<actual auto-reload Value */
3489
3490 /******************* Bit definition for TIM_RCR register ********************/
3491 #define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
3492
3493 /******************* Bit definition for TIM_CCR1 register *******************/
3494 #define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
3495
3496 /******************* Bit definition for TIM_CCR2 register *******************/
3497 #define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */
3498
3499 /******************* Bit definition for TIM_CCR3 register *******************/
3500 #define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */
3501
3502 /******************* Bit definition for TIM_CCR4 register *******************/
3503 #define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */
3504
3505 /******************* Bit definition for TIM_BDTR register *******************/
3506 #define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
3507 #define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3508 #define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3509 #define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3510 #define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3511 #define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
3512 #define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
3513 #define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
3514 #define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
3515
3516 #define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
3517 #define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3518 #define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3519
3520 #define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
3521 #define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
3522 #define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable */
3523 #define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity */
3524 #define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
3525 #define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
3526
3527 /******************* Bit definition for TIM_DCR register ********************/
3528 #define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */
3529 #define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3530 #define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3531 #define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3532 #define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3533 #define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */
3534
3535 #define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */
3536 #define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3537 #define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3538 #define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3539 #define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3540 #define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
3541
3542 /******************* Bit definition for TIM_DMAR register *******************/
3543 #define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */
3544
3545 /******************* Bit definition for TIM_OR register *********************/
3546 #define TIM2_OR_ETR_RMP ((uint32_t)0x00000007) /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
3547 #define TIM2_OR_ETR_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3548 #define TIM2_OR_ETR_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3549 #define TIM2_OR_ETR_RMP_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3550 #define TIM2_OR_TI4_RMP ((uint32_t)0x0000018) /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
3551 #define TIM2_OR_TI4_RMP_0 ((uint32_t)0x00000008) /*!<Bit 0 */
3552 #define TIM2_OR_TI4_RMP_1 ((uint32_t)0x00000010) /*!<Bit 1 */
3553
3554 #define TIM21_OR_ETR_RMP ((uint32_t)0x00000003) /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
3555 #define TIM21_OR_ETR_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3556 #define TIM21_OR_ETR_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3557 #define TIM21_OR_TI1_RMP ((uint32_t)0x0000001C) /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
3558 #define TIM21_OR_TI1_RMP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
3559 #define TIM21_OR_TI1_RMP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
3560 #define TIM21_OR_TI1_RMP_2 ((uint32_t)0x00000010) /*!<Bit 2 */
3561 #define TIM21_OR_TI2_RMP ((uint32_t)0x00000020) /*!<TI2_RMP bit (TIM21 Input 2 remap) */
3562
3563 #define TIM22_OR_ETR_RMP ((uint32_t)0x00000003) /*!<ETR_RMP[1:0] bits (TIM22 ETR remap) */
3564 #define TIM22_OR_ETR_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3565 #define TIM22_OR_ETR_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3566 #define TIM22_OR_TI1_RMP ((uint32_t)0x0000000C) /*!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) */
3567 #define TIM22_OR_TI1_RMP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
3568 #define TIM22_OR_TI1_RMP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
3569
3570 #define TIM3_OR_ETR_RMP ((uint32_t)0x00000003) /*!<ETR_RMP[1:0] bits (TIM3 ETR remap) */
3571 #define TIM3_OR_ETR_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3572 #define TIM3_OR_ETR_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3573 #define TIM3_OR_TI1_RMP ((uint32_t)0x00000004) /*!<TI1_RMP[2] bit */
3574 #define TIM3_OR_TI2_RMP ((uint32_t)0x00000008) /*!<TI2_RMP[3] bit */
3575 #define TIM3_OR_TI4_RMP ((uint32_t)0x00000010) /*!<TI4_RMP[4] bit */
3576
3577
3578 /******************************************************************************/
3579 /* */
3580 /* Touch Sensing Controller (TSC) */
3581 /* */
3582 /******************************************************************************/
3583 /******************* Bit definition for TSC_CR register *********************/
3584 #define TSC_CR_TSCE ((uint32_t)0x00000001) /*!<Touch sensing controller enable */
3585 #define TSC_CR_START ((uint32_t)0x00000002) /*!<Start acquisition */
3586 #define TSC_CR_AM ((uint32_t)0x00000004) /*!<Acquisition mode */
3587 #define TSC_CR_SYNCPOL ((uint32_t)0x00000008) /*!<Synchronization pin polarity */
3588 #define TSC_CR_IODEF ((uint32_t)0x00000010) /*!<IO default mode */
3589
3590 #define TSC_CR_MCV ((uint32_t)0x000000E0) /*!<MCV[2:0] bits (Max Count Value) */
3591 #define TSC_CR_MCV_0 ((uint32_t)0x00000020) /*!<Bit 0 */
3592 #define TSC_CR_MCV_1 ((uint32_t)0x00000040) /*!<Bit 1 */
3593 #define TSC_CR_MCV_2 ((uint32_t)0x00000080) /*!<Bit 2 */
3594
3595 #define TSC_CR_PGPSC ((uint32_t)0x00007000) /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
3596 #define TSC_CR_PGPSC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
3597 #define TSC_CR_PGPSC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
3598 #define TSC_CR_PGPSC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
3599
3600 #define TSC_CR_SSPSC ((uint32_t)0x00008000) /*!<Spread Spectrum Prescaler */
3601 #define TSC_CR_SSE ((uint32_t)0x00010000) /*!<Spread Spectrum Enable */
3602
3603 #define TSC_CR_SSD ((uint32_t)0x00FE0000) /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
3604 #define TSC_CR_SSD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
3605 #define TSC_CR_SSD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
3606 #define TSC_CR_SSD_2 ((uint32_t)0x00080000) /*!<Bit 2 */
3607 #define TSC_CR_SSD_3 ((uint32_t)0x00100000) /*!<Bit 3 */
3608 #define TSC_CR_SSD_4 ((uint32_t)0x00200000) /*!<Bit 4 */
3609 #define TSC_CR_SSD_5 ((uint32_t)0x00400000) /*!<Bit 5 */
3610 #define TSC_CR_SSD_6 ((uint32_t)0x00800000) /*!<Bit 6 */
3611
3612 #define TSC_CR_CTPL ((uint32_t)0x0F000000) /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
3613 #define TSC_CR_CTPL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3614 #define TSC_CR_CTPL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3615 #define TSC_CR_CTPL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3616 #define TSC_CR_CTPL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3617
3618 #define TSC_CR_CTPH ((uint32_t)0xF0000000) /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
3619 #define TSC_CR_CTPH_0 ((uint32_t)0x10000000) /*!<Bit 0 */
3620 #define TSC_CR_CTPH_1 ((uint32_t)0x20000000) /*!<Bit 1 */
3621 #define TSC_CR_CTPH_2 ((uint32_t)0x40000000) /*!<Bit 2 */
3622 #define TSC_CR_CTPH_3 ((uint32_t)0x80000000) /*!<Bit 3 */
3623
3624 /******************* Bit definition for TSC_IER register ********************/
3625 #define TSC_IER_EOAIE ((uint32_t)0x00000001) /*!<End of acquisition interrupt enable */
3626 #define TSC_IER_MCEIE ((uint32_t)0x00000002) /*!<Max count error interrupt enable */
3627
3628 /******************* Bit definition for TSC_ICR register ********************/
3629 #define TSC_ICR_EOAIC ((uint32_t)0x00000001) /*!<End of acquisition interrupt clear */
3630 #define TSC_ICR_MCEIC ((uint32_t)0x00000002) /*!<Max count error interrupt clear */
3631
3632 /******************* Bit definition for TSC_ISR register ********************/
3633 #define TSC_ISR_EOAF ((uint32_t)0x00000001) /*!<End of acquisition flag */
3634 #define TSC_ISR_MCEF ((uint32_t)0x00000002) /*!<Max count error flag */
3635
3636 /******************* Bit definition for TSC_IOHCR register ******************/
3637 #define TSC_IOHCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
3638 #define TSC_IOHCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
3639 #define TSC_IOHCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
3640 #define TSC_IOHCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
3641 #define TSC_IOHCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
3642 #define TSC_IOHCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
3643 #define TSC_IOHCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
3644 #define TSC_IOHCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
3645 #define TSC_IOHCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
3646 #define TSC_IOHCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
3647 #define TSC_IOHCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
3648 #define TSC_IOHCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
3649 #define TSC_IOHCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
3650 #define TSC_IOHCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
3651 #define TSC_IOHCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
3652 #define TSC_IOHCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
3653 #define TSC_IOHCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
3654 #define TSC_IOHCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
3655 #define TSC_IOHCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
3656 #define TSC_IOHCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
3657 #define TSC_IOHCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
3658 #define TSC_IOHCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
3659 #define TSC_IOHCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
3660 #define TSC_IOHCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
3661 #define TSC_IOHCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
3662 #define TSC_IOHCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
3663 #define TSC_IOHCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
3664 #define TSC_IOHCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
3665 #define TSC_IOHCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
3666 #define TSC_IOHCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
3667 #define TSC_IOHCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
3668 #define TSC_IOHCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
3669
3670 /******************* Bit definition for TSC_IOASCR register *****************/
3671 #define TSC_IOASCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 analog switch enable */
3672 #define TSC_IOASCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 analog switch enable */
3673 #define TSC_IOASCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 analog switch enable */
3674 #define TSC_IOASCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 analog switch enable */
3675 #define TSC_IOASCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 analog switch enable */
3676 #define TSC_IOASCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 analog switch enable */
3677 #define TSC_IOASCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 analog switch enable */
3678 #define TSC_IOASCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 analog switch enable */
3679 #define TSC_IOASCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 analog switch enable */
3680 #define TSC_IOASCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 analog switch enable */
3681 #define TSC_IOASCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 analog switch enable */
3682 #define TSC_IOASCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 analog switch enable */
3683 #define TSC_IOASCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 analog switch enable */
3684 #define TSC_IOASCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 analog switch enable */
3685 #define TSC_IOASCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 analog switch enable */
3686 #define TSC_IOASCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 analog switch enable */
3687 #define TSC_IOASCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 analog switch enable */
3688 #define TSC_IOASCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 analog switch enable */
3689 #define TSC_IOASCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 analog switch enable */
3690 #define TSC_IOASCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 analog switch enable */
3691 #define TSC_IOASCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 analog switch enable */
3692 #define TSC_IOASCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 analog switch enable */
3693 #define TSC_IOASCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 analog switch enable */
3694 #define TSC_IOASCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 analog switch enable */
3695 #define TSC_IOASCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 analog switch enable */
3696 #define TSC_IOASCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 analog switch enable */
3697 #define TSC_IOASCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 analog switch enable */
3698 #define TSC_IOASCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 analog switch enable */
3699 #define TSC_IOASCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 analog switch enable */
3700 #define TSC_IOASCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 analog switch enable */
3701 #define TSC_IOASCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 analog switch enable */
3702 #define TSC_IOASCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 analog switch enable */
3703
3704 /******************* Bit definition for TSC_IOSCR register ******************/
3705 #define TSC_IOSCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 sampling mode */
3706 #define TSC_IOSCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 sampling mode */
3707 #define TSC_IOSCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 sampling mode */
3708 #define TSC_IOSCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 sampling mode */
3709 #define TSC_IOSCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 sampling mode */
3710 #define TSC_IOSCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 sampling mode */
3711 #define TSC_IOSCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 sampling mode */
3712 #define TSC_IOSCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 sampling mode */
3713 #define TSC_IOSCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 sampling mode */
3714 #define TSC_IOSCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 sampling mode */
3715 #define TSC_IOSCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 sampling mode */
3716 #define TSC_IOSCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 sampling mode */
3717 #define TSC_IOSCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 sampling mode */
3718 #define TSC_IOSCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 sampling mode */
3719 #define TSC_IOSCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 sampling mode */
3720 #define TSC_IOSCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 sampling mode */
3721 #define TSC_IOSCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 sampling mode */
3722 #define TSC_IOSCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 sampling mode */
3723 #define TSC_IOSCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 sampling mode */
3724 #define TSC_IOSCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 sampling mode */
3725 #define TSC_IOSCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 sampling mode */
3726 #define TSC_IOSCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 sampling mode */
3727 #define TSC_IOSCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 sampling mode */
3728 #define TSC_IOSCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 sampling mode */
3729 #define TSC_IOSCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 sampling mode */
3730 #define TSC_IOSCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 sampling mode */
3731 #define TSC_IOSCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 sampling mode */
3732 #define TSC_IOSCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 sampling mode */
3733 #define TSC_IOSCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 sampling mode */
3734 #define TSC_IOSCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 sampling mode */
3735 #define TSC_IOSCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 sampling mode */
3736 #define TSC_IOSCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 sampling mode */
3737
3738 /******************* Bit definition for TSC_IOCCR register ******************/
3739 #define TSC_IOCCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 channel mode */
3740 #define TSC_IOCCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 channel mode */
3741 #define TSC_IOCCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 channel mode */
3742 #define TSC_IOCCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 channel mode */
3743 #define TSC_IOCCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 channel mode */
3744 #define TSC_IOCCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 channel mode */
3745 #define TSC_IOCCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 channel mode */
3746 #define TSC_IOCCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 channel mode */
3747 #define TSC_IOCCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 channel mode */
3748 #define TSC_IOCCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 channel mode */
3749 #define TSC_IOCCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 channel mode */
3750 #define TSC_IOCCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 channel mode */
3751 #define TSC_IOCCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 channel mode */
3752 #define TSC_IOCCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 channel mode */
3753 #define TSC_IOCCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 channel mode */
3754 #define TSC_IOCCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 channel mode */
3755 #define TSC_IOCCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 channel mode */
3756 #define TSC_IOCCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 channel mode */
3757 #define TSC_IOCCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 channel mode */
3758 #define TSC_IOCCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 channel mode */
3759 #define TSC_IOCCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 channel mode */
3760 #define TSC_IOCCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 channel mode */
3761 #define TSC_IOCCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 channel mode */
3762 #define TSC_IOCCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 channel mode */
3763 #define TSC_IOCCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 channel mode */
3764 #define TSC_IOCCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 channel mode */
3765 #define TSC_IOCCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 channel mode */
3766 #define TSC_IOCCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 channel mode */
3767 #define TSC_IOCCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 channel mode */
3768 #define TSC_IOCCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 channel mode */
3769 #define TSC_IOCCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 channel mode */
3770 #define TSC_IOCCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 channel mode */
3771
3772 /******************* Bit definition for TSC_IOGCSR register *****************/
3773 #define TSC_IOGCSR_G1E ((uint32_t)0x00000001) /*!<Analog IO GROUP1 enable */
3774 #define TSC_IOGCSR_G2E ((uint32_t)0x00000002) /*!<Analog IO GROUP2 enable */
3775 #define TSC_IOGCSR_G3E ((uint32_t)0x00000004) /*!<Analog IO GROUP3 enable */
3776 #define TSC_IOGCSR_G4E ((uint32_t)0x00000008) /*!<Analog IO GROUP4 enable */
3777 #define TSC_IOGCSR_G5E ((uint32_t)0x00000010) /*!<Analog IO GROUP5 enable */
3778 #define TSC_IOGCSR_G6E ((uint32_t)0x00000020) /*!<Analog IO GROUP6 enable */
3779 #define TSC_IOGCSR_G7E ((uint32_t)0x00000040) /*!<Analog IO GROUP7 enable */
3780 #define TSC_IOGCSR_G8E ((uint32_t)0x00000080) /*!<Analog IO GROUP8 enable */
3781 #define TSC_IOGCSR_G1S ((uint32_t)0x00010000) /*!<Analog IO GROUP1 status */
3782 #define TSC_IOGCSR_G2S ((uint32_t)0x00020000) /*!<Analog IO GROUP2 status */
3783 #define TSC_IOGCSR_G3S ((uint32_t)0x00040000) /*!<Analog IO GROUP3 status */
3784 #define TSC_IOGCSR_G4S ((uint32_t)0x00080000) /*!<Analog IO GROUP4 status */
3785 #define TSC_IOGCSR_G5S ((uint32_t)0x00100000) /*!<Analog IO GROUP5 status */
3786 #define TSC_IOGCSR_G6S ((uint32_t)0x00200000) /*!<Analog IO GROUP6 status */
3787 #define TSC_IOGCSR_G7S ((uint32_t)0x00400000) /*!<Analog IO GROUP7 status */
3788 #define TSC_IOGCSR_G8S ((uint32_t)0x00800000) /*!<Analog IO GROUP8 status */
3789
3790 /******************* Bit definition for TSC_IOGXCR register *****************/
3791 #define TSC_IOGXCR_CNT ((uint32_t)0x00003FFF) /*!<CNT[13:0] bits (Counter value) */
3792
3793 /******************************************************************************/
3794 /* */
3795 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
3796 /* */
3797 /******************************************************************************/
3798 /****************** Bit definition for USART_CR1 register *******************/
3799 #define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
3800 #define USART_CR1_UESM ((uint32_t)0x00000002) /*!< USART Enable in STOP Mode */
3801 #define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
3802 #define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
3803 #define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
3804 #define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
3805 #define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
3806 #define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
3807 #define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
3808 #define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
3809 #define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
3810 #define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
3811 #define USART_CR1_M ((uint32_t)0x10001000) /*!< Word length */
3812 #define USART_CR1_M_0 ((uint32_t)0x00001000) /*!< Word length - Bit 0 */
3813 #define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
3814 #define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
3815 #define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
3816 #define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
3817 #define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
3818 #define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
3819 #define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
3820 #define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
3821 #define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
3822 #define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
3823 #define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
3824 #define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
3825 #define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
3826 #define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
3827 #define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
3828 #define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
3829 #define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
3830 #define USART_CR1_M_1 ((uint32_t)0x10000000) /*!< Word length - Bit 1 */
3831 /****************** Bit definition for USART_CR2 register *******************/
3832 #define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
3833 #define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
3834 #define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
3835 #define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
3836 #define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
3837 #define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
3838 #define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
3839 #define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
3840 #define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
3841 #define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
3842 #define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
3843 #define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
3844 #define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
3845 #define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
3846 #define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
3847 #define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
3848 #define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/
3849 #define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
3850 #define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
3851 #define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
3852 #define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
3853 #define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
3854
3855 /****************** Bit definition for USART_CR3 register *******************/
3856 #define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
3857 #define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
3858 #define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
3859 #define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
3860 #define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */
3861 #define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */
3862 #define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
3863 #define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
3864 #define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
3865 #define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
3866 #define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
3867 #define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
3868 #define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
3869 #define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
3870 #define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
3871 #define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
3872 #define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
3873 #define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */
3874 #define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */
3875 #define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */
3876 #define USART_CR3_WUS ((uint32_t)0x00300000) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
3877 #define USART_CR3_WUS_0 ((uint32_t)0x00100000) /*!< Bit 0 */
3878 #define USART_CR3_WUS_1 ((uint32_t)0x00200000) /*!< Bit 1 */
3879 #define USART_CR3_WUFIE ((uint32_t)0x00400000) /*!< Wake Up Interrupt Enable */
3880 #define USART_CR3_UCESM ((uint32_t)0x00800000) /*!< Clock Enable in Stop mode */
3881
3882 /****************** Bit definition for USART_BRR register *******************/
3883 #define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /*!< Fraction of USARTDIV */
3884 #define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /*!< Mantissa of USARTDIV */
3885
3886 /****************** Bit definition for USART_GTPR register ******************/
3887 #define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */
3888 #define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< GT[7:0] bits (Guard time value) */
3889
3890
3891 /******************* Bit definition for USART_RTOR register *****************/
3892 #define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
3893 #define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
3894
3895 /******************* Bit definition for USART_RQR register ******************/
3896 #define USART_RQR_ABRRQ ((uint32_t)0x00000001) /*!< Auto-Baud Rate Request */
3897 #define USART_RQR_SBKRQ ((uint32_t)0x00000002) /*!< Send Break Request */
3898 #define USART_RQR_MMRQ ((uint32_t)0x00000004) /*!< Mute Mode Request */
3899 #define USART_RQR_RXFRQ ((uint32_t)0x00000008) /*!< Receive Data flush Request */
3900 #define USART_RQR_TXFRQ ((uint32_t)0x00000010) /*!< Transmit data flush Request */
3901
3902 /******************* Bit definition for USART_ISR register ******************/
3903 #define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
3904 #define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
3905 #define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
3906 #define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
3907 #define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
3908 #define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
3909 #define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
3910 #define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
3911 #define USART_ISR_LBD ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
3912 #define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
3913 #define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
3914 #define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
3915 #define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
3916 #define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
3917 #define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
3918 #define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
3919 #define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
3920 #define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
3921 #define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */
3922 #define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */
3923 #define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
3924 #define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
3925
3926 /******************* Bit definition for USART_ICR register ******************/
3927 #define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
3928 #define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
3929 #define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
3930 #define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
3931 #define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
3932 #define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
3933 #define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */
3934 #define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
3935 #define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
3936 #define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */
3937 #define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
3938 #define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */
3939
3940 /******************* Bit definition for USART_RDR register ******************/
3941 #define USART_RDR_RDR ((uint32_t)0x000001FF) /*!< RDR[8:0] bits (Receive Data value) */
3942
3943 /******************* Bit definition for USART_TDR register ******************/
3944 #define USART_TDR_TDR ((uint32_t)0x000001FF) /*!< TDR[8:0] bits (Transmit Data value) */
3945
3946 /******************************************************************************/
3947 /* */
3948 /* USB Device General registers */
3949 /* */
3950 /******************************************************************************/
3951 #define USB_BASE ((uint32_t)0x40005C00) /*!< USB_IP Peripheral Registers base address */
3952 #define USB_PMAADDR ((uint32_t)0x40006000) /*!< USB_IP Packet Memory Area base address */
3953
3954 #define USB_CNTR (USB_BASE + 0x40) /*!< Control register */
3955 #define USB_ISTR (USB_BASE + 0x44) /*!< Interrupt status register */
3956 #define USB_FNR (USB_BASE + 0x48) /*!< Frame number register */
3957 #define USB_DADDR (USB_BASE + 0x4C) /*!< Device address register */
3958 #define USB_BTABLE (USB_BASE + 0x50) /*!< Buffer Table address register */
3959 #define USB_LPMCSR (USB_BASE + 0x54) /*!< LPM Control and Status register */
3960 #define USB_BCDR (USB_BASE + 0x58) /*!< Battery Charging detector register*/
3961
3962 /**************************** ISTR interrupt events *************************/
3963 #define USB_ISTR_CTR ((uint16_t)0x8000) /*!< Correct TRansfer (clear-only bit) */
3964 #define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!< DMA OVeR/underrun (clear-only bit) */
3965 #define USB_ISTR_ERR ((uint16_t)0x2000) /*!< ERRor (clear-only bit) */
3966 #define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< WaKe UP (clear-only bit) */
3967 #define USB_ISTR_SUSP ((uint16_t)0x0800) /*!< SUSPend (clear-only bit) */
3968 #define USB_ISTR_RESET ((uint16_t)0x0400) /*!< RESET (clear-only bit) */
3969 #define USB_ISTR_SOF ((uint16_t)0x0200) /*!< Start Of Frame (clear-only bit) */
3970 #define USB_ISTR_ESOF ((uint16_t)0x0100) /*!< Expected Start Of Frame (clear-only bit) */
3971 #define USB_ISTR_L1REQ ((uint16_t)0x0080) /*!< LPM L1 state request */
3972 #define USB_ISTR_DIR ((uint16_t)0x0010) /*!< DIRection of transaction (read-only bit) */
3973 #define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< EndPoint IDentifier (read-only bit) */
3974
3975 #define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
3976 #define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
3977 #define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
3978 #define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
3979 #define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
3980 #define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
3981 #define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
3982 #define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
3983 #define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */
3984 /************************* CNTR control register bits definitions ***********/
3985 #define USB_CNTR_CTRM ((uint16_t)0x8000) /*!< Correct TRansfer Mask */
3986 #define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!< DMA OVeR/underrun Mask */
3987 #define USB_CNTR_ERRM ((uint16_t)0x2000) /*!< ERRor Mask */
3988 #define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!< WaKe UP Mask */
3989 #define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!< SUSPend Mask */
3990 #define USB_CNTR_RESETM ((uint16_t)0x0400) /*!< RESET Mask */
3991 #define USB_CNTR_SOFM ((uint16_t)0x0200) /*!< Start Of Frame Mask */
3992 #define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Mask */
3993 #define USB_CNTR_L1REQM ((uint16_t)0x0080) /*!< LPM L1 state request interrupt mask */
3994 #define USB_CNTR_L1RESUME ((uint16_t)0x0020) /*!< LPM L1 Resume request */
3995 #define USB_CNTR_RESUME ((uint16_t)0x0010) /*!< RESUME request */
3996 #define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!< Force SUSPend */
3997 #define USB_CNTR_LPMODE ((uint16_t)0x0004) /*!< Low-power MODE */
3998 #define USB_CNTR_PDWN ((uint16_t)0x0002) /*!< Power DoWN */
3999 #define USB_CNTR_FRES ((uint16_t)0x0001) /*!< Force USB RESet */
4000 /************************* BCDR control register bits definitions ***********/
4001 #define USB_BCDR_DPPU ((uint16_t)0x8000) /*!< DP Pull-up Enable */
4002 #define USB_BCDR_PS2DET ((uint16_t)0x0080) /*!< PS2 port or proprietary charger detected */
4003 #define USB_BCDR_SDET ((uint16_t)0x0040) /*!< Secondary detection (SD) status */
4004 #define USB_BCDR_PDET ((uint16_t)0x0020) /*!< Primary detection (PD) status */
4005 #define USB_BCDR_DCDET ((uint16_t)0x0010) /*!< Data contact detection (DCD) status */
4006 #define USB_BCDR_SDEN ((uint16_t)0x0008) /*!< Secondary detection (SD) mode enable */
4007 #define USB_BCDR_PDEN ((uint16_t)0x0004) /*!< Primary detection (PD) mode enable */
4008 #define USB_BCDR_DCDEN ((uint16_t)0x0002) /*!< Data contact detection (DCD) mode enable */
4009 #define USB_BCDR_BCDEN ((uint16_t)0x0001) /*!< Battery charging detector (BCD) enable */
4010 /*************************** LPM register bits definitions ******************/
4011 #define USB_LPMCSR_BESL ((uint16_t)0x00F0) /*!< BESL value received with last ACKed LPM Token */
4012 #define USB_LPMCSR_REMWAKE ((uint16_t)0x0008) /*!< bRemoteWake value received with last ACKed LPM Token */
4013 #define USB_LPMCSR_LPMACK ((uint16_t)0x0002) /*!< LPM Token acknowledge enable*/
4014 #define USB_LPMCSR_LMPEN ((uint16_t)0x0001) /*!< LPM support enable */
4015 /******************** FNR Frame Number Register bit definitions ************/
4016 #define USB_FNR_RXDP ((uint16_t)0x8000) /*!< status of D+ data line */
4017 #define USB_FNR_RXDM ((uint16_t)0x4000) /*!< status of D- data line */
4018 #define USB_FNR_LCK ((uint16_t)0x2000) /*!< LoCKed */
4019 #define USB_FNR_LSOF ((uint16_t)0x1800) /*!< Lost SOF */
4020 #define USB_FNR_FN ((uint16_t)0x07FF) /*!< Frame Number */
4021 /******************** DADDR Device ADDRess bit definitions ****************/
4022 #define USB_DADDR_EF ((uint8_t)0x80) /*!< USB device address Enable Function */
4023 #define USB_DADDR_ADD ((uint8_t)0x7F) /*!< USB device address */
4024 /****************************** Endpoint register *************************/
4025 #define USB_EP0R USB_BASE /*!< endpoint 0 register address */
4026 #define USB_EP1R (USB_BASE + 0x04) /*!< endpoint 1 register address */
4027 #define USB_EP2R (USB_BASE + 0x08) /*!< endpoint 2 register address */
4028 #define USB_EP3R (USB_BASE + 0x0C) /*!< endpoint 3 register address */
4029 #define USB_EP4R (USB_BASE + 0x10) /*!< endpoint 4 register address */
4030 #define USB_EP5R (USB_BASE + 0x14) /*!< endpoint 5 register address */
4031 #define USB_EP6R (USB_BASE + 0x18) /*!< endpoint 6 register address */
4032 #define USB_EP7R (USB_BASE + 0x1C) /*!< endpoint 7 register address */
4033 /* bit positions */
4034 #define USB_EP_CTR_RX ((uint16_t)0x8000) /*!< EndPoint Correct TRansfer RX */
4035 #define USB_EP_DTOG_RX ((uint16_t)0x4000) /*!< EndPoint Data TOGGLE RX */
4036 #define USB_EPRX_STAT ((uint16_t)0x3000) /*!< EndPoint RX STATus bit field */
4037 #define USB_EP_SETUP ((uint16_t)0x0800) /*!< EndPoint SETUP */
4038 #define USB_EP_T_FIELD ((uint16_t)0x0600) /*!< EndPoint TYPE */
4039 #define USB_EP_KIND ((uint16_t)0x0100) /*!< EndPoint KIND */
4040 #define USB_EP_CTR_TX ((uint16_t)0x0080) /*!< EndPoint Correct TRansfer TX */
4041 #define USB_EP_DTOG_TX ((uint16_t)0x0040) /*!< EndPoint Data TOGGLE TX */
4042 #define USB_EPTX_STAT ((uint16_t)0x0030) /*!< EndPoint TX STATus bit field */
4043 #define USB_EPADDR_FIELD ((uint16_t)0x000F) /*!< EndPoint ADDRess FIELD */
4044
4045 /* EndPoint REGister MASK (no toggle fields) */
4046 #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
4047 /*!< EP_TYPE[1:0] EndPoint TYPE */
4048 #define USB_EP_TYPE_MASK ((uint16_t)0x0600) /*!< EndPoint TYPE Mask */
4049 #define USB_EP_BULK ((uint16_t)0x0000) /*!< EndPoint BULK */
4050 #define USB_EP_CONTROL ((uint16_t)0x0200) /*!< EndPoint CONTROL */
4051 #define USB_EP_ISOCHRONOUS ((uint16_t)0x0400) /*!< EndPoint ISOCHRONOUS */
4052 #define USB_EP_INTERRUPT ((uint16_t)0x0600) /*!< EndPoint INTERRUPT */
4053 #define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
4054
4055 #define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
4056 /*!< STAT_TX[1:0] STATus for TX transfer */
4057 #define USB_EP_TX_DIS ((uint16_t)0x0000) /*!< EndPoint TX DISabled */
4058 #define USB_EP_TX_STALL ((uint16_t)0x0010) /*!< EndPoint TX STALLed */
4059 #define USB_EP_TX_NAK ((uint16_t)0x0020) /*!< EndPoint TX NAKed */
4060 #define USB_EP_TX_VALID ((uint16_t)0x0030) /*!< EndPoint TX VALID */
4061 #define USB_EPTX_DTOG1 ((uint16_t)0x0010) /*!< EndPoint TX Data TOGgle bit1 */
4062 #define USB_EPTX_DTOG2 ((uint16_t)0x0020) /*!< EndPoint TX Data TOGgle bit2 */
4063 #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
4064 /*!< STAT_RX[1:0] STATus for RX transfer */
4065 #define USB_EP_RX_DIS ((uint16_t)0x0000) /*!< EndPoint RX DISabled */
4066 #define USB_EP_RX_STALL ((uint16_t)0x1000) /*!< EndPoint RX STALLed */
4067 #define USB_EP_RX_NAK ((uint16_t)0x2000) /*!< EndPoint RX NAKed */
4068 #define USB_EP_RX_VALID ((uint16_t)0x3000) /*!< EndPoint RX VALID */
4069 #define USB_EPRX_DTOG1 ((uint16_t)0x1000) /*!< EndPoint RX Data TOGgle bit1 */
4070 #define USB_EPRX_DTOG2 ((uint16_t)0x2000) /*!< EndPoint RX Data TOGgle bit1 */
4071 #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
4072
4073 /******************************************************************************/
4074 /* */
4075 /* Window WATCHDOG (WWDG) */
4076 /* */
4077 /******************************************************************************/
4078
4079 /******************* Bit definition for WWDG_CR register ********************/
4080 #define WWDG_CR_T ((uint32_t)0x0000007F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
4081 #define WWDG_CR_T0 ((uint32_t)0x00000001) /*!< Bit 0 */
4082 #define WWDG_CR_T1 ((uint32_t)0x00000002) /*!< Bit 1 */
4083 #define WWDG_CR_T2 ((uint32_t)0x00000004) /*!< Bit 2 */
4084 #define WWDG_CR_T3 ((uint32_t)0x00000008) /*!< Bit 3 */
4085 #define WWDG_CR_T4 ((uint32_t)0x00000010) /*!< Bit 4 */
4086 #define WWDG_CR_T5 ((uint32_t)0x00000020) /*!< Bit 5 */
4087 #define WWDG_CR_T6 ((uint32_t)0x00000040) /*!< Bit 6 */
4088
4089 #define WWDG_CR_WDGA ((uint32_t)0x00000080) /*!< Activation bit */
4090
4091 /******************* Bit definition for WWDG_CFR register *******************/
4092 #define WWDG_CFR_W ((uint32_t)0x0000007F) /*!< W[6:0] bits (7-bit window value) */
4093 #define WWDG_CFR_W0 ((uint32_t)0x00000001) /*!< Bit 0 */
4094 #define WWDG_CFR_W1 ((uint32_t)0x00000002) /*!< Bit 1 */
4095 #define WWDG_CFR_W2 ((uint32_t)0x00000004) /*!< Bit 2 */
4096 #define WWDG_CFR_W3 ((uint32_t)0x00000008) /*!< Bit 3 */
4097 #define WWDG_CFR_W4 ((uint32_t)0x00000010) /*!< Bit 4 */
4098 #define WWDG_CFR_W5 ((uint32_t)0x00000020) /*!< Bit 5 */
4099 #define WWDG_CFR_W6 ((uint32_t)0x00000040) /*!< Bit 6 */
4100
4101 #define WWDG_CFR_WDGTB ((uint32_t)0x00000180) /*!< WDGTB[1:0] bits (Timer Base) */
4102 #define WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) /*!< Bit 0 */
4103 #define WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) /*!< Bit 1 */
4104
4105 #define WWDG_CFR_EWI ((uint32_t)0x00000200) /*!< Early Wakeup Interrupt */
4106
4107 /******************* Bit definition for WWDG_SR register ********************/
4108 #define WWDG_SR_EWIF ((uint32_t)0x00000001) /*!< Early Wakeup Interrupt Flag */
4109
4110 /**
4111 * @}
4112 */
4113
4114 /**
4115 * @}
4116 */
4117
4118 /** @addtogroup Exported_macros
4119 * @{
4120 */
4121
4122 /******************************* ADC Instances ********************************/
4123 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
4124
4125 /******************************* COMP Instances *******************************/
4126 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
4127 ((INSTANCE) == COMP2))
4128
4129 /******************************* CRC Instances ********************************/
4130 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
4131
4132 /******************************* DAC Instances *********************************/
4133 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
4134
4135 /******************************* DMA Instances *********************************/
4136 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
4137 ((INSTANCE) == DMA1_Stream1) || \
4138 ((INSTANCE) == DMA1_Stream2) || \
4139 ((INSTANCE) == DMA1_Stream3) || \
4140 ((INSTANCE) == DMA1_Stream4) || \
4141 ((INSTANCE) == DMA1_Stream5) || \
4142 ((INSTANCE) == DMA1_Stream6) || \
4143 ((INSTANCE) == DMA1_Stream7))
4144
4145 /******************************* GPIO Instances *******************************/
4146 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
4147 ((INSTANCE) == GPIOB) || \
4148 ((INSTANCE) == GPIOC) || \
4149 ((INSTANCE) == GPIOD) || \
4150 ((INSTANCE) == GPIOE) || \
4151 ((INSTANCE) == GPIOH))
4152
4153 /******************************** I2C Instances *******************************/
4154 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
4155 ((INSTANCE) == I2C2) || \
4156 ((INSTANCE) == I2C3))
4157
4158 /******************************** I2S Instances *******************************/
4159 #define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI2)
4160
4161 /******************************* RNG Instances ********************************/
4162 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
4163
4164 /****************************** RTC Instances *********************************/
4165 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
4166
4167 /******************************** SMBUS Instances *****************************/
4168 #define IS_SMBUS_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
4169 ((INSTANCE) == I2C3))
4170
4171 /******************************** SPI Instances *******************************/
4172 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
4173 ((INSTANCE) == SPI2))
4174
4175 /****************** LPTIM Instances : All supported instances *****************/
4176 #define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
4177
4178 /****************** TIM Instances : All supported instances *******************/
4179 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
4180 ((INSTANCE) == TIM3) || \
4181 ((INSTANCE) == TIM6) || \
4182 ((INSTANCE) == TIM7) || \
4183 ((INSTANCE) == TIM21) || \
4184 ((INSTANCE) == TIM22))
4185
4186 /************* TIM Instances : at least 1 capture/compare channel *************/
4187 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
4188 ((INSTANCE) == TIM3) || \
4189 ((INSTANCE) == TIM21) || \
4190 ((INSTANCE) == TIM22))
4191
4192 /************ TIM Instances : at least 2 capture/compare channels *************/
4193 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
4194 ((INSTANCE) == TIM3) || \
4195 ((INSTANCE) == TIM21) || \
4196 ((INSTANCE) == TIM22))
4197
4198 /************ TIM Instances : at least 3 capture/compare channels *************/
4199 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
4200 ((INSTANCE) == TIM3))
4201
4202 /************ TIM Instances : at least 4 capture/compare channels *************/
4203 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
4204 ((INSTANCE) == TIM3))
4205
4206 /******************** TIM Instances : Advanced-control timers *****************/
4207
4208 /******************* TIM Instances : Timer input XOR function *****************/
4209 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
4210 ((INSTANCE) == TIM3))
4211
4212 /****************** TIM Instances : DMA requests generation (UDE) *************/
4213 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
4214 ((INSTANCE) == TIM3) || \
4215 ((INSTANCE) == TIM6) || \
4216 ((INSTANCE) == TIM7))
4217
4218 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
4219 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
4220 ((INSTANCE) == TIM3))
4221
4222 /************ TIM Instances : DMA requests generation (COMDE) *****************/
4223 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
4224 (INSTANCE) == TIM3))
4225
4226 /******************** TIM Instances : DMA burst feature ***********************/
4227 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
4228 ((INSTANCE) == TIM3))
4229
4230 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
4231 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
4232 ((INSTANCE) == TIM3) || \
4233 ((INSTANCE) == TIM6) || \
4234 ((INSTANCE) == TIM7) || \
4235 ((INSTANCE) == TIM21) || \
4236 ((INSTANCE) == TIM22))
4237
4238 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
4239 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
4240 ((INSTANCE) == TIM3) || \
4241 ((INSTANCE) == TIM21) || \
4242 ((INSTANCE) == TIM22))
4243
4244 /********************** TIM Instances : 32 bit Counter ************************/
4245
4246 /***************** TIM Instances : external trigger input availabe ************/
4247 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
4248 ((INSTANCE) == TIM3) || \
4249 ((INSTANCE) == TIM21) || \
4250 ((INSTANCE) == TIM22))
4251
4252 /****************** TIM Instances : remapping capability **********************/
4253 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
4254 ((INSTANCE) == TIM3) || \
4255 ((INSTANCE) == TIM21) || \
4256 ((INSTANCE) == TIM22))
4257
4258 /******************* TIM Instances : output(s) available **********************/
4259 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
4260 (((((INSTANCE) == TIM2) || \
4261 ((INSTANCE) == TIM3)) \
4262 && \
4263 (((CHANNEL) == TIM_CHANNEL_1) || \
4264 ((CHANNEL) == TIM_CHANNEL_2) || \
4265 ((CHANNEL) == TIM_CHANNEL_3) || \
4266 ((CHANNEL) == TIM_CHANNEL_4))) \
4267 || \
4268 (((INSTANCE) == TIM21) && \
4269 (((CHANNEL) == TIM_CHANNEL_1) || \
4270 ((CHANNEL) == TIM_CHANNEL_2))) \
4271 || \
4272 (((INSTANCE) == TIM22) && \
4273 (((CHANNEL) == TIM_CHANNEL_1) || \
4274 ((CHANNEL) == TIM_CHANNEL_2))))
4275
4276 /******************** UART Instances : Asynchronous mode **********************/
4277 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
4278 ((INSTANCE) == USART2) || \
4279 ((INSTANCE) == USART4) || \
4280 ((INSTANCE) == USART5) || \
4281 ((INSTANCE) == LPUART1))
4282
4283 /******************** USART Instances : Synchronous mode **********************/
4284 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
4285 ((INSTANCE) == USART2) || \
4286 ((INSTANCE) == USART4) || \
4287 ((INSTANCE) == USART5))
4288
4289 /****************** USART Instances : Auto Baud Rate detection ****************/
4290
4291 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
4292 ((INSTANCE) == USART2))
4293
4294 /******************** UART Instances : Half-Duplex mode **********************/
4295 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
4296 ((INSTANCE) == USART2) || \
4297 ((INSTANCE) == USART4) || \
4298 ((INSTANCE) == USART5) || \
4299 ((INSTANCE) == LPUART1))
4300
4301 /******************** UART Instances : LIN mode **********************/
4302 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
4303 ((INSTANCE) == USART2))
4304
4305 /******************** UART Instances : Wake-up from Stop mode **********************/
4306
4307 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
4308 ((INSTANCE) == USART2) || \
4309 ((INSTANCE) == LPUART1))
4310
4311 /****************** UART Instances : Hardware Flow control ********************/
4312 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
4313 ((INSTANCE) == USART2) || \
4314 ((INSTANCE) == USART4) || \
4315 ((INSTANCE) == USART5) || \
4316 ((INSTANCE) == LPUART1))
4317
4318 /********************* UART Instances : Smard card mode ***********************/
4319 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
4320 ((INSTANCE) == USART2))
4321
4322 /*********************** UART Instances : IRDA mode ***************************/
4323 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
4324 ((INSTANCE) == USART2))
4325
4326 /****************************** IWDG Instances ********************************/
4327 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
4328
4329 /****************************** USB Instances ********************************/
4330 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
4331
4332 /****************************** WWDG Instances ********************************/
4333 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
4334
4335 /****************************** LCD Instances ********************************/
4336 #define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
4337
4338 /**
4339 * @}
4340 */
4341
4342 /******************************************************************************/
4343 /* For a painless codes migration between the STM32L0xx device product */
4344 /* lines, the aliases defined below are put in place to overcome the */
4345 /* differences in the interrupt handlers and IRQn definitions. */
4346 /* No need to update developed interrupt code when moving across */
4347 /* product lines within the same STM32L0 Family */
4348 /******************************************************************************/
4349
4350 /* Aliases for __IRQn */
4351
4352 #define LPUART1_IRQn RNG_LPUART1_IRQn
4353 #define AES_LPUART1_IRQn RNG_LPUART1_IRQn
4354 #define AES_RNG_LPUART1_IRQn RNG_LPUART1_IRQn
4355 #define TIM6_IRQn TIM6_DAC_IRQn
4356 #define RCC_IRQn RCC_CRS_IRQn
4357
4358 /* Aliases for __IRQHandler */
4359 #define LPUART1_IRQHandler RNG_LPUART1_IRQHandler
4360 #define AES_LPUART1_IRQHandler RNG_LPUART1_IRQHandler
4361 #define AES_RNG_LPUART1_IRQHandler RNG_LPUART1_IRQHandler
4362 #define TIM6_IRQHandler TIM6_DAC_IRQHandler
4363 #define RCC_IRQHandler RCC_CRS_IRQHandler
4364
4365 /**
4366 * @}
4367 */
4368
4369 /**
4370 * @}
4371 */
4372
4373 #ifdef __cplusplus
4374 }
4375 #endif /* __cplusplus */
4376
4377 #endif /* __STM32L073xx_H */
4378
4379
4380
4381 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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