tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/system_stm32l0xx.c

   1 /**
   2   ******************************************************************************
   3   * @file    system_stm32l0xx.c
   4   * @author  MCD Application Team
   5   * @version V1.2.0
   6   * @date    06-February-2015
   7   * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File.
   8   *
   9   *   This file provides two functions and one global variable to be called from
  10   *   user application:
  11   *      - SystemInit(): This function is called at startup just after reset and
  12   *                      before branch to main program. This call is made inside
  13   *                      the "startup_stm32l0xx.s" file.
  14   *
  15   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
  16   *                                  by the user application to setup the SysTick
  17   *                                  timer or configure other parameters.
  18   *
  19   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
  20   *                                 be called whenever the core clock is changed
  21   *                                 during program execution.
  22   *
  23   * This file configures the system clock as follows:
  24   *-----------------------------------------------------------------------------
  25   * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
  26   *                                    | (external 8 MHz clock) | (internal 16 MHz)
  27   *                                    | 2- PLL_HSE_XTAL        |
  28   *                                    | (external 8 MHz xtal)  |
  29   *-----------------------------------------------------------------------------
  30   * SYSCLK(MHz)                        | 32                     | 32
  31   *-----------------------------------------------------------------------------
  32   * AHBCLK (MHz)                       | 32                     | 32
  33   *-----------------------------------------------------------------------------
  34   * APB1CLK (MHz)                      | 32                     | 32
  35   *-----------------------------------------------------------------------------
  36   * APB2CLK (MHz)                      | 32                     | 32
  37   *-----------------------------------------------------------------------------
  38   * USB capable (48 MHz precise clock) | YES                    | YES
  39   *-----------------------------------------------------------------------------
  40   ******************************************************************************
  41   * @attention
  42   *
  43   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
  44   *
  45   * Redistribution and use in source and binary forms, with or without modification,
  46   * are permitted provided that the following conditions are met:
  47   *   1. Redistributions of source code must retain the above copyright notice,
  48   *      this list of conditions and the following disclaimer.
  49   *   2. Redistributions in binary form must reproduce the above copyright notice,
  50   *      this list of conditions and the following disclaimer in the documentation
  51   *      and/or other materials provided with the distribution.
  52   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  53   *      may be used to endorse or promote products derived from this software
  54   *      without specific prior written permission.
  55   *
  56   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  57   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  58   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  59   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  60   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  61   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  62   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  63   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  64   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  65   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  66   *
  67   ******************************************************************************
  68   */
  69
  70 /** @addtogroup CMSIS
  71   * @{
  72   */
  73
  74 /** @addtogroup stm32l0xx_system
  75   * @{
  76   */
  77
  78 /** @addtogroup STM32L0xx_System_Private_Includes
  79   * @{
  80   */
  81
  82 #include "stm32l0xx.h"
  83 #include "hal_tick.h"
  84
  85 #if !defined  (HSE_VALUE)
  86   #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
  87 #endif /* HSE_VALUE */
  88
  89 #if !defined  (MSI_VALUE)
  90   #define MSI_VALUE    ((uint32_t)2000000) /*!< Value of the Internal oscillator in Hz*/
  91 #endif /* MSI_VALUE */
  92
  93 #if !defined  (HSI_VALUE)
  94   #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
  95 #endif /* HSI_VALUE */
  96
  97
  98 /**
  99   * @}
 100   */
 101
 102 /** @addtogroup STM32L0xx_System_Private_TypesDefinitions
 103   * @{
 104   */
 105
 106 /**
 107   * @}
 108   */
 109
 110 /** @addtogroup STM32L0xx_System_Private_Defines
 111   * @{
 112   */
 113 /************************* Miscellaneous Configuration ************************/
 114
 115 /*!< Uncomment the following line if you need to relocate your vector Table in
 116      Internal SRAM. */
 117 /* #define VECT_TAB_SRAM */
 118 #define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field.
 119                                    This value must be a multiple of 0x200. */
 120 /******************************************************************************/
 121 /**
 122   * @}
 123   */
 124
 125 /** @addtogroup STM32L0xx_System_Private_Macros
 126   * @{
 127   */
 128
 129 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
 130 #define USE_PLL_HSE_EXTC (1) /* Use external clock */
 131 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
 132
 133 /**
 134   * @}
 135   */
 136
 137 /** @addtogroup STM32L0xx_System_Private_Variables
 138   * @{
 139   */
 140   /* This variable is updated in three ways:
 141       1) by calling CMSIS function SystemCoreClockUpdate()
 142       2) by calling HAL API function HAL_RCC_GetHCLKFreq()
 143       3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
 144          Note: If you use this function to configure the system clock; then there
 145                is no need to call the 2 first functions listed above, since SystemCoreClock
 146                variable is updated automatically.
 147   */
 148 uint32_t SystemCoreClock = 32000000;
 149 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
 150 const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
 151
 152 /**
 153   * @}
 154   */
 155
 156 /** @addtogroup STM32L0xx_System_Private_FunctionPrototypes
 157   * @{
 158   */
 159
 160 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
 161 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
 162 #endif
 163
 164 uint8_t SetSysClock_PLL_HSI(void);
 165
 166 /**
 167   * @}
 168   */
 169
 170 /** @addtogroup STM32L0xx_System_Private_Functions
 171   * @{
 172   */
 173
 174 /**
 175   * @brief  Setup the microcontroller system.
 176   * @param  None
 177   * @retval None
 178   */
 179 void SystemInit (void)
 180 {
 181 /*!< Set MSION bit */
 182   RCC->CR |= (uint32_t)0x00000100;
 183
 184   /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
 185   RCC->CFGR &= (uint32_t) 0x88FF400C;
 186
 187   /*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */
 188   RCC->CR &= (uint32_t)0xFEF6FFF6;
 189
 190   /*!< Reset HSI48ON  bit */
 191   RCC->CRRCR &= (uint32_t)0xFFFFFFFE;
 192
 193   /*!< Reset HSEBYP bit */
 194   RCC->CR &= (uint32_t)0xFFFBFFFF;
 195
 196   /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
 197   RCC->CFGR &= (uint32_t)0xFF02FFFF;
 198
 199   /*!< Disable all interrupts */
 200   RCC->CIER = 0x00000000;
 201
 202   /* Configure the Vector Table location add offset address ------------------*/
 203 #ifdef VECT_TAB_SRAM
 204   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
 205 #else
 206   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
 207 #endif
 208
 209   /* Configure the Cube driver */
 210   SystemCoreClock = 8000000; // At this stage the HSI is used as system clock
 211   HAL_Init();
 212
 213   /* Configure the System clock source, PLL Multiplier and Divider factors,
 214      AHB/APBx prescalers and Flash settings */
 215   SetSysClock();
 216
 217   /* Reset the timer to avoid issues after the RAM initialization */
 218   TIM_MST_RESET_ON;
 219   TIM_MST_RESET_OFF;
 220 }
 221
 222 /**
 223   * @brief  Update SystemCoreClock according to Clock Register Values
 224   *         The SystemCoreClock variable contains the core clock (HCLK), it can
 225   *         be used by the user application to setup the SysTick timer or configure
 226   *         other parameters.
 227   *
 228   * @note   Each time the core clock (HCLK) changes, this function must be called
 229   *         to update SystemCoreClock variable value. Otherwise, any configuration
 230   *         based on this variable will be incorrect.
 231   *
 232   * @note   - The system frequency computed by this function is not the real
 233   *           frequency in the chip. It is calculated based on the predefined
 234   *           constant and the selected clock source:
 235   *
 236   *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
 237   *             value as defined by the MSI range.
 238   *
 239   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
 240   *
 241   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
 242   *
 243   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
 244   *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
 245   *
 246   *         (*) HSI_VALUE is a constant defined in stm32l0xx_hal.h file (default value
 247   *             16 MHz) but the real value may vary depending on the variations
 248   *             in voltage and temperature.
 249   *
 250   *         (**) HSE_VALUE is a constant defined in stm32l0xx_hal.h file (default value
 251   *              8 MHz), user has to ensure that HSE_VALUE is same as the real
 252   *              frequency of the crystal used. Otherwise, this function may
 253   *              have wrong result.
 254   *
 255   *         - The result of this function could be not correct when using fractional
 256   *           value for HSE crystal.
 257   * @param  None
 258   * @retval None
 259   */
 260 void SystemCoreClockUpdate (void)
 261 {
 262   uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
 263
 264   /* Get SYSCLK source -------------------------------------------------------*/
 265   tmp = RCC->CFGR & RCC_CFGR_SWS;
 266
 267   switch (tmp)
 268   {
 269     case 0x00:  /* MSI used as system clock */
 270       msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
 271       SystemCoreClock = (32768 * (1 << (msirange + 1)));
 272       break;
 273     case 0x04:  /* HSI used as system clock */
 274       SystemCoreClock = HSI_VALUE;
 275       break;
 276     case 0x08:  /* HSE used as system clock */
 277       SystemCoreClock = HSE_VALUE;
 278       break;
 279     case 0x0C:  /* PLL used as system clock */
 280       /* Get PLL clock source and multiplication factor ----------------------*/
 281       pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
 282       plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
 283       pllmul = PLLMulTable[(pllmul >> 18)];
 284       plldiv = (plldiv >> 22) + 1;
 285
 286       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
 287
 288       if (pllsource == 0x00)
 289       {
 290         /* HSI oscillator clock selected as PLL clock entry */
 291         SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
 292       }
 293       else
 294       {
 295         /* HSE selected as PLL clock entry */
 296         SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
 297       }
 298       break;
 299     default: /* MSI used as system clock */
 300       msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
 301       SystemCoreClock = (32768 * (1 << (msirange + 1)));
 302       break;
 303   }
 304   /* Compute HCLK clock frequency --------------------------------------------*/
 305   /* Get HCLK prescaler */
 306   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
 307   /* HCLK clock frequency */
 308   SystemCoreClock >>= tmp;
 309 }
 310
 311 /**
 312   * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
 313   *               AHB/APBx prescalers and Flash settings
 314   * @note   This function should be called only once the RCC clock configuration
 315   *         is reset to the default reset state (done in SystemInit() function).
 316   * @param  None
 317   * @retval None
 318   */
 319 void SetSysClock(void)
 320 {
 321   /* 1- Try to start with HSE and external clock */
 322 #if USE_PLL_HSE_EXTC != 0
 323   if (SetSysClock_PLL_HSE(1) == 0)
 324 #endif
 325   {
 326     /* 2- If fail try to start with HSE and external xtal */
 327     #if USE_PLL_HSE_XTAL != 0
 328     if (SetSysClock_PLL_HSE(0) == 0)
 329     #endif
 330     {
 331       /* 3- If fail start with HSI clock */
 332       if (SetSysClock_PLL_HSI() == 0)
 333       {
 334         while(1)
 335         {
 336           // [TODO] Put something here to tell the user that a problem occured...
 337         }
 338       }
 339     }
 340   }
 341
 342   /* Output clock on MCO1 pin(PA8) for debugging purpose */
 343   //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
 344   //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI48, RCC_MCODIV_1);
 345 }
 346
 347 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
 348 /******************************************************************************/
 349 /*            PLL (clocked by HSE) used as System clock source                */
 350 /******************************************************************************/
 351 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
 352 {
 353   RCC_ClkInitTypeDef RCC_ClkInitStruct;
 354   RCC_OscInitTypeDef RCC_OscInitStruct;
 355
 356   /* Used to gain time after DeepSleep in case HSI is used */
 357   if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
 358   {
 359     return 0;
 360   }
 361
 362   /* The voltage scaling allows optimizing the power consumption when the device is
 363      clocked below the maximum system frequency, to update the voltage scaling value
 364      regarding system frequency refer to product datasheet. */
 365   __PWR_CLK_ENABLE();
 366   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
 367
 368   /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */
 369   RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
 370   if (bypass == 0)
 371   {
 372     RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
 373   }
 374   else
 375   {
 376     RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
 377   }
 378   RCC_OscInitStruct.HSIState            = RCC_HSI_OFF;
 379   RCC_OscInitStruct.HSI48State          = RCC_HSI48_ON; /* For USB and RNG clock */
 380   // PLLCLK = (8 MHz * 8)/2 = 32 MHz
 381   RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
 382   RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
 383   RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLLMUL_8;
 384   RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLLDIV_2;
 385   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 386   {
 387     return 0; // FAIL
 388   }
 389
 390   /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
 391   RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
 392   RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
 393   RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
 394   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
 395   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
 396   if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
 397   {
 398     return 0; // FAIL
 399   }
 400
 401   /* Output clock on MCO1 pin(PA8) for debugging purpose */
 402   //if (bypass == 0)
 403   //  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
 404   //else
 405   //  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
 406
 407   return 1; // OK
 408 }
 409 #endif
 410
 411 /******************************************************************************/
 412 /*            PLL (clocked by HSI) used as System clock source                */
 413 /******************************************************************************/
 414 uint8_t SetSysClock_PLL_HSI(void)
 415 {
 416   RCC_ClkInitTypeDef RCC_ClkInitStruct;
 417   RCC_OscInitTypeDef RCC_OscInitStruct;
 418
 419   /* The voltage scaling allows optimizing the power consumption when the device is
 420      clocked below the maximum system frequency, to update the voltage scaling value
 421      regarding system frequency refer to product datasheet. */
 422   __PWR_CLK_ENABLE();
 423   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
 424
 425   /* Enable HSI and HSI48 oscillators and activate PLL with HSI as source */
 426   RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
 427   RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
 428   RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
 429   RCC_OscInitStruct.HSI48State          = RCC_HSI48_ON; /* For USB and RNG clock */
 430   // PLLCLK = (16 MHz * 4)/2 = 32 MHz
 431   RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
 432   RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
 433   RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLLMUL_4;
 434   RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLLDIV_2;
 435   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 436   {
 437     return 0; // FAIL
 438   }
 439
 440   /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
 441   RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
 442   RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
 443   RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
 444   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
 445   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
 446   if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
 447   {
 448     return 0; // FAIL
 449   }
 450
 451   /* Output clock on MCO1 pin(PA8) for debugging purpose */
 452   //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
 453
 454   return 1; // OK
 455 }
 456
 457 /**
 458   * @}
 459   */
 460
 461 /**
 462   * @}
 463   */
 464
 465 /**
 466   * @}
 467   */
 468
 469 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/