tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32_hal_legacy.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32_hal_legacy.h
   4   * @author  MCD Application Team
   5   * @version V1.2.0RC4
   6   * @date    23-January-2015
   7   * @brief   This file contains aliases definition for the STM32Cube HAL constants
   8   *          macros and functions maintained for legacy purpose.
   9   ******************************************************************************
  10   * @attention
  11   *
  12   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
  13   *
  14   * Redistribution and use in source and binary forms, with or without modification,
  15   * are permitted provided that the following conditions are met:
  16   *   1. Redistributions of source code must retain the above copyright notice,
  17   *      this list of conditions and the following disclaimer.
  18   *   2. Redistributions in binary form must reproduce the above copyright notice,
  19   *      this list of conditions and the following disclaimer in the documentation
  20   *      and/or other materials provided with the distribution.
  21   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  22   *      may be used to endorse or promote products derived from this software
  23   *      without specific prior written permission.
  24   *
  25   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  26   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  27   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  28   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  29   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  30   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  31   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  32   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  33  UART * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  34   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35   *
  36   ******************************************************************************
  37   */
  38
  39 /* Define to prevent recursive inclusion -------------------------------------*/
  40 #ifndef __STM32_HAL_LEGACY
  41 #define __STM32_HAL_LEGACY
  42
  43 #ifdef __cplusplus
  44  extern "C" {
  45 #endif
  46
  47 /* Includes ------------------------------------------------------------------*/
  48 /* Exported types ------------------------------------------------------------*/
  49 /* Exported constants --------------------------------------------------------*/
  50
  51 /** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
  52   * @{
  53   */
  54 #define AES_FLAG_RDERR                 CRYP_FLAG_RDERR
  55 #define AES_FLAG_WRERR                 CRYP_FLAG_WRERR
  56 #define AES_CLEARFLAG_CCF               CRYP_CLEARFLAG_CCF
  57 #define AES_CLEARFLAG_RDERR             CRYP_CLEARFLAG_RDERR
  58 #define AES_CLEARFLAG_WRERR             CRYP_CLEARFLAG_WRERR
  59
  60 /**
  61   * @}
  62   */
  63
  64 /** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
  65   * @{
  66   */
  67 #define ADC_RESOLUTION12b               ADC_RESOLUTION_12B
  68 #define ADC_RESOLUTION10b               ADC_RESOLUTION_10B
  69 #define ADC_RESOLUTION8b                ADC_RESOLUTION_8B
  70 #define ADC_RESOLUTION6b                ADC_RESOLUTION_6B
  71 #define OVR_DATA_OVERWRITTEN            ADC_OVR_DATA_OVERWRITTEN
  72 #define OVR_DATA_PRESERVED              ADC_OVR_DATA_PRESERVED
  73 #define EOC_SINGLE_CONV                 ADC_EOC_SINGLE_CONV
  74 #define EOC_SEQ_CONV                    ADC_EOC_SEQ_CONV
  75 #define EOC_SINGLE_SEQ_CONV             ADC_EOC_SINGLE_SEQ_CONV
  76 #define REGULAR_GROUP                   ADC_REGULAR_GROUP
  77 #define INJECTED_GROUP                  ADC_INJECTED_GROUP
  78 #define REGULAR_INJECTED_GROUP          ADC_REGULAR_INJECTED_GROUP
  79 #define AWD_EVENT                       ADC_AWD_EVENT
  80 #define AWD1_EVENT                      ADC_AWD1_EVENT
  81 #define AWD2_EVENT                      ADC_AWD2_EVENT
  82 #define AWD3_EVENT                      ADC_AWD3_EVENT
  83 #define OVR_EVENT                       ADC_OVR_EVENT
  84 #define JQOVF_EVENT                     ADC_JQOVF_EVENT
  85 #define ALL_CHANNELS                    ADC_ALL_CHANNELS
  86 #define REGULAR_CHANNELS                ADC_REGULAR_CHANNELS
  87 #define INJECTED_CHANNELS               ADC_INJECTED_CHANNELS
  88 #define SYSCFG_FLAG_SENSOR_ADC          ADC_FLAG_SENSOR
  89 #define SYSCFG_FLAG_VREF_ADC            ADC_FLAG_VREFINT
  90 #define ADC_CLOCKPRESCALER_PCLK_DIV1    ADC_CLOCK_SYNC_PCLK_DIV1
  91 #define ADC_CLOCKPRESCALER_PCLK_DIV2    ADC_CLOCK_SYNC_PCLK_DIV2
  92 #define ADC_CLOCKPRESCALER_PCLK_DIV4    ADC_CLOCK_SYNC_PCLK_DIV4
  93 #define ADC_EXTERNALTRIG0_T6_TRGO       ADC_EXTERNALTRIGCONV_T6_TRGO
  94 #define ADC_EXTERNALTRIG1_T21_CC2       ADC_EXTERNALTRIGCONV_T21_CC2
  95 #define ADC_EXTERNALTRIG2_T2_TRGO       ADC_EXTERNALTRIGCONV_T2_TRGO
  96 #define ADC_EXTERNALTRIG3_T2_CC4        ADC_EXTERNALTRIGCONV_T2_CC4
  97 #define ADC_EXTERNALTRIG4_T22_TRGO      ADC_EXTERNALTRIGCONV_T22_TRGO
  98 #define ADC_EXTERNALTRIG7_EXT_IT11      ADC_EXTERNALTRIGCONV_EXT_IT11
  99 #define ADC_CLOCK_ASYNC                 ADC_CLOCK_ASYNC_DIV1
 100 #define ADC_EXTERNALTRIG_EDGE_NONE      ADC_EXTERNALTRIGCONVEDGE_NONE
 101 #define ADC_EXTERNALTRIG_EDGE_RISING    ADC_EXTERNALTRIGCONVEDGE_RISING
 102 #define ADC_EXTERNALTRIG_EDGE_FALLING   ADC_EXTERNALTRIGCONVEDGE_FALLING
 103 #define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
 104 /**
 105   * @}
 106   */
 107
 108 /** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
 109   * @{
 110   */
 111
 112 #define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
 113
 114 /**
 115   * @}
 116   */
 117
 118 /** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
 119   * @{
 120   */
 121
 122 #define COMP_WINDOWMODE_DISABLED    COMP_WINDOWMODE_DISABLE
 123 #define COMP_WINDOWMODE_ENABLED     COMP_WINDOWMODE_ENABLE
 124 #define COMP_EXTI_LINE_COMP1_EVENT  COMP_EXTI_LINE_COMP1
 125 #define COMP_EXTI_LINE_COMP2_EVENT  COMP_EXTI_LINE_COMP2
 126
 127 /**
 128   * @}
 129   */
 130
 131 /** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
 132   * @{
 133   */
 134
 135 #define CRC_OUTPUTDATA_INVERSION_DISABLED    CRC_OUTPUTDATA_INVERSION_DISABLE
 136 #define CRC_OUTPUTDATA_INVERSION_ENABLED     CRC_OUTPUTDATA_INVERSION_ENABLE
 137
 138 /**
 139   * @}
 140   */
 141
 142 /** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
 143   * @{
 144   */
 145
 146 #define DAC1_CHANNEL_1                                  DAC_CHANNEL_1
 147 #define DAC1_CHANNEL_2                                  DAC_CHANNEL_2
 148 #define DAC2_CHANNEL_1                                  DAC_CHANNEL_1
 149 #define DAC_WAVE_NONE                                   ((uint32_t)0x00000000)
 150 #define DAC_WAVE_NOISE                                  ((uint32_t)DAC_CR_WAVE1_0)
 151 #define DAC_WAVE_TRIANGLE                               ((uint32_t)DAC_CR_WAVE1_1)
 152 #define DAC_WAVEGENERATION_NONE                         DAC_WAVE_NONE
 153 #define DAC_WAVEGENERATION_NOISE                        DAC_WAVE_NOISE
 154 #define DAC_WAVEGENERATION_TRIANGLE                     DAC_WAVE_TRIANGLE
 155
 156 /**
 157   * @}
 158   */
 159
 160
 161 /** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
 162   * @{
 163   */
 164
 165 #define TYPEPROGRAM_BYTE              FLASH_TYPEPROGRAM_BYTE
 166 #define TYPEPROGRAM_HALFWORD          FLASH_TYPEPROGRAM_HALFWORD
 167 #define TYPEPROGRAM_WORD              FLASH_TYPEPROGRAM_WORD
 168 #define TYPEPROGRAM_DOUBLEWORD        FLASH_TYPEPROGRAM_DOUBLEWORD
 169 #define TYPEERASE_SECTORS             FLASH_TYPEERASE_SECTORS
 170 #define TYPEERASE_PAGES               FLASH_TYPEERASE_PAGES
 171 #define TYPEERASE_PAGEERASE           FLASH_TYPEERASE_PAGES
 172 #define TYPEERASE_MASSERASE           FLASH_TYPEERASE_MASSERASE
 173 #define WRPSTATE_DISABLE              OB_WRPSTATE_DISABLE
 174 #define WRPSTATE_ENABLE               OB_WRPSTATE_ENABLE
 175 #define HAL_FLASH_TIMEOUT_VALUE       FLASH_TIMEOUT_VALUE
 176 #define OBEX_PCROP                    OPTIONBYTE_PCROP
 177 #define OBEX_BOOTCONFIG               OPTIONBYTE_BOOTCONFIG
 178 #define PCROPSTATE_DISABLE            OB_PCROP_STATE_DISABLE
 179 #define PCROPSTATE_ENABLE             OB_PCROP_STATE_ENABLE
 180 #define TYPEERASEDATA_BYTE            FLASH_TYPEERASEDATA_BYTE
 181 #define TYPEERASEDATA_HALFWORD        FLASH_TYPEERASEDATA_HALFWORD
 182 #define TYPEERASEDATA_WORD            FLASH_TYPEERASEDATA_WORD
 183 #define TYPEPROGRAMDATA_BYTE          FLASH_TYPEPROGRAMDATA_BYTE
 184 #define TYPEPROGRAMDATA_HALFWORD      FLASH_TYPEPROGRAMDATA_HALFWORD
 185 #define TYPEPROGRAMDATA_WORD          FLASH_TYPEPROGRAMDATA_WORD
 186 #define TYPEPROGRAMDATA_FASTBYTE      FLASH_TYPEPROGRAMDATA_FASTBYTE
 187 #define TYPEPROGRAMDATA_FASTHALFWORD  FLASH_TYPEPROGRAMDATA_FASTHALFWORD
 188 #define TYPEPROGRAMDATA_FASTWORD      FLASH_TYPEPROGRAMDATA_FASTWORD
 189 #define PAGESIZE                      FLASH_PAGE_SIZE
 190 #define TYPEPROGRAM_FASTBYTE          FLASH_TYPEPROGRAM_BYTE
 191 #define TYPEPROGRAM_FASTHALFWORD      FLASH_TYPEPROGRAM_HALFWORD
 192 #define TYPEPROGRAM_FASTWORD          FLASH_TYPEPROGRAM_WORD
 193 #define VOLTAGE_RANGE_1               FLASH_VOLTAGE_RANGE_1
 194 #define VOLTAGE_RANGE_2               FLASH_VOLTAGE_RANGE_2
 195 #define VOLTAGE_RANGE_3               FLASH_VOLTAGE_RANGE_3
 196 #define VOLTAGE_RANGE_4               FLASH_VOLTAGE_RANGE_4
 197 #define TYPEPROGRAM_FAST              FLASH_TYPEPROGRAM_FAST
 198 #define TYPEPROGRAM_FAST_AND_LAST     FLASH_TYPEPROGRAM_FAST_AND_LAST
 199 #define WRPAREA_BANK1_AREAA           OB_WRPAREA_BANK1_AREAA
 200 #define WRPAREA_BANK1_AREAB           OB_WRPAREA_BANK1_AREAB
 201 #define WRPAREA_BANK2_AREAA           OB_WRPAREA_BANK2_AREAA
 202 #define WRPAREA_BANK2_AREAB           OB_WRPAREA_BANK2_AREAB
 203 #define IWDG_STDBY_FREEZE             OB_IWDG_STDBY_FREEZE
 204 #define IWDG_STDBY_ACTIVE             OB_IWDG_STDBY_RUN
 205 #define IWDG_STOP_FREEZE              OB_IWDG_STOP_FREEZE
 206 #define IWDG_STOP_ACTIVE              OB_IWDG_STOP_RUN
 207 #define IS_NBSECTORS                  IS_FLASH_NBSECTORS
 208 #define FLASH_ERROR_NONE              HAL_FLASH_ERROR_NONE
 209 #define FLASH_ERROR_RD                HAL_FLASH_ERROR_RD
 210 #define FLASH_ERROR_PG                HAL_FLASH_ERROR_PROG
 211 #define FLASH_ERROR_PGP               HAL_FLASH_ERROR_PGS
 212 #define FLASH_ERROR_WRP               HAL_FLASH_ERROR_WRP
 213 #define FLASH_ERROR_OPTV              HAL_FLASH_ERROR_OPTV
 214 #define FLASH_ERROR_OPTVUSR           HAL_FLASH_ERROR_OPTVUSR
 215 #define FLASH_ERROR_PROG              HAL_FLASH_ERROR_PROG
 216 #define FLASH_ERROR_OP                HAL_FLASH_ERROR_OPERATION
 217 #define FLASH_ERROR_PGA               HAL_FLASH_ERROR_PGA
 218 #define FLASH_ERROR_SIZE              HAL_FLASH_ERROR_SIZE
 219 #define FLASH_ERROR_SIZ               HAL_FLASH_ERROR_SIZE
 220 #define FLASH_ERROR_PGS               HAL_FLASH_ERROR_PGS
 221 #define FLASH_ERROR_MIS               HAL_FLASH_ERROR_MIS
 222 #define FLASH_ERROR_FAST              HAL_FLASH_ERROR_FAST
 223 #define FLASH_ERROR_FWWERR            HAL_FLASH_ERROR_FWWERR
 224 #define FLASH_ERROR_NOTZERO           HAL_FLASH_ERROR_NOTZERO
 225 #define FLASH_ERROR_OPERATION         HAL_FLASH_ERROR_OPERATION
 226 #define FLASH_ERROR_ERS               HAL_FLASH_ERROR_ERS
 227
 228 /**
 229   * @}
 230   */
 231
 232 /** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
 233   * @{
 234   */
 235
 236 #define SYSCFG_FASTMODEPLUS_I2C_PB6    I2C_FASTMODEPLUS_PB6
 237 #define SYSCFG_FASTMODEPLUS_I2C_PB7    I2C_FASTMODEPLUS_PB7
 238 #define SYSCFG_FASTMODEPLUS_I2C_PB8    I2C_FASTMODEPLUS_PB8
 239 #define SYSCFG_FASTMODEPLUS_I2C_PB9    I2C_FASTMODEPLUS_PB9
 240 #define SYSCFG_FASTMODEPLUS_I2C1       I2C_FASTMODEPLUS_I2C1
 241 #define SYSCFG_FASTMODEPLUS_I2C2       I2C_FASTMODEPLUS_I2C2
 242 #define SYSCFG_FASTMODEPLUS_I2C3       I2C_FASTMODEPLUS_I2C3
 243
 244 /**
 245   * @}
 246   */
 247
 248
 249 /** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
 250   * @{
 251   */
 252
 253 #define FSMC_NORSRAM_TYPEDEF                      FSMC_NORSRAM_TypeDef
 254 #define FSMC_NORSRAM_EXTENDED_TYPEDEF             FSMC_NORSRAM_EXTENDED_TypeDef
 255 /**
 256   * @}
 257   */
 258
 259 /** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
 260   * @{
 261   */
 262 #define GET_GPIO_SOURCE                           GPIO_GET_INDEX
 263 #define GET_GPIO_INDEX                            GPIO_GET_INDEX
 264 /**
 265   * @}
 266   */
 267
 268
 269 /** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
 270   * @{
 271   */
 272 #define I2C_DUALADDRESS_DISABLED                I2C_DUALADDRESS_DISABLE
 273 #define I2C_DUALADDRESS_ENABLED                 I2C_DUALADDRESS_ENABLE
 274 #define I2C_GENERALCALL_DISABLED                I2C_GENERALCALL_DISABLE
 275 #define I2C_GENERALCALL_ENABLED                 I2C_GENERALCALL_ENABLE
 276 #define I2C_NOSTRETCH_DISABLED                  I2C_NOSTRETCH_DISABLE
 277 #define I2C_NOSTRETCH_ENABLED                   I2C_NOSTRETCH_ENABLE
 278 #define I2C_ANALOGFILTER_ENABLED                I2C_ANALOGFILTER_ENABLE
 279 #define I2C_ANALOGFILTER_DISABLED               I2C_ANALOGFILTER_DISABLE
 280 /**
 281   * @}
 282   */
 283
 284 /** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
 285   * @{
 286   */
 287 #define IRDA_ONE_BIT_SAMPLE_DISABLED            IRDA_ONE_BIT_SAMPLE_DISABLE
 288 #define IRDA_ONE_BIT_SAMPLE_ENABLED             IRDA_ONE_BIT_SAMPLE_ENABLE
 289
 290 /**
 291   * @}
 292   */
 293
 294 /** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
 295   * @{
 296   */
 297 #define KR_KEY_RELOAD                   IWDG_KEY_RELOAD
 298 #define KR_KEY_ENABLE                   IWDG_KEY_ENABLE
 299 #define KR_KEY_EWA                      IWDG_KEY_WRITE_ACCESS_ENABLE
 300 #define KR_KEY_DWA                      IWDG_KEY_WRITE_ACCESS_DISABLE
 301 /**
 302   * @}
 303   */
 304
 305 /** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
 306   * @{
 307   */
 308
 309 #define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
 310 #define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
 311 #define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
 312 #define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
 313
 314 #define LPTIM_CLOCKPOLARITY_RISINGEDGE          LPTIM_CLOCKPOLARITY_RISING
 315 #define LPTIM_CLOCKPOLARITY_FALLINGEDGE         LPTIM_CLOCKPOLARITY_FALLING
 316 #define LPTIM_CLOCKPOLARITY_BOTHEDGES           LPTIM_CLOCKPOLARITY_RISING_FALLING
 317 /**
 318   * @}
 319   */
 320
 321 /** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
 322   * @{
 323   */
 324 #define NAND_AddressTypedef             NAND_AddressTypeDef
 325
 326 /**
 327   * @}
 328   */
 329
 330 /** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
 331   * @{
 332   */
 333 #define NOR_StatusTypedef              HAL_NOR_StatusTypeDef
 334 #define NOR_SUCCESS                    HAL_NOR_STATUS_SUCCESS
 335 #define NOR_ONGOING                    HAL_NOR_STATUS_ONGOING
 336 #define NOR_ERROR                      HAL_NOR_STATUS_ERROR
 337 #define NOR_TIMEOUT                    HAL_NOR_STATUS_TIMEOUT
 338
 339 /**
 340   * @}
 341   */
 342
 343 /** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
 344   * @{
 345   */
 346
 347 #define OPAMP_NONINVERTINGINPUT_VP0           OPAMP_NONINVERTINGINPUT_IO0
 348 #define OPAMP_NONINVERTINGINPUT_VP1           OPAMP_NONINVERTINGINPUT_IO1
 349 #define OPAMP_NONINVERTINGINPUT_VP2           OPAMP_NONINVERTINGINPUT_IO2
 350 #define OPAMP_NONINVERTINGINPUT_VP3           OPAMP_NONINVERTINGINPUT_IO3
 351
 352 #define OPAMP_SEC_NONINVERTINGINPUT_VP0       OPAMP_SEC_NONINVERTINGINPUT_IO0
 353 #define OPAMP_SEC_NONINVERTINGINPUT_VP1       OPAMP_SEC_NONINVERTINGINPUT_IO1
 354 #define OPAMP_SEC_NONINVERTINGINPUT_VP2       OPAMP_SEC_NONINVERTINGINPUT_IO2
 355 #define OPAMP_SEC_NONINVERTINGINPUT_VP3       OPAMP_SEC_NONINVERTINGINPUT_IO3
 356
 357 #define OPAMP_INVERTINGINPUT_VM0              OPAMP_INVERTINGINPUT_IO0
 358 #define OPAMP_INVERTINGINPUT_VM1              OPAMP_INVERTINGINPUT_IO1
 359
 360 #define IOPAMP_INVERTINGINPUT_VM0             OPAMP_INVERTINGINPUT_IO0
 361 #define IOPAMP_INVERTINGINPUT_VM1             OPAMP_INVERTINGINPUT_IO1
 362
 363 #define OPAMP_SEC_INVERTINGINPUT_VM0          OPAMP_SEC_INVERTINGINPUT_IO0
 364 #define OPAMP_SEC_INVERTINGINPUT_VM1          OPAMP_SEC_INVERTINGINPUT_IO1
 365
 366 #define OPAMP_INVERTINGINPUT_VINM             OPAMP_SEC_INVERTINGINPUT_IO1
 367
 368 #define OPAMP_PGACONNECT_NO                   OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
 369 #define OPAMP_PGACONNECT_VM0                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
 370 #define OPAMP_PGACONNECT_VM1                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
 371
 372 /**
 373   * @}
 374   */
 375
 376 /** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
 377   * @{
 378   */
 379 #define I2S_STANDARD_PHILLIPS      I2S_STANDARD_PHILIPS
 380 /**
 381   * @}
 382   */
 383
 384 /** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
 385   * @{
 386   */
 387
 388 /* Compact Flash-ATA registers description */
 389 #define CF_DATA                       ATA_DATA
 390 #define CF_SECTOR_COUNT               ATA_SECTOR_COUNT
 391 #define CF_SECTOR_NUMBER              ATA_SECTOR_NUMBER
 392 #define CF_CYLINDER_LOW               ATA_CYLINDER_LOW
 393 #define CF_CYLINDER_HIGH              ATA_CYLINDER_HIGH
 394 #define CF_CARD_HEAD                  ATA_CARD_HEAD
 395 #define CF_STATUS_CMD                 ATA_STATUS_CMD
 396 #define CF_STATUS_CMD_ALTERNATE       ATA_STATUS_CMD_ALTERNATE
 397 #define CF_COMMON_DATA_AREA           ATA_COMMON_DATA_AREA
 398
 399 /* Compact Flash-ATA commands */
 400 #define CF_READ_SECTOR_CMD            ATA_READ_SECTOR_CMD
 401 #define CF_WRITE_SECTOR_CMD           ATA_WRITE_SECTOR_CMD
 402 #define CF_ERASE_SECTOR_CMD           ATA_ERASE_SECTOR_CMD
 403 #define CF_IDENTIFY_CMD               ATA_IDENTIFY_CMD
 404
 405 #define PCCARD_StatusTypedef          HAL_PCCARD_StatusTypeDef
 406 #define PCCARD_SUCCESS                HAL_PCCARD_STATUS_SUCCESS
 407 #define PCCARD_ONGOING                HAL_PCCARD_STATUS_ONGOING
 408 #define PCCARD_ERROR                  HAL_PCCARD_STATUS_ERROR
 409 #define PCCARD_TIMEOUT                HAL_PCCARD_STATUS_TIMEOUT
 410 /**
 411   * @}
 412   */
 413
 414 /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
 415   * @{
 416   */
 417
 418 #define FORMAT_BIN                  RTC_FORMAT_BIN
 419 #define FORMAT_BCD                  RTC_FORMAT_BCD
 420
 421 #define RTC_ALARMSUBSECONDMASK_None     RTC_ALARMSUBSECONDMASK_NONE
 422 #define RTC_TAMPERERASEBACKUP_ENABLED   RTC_TAMPER_ERASE_BACKUP_ENABLE
 423 #define RTC_TAMPERERASEBACKUP_DISABLED  RTC_TAMPER_ERASE_BACKUP_DISABLE
 424 #define RTC_TAMPERMASK_FLAG_DISABLED    RTC_TAMPERMASK_FLAG_DISABLE
 425 #define RTC_TAMPERMASK_FLAG_ENABLED     RTC_TAMPERMASK_FLAG_ENABLE
 426
 427 #define RTC_MASKTAMPERFLAG_DISABLED    RTC_TAMPERMASK_FLAG_DISABLE
 428 #define RTC_MASKTAMPERFLAG_ENABLED      RTC_TAMPERMASK_FLAG_ENABLE
 429 #define RTC_TAMPERERASEBACKUP_ENABLED  RTC_TAMPER_ERASE_BACKUP_ENABLE
 430 #define RTC_TAMPERERASEBACKUP_DISABLED   RTC_TAMPER_ERASE_BACKUP_DISABLE
 431 #define RTC_MASKTAMPERFLAG_DISABLED   RTC_TAMPERMASK_FLAG_DISABLE
 432 #define RTC_MASKTAMPERFLAG_ENABLED      RTC_TAMPERMASK_FLAG_ENABLE
 433 #define RTC_TAMPER1_2_INTERRUPT          RTC_ALL_TAMPER_INTERRUPT
 434 #define RTC_TAMPER1_2_3_INTERRUPT     RTC_ALL_TAMPER_INTERRUPT
 435
 436 /**
 437   * @}
 438   */
 439
 440
 441 /** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
 442   * @{
 443   */
 444 #define SMARTCARD_NACK_ENABLED                  SMARTCARD_NACK_ENABLE
 445 #define SMARTCARD_NACK_DISABLED                 SMARTCARD_NACK_DISABLE
 446
 447 #define SMARTCARD_ONEBIT_SAMPLING_DISABLED      SMARTCARD_ONE_BIT_SAMPLE_DISABLE
 448 #define SMARTCARD_ONEBIT_SAMPLING_ENABLED       SMARTCARD_ONE_BIT_SAMPLE_ENABLE
 449 #define SMARTCARD_ONEBIT_SAMPLING_DISABLE       SMARTCARD_ONE_BIT_SAMPLE_DISABLE
 450 #define SMARTCARD_ONEBIT_SAMPLING_ENABLE        SMARTCARD_ONE_BIT_SAMPLE_ENABLE
 451
 452 #define SMARTCARD_TIMEOUT_DISABLED              SMARTCARD_TIMEOUT_DISABLE
 453 #define SMARTCARD_TIMEOUT_ENABLED               SMARTCARD_TIMEOUT_ENABLE
 454
 455 #define SMARTCARD_LASTBIT_DISABLED              SMARTCARD_LASTBIT_DISABLE
 456 #define SMARTCARD_LASTBIT_ENABLED               SMARTCARD_LASTBIT_ENABLE
 457 /**
 458   * @}
 459   */
 460
 461
 462   /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
 463   * @{
 464   */
 465 #define SMBUS_DUALADDRESS_DISABLED      SMBUS_DUALADDRESS_DISABLE
 466 #define SMBUS_DUALADDRESS_ENABLED       SMBUS_DUALADDRESS_ENABLE
 467 #define SMBUS_GENERALCALL_DISABLED      SMBUS_GENERALCALL_DISABLE
 468 #define SMBUS_GENERALCALL_ENABLED       SMBUS_GENERALCALL_ENABLE
 469 #define SMBUS_NOSTRETCH_DISABLED        SMBUS_NOSTRETCH_DISABLE
 470 #define SMBUS_NOSTRETCH_ENABLED         SMBUS_NOSTRETCH_ENABLE
 471 #define SMBUS_ANALOGFILTER_ENABLED      SMBUS_ANALOGFILTER_ENABLE
 472 #define SMBUS_ANALOGFILTER_DISABLED     SMBUS_ANALOGFILTER_DISABLE
 473 #define HAL_SMBUS_STATE_SLAVE_LISTEN    HAL_SMBUS_STATE_LISTEN
 474 /**
 475   * @}
 476   */
 477
 478   /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
 479   * @{
 480   */
 481 #define SPI_TIMODE_DISABLED             SPI_TIMODE_DISABLE
 482 #define SPI_TIMODE_ENABLED              SPI_TIMODE_ENABLE
 483
 484 #define SPI_CRCCALCULATION_DISABLED     SPI_CRCCALCULATION_DISABLE
 485 #define SPI_CRCCALCULATION_ENABLED      SPI_CRCCALCULATION_ENABLE
 486
 487 #define SPI_NSS_PULSE_DISABLED          SPI_NSS_PULSE_DISABLE
 488 #define SPI_NSS_PULSE_ENABLED           SPI_NSS_PULSE_ENABLE
 489
 490 /**
 491   * @}
 492   */
 493
 494 /** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
 495   * @{
 496   */
 497 #define CCER_CCxE_MASK                   TIM_CCER_CCxE_MASK
 498 #define CCER_CCxNE_MASK                  TIM_CCER_CCxNE_MASK
 499
 500 #define TIM_DMABase_CR1                  TIM_DMABASE_CR1
 501 #define TIM_DMABase_CR2                  TIM_DMABASE_CR2
 502 #define TIM_DMABase_SMCR                 TIM_DMABASE_SMCR
 503 #define TIM_DMABase_DIER                 TIM_DMABASE_DIER
 504 #define TIM_DMABase_SR                   TIM_DMABASE_SR
 505 #define TIM_DMABase_EGR                  TIM_DMABASE_EGR
 506 #define TIM_DMABase_CCMR1                TIM_DMABASE_CCMR1
 507 #define TIM_DMABase_CCMR2                TIM_DMABASE_CCMR2
 508 #define TIM_DMABase_CCER                 TIM_DMABASE_CCER
 509 #define TIM_DMABase_CNT                  TIM_DMABASE_CNT
 510 #define TIM_DMABase_PSC                  TIM_DMABASE_PSC
 511 #define TIM_DMABase_ARR                  TIM_DMABASE_ARR
 512 #define TIM_DMABase_RCR                  TIM_DMABASE_RCR
 513 #define TIM_DMABase_CCR1                 TIM_DMABASE_CCR1
 514 #define TIM_DMABase_CCR2                 TIM_DMABASE_CCR2
 515 #define TIM_DMABase_CCR3                 TIM_DMABASE_CCR3
 516 #define TIM_DMABase_CCR4                 TIM_DMABASE_CCR4
 517 #define TIM_DMABase_BDTR                 TIM_DMABASE_BDTR
 518 #define TIM_DMABase_DCR                  TIM_DMABASE_DCR
 519 #define TIM_DMABase_DMAR                 TIM_DMABASE_DMAR
 520 #define TIM_DMABase_OR1                  TIM_DMABASE_OR1
 521 #define TIM_DMABase_CCMR3                TIM_DMABASE_CCMR3
 522 #define TIM_DMABase_CCR5                 TIM_DMABASE_CCR5
 523 #define TIM_DMABase_CCR6                 TIM_DMABASE_CCR6
 524 #define TIM_DMABase_OR2                  TIM_DMABASE_OR2
 525 #define TIM_DMABase_OR3                  TIM_DMABASE_OR3
 526
 527 #define TIM_EventSource_Update           TIM_EVENTSOURCE_UPDATE
 528 #define TIM_EventSource_CC1              TIM_EVENTSOURCE_CC1
 529 #define TIM_EventSource_CC2              TIM_EVENTSOURCE_CC2
 530 #define TIM_EventSource_CC3              TIM_EVENTSOURCE_CC3
 531 #define TIM_EventSource_CC4              TIM_EVENTSOURCE_CC4
 532 #define TIM_EventSource_COM              TIM_EVENTSOURCE_COM
 533 #define TIM_EventSource_Trigger          TIM_EVENTSOURCE_TRIGGER
 534 #define TIM_EventSource_Break            TIM_EVENTSOURCE_BREAK
 535 #define TIM_EventSource_Break2           TIM_EVENTSOURCE_BREAK2
 536
 537 #define TIM_DMABurstLength_1Transfer     TIM_DMABURSTLENGTH_1TRANSFER
 538 #define TIM_DMABurstLength_2Transfers    TIM_DMABURSTLENGTH_2TRANSFERS
 539 #define TIM_DMABurstLength_3Transfers    TIM_DMABURSTLENGTH_3TRANSFERS
 540 #define TIM_DMABurstLength_4Transfers    TIM_DMABURSTLENGTH_4TRANSFERS
 541 #define TIM_DMABurstLength_5Transfers    TIM_DMABURSTLENGTH_5TRANSFERS
 542 #define TIM_DMABurstLength_6Transfers    TIM_DMABURSTLENGTH_6TRANSFERS
 543 #define TIM_DMABurstLength_7Transfers    TIM_DMABURSTLENGTH_7TRANSFERS
 544 #define TIM_DMABurstLength_8Transfers    TIM_DMABURSTLENGTH_8TRANSFERS
 545 #define TIM_DMABurstLength_9Transfers    TIM_DMABURSTLENGTH_9TRANSFERS
 546 #define TIM_DMABurstLength_10Transfers   TIM_DMABURSTLENGTH_10TRANSFERS
 547 #define TIM_DMABurstLength_11Transfers   TIM_DMABURSTLENGTH_11TRANSFERS
 548 #define TIM_DMABurstLength_12Transfers   TIM_DMABURSTLENGTH_12TRANSFERS
 549 #define TIM_DMABurstLength_13Transfers   TIM_DMABURSTLENGTH_13TRANSFERS
 550 #define TIM_DMABurstLength_14Transfers   TIM_DMABURSTLENGTH_14TRANSFERS
 551 #define TIM_DMABurstLength_15Transfers   TIM_DMABURSTLENGTH_15TRANSFERS
 552 #define TIM_DMABurstLength_16Transfers   TIM_DMABURSTLENGTH_16TRANSFERS
 553 #define TIM_DMABurstLength_17Transfers   TIM_DMABURSTLENGTH_17TRANSFERS
 554 #define TIM_DMABurstLength_18Transfers   TIM_DMABURSTLENGTH_18TRANSFERS
 555
 556 /**
 557   * @}
 558   */
 559
 560 /** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
 561   * @{
 562   */
 563 #define UART_ONEBIT_SAMPLING_DISABLED   UART_ONE_BIT_SAMPLE_DISABLE
 564 #define UART_ONEBIT_SAMPLING_ENABLED    UART_ONE_BIT_SAMPLE_ENABLE
 565 #define UART_ONE_BIT_SAMPLE_DISABLED    UART_ONE_BIT_SAMPLE_DISABLE
 566 #define UART_ONE_BIT_SAMPLE_ENABLED     UART_ONE_BIT_SAMPLE_ENABLE
 567
 568 #define __HAL_UART_ONEBIT_ENABLE        __HAL_UART_ONE_BIT_SAMPLE_ENABLE
 569 #define __HAL_UART_ONEBIT_DISABLE       __HAL_UART_ONE_BIT_SAMPLE_DISABLE
 570
 571 #define __DIV_SAMPLING16                UART_DIV_SAMPLING16
 572 #define __DIVMANT_SAMPLING16            UART_DIVMANT_SAMPLING16
 573 #define __DIVFRAQ_SAMPLING16            UART_DIVFRAQ_SAMPLING16
 574 #define __UART_BRR_SAMPLING16           UART_BRR_SAMPLING16
 575
 576 #define __DIV_SAMPLING8                 UART_DIV_SAMPLING8
 577 #define __DIVMANT_SAMPLING8             UART_DIVMANT_SAMPLING8
 578 #define __DIVFRAQ_SAMPLING8             UART_DIVFRAQ_SAMPLING8
 579 #define __UART_BRR_SAMPLING8            UART_BRR_SAMPLING8
 580
 581 #define UART_WAKEUPMETHODE_IDLELINE     UART_WAKEUPMETHOD_IDLELINE
 582 #define UART_WAKEUPMETHODE_ADDRESSMARK  UART_WAKEUPMETHOD_ADDRESSMARK
 583
 584 /**
 585   * @}
 586   */
 587
 588
 589 /** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
 590   * @{
 591   */
 592
 593 #define USART_CLOCK_DISABLED            USART_CLOCK_DISABLE
 594 #define USART_CLOCK_ENABLED             USART_CLOCK_ENABLE
 595
 596 #define USARTNACK_ENABLED               USART_NACK_ENABLE
 597 #define USARTNACK_DISABLED              USART_NACK_DISABLE
 598 /**
 599   * @}
 600   */
 601
 602 /** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
 603   * @{
 604   */
 605 #define CFR_BASE                    WWDG_CFR_BASE
 606
 607 /**
 608   * @}
 609   */
 610
 611 /** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
 612   * @{
 613   */
 614 #define CAN_FilterFIFO0             CAN_FILTER_FIFO0
 615 #define CAN_FilterFIFO1             CAN_FILTER_FIFO1
 616 #define CAN_IT_RQCP0                CAN_IT_TME
 617 #define CAN_IT_RQCP1                CAN_IT_TME
 618 #define CAN_IT_RQCP2                CAN_IT_TME
 619 #define INAK_TIMEOUT                CAN_TIMEOUT_VALUE
 620 #define SLAK_TIMEOUT                CAN_TIMEOUT_VALUE
 621 #define CAN_TXSTATUS_FAILED         ((uint8_t)0x00)
 622 #define CAN_TXSTATUS_OK             ((uint8_t)0x01)
 623 #define CAN_TXSTATUS_PENDING        ((uint8_t)0x02)
 624
 625 /**
 626   * @}
 627   */
 628
 629 /** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
 630   * @{
 631   */
 632
 633 #define VLAN_TAG                ETH_VLAN_TAG
 634 #define MIN_ETH_PAYLOAD         ETH_MIN_ETH_PAYLOAD
 635 #define MAX_ETH_PAYLOAD         ETH_MAX_ETH_PAYLOAD
 636 #define JUMBO_FRAME_PAYLOAD     ETH_JUMBO_FRAME_PAYLOAD
 637 #define MACMIIAR_CR_MASK        ETH_MACMIIAR_CR_MASK
 638 #define MACCR_CLEAR_MASK        ETH_MACCR_CLEAR_MASK
 639 #define MACFCR_CLEAR_MASK       ETH_MACFCR_CLEAR_MASK
 640 #define DMAOMR_CLEAR_MASK       ETH_DMAOMR_CLEAR_MASK
 641
 642 #define ETH_MMCCR              ((uint32_t)0x00000100)
 643 #define ETH_MMCRIR             ((uint32_t)0x00000104)
 644 #define ETH_MMCTIR             ((uint32_t)0x00000108)
 645 #define ETH_MMCRIMR            ((uint32_t)0x0000010C)
 646 #define ETH_MMCTIMR            ((uint32_t)0x00000110)
 647 #define ETH_MMCTGFSCCR         ((uint32_t)0x0000014C)
 648 #define ETH_MMCTGFMSCCR        ((uint32_t)0x00000150)
 649 #define ETH_MMCTGFCR           ((uint32_t)0x00000168)
 650 #define ETH_MMCRFCECR          ((uint32_t)0x00000194)
 651 #define ETH_MMCRFAECR          ((uint32_t)0x00000198)
 652 #define ETH_MMCRGUFCR          ((uint32_t)0x000001C4)
 653
 654 /**
 655   * @}
 656   */
 657
 658 /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
 659   * @{
 660   */
 661
 662 /**
 663   * @}
 664   */
 665
 666 /* Exported functions --------------------------------------------------------*/
 667
 668 /** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
 669   * @{
 670   */
 671 #define HAL_CRYP_ComputationCpltCallback     HAL_CRYPEx_ComputationCpltCallback
 672 /**
 673   * @}
 674   */
 675
 676 /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
 677   * @{
 678   */
 679
 680 #define HAL_HMAC_MD5_Finish          HAL_HASH_MD5_Finish
 681 #define HAL_HMAC_SHA1_Finish         HAL_HASH_SHA1_Finish
 682 #define HAL_HMAC_SHA224_Finish       HAL_HASH_SHA224_Finish
 683 #define HAL_HMAC_SHA256_Finish       HAL_HASH_SHA256_Finish
 684
 685 /*HASH Algorithm Selection*/
 686
 687 #define HASH_AlgoSelection_SHA1      HASH_ALGOSELECTION_SHA1
 688 #define HASH_AlgoSelection_SHA224    HASH_ALGOSELECTION_SHA224
 689 #define HASH_AlgoSelection_SHA256    HASH_ALGOSELECTION_SHA256
 690 #define HASH_AlgoSelection_MD5       HASH_ALGOSELECTION_MD5
 691
 692 #define HASH_AlgoMode_HASH         HASH_ALGOMODE_HASH
 693 #define HASH_AlgoMode_HMAC         HASH_ALGOMODE_HMAC
 694
 695 #define HASH_HMACKeyType_ShortKey  HASH_HMAC_KEYTYPE_SHORTKEY
 696 #define HASH_HMACKeyType_LongKey   HASH_HMAC_KEYTYPE_LONGKEY
 697 /**
 698   * @}
 699   */
 700
 701 /** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
 702   * @{
 703   */
 704 #define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
 705 #define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
 706 #define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
 707 #define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
 708 #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
 709 #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
 710 #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
 711 #define HAL_VREFINT_OutputSelect  HAL_SYSCFG_VREFINT_OutputSelect
 712 #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
 713 #define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
 714 #define HAL_ADC_EnableBuffer_Cmd(cmd)  (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
 715 #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ?  HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
 716 /**
 717   * @}
 718   */
 719
 720 /** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
 721   * @{
 722   */
 723 #define FLASH_HalfPageProgram      HAL_FLASHEx_HalfPageProgram
 724 #define FLASH_EnableRunPowerDown   HAL_FLASHEx_EnableRunPowerDown
 725 #define FLASH_DisableRunPowerDown  HAL_FLASHEx_DisableRunPowerDown
 726 #define HAL_DATA_EEPROMEx_Unlock   HAL_FLASHEx_DATAEEPROM_Unlock
 727 #define HAL_DATA_EEPROMEx_Lock     HAL_FLASHEx_DATAEEPROM_Lock
 728 #define HAL_DATA_EEPROMEx_Erase    HAL_FLASHEx_DATAEEPROM_Erase
 729 #define HAL_DATA_EEPROMEx_Program  HAL_FLASHEx_DATAEEPROM_Program
 730
 731  /**
 732   * @}
 733   */
 734
 735 /** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
 736   * @{
 737   */
 738 #define HAL_I2CEx_AnalogFilter_Config      HAL_I2CEx_ConfigAnalogFilter
 739 #define HAL_I2CEx_DigitalFilter_Config     HAL_I2CEx_ConfigDigitalFilter
 740
 741 #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
 742  /**
 743   * @}
 744   */
 745
 746 /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
 747   * @{
 748   */
 749 #define HAL_PWR_PVDConfig                             HAL_PWR_ConfigPVD
 750 #define HAL_PWR_DisableBkUpReg                        HAL_PWREx_DisableBkUpReg
 751 #define HAL_PWR_DisableFlashPowerDown                 HAL_PWREx_DisableFlashPowerDown
 752 #define HAL_PWR_DisableVddio2Monitor                  HAL_PWREx_DisableVddio2Monitor
 753 #define HAL_PWR_EnableBkUpReg                         HAL_PWREx_EnableBkUpReg
 754 #define HAL_PWR_EnableFlashPowerDown                  HAL_PWREx_EnableFlashPowerDown
 755 #define HAL_PWR_EnableVddio2Monitor                   HAL_PWREx_EnableVddio2Monitor
 756 #define HAL_PWR_PVD_PVM_IRQHandler                    HAL_PWREx_PVD_PVM_IRQHandler
 757 #define HAL_PWR_PVDLevelConfig                        HAL_PWR_ConfigPVD
 758 #define HAL_PWR_Vddio2Monitor_IRQHandler              HAL_PWREx_Vddio2Monitor_IRQHandler
 759 #define HAL_PWR_Vddio2MonitorCallback                 HAL_PWREx_Vddio2MonitorCallback
 760 #define HAL_PWREx_ActivateOverDrive                   HAL_PWREx_EnableOverDrive
 761 #define HAL_PWREx_DeactivateOverDrive                 HAL_PWREx_DisableOverDrive
 762 #define HAL_PWREx_DisableSDADCAnalog                  HAL_PWREx_DisableSDADC
 763 #define HAL_PWREx_EnableSDADCAnalog                   HAL_PWREx_EnableSDADC
 764 #define HAL_PWREx_PVMConfig                           HAL_PWREx_ConfigPVM
 765
 766 #define PWR_MODE_NORMAL                               PWR_PVD_MODE_NORMAL
 767 #define PWR_MODE_IT_RISING                            PWR_PVD_MODE_IT_RISING
 768 #define PWR_MODE_IT_FALLING                           PWR_PVD_MODE_IT_FALLING
 769 #define PWR_MODE_IT_RISING_FALLING                    PWR_PVD_MODE_IT_RISING_FALLING
 770 #define PWR_MODE_EVENT_RISING                         PWR_PVD_MODE_EVENT_RISING
 771 #define PWR_MODE_EVENT_FALLING                        PWR_PVD_MODE_EVENT_FALLING
 772 #define PWR_MODE_EVENT_RISING_FALLING                 PWR_PVD_MODE_EVENT_RISING_FALLING
 773
 774 #define CR_OFFSET_BB                                  PWR_CR_OFFSET_BB
 775 #define CSR_OFFSET_BB                                 PWR_CSR_OFFSET_BB
 776
 777 #define DBP_BitNumber                                 DBP_BIT_NUMBER
 778 #define PVDE_BitNumber                                PVDE_BIT_NUMBER
 779 #define PMODE_BitNumber                               PMODE_BIT_NUMBER
 780 #define EWUP_BitNumber                                EWUP_BIT_NUMBER
 781 #define FPDS_BitNumber                                FPDS_BIT_NUMBER
 782 #define ODEN_BitNumber                                ODEN_BIT_NUMBER
 783 #define ODSWEN_BitNumber                              ODSWEN_BIT_NUMBER
 784 #define MRLVDS_BitNumber                              MRLVDS_BIT_NUMBER
 785 #define LPLVDS_BitNumber                              LPLVDS_BIT_NUMBER
 786 #define BRE_BitNumber                                 BRE_BIT_NUMBER
 787
 788 #define PWR_MODE_EVT                                  PWR_PVD_MODE_NORMAL
 789
 790  /**
 791   * @}
 792   */
 793
 794 /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
 795   * @{
 796   */
 797 #define HAL_SMBUS_Slave_Listen_IT          HAL_SMBUS_EnableListen_IT
 798 #define HAL_SMBUS_SlaveAddrCallback        HAL_SMBUS_AddrCallback
 799 #define HAL_SMBUS_SlaveListenCpltCallback  HAL_SMBUS_ListenCpltCallback
 800 /**
 801   * @}
 802   */
 803
 804 /** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
 805   * @{
 806   */
 807 #define HAL_SPI_FlushRxFifo                HAL_SPIEx_FlushRxFifo
 808 /**
 809   * @}
 810   */
 811
 812 /** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
 813   * @{
 814   */
 815 #define HAL_TIM_DMADelayPulseCplt                       TIM_DMADelayPulseCplt
 816 #define HAL_TIM_DMAError                                TIM_DMAError
 817 #define HAL_TIM_DMACaptureCplt                          TIM_DMACaptureCplt
 818 #define HAL_TIMEx_DMACommutationCplt                    TIMEx_DMACommutationCplt
 819 /**
 820   * @}
 821   */
 822
 823 /** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
 824   * @{
 825   */
 826 #define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
 827 /**
 828   * @}
 829   */
 830
 831
 832    /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
 833   * @{
 834   */
 835
 836 /**
 837   * @}
 838   */
 839
 840 /* Exported macros ------------------------------------------------------------*/
 841
 842 /** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
 843   * @{
 844   */
 845 #define AES_IT_CC                      CRYP_IT_CC
 846 #define AES_IT_ERR                     CRYP_IT_ERR
 847 #define AES_FLAG_CCF                   CRYP_FLAG_CCF
 848 /**
 849   * @}
 850   */
 851
 852 /** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
 853   * @{
 854   */
 855 #define __HAL_GET_BOOT_MODE                   __HAL_SYSCFG_GET_BOOT_MODE
 856 #define __HAL_REMAPMEMORY_FLASH               __HAL_SYSCFG_REMAPMEMORY_FLASH
 857 #define __HAL_REMAPMEMORY_SYSTEMFLASH         __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
 858 #define __HAL_REMAPMEMORY_SRAM                __HAL_SYSCFG_REMAPMEMORY_SRAM
 859 #define __HAL_REMAPMEMORY_FMC                 __HAL_SYSCFG_REMAPMEMORY_FMC
 860 #define __HAL_REMAPMEMORY_FMC_SDRAM           __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
 861 #define __HAL_REMAPMEMORY_FSMC                __HAL_SYSCFG_REMAPMEMORY_FSMC
 862 #define __HAL_REMAPMEMORY_QUADSPI             __HAL_SYSCFG_REMAPMEMORY_QUADSPI
 863 #define __HAL_FMC_BANK                        __HAL_SYSCFG_FMC_BANK
 864 #define __HAL_GET_FLAG                        __HAL_SYSCFG_GET_FLAG
 865 #define __HAL_CLEAR_FLAG                      __HAL_SYSCFG_CLEAR_FLAG
 866 #define __HAL_VREFINT_OUT_ENABLE              __HAL_SYSCFG_VREFINT_OUT_ENABLE
 867 #define __HAL_VREFINT_OUT_DISABLE             __HAL_SYSCFG_VREFINT_OUT_DISABLE
 868
 869 #define SYSCFG_FLAG_VREF_READY                SYSCFG_FLAG_VREFINT_READY
 870 #define SYSCFG_FLAG_RC48                      RCC_FLAG_HSI48
 871 #define IS_SYSCFG_FASTMODEPLUS_CONFIG         IS_I2C_FASTMODEPLUS
 872 #define UFB_MODE_BitNumber                    UFB_MODE_BIT_NUMBER
 873 #define CMP_PD_BitNumber                      CMP_PD_BIT_NUMBER
 874
 875 /**
 876   * @}
 877   */
 878
 879
 880 /** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
 881   * @{
 882   */
 883 #define __ADC_ENABLE                                     __HAL_ADC_ENABLE
 884 #define __ADC_DISABLE                                    __HAL_ADC_DISABLE
 885 #define __HAL_ADC_ENABLING_CONDITIONS                    ADC_ENABLING_CONDITIONS
 886 #define __HAL_ADC_DISABLING_CONDITIONS                   ADC_DISABLING_CONDITIONS
 887 #define __HAL_ADC_IS_ENABLED                             ADC_IS_ENABLE
 888 #define __ADC_IS_ENABLED                                 ADC_IS_ENABLE
 889 #define __HAL_ADC_IS_SOFTWARE_START_REGULAR              ADC_IS_SOFTWARE_START_REGULAR
 890 #define __HAL_ADC_IS_SOFTWARE_START_INJECTED             ADC_IS_SOFTWARE_START_INJECTED
 891 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
 892 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR          ADC_IS_CONVERSION_ONGOING_REGULAR
 893 #define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED         ADC_IS_CONVERSION_ONGOING_INJECTED
 894 #define __HAL_ADC_IS_CONVERSION_ONGOING                  ADC_IS_CONVERSION_ONGOING
 895 #define __HAL_ADC_CLEAR_ERRORCODE                        ADC_CLEAR_ERRORCODE
 896
 897 #define __HAL_ADC_GET_RESOLUTION                         ADC_GET_RESOLUTION
 898 #define __HAL_ADC_JSQR_RK                                ADC_JSQR_RK
 899 #define __HAL_ADC_CFGR_AWD1CH                            ADC_CFGR_AWD1CH_SHIFT
 900 #define __HAL_ADC_CFGR_AWD23CR                           ADC_CFGR_AWD23CR
 901 #define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION            ADC_CFGR_INJECT_AUTO_CONVERSION
 902 #define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE              ADC_CFGR_INJECT_CONTEXT_QUEUE
 903 #define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS             ADC_CFGR_INJECT_DISCCONTINUOUS
 904 #define __HAL_ADC_CFGR_REG_DISCCONTINUOUS                ADC_CFGR_REG_DISCCONTINUOUS
 905 #define __HAL_ADC_CFGR_DISCONTINUOUS_NUM                 ADC_CFGR_DISCONTINUOUS_NUM
 906 #define __HAL_ADC_CFGR_AUTOWAIT                          ADC_CFGR_AUTOWAIT
 907 #define __HAL_ADC_CFGR_CONTINUOUS                        ADC_CFGR_CONTINUOUS
 908 #define __HAL_ADC_CFGR_OVERRUN                           ADC_CFGR_OVERRUN
 909 #define __HAL_ADC_CFGR_DMACONTREQ                        ADC_CFGR_DMACONTREQ
 910 #define __HAL_ADC_CFGR_EXTSEL                            ADC_CFGR_EXTSEL_SET
 911 #define __HAL_ADC_JSQR_JEXTSEL                           ADC_JSQR_JEXTSEL_SET
 912 #define __HAL_ADC_OFR_CHANNEL                            ADC_OFR_CHANNEL
 913 #define __HAL_ADC_DIFSEL_CHANNEL                         ADC_DIFSEL_CHANNEL
 914 #define __HAL_ADC_CALFACT_DIFF_SET                       ADC_CALFACT_DIFF_SET
 915 #define __HAL_ADC_CALFACT_DIFF_GET                       ADC_CALFACT_DIFF_GET
 916 #define __HAL_ADC_TRX_HIGHTHRESHOLD                      ADC_TRX_HIGHTHRESHOLD
 917
 918 #define __HAL_ADC_OFFSET_SHIFT_RESOLUTION                ADC_OFFSET_SHIFT_RESOLUTION
 919 #define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION         ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
 920 #define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION        ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
 921 #define __HAL_ADC_COMMON_REGISTER                        ADC_COMMON_REGISTER
 922 #define __HAL_ADC_COMMON_CCR_MULTI                       ADC_COMMON_CCR_MULTI
 923 #define __HAL_ADC_MULTIMODE_IS_ENABLED                   ADC_MULTIMODE_IS_ENABLE
 924 #define __ADC_MULTIMODE_IS_ENABLED                       ADC_MULTIMODE_IS_ENABLE
 925 #define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER        ADC_NONMULTIMODE_OR_MULTIMODEMASTER
 926 #define __HAL_ADC_COMMON_ADC_OTHER                       ADC_COMMON_ADC_OTHER
 927 #define __HAL_ADC_MULTI_SLAVE                            ADC_MULTI_SLAVE
 928
 929 #define __HAL_ADC_SQR1_L                                 ADC_SQR1_L_SHIFT
 930 #define __HAL_ADC_JSQR_JL                                ADC_JSQR_JL_SHIFT
 931 #define __HAL_ADC_JSQR_RK_JL                             ADC_JSQR_RK_JL
 932 #define __HAL_ADC_CR1_DISCONTINUOUS_NUM                  ADC_CR1_DISCONTINUOUS_NUM
 933 #define __HAL_ADC_CR1_SCAN                               ADC_CR1_SCAN_SET
 934 #define __HAL_ADC_CONVCYCLES_MAX_RANGE                   ADC_CONVCYCLES_MAX_RANGE
 935 #define __HAL_ADC_CLOCK_PRESCALER_RANGE                  ADC_CLOCK_PRESCALER_RANGE
 936 #define __HAL_ADC_GET_CLOCK_PRESCALER                    ADC_GET_CLOCK_PRESCALER
 937
 938 #define __HAL_ADC_SQR1                                   ADC_SQR1
 939 #define __HAL_ADC_SMPR1                                  ADC_SMPR1
 940 #define __HAL_ADC_SMPR2                                  ADC_SMPR2
 941 #define __HAL_ADC_SQR3_RK                                ADC_SQR3_RK
 942 #define __HAL_ADC_SQR2_RK                                ADC_SQR2_RK
 943 #define __HAL_ADC_SQR1_RK                                ADC_SQR1_RK
 944 #define __HAL_ADC_CR2_CONTINUOUS                         ADC_CR2_CONTINUOUS
 945 #define __HAL_ADC_CR1_DISCONTINUOUS                      ADC_CR1_DISCONTINUOUS
 946 #define __HAL_ADC_CR1_SCANCONV                           ADC_CR1_SCANCONV
 947 #define __HAL_ADC_CR2_EOCSelection                       ADC_CR2_EOCSelection
 948 #define __HAL_ADC_CR2_DMAContReq                         ADC_CR2_DMAContReq
 949 #define __HAL_ADC_GET_RESOLUTION                         ADC_GET_RESOLUTION
 950 #define __HAL_ADC_JSQR                                   ADC_JSQR
 951
 952 #define __HAL_ADC_CHSELR_CHANNEL                         ADC_CHSELR_CHANNEL
 953 #define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS               ADC_CFGR1_REG_DISCCONTINUOUS
 954 #define __HAL_ADC_CFGR1_AUTOOFF                          ADC_CFGR1_AUTOOFF
 955 #define __HAL_ADC_CFGR1_AUTOWAIT                         ADC_CFGR1_AUTOWAIT
 956 #define __HAL_ADC_CFGR1_CONTINUOUS                       ADC_CFGR1_CONTINUOUS
 957 #define __HAL_ADC_CFGR1_OVERRUN                          ADC_CFGR1_OVERRUN
 958 #define __HAL_ADC_CFGR1_SCANDIR                          ADC_CFGR1_SCANDIR
 959 #define __HAL_ADC_CFGR1_DMACONTREQ                       ADC_CFGR1_DMACONTREQ
 960
 961 /**
 962   * @}
 963   */
 964
 965 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
 966   * @{
 967   */
 968 #define __HAL_DHR12R1_ALIGNEMENT                        DAC_DHR12R1_ALIGNMENT
 969 #define __HAL_DHR12R2_ALIGNEMENT                        DAC_DHR12R2_ALIGNMENT
 970 #define __HAL_DHR12RD_ALIGNEMENT                        DAC_DHR12RD_ALIGNMENT
 971 #define IS_DAC_GENERATE_WAVE                            IS_DAC_WAVE
 972
 973 /**
 974   * @}
 975   */
 976
 977 /** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
 978   * @{
 979   */
 980 #define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
 981 #define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
 982 #define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
 983 #define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
 984 #define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
 985 #define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
 986 #define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
 987 #define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
 988 #define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
 989 #define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
 990 #define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
 991 #define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
 992 #define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
 993 #define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
 994 #define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
 995 #define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
 996
 997 #define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
 998 #define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
 999 #define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
1000 #define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
1001 #define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
1002 #define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
1003 #define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
1004 #define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
1005 #define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
1006 #define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
1007 #define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
1008 #define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
1009 #define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
1010 #define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
1011
1012
1013 #define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
1014 #define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
1015 #define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
1016 #define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
1017 #define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
1018 #define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
1019 #define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
1020 #define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
1021 #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
1022 #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
1023 #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
1024 #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
1025 #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
1026 #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
1027 #define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
1028 #define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
1029 #define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
1030 #define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
1031 #define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
1032 #define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
1033 #define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
1034 #define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
1035 #define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
1036 #define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
1037
1038 /**
1039   * @}
1040   */
1041
1042 /** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
1043   * @{
1044   */
1045
1046 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
1047                                                           __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
1048 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
1049                                                           __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
1050 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
1051                                                           __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
1052 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
1053                                                           __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
1054 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
1055                                                           __HAL_COMP_COMP2_EXTI_ENABLE_IT())
1056 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
1057                                                           __HAL_COMP_COMP2_EXTI_DISABLE_IT())
1058 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)   (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
1059                                                           __HAL_COMP_COMP2_EXTI_GET_FLAG())
1060 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)   (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
1061                                                           __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
1062 #define __HAL_COMP_GET_EXTI_LINE  COMP_GET_EXTI_LINE
1063
1064 /**
1065   * @}
1066   */
1067
1068 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
1069   * @{
1070   */
1071
1072 #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
1073                           ((WAVE) == DAC_WAVE_NOISE)|| \
1074                           ((WAVE) == DAC_WAVE_TRIANGLE))
1075
1076 /**
1077   * @}
1078   */
1079
1080 /** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
1081   * @{
1082   */
1083
1084 #define IS_WRPAREA          IS_OB_WRPAREA
1085 #define IS_TYPEPROGRAM      IS_FLASH_TYPEPROGRAM
1086 #define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
1087 #define IS_TYPEERASE        IS_FLASH_TYPEERASE
1088
1089 /**
1090   * @}
1091   */
1092
1093 /** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
1094   * @{
1095   */
1096
1097 #define __HAL_I2C_RESET_CR2             I2C_RESET_CR2
1098 #define __HAL_I2C_GENERATE_START        I2C_GENERATE_START
1099 #define __HAL_I2C_FREQ_RANGE            I2C_FREQ_RANGE
1100 #define __HAL_I2C_RISE_TIME             I2C_RISE_TIME
1101 #define __HAL_I2C_SPEED_STANDARD        I2C_SPEED_STANDARD
1102 #define __HAL_I2C_SPEED_FAST            I2C_SPEED_FAST
1103 #define __HAL_I2C_SPEED                 I2C_SPEED
1104 #define __HAL_I2C_7BIT_ADD_WRITE        I2C_7BIT_ADD_WRITE
1105 #define __HAL_I2C_7BIT_ADD_READ         I2C_7BIT_ADD_READ
1106 #define __HAL_I2C_10BIT_ADDRESS         I2C_10BIT_ADDRESS
1107 #define __HAL_I2C_10BIT_HEADER_WRITE    I2C_10BIT_HEADER_WRITE
1108 #define __HAL_I2C_10BIT_HEADER_READ     I2C_10BIT_HEADER_READ
1109 #define __HAL_I2C_MEM_ADD_MSB           I2C_MEM_ADD_MSB
1110 #define __HAL_I2C_MEM_ADD_LSB           I2C_MEM_ADD_LSB
1111 #define __HAL_I2C_FREQRANGE             I2C_FREQRANGE
1112 /**
1113   * @}
1114   */
1115
1116 /** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
1117   * @{
1118   */
1119
1120 #define IS_I2S_INSTANCE                 IS_I2S_ALL_INSTANCE
1121 #define IS_I2S_INSTANCE_EXT             IS_I2S_ALL_INSTANCE_EXT
1122
1123 /**
1124   * @}
1125   */
1126
1127 /** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
1128   * @{
1129   */
1130
1131 #define __IRDA_DISABLE                  __HAL_IRDA_DISABLE
1132 #define __IRDA_ENABLE                   __HAL_IRDA_ENABLE
1133
1134 #define __HAL_IRDA_GETCLOCKSOURCE       IRDA_GETCLOCKSOURCE
1135 #define __HAL_IRDA_MASK_COMPUTATION     IRDA_MASK_COMPUTATION
1136 #define __IRDA_GETCLOCKSOURCE           IRDA_GETCLOCKSOURCE
1137 #define __IRDA_MASK_COMPUTATION         IRDA_MASK_COMPUTATION
1138
1139 #define IS_IRDA_ONEBIT_SAMPLE           IS_IRDA_ONE_BIT_SAMPLE
1140
1141
1142 /**
1143   * @}
1144   */
1145
1146
1147 /** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
1148   * @{
1149   */
1150 #define __HAL_IWDG_ENABLE_WRITE_ACCESS  IWDG_ENABLE_WRITE_ACCESS
1151 #define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
1152 /**
1153   * @}
1154   */
1155
1156
1157 /** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
1158   * @{
1159   */
1160
1161 #define __HAL_LPTIM_ENABLE_INTERRUPT    __HAL_LPTIM_ENABLE_IT
1162 #define __HAL_LPTIM_DISABLE_INTERRUPT   __HAL_LPTIM_DISABLE_IT
1163 #define __HAL_LPTIM_GET_ITSTATUS        __HAL_LPTIM_GET_IT_SOURCE
1164
1165 /**
1166   * @}
1167   */
1168
1169
1170 /** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
1171   * @{
1172   */
1173 #define __OPAMP_CSR_OPAXPD                OPAMP_CSR_OPAXPD
1174 #define __OPAMP_CSR_S3SELX                OPAMP_CSR_S3SELX
1175 #define __OPAMP_CSR_S4SELX                OPAMP_CSR_S4SELX
1176 #define __OPAMP_CSR_S5SELX                OPAMP_CSR_S5SELX
1177 #define __OPAMP_CSR_S6SELX                OPAMP_CSR_S6SELX
1178 #define __OPAMP_CSR_OPAXCAL_L             OPAMP_CSR_OPAXCAL_L
1179 #define __OPAMP_CSR_OPAXCAL_H             OPAMP_CSR_OPAXCAL_H
1180 #define __OPAMP_CSR_OPAXLPM               OPAMP_CSR_OPAXLPM
1181 #define __OPAMP_CSR_ALL_SWITCHES          OPAMP_CSR_ALL_SWITCHES
1182 #define __OPAMP_CSR_ANAWSELX              OPAMP_CSR_ANAWSELX
1183 #define __OPAMP_CSR_OPAXCALOUT            OPAMP_CSR_OPAXCALOUT
1184 #define __OPAMP_OFFSET_TRIM_BITSPOSITION  OPAMP_OFFSET_TRIM_BITSPOSITION
1185 #define __OPAMP_OFFSET_TRIM_SET           OPAMP_OFFSET_TRIM_SET
1186
1187 /**
1188   * @}
1189   */
1190
1191
1192 /** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
1193   * @{
1194   */
1195 #define __HAL_PVD_EVENT_DISABLE                                  __HAL_PWR_PVD_EXTI_DISABLE_EVENT
1196 #define __HAL_PVD_EVENT_ENABLE                                   __HAL_PWR_PVD_EXTI_ENABLE_EVENT
1197 #define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
1198 #define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
1199 #define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
1200 #define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
1201 #define __HAL_PVM_EVENT_DISABLE                                  __HAL_PWR_PVM_EVENT_DISABLE
1202 #define __HAL_PVM_EVENT_ENABLE                                   __HAL_PWR_PVM_EVENT_ENABLE
1203 #define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
1204 #define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
1205 #define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
1206 #define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
1207 #define __HAL_PWR_INTERNALWAKEUP_DISABLE                         HAL_PWREx_DisableInternalWakeUpLine
1208 #define __HAL_PWR_INTERNALWAKEUP_ENABLE                          HAL_PWREx_EnableInternalWakeUpLine
1209 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE                    HAL_PWREx_DisablePullUpPullDownConfig
1210 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE                     HAL_PWREx_EnablePullUpPullDownConfig
1211 #define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER()                  __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()
1212 #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE                         __HAL_PWR_PVD_EXTI_DISABLE_EVENT
1213 #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE                          __HAL_PWR_PVD_EXTI_ENABLE_EVENT
1214 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE                __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
1215 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE                 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
1216 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE                 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
1217 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE                  __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
1218 #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER              __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
1219 #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER               __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
1220 #define __HAL_PWR_PVM_DISABLE()                                  HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4()
1221 #define __HAL_PWR_PVM_ENABLE()                                   HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4()
1222 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE                  HAL_PWREx_DisableSRAM2ContentRetention
1223 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE                   HAL_PWREx_EnableSRAM2ContentRetention
1224 #define __HAL_PWR_VDDIO2_DISABLE                                 HAL_PWREx_DisableVddIO2
1225 #define __HAL_PWR_VDDIO2_ENABLE                                  HAL_PWREx_EnableVddIO2
1226 #define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER                 __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
1227 #define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER           __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
1228 #define __HAL_PWR_VDDUSB_DISABLE                                 HAL_PWREx_DisableVddUSB
1229 #define __HAL_PWR_VDDUSB_ENABLE                                  HAL_PWREx_EnableVddUSB
1230
1231 #if defined (STM32F4)
1232 #define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD)         __HAL_PWR_PVD_EXTI_ENABLE_IT()
1233 #define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_DISABLE_IT()
1234 #define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD)          __HAL_PWR_PVD_EXTI_GET_FLAG()
1235 #define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
1236 #define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD)     __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
1237 #else
1238 #define __HAL_PVD_EXTI_CLEAR_FLAG                                __HAL_PWR_PVD_EXTI_CLEAR_FLAG
1239 #define __HAL_PVD_EXTI_DISABLE_IT                                __HAL_PWR_PVD_EXTI_DISABLE_IT
1240 #define __HAL_PVD_EXTI_ENABLE_IT                                 __HAL_PWR_PVD_EXTI_ENABLE_IT
1241 #define __HAL_PVD_EXTI_GENERATE_SWIT                             __HAL_PWR_PVD_EXTI_GENERATE_SWIT
1242 #define __HAL_PVD_EXTI_GET_FLAG                                  __HAL_PWR_PVD_EXTI_GET_FLAG
1243 #endif /* STM32F4 */
1244 /**
1245   * @}
1246   */
1247
1248
1249 /** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
1250   * @{
1251   */
1252
1253 #define RCC_StopWakeUpClock_MSI     RCC_STOP_WAKEUPCLOCK_MSI
1254 #define RCC_StopWakeUpClock_HSI     RCC_STOP_WAKEUPCLOCK_HSI
1255
1256 #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
1257 #define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
1258
1259 #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
1260 #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
1261 #define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
1262 #define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
1263 #define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
1264 #define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
1265 #define __ADC1_CLK_DISABLE        __HAL_RCC_ADC1_CLK_DISABLE
1266 #define __ADC1_CLK_ENABLE         __HAL_RCC_ADC1_CLK_ENABLE
1267 #define __ADC1_FORCE_RESET        __HAL_RCC_ADC1_FORCE_RESET
1268 #define __ADC1_RELEASE_RESET      __HAL_RCC_ADC1_RELEASE_RESET
1269 #define __ADC1_CLK_SLEEP_ENABLE   __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
1270 #define __ADC1_CLK_SLEEP_DISABLE  __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
1271 #define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
1272 #define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
1273 #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
1274 #define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
1275 #define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
1276 #define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
1277 #define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
1278 #define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
1279 #define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
1280 #define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
1281 #define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
1282 #define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
1283 #define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
1284 #define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
1285 #define __CRYP_CLK_SLEEP_ENABLE      __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
1286 #define __CRYP_CLK_SLEEP_DISABLE  __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
1287 #define __CRYP_CLK_ENABLE  __HAL_RCC_CRYP_CLK_ENABLE
1288 #define __CRYP_CLK_DISABLE  __HAL_RCC_CRYP_CLK_DISABLE
1289 #define __CRYP_FORCE_RESET  __HAL_RCC_CRYP_FORCE_RESET
1290 #define __CRYP_RELEASE_RESET  __HAL_RCC_CRYP_RELEASE_RESET
1291 #define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
1292 #define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
1293 #define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
1294 #define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
1295 #define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
1296 #define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
1297 #define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
1298 #define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
1299 #define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
1300 #define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
1301 #define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
1302 #define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
1303 #define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
1304 #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
1305 #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
1306 #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
1307 #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
1308 #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
1309 #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
1310 #define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
1311 #define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
1312 #define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
1313 #define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
1314 #define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
1315 #define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
1316 #define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
1317 #define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
1318 #define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
1319 #define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
1320 #define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
1321 #define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
1322 #define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
1323 #define __COMP_CLK_DISABLE        __HAL_RCC_COMP_CLK_DISABLE
1324 #define __COMP_CLK_ENABLE         __HAL_RCC_COMP_CLK_ENABLE
1325 #define __COMP_FORCE_RESET        __HAL_RCC_COMP_FORCE_RESET
1326 #define __COMP_RELEASE_RESET      __HAL_RCC_COMP_RELEASE_RESET
1327 #define __COMP_CLK_SLEEP_ENABLE   __HAL_RCC_COMP_CLK_SLEEP_ENABLE
1328 #define __COMP_CLK_SLEEP_DISABLE  __HAL_RCC_COMP_CLK_SLEEP_DISABLE
1329 #define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
1330 #define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
1331 #define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
1332 #define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
1333 #define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
1334 #define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
1335 #define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
1336 #define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
1337 #define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
1338 #define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
1339 #define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
1340 #define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
1341 #define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
1342 #define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
1343 #define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
1344 #define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
1345 #define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
1346 #define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
1347 #define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
1348 #define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
1349 #define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
1350 #define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
1351 #define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
1352 #define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
1353 #define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
1354 #define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
1355 #define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
1356 #define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
1357 #define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
1358 #define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
1359 #define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
1360 #define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
1361 #define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
1362 #define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
1363 #define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
1364 #define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
1365 #define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
1366 #define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
1367 #define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
1368 #define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
1369 #define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
1370 #define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
1371 #define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
1372 #define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
1373 #define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
1374 #define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
1375 #define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
1376 #define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
1377 #define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
1378 #define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
1379 #define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
1380 #define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
1381 #define __FLITF_CLK_DISABLE       __HAL_RCC_FLITF_CLK_DISABLE
1382 #define __FLITF_CLK_ENABLE        __HAL_RCC_FLITF_CLK_ENABLE
1383 #define __FLITF_FORCE_RESET       __HAL_RCC_FLITF_FORCE_RESET
1384 #define __FLITF_RELEASE_RESET     __HAL_RCC_FLITF_RELEASE_RESET
1385 #define __FLITF_CLK_SLEEP_ENABLE  __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
1386 #define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
1387 #define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
1388 #define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
1389 #define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
1390 #define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
1391 #define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
1392 #define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
1393 #define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
1394 #define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
1395 #define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
1396 #define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
1397 #define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
1398 #define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
1399 #define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
1400 #define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
1401 #define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
1402 #define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
1403 #define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
1404 #define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
1405 #define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
1406 #define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
1407 #define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
1408 #define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
1409 #define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
1410 #define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
1411 #define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
1412 #define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
1413 #define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
1414 #define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
1415 #define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
1416 #define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
1417 #define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
1418 #define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
1419 #define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
1420 #define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
1421 #define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
1422 #define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
1423 #define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
1424 #define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
1425 #define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
1426 #define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
1427 #define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
1428 #define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
1429 #define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
1430 #define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
1431 #define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
1432 #define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
1433 #define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
1434 #define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
1435 #define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
1436 #define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
1437 #define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
1438 #define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
1439 #define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
1440 #define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
1441 #define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
1442 #define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
1443 #define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
1444 #define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
1445 #define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
1446 #define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
1447 #define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
1448 #define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
1449 #define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
1450 #define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
1451 #define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
1452 #define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
1453 #define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
1454 #define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
1455 #define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
1456 #define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
1457 #define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
1458 #define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
1459 #define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
1460 #define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
1461 #define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
1462 #define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
1463 #define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
1464 #define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
1465 #define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
1466 #define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
1467 #define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
1468 #define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
1469 #define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
1470 #define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
1471 #define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
1472 #define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
1473 #define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
1474 #define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
1475 #define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
1476 #define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
1477 #define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
1478 #define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
1479 #define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
1480 #define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
1481 #define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
1482 #define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
1483 #define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
1484 #define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
1485 #define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
1486 #define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
1487 #define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
1488 #define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
1489 #define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
1490 #define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
1491 #define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
1492 #define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
1493 #define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
1494 #define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
1495 #define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
1496 #define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
1497 #define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
1498 #define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
1499 #define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
1500 #define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
1501 #define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
1502 #define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
1503 #define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
1504 #define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
1505 #define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
1506 #define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
1507 #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
1508 #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
1509 #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
1510 #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
1511 #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
1512 #define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
1513 #define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
1514 #define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
1515 #define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
1516 #define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
1517 #define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
1518 #define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
1519 #define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
1520 #define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
1521 #define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
1522 #define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
1523 #define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
1524 #define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
1525 #define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
1526 #define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
1527 #define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
1528 #define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
1529 #define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
1530 #define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
1531 #define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
1532 #define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
1533 #define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
1534 #define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
1535 #define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
1536 #define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
1537 #define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
1538 #define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
1539 #define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
1540 #define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
1541 #define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
1542 #define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
1543 #define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
1544 #define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
1545 #define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
1546 #define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
1547 #define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
1548 #define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
1549 #define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
1550 #define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
1551 #define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
1552 #define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
1553 #define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
1554 #define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
1555 #define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
1556 #define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
1557 #define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
1558 #define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
1559 #define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
1560 #define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
1561 #define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
1562 #define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
1563 #define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
1564 #define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
1565 #define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
1566 #define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
1567 #define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
1568 #define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
1569 #define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
1570 #define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
1571 #define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
1572 #define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
1573 #define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
1574 #define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
1575 #define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
1576 #define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
1577 #define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
1578 #define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
1579 #define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
1580 #define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
1581 #define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
1582 #define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
1583 #define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
1584 #define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
1585 #define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
1586 #define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
1587 #define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
1588 #define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
1589 #define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
1590 #define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
1591 #define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
1592 #define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
1593 #define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
1594 #define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
1595 #define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
1596 #define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
1597 #define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
1598 #define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
1599 #define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
1600 #define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
1601 #define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
1602 #define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
1603 #define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
1604 #define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
1605 #define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
1606 #define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
1607 #define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
1608 #define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
1609 #define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
1610 #define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
1611 #define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
1612 #define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
1613 #define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
1614 #define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
1615 #define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
1616 #define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
1617 #define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
1618 #define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
1619 #define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
1620 #define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
1621 #define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
1622 #define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
1623 #define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
1624 #define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
1625 #define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
1626 #define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
1627 #define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
1628 #define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
1629 #define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
1630 #define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
1631 #define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
1632 #define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
1633 #define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
1634 #define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
1635 #define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
1636 #define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
1637 #define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
1638 #define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
1639 #define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
1640 #define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
1641 #define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
1642 #define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
1643 #define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
1644 #define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
1645 #define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
1646 #define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
1647 #define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
1648 #define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
1649 #define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
1650 #define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
1651 #define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
1652 #define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
1653 #define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
1654 #define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
1655 #define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
1656 #define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
1657 #define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
1658 #define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
1659 #define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
1660 #define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
1661 #define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
1662 #define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
1663 #define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
1664 #define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
1665 #define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
1666 #define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
1667 #define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
1668 #define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
1669 #define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
1670 #define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
1671 #define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
1672 #define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
1673 #define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
1674 #define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
1675 #define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
1676 #define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
1677 #define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
1678 #define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
1679 #define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
1680 #define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
1681 #define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
1682 #define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
1683 #define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
1684 #define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
1685 #define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
1686 #define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
1687 #define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
1688 #define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
1689 #define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
1690 #define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
1691 #define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
1692 #define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
1693 #define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
1694 #define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
1695 #define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
1696 #define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
1697 #define __USB_CLK_DISABLE         __HAL_RCC_USB_CLK_DISABLE
1698 #define __USB_CLK_ENABLE          __HAL_RCC_USB_CLK_ENABLE
1699 #define __USB_FORCE_RESET         __HAL_RCC_USB_FORCE_RESET
1700 #define __USB_CLK_SLEEP_ENABLE    __HAL_RCC_USB_CLK_SLEEP_ENABLE
1701 #define __USB_CLK_SLEEP_DISABLE   __HAL_RCC_USB_CLK_SLEEP_DISABLE
1702 #define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
1703 #define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
1704 #define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
1705 #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
1706 #define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
1707 #define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
1708 #define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
1709 #define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
1710 #define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
1711 #define __TIM21_CLK_ENABLE   __HAL_RCC_TIM21_CLK_ENABLE
1712 #define __TIM21_CLK_DISABLE   __HAL_RCC_TIM21_CLK_DISABLE
1713 #define __TIM21_FORCE_RESET   __HAL_RCC_TIM21_FORCE_RESET
1714 #define __TIM21_RELEASE_RESET  __HAL_RCC_TIM21_RELEASE_RESET
1715 #define __TIM21_CLK_SLEEP_ENABLE   __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
1716 #define __TIM21_CLK_SLEEP_DISABLE   __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
1717 #define __TIM22_CLK_ENABLE   __HAL_RCC_TIM22_CLK_ENABLE
1718 #define __TIM22_CLK_DISABLE   __HAL_RCC_TIM22_CLK_DISABLE
1719 #define __TIM22_FORCE_RESET   __HAL_RCC_TIM22_FORCE_RESET
1720 #define __TIM22_RELEASE_RESET  __HAL_RCC_TIM22_RELEASE_RESET
1721 #define __TIM22_CLK_SLEEP_ENABLE   __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
1722 #define __TIM22_CLK_SLEEP_DISABLE   __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
1723 #define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
1724 #define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
1725 #define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
1726 #define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
1727 #define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
1728 #define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
1729 #define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
1730 #define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
1731
1732 #define __USB_OTG_FS_FORCE_RESET  __HAL_RCC_USB_OTG_FS_FORCE_RESET
1733 #define __USB_OTG_FS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET
1734 #define __USB_OTG_FS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
1735 #define __USB_OTG_FS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
1736 #define __USB_OTG_HS_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_DISABLE
1737 #define __USB_OTG_HS_CLK_ENABLE          __HAL_RCC_USB_OTG_HS_CLK_ENABLE
1738 #define __USB_OTG_HS_ULPI_CLK_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
1739 #define __USB_OTG_HS_ULPI_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
1740 #define __TIM9_CLK_SLEEP_ENABLE          __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
1741 #define __TIM9_CLK_SLEEP_DISABLE  __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
1742 #define __TIM10_CLK_SLEEP_ENABLE  __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
1743 #define __TIM10_CLK_SLEEP_DISABLE  __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
1744 #define __TIM11_CLK_SLEEP_ENABLE  __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
1745 #define __TIM11_CLK_SLEEP_DISABLE  __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
1746 #define __ETHMACPTP_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
1747 #define __ETHMACPTP_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
1748 #define __ETHMACPTP_CLK_ENABLE          __HAL_RCC_ETHMACPTP_CLK_ENABLE
1749 #define __ETHMACPTP_CLK_DISABLE          __HAL_RCC_ETHMACPTP_CLK_DISABLE
1750 #define __HASH_CLK_ENABLE          __HAL_RCC_HASH_CLK_ENABLE
1751 #define __HASH_FORCE_RESET          __HAL_RCC_HASH_FORCE_RESET
1752 #define __HASH_RELEASE_RESET          __HAL_RCC_HASH_RELEASE_RESET
1753 #define __HASH_CLK_SLEEP_ENABLE          __HAL_RCC_HASH_CLK_SLEEP_ENABLE
1754 #define __HASH_CLK_SLEEP_DISABLE  __HAL_RCC_HASH_CLK_SLEEP_DISABLE
1755 #define __HASH_CLK_DISABLE            __HAL_RCC_HASH_CLK_DISABLE
1756 #define __SPI5_CLK_ENABLE          __HAL_RCC_SPI5_CLK_ENABLE
1757 #define __SPI5_CLK_DISABLE              __HAL_RCC_SPI5_CLK_DISABLE
1758 #define __SPI5_FORCE_RESET          __HAL_RCC_SPI5_FORCE_RESET
1759 #define __SPI5_RELEASE_RESET          __HAL_RCC_SPI5_RELEASE_RESET
1760 #define __SPI5_CLK_SLEEP_ENABLE          __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
1761 #define __SPI5_CLK_SLEEP_DISABLE  __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
1762 #define __SPI6_CLK_ENABLE          __HAL_RCC_SPI6_CLK_ENABLE
1763 #define __SPI6_CLK_DISABLE          __HAL_RCC_SPI6_CLK_DISABLE
1764 #define __SPI6_FORCE_RESET          __HAL_RCC_SPI6_FORCE_RESET
1765 #define __SPI6_RELEASE_RESET         __HAL_RCC_SPI6_RELEASE_RESET
1766 #define __SPI6_CLK_SLEEP_ENABLE          __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
1767 #define __SPI6_CLK_SLEEP_DISABLE  __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
1768 #define __LTDC_CLK_ENABLE          __HAL_RCC_LTDC_CLK_ENABLE
1769 #define __LTDC_CLK_DISABLE          __HAL_RCC_LTDC_CLK_DISABLE
1770 #define __LTDC_FORCE_RESET          __HAL_RCC_LTDC_FORCE_RESET
1771 #define __LTDC_RELEASE_RESET          __HAL_RCC_LTDC_RELEASE_RESET
1772 #define __LTDC_CLK_SLEEP_ENABLE          __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
1773 #define __ETHMAC_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
1774 #define __ETHMAC_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
1775 #define __ETHMACTX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
1776 #define __ETHMACTX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
1777 #define __ETHMACRX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
1778 #define __ETHMACRX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
1779 #define __TIM12_CLK_SLEEP_ENABLE  __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
1780 #define __TIM12_CLK_SLEEP_DISABLE  __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
1781 #define __TIM13_CLK_SLEEP_ENABLE  __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
1782 #define __TIM13_CLK_SLEEP_DISABLE  __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
1783 #define __TIM14_CLK_SLEEP_ENABLE  __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
1784 #define __TIM14_CLK_SLEEP_DISABLE  __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
1785 #define __BKPSRAM_CLK_ENABLE          __HAL_RCC_BKPSRAM_CLK_ENABLE
1786 #define __BKPSRAM_CLK_DISABLE          __HAL_RCC_BKPSRAM_CLK_DISABLE
1787 #define __BKPSRAM_CLK_SLEEP_ENABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
1788 #define __BKPSRAM_CLK_SLEEP_DISABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
1789 #define __CCMDATARAMEN_CLK_ENABLE  __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
1790 #define __CCMDATARAMEN_CLK_DISABLE  __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
1791 #define __USART6_CLK_ENABLE          __HAL_RCC_USART6_CLK_ENABLE
1792 #define __USART6_CLK_DISABLE          __HAL_RCC_USART6_CLK_DISABLE
1793 #define __USART6_FORCE_RESET        __HAL_RCC_USART6_FORCE_RESET
1794 #define __USART6_RELEASE_RESET        __HAL_RCC_USART6_RELEASE_RESET
1795 #define __USART6_CLK_SLEEP_ENABLE  __HAL_RCC_USART6_CLK_SLEEP_ENABLE
1796 #define __USART6_CLK_SLEEP_DISABLE  __HAL_RCC_USART6_CLK_SLEEP_DISABLE
1797 #define __SPI4_CLK_ENABLE          __HAL_RCC_SPI4_CLK_ENABLE
1798 #define __SPI4_CLK_DISABLE          __HAL_RCC_SPI4_CLK_DISABLE
1799 #define __SPI4_FORCE_RESET          __HAL_RCC_SPI4_FORCE_RESET
1800 #define __SPI4_RELEASE_RESET        __HAL_RCC_SPI4_RELEASE_RESET
1801 #define __SPI4_CLK_SLEEP_ENABLE   __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
1802 #define __SPI4_CLK_SLEEP_DISABLE  __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
1803 #define __GPIOI_CLK_ENABLE          __HAL_RCC_GPIOI_CLK_ENABLE
1804 #define __GPIOI_CLK_DISABLE          __HAL_RCC_GPIOI_CLK_DISABLE
1805 #define __GPIOI_FORCE_RESET          __HAL_RCC_GPIOI_FORCE_RESET
1806 #define __GPIOI_RELEASE_RESET          __HAL_RCC_GPIOI_RELEASE_RESET
1807 #define __GPIOI_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
1808 #define __GPIOI_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
1809 #define __GPIOJ_CLK_ENABLE          __HAL_RCC_GPIOJ_CLK_ENABLE
1810 #define __GPIOJ_CLK_DISABLE          __HAL_RCC_GPIOJ_CLK_DISABLE
1811 #define __GPIOJ_FORCE_RESET         __HAL_RCC_GPIOJ_FORCE_RESET
1812 #define __GPIOJ_RELEASE_RESET          __HAL_RCC_GPIOJ_RELEASE_RESET
1813 #define __GPIOJ_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
1814 #define __GPIOJ_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
1815 #define __GPIOK_CLK_ENABLE          __HAL_RCC_GPIOK_CLK_ENABLE
1816 #define __GPIOK_CLK_DISABLE          __HAL_RCC_GPIOK_CLK_DISABLE
1817 #define __GPIOK_RELEASE_RESET          __HAL_RCC_GPIOK_RELEASE_RESET
1818 #define __GPIOK_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
1819 #define __GPIOK_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
1820 #define __ETH_CLK_ENABLE          __HAL_RCC_ETH_CLK_ENABLE
1821 #define __ETH_CLK_DISABLE          __HAL_RCC_ETH_CLK_DISABLE
1822 #define __DCMI_CLK_ENABLE          __HAL_RCC_DCMI_CLK_ENABLE
1823 #define __DCMI_CLK_DISABLE          __HAL_RCC_DCMI_CLK_DISABLE
1824 #define __DCMI_FORCE_RESET          __HAL_RCC_DCMI_FORCE_RESET
1825 #define __DCMI_RELEASE_RESET          __HAL_RCC_DCMI_RELEASE_RESET
1826 #define __DCMI_CLK_SLEEP_ENABLE   __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
1827 #define __DCMI_CLK_SLEEP_DISABLE  __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
1828 #define __UART7_CLK_ENABLE          __HAL_RCC_UART7_CLK_ENABLE
1829 #define __UART7_CLK_DISABLE          __HAL_RCC_UART7_CLK_DISABLE
1830 #define __UART7_RELEASE_RESET       __HAL_RCC_UART7_RELEASE_RESET
1831 #define __UART7_FORCE_RESET       __HAL_RCC_UART7_FORCE_RESET
1832 #define __UART7_CLK_SLEEP_ENABLE  __HAL_RCC_UART7_CLK_SLEEP_ENABLE
1833 #define __UART7_CLK_SLEEP_DISABLE  __HAL_RCC_UART7_CLK_SLEEP_DISABLE
1834 #define __UART8_CLK_ENABLE          __HAL_RCC_UART8_CLK_ENABLE
1835 #define __UART8_CLK_DISABLE          __HAL_RCC_UART8_CLK_DISABLE
1836 #define __UART8_FORCE_RESET          __HAL_RCC_UART8_FORCE_RESET
1837 #define __UART8_RELEASE_RESET          __HAL_RCC_UART8_RELEASE_RESET
1838 #define __UART8_CLK_SLEEP_ENABLE  __HAL_RCC_UART8_CLK_SLEEP_ENABLE
1839 #define __UART8_CLK_SLEEP_DISABLE  __HAL_RCC_UART8_CLK_SLEEP_DISABLE
1840 #define __OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE
1841 #define __OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE
1842 #define __OTGHS_FORCE_RESET          __HAL_RCC_OTGHS_FORCE_RESET
1843 #define __OTGHS_RELEASE_RESET          __HAL_RCC_OTGHS_RELEASE_RESET
1844 #define __OTGHSULPI_CLK_SLEEP_ENABLE  __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE
1845 #define __OTGHSULPI_CLK_SLEEP_DISABLE  __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE
1846 #define __CRYP_FORCE_RESET          __HAL_RCC_CRYP_FORCE_RESET
1847 #define __SRAM3_CLK_SLEEP_ENABLE  __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
1848 #define __CAN2_CLK_SLEEP_ENABLE          __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
1849 #define __CAN2_CLK_SLEEP_DISABLE  __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
1850 #define __DAC_CLK_SLEEP_ENABLE          __HAL_RCC_DAC_CLK_SLEEP_ENABLE
1851 #define __DAC_CLK_SLEEP_DISABLE   __HAL_RCC_DAC_CLK_SLEEP_DISABLE
1852 #define __ADC2_CLK_SLEEP_ENABLE   __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
1853 #define __ADC2_CLK_SLEEP_DISABLE  __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
1854 #define __ADC3_CLK_SLEEP_ENABLE          __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
1855 #define __ADC3_CLK_SLEEP_DISABLE  __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
1856 #define __FSMC_FORCE_RESET          __HAL_RCC_FSMC_FORCE_RESET
1857 #define __FSMC_RELEASE_RESET          __HAL_RCC_FSMC_RELEASE_RESET
1858 #define __FSMC_CLK_SLEEP_ENABLE          __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
1859 #define __FSMC_CLK_SLEEP_DISABLE  __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
1860 #define __SDIO_FORCE_RESET          __HAL_RCC_SDIO_FORCE_RESET
1861 #define __SDIO_RELEASE_RESET          __HAL_RCC_SDIO_RELEASE_RESET
1862 #define __SDIO_CLK_SLEEP_DISABLE  __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
1863 #define __SDIO_CLK_SLEEP_ENABLE          __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
1864 #define __DMA2D_CLK_ENABLE          __HAL_RCC_DMA2D_CLK_ENABLE
1865 #define __DMA2D_CLK_DISABLE          __HAL_RCC_DMA2D_CLK_DISABLE
1866 #define __DMA2D_FORCE_RESET          __HAL_RCC_DMA2D_FORCE_RESET
1867 #define __DMA2D_RELEASE_RESET          __HAL_RCC_DMA2D_RELEASE_RESET
1868 #define __DMA2D_CLK_SLEEP_ENABLE  __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
1869 #define __DMA2D_CLK_SLEEP_DISABLE  __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
1870
1871 /* alias define maintained for legacy */
1872 #define __HAL_RCC_OTGFS_FORCE_RESET    __HAL_RCC_USB_OTG_FS_FORCE_RESET
1873 #define __HAL_RCC_OTGFS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET
1874
1875 #define __HAL_RCC_I2SCLK            __HAL_RCC_I2S_CONFIG
1876 #define __HAL_RCC_I2SCLK_CONFIG     __HAL_RCC_I2S_CONFIG
1877
1878 #define __RCC_PLLSRC           RCC_GET_PLL_OSCSOURCE
1879
1880 #define IS_RCC_MSIRANGE        IS_RCC_MSI_CLOCK_RANGE
1881 #define IS_RCC_RTCCLK_SOURCE   IS_RCC_RTCCLKSOURCE
1882 #define IS_RCC_SYSCLK_DIV      IS_RCC_HCLK
1883 #define IS_RCC_HCLK_DIV        IS_RCC_PCLK
1884
1885 #define RCC_MCO_NODIV          RCC_MCODIV_1
1886
1887 #define HSION_BitNumber        RCC_HSION_BIT_NUMBER
1888 #define CSSON_BitNumber        RCC_CSSON_BIT_NUMBER
1889 #define PLLON_BitNumber        RCC_PLLON_BIT_NUMBER
1890 #define PLLI2SON_BitNumber     RCC_PLLI2SON_BIT_NUMBER
1891 #define I2SSRC_BitNumber       RCC_I2SSRC_BIT_NUMBER
1892 #define RTCEN_BitNumber        RCC_RTCEN_BIT_NUMBER
1893 #define BDRST_BitNumber        RCC_BDRST_BIT_NUMBER
1894 #define LSION_BitNumber        RCC_LSION_BIT_NUMBER
1895 #define PLLSAION_BitNumber     RCC_PLLSAION_BIT_NUMBER
1896 #define TIMPRE_BitNumber       RCC_TIMPRE_BIT_NUMBER
1897
1898 #define CR_BYTE2_ADDRESS       RCC_CR_BYTE2_ADDRESS
1899 #define CIR_BYTE1_ADDRESS      RCC_CIR_BYTE1_ADDRESS
1900 #define CIR_BYTE2_ADDRESS      RCC_CIR_BYTE2_ADDRESS
1901 #define BDCR_BYTE0_ADDRESS     RCC_BDCR_BYTE0_ADDRESS
1902 #define DBP_TIMEOUT_VALUE      RCC_DBP_TIMEOUT_VALUE
1903 #define LSE_TIMEOUT_VALUE      RCC_LSE_TIMEOUT_VALUE
1904
1905 #define CR_HSION_BB            RCC_CR_HSION_BB
1906 #define CR_CSSON_BB            RCC_CR_CSSON_BB
1907 #define CR_PLLON_BB            RCC_CR_PLLON_BB
1908 #define CR_PLLI2SON_BB         RCC_CR_PLLI2SON_BB
1909 #define CR_MSION_BB            RCC_CR_MSION_BB
1910 #define CSR_LSION_BB           RCC_CSR_LSION_BB
1911 #define CSR_LSEON_BB           RCC_CSR_LSEON_BB
1912 #define CSR_LSEBYP_BB          RCC_CSR_LSEBYP_BB
1913 #define CSR_RTCEN_BB           RCC_CSR_RTCEN_BB
1914 #define CSR_RTCRST_BB          RCC_CSR_RTCRST_BB
1915 #define CFGR_I2SSRC_BB         RCC_CFGR_I2SSRC_BB
1916 #define BDCR_RTCEN_BB          RCC_BDCR_RTCEN_BB
1917 #define BDCR_BDRST_BB          RCC_BDCR_BDRST_BB
1918 #define CR_PLLSAION_BB         RCC_CR_PLLSAION_BB
1919 #define DCKCFGR_TIMPRE_BB      RCC_DCKCFGR_TIMPRE_BB
1920
1921 /**
1922   * @}
1923   */
1924
1925 /** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
1926   * @{
1927   */
1928 #define  HAL_RNG_ReadyCallback(__HANDLE__)  HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
1929
1930 /**
1931   * @}
1932   */
1933
1934 /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
1935   * @{
1936   */
1937
1938 #define __HAL_RTC_CLEAR_FLAG                      __HAL_RTC_EXTI_CLEAR_FLAG
1939 #define __HAL_RTC_DISABLE_IT                      __HAL_RTC_EXTI_DISABLE_IT
1940 #define __HAL_RTC_ENABLE_IT                       __HAL_RTC_EXTI_ENABLE_IT
1941 #if defined (RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
1942 #define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__)  ((__EXTI_LINE__ == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
1943 ((__EXTI_LINE__ == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
1944                                                       __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
1945 #define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__)   ((__EXTI_LINE__  == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
1946                                                   ((__EXTI_LINE__ == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
1947                                                       __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
1948 #define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__)  ((__EXTI_LINE__ == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
1949                                                   ((__EXTI_LINE__ == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
1950                                                       __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
1951 #define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__)    ((__EXTI_LINE__ == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
1952                                                   ((__EXTI_LINE__ == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
1953                                                       __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
1954 #define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__)   ((__EXTI_LINE__ == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
1955                                                       ((__EXTI_LINE__ == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() :  \
1956                                                           __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
1957
1958 #else
1959 #define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
1960
1961 #define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_ENABLE_IT()
1962
1963 #define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_DISABLE_IT()
1964
1965 #define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT)    __HAL_RTC_ALARM_EXTI_GET_FLAG()
1966
1967 #define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
1968
1969 #endif
1970
1971 #define IS_ALARM                                  IS_RTC_ALARM
1972 #define IS_ALARM_MASK                             IS_RTC_ALARM_MASK
1973 #define IS_TAMPER                                 IS_RTC_TAMPER
1974 #define IS_TAMPER_ERASE_MODE                      IS_RTC_TAMPER_ERASE_MODE
1975 #define IS_TAMPER_FILTER                          IS_RTC_TAMPER_FILTER
1976 #define IS_TAMPER_INTERRUPT                       IS_RTC_TAMPER_INTERRUPT
1977 #define IS_TAMPER_MASKFLAG_STATE                  IS_RTC_TAMPER_MASKFLAG_STATE
1978 #define IS_TAMPER_PRECHARGE_DURATION              IS_RTC_TAMPER_PRECHARGE_DURATION
1979 #define IS_TAMPER_PULLUP_STATE                    IS_RTC_TAMPER_PULLUP_STATE
1980 #define IS_TAMPER_SAMPLING_FREQ                   IS_RTC_TAMPER_SAMPLING_FREQ
1981 #define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION     IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
1982 #define IS_TAMPER_TRIGGER                         IS_RTC_TAMPER_TRIGGER
1983 #define IS_WAKEUP_CLOCK                           IS_RTC_WAKEUP_CLOCK
1984 #define IS_WAKEUP_COUNTER                         IS_RTC_WAKEUP_COUNTER
1985
1986 #define __RTC_WRITEPROTECTION_ENABLE  __HAL_RTC_WRITEPROTECTION_ENABLE
1987 #define __RTC_WRITEPROTECTION_DISABLE  __HAL_RTC_WRITEPROTECTION_DISABLE
1988
1989 /**
1990   * @}
1991   */
1992
1993 /** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
1994   * @{
1995   */
1996
1997 #define SD_OCR_CID_CSD_OVERWRIETE   SD_OCR_CID_CSD_OVERWRITE
1998 #define SD_CMD_SD_APP_STAUS         SD_CMD_SD_APP_STATUS
1999
2000 /**
2001   * @}
2002   */
2003
2004 /** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
2005   * @{
2006   */
2007
2008 #define __SMARTCARD_ENABLE_IT           __HAL_SMARTCARD_ENABLE_IT
2009 #define __SMARTCARD_DISABLE_IT          __HAL_SMARTCARD_DISABLE_IT
2010 #define __SMARTCARD_ENABLE              __HAL_SMARTCARD_ENABLE
2011 #define __SMARTCARD_DISABLE             __HAL_SMARTCARD_DISABLE
2012 #define __SMARTCARD_DMA_REQUEST_ENABLE  __HAL_SMARTCARD_DMA_REQUEST_ENABLE
2013 #define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
2014
2015 #define __HAL_SMARTCARD_GETCLOCKSOURCE  SMARTCARD_GETCLOCKSOURCE
2016 #define __SMARTCARD_GETCLOCKSOURCE      SMARTCARD_GETCLOCKSOURCE
2017
2018 #define IS_SMARTCARD_ONEBIT_SAMPLING    IS_SMARTCARD_ONE_BIT_SAMPLE
2019
2020 /**
2021   * @}
2022   */
2023
2024 /** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
2025   * @{
2026   */
2027 #define __HAL_SMBUS_RESET_CR1           SMBUS_RESET_CR1
2028 #define __HAL_SMBUS_RESET_CR2           SMBUS_RESET_CR2
2029 #define __HAL_SMBUS_GENERATE_START      SMBUS_GENERATE_START
2030 #define __HAL_SMBUS_GET_ADDR_MATCH      SMBUS_GET_ADDR_MATCH
2031 #define __HAL_SMBUS_GET_DIR             SMBUS_GET_DIR
2032 #define __HAL_SMBUS_GET_STOP_MODE       SMBUS_GET_STOP_MODE
2033 #define __HAL_SMBUS_GET_PEC_MODE        SMBUS_GET_PEC_MODE
2034 #define __HAL_SMBUS_GET_ALERT_ENABLED   SMBUS_GET_ALERT_ENABLED
2035 /**
2036   * @}
2037   */
2038
2039 /** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
2040   * @{
2041   */
2042
2043 #define __HAL_SPI_1LINE_TX              SPI_1LINE_TX
2044 #define __HAL_SPI_1LINE_RX              SPI_1LINE_RX
2045 #define __HAL_SPI_RESET_CRC             SPI_RESET_CRC
2046
2047 /**
2048   * @}
2049   */
2050
2051 /** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
2052   * @{
2053   */
2054
2055 #define __HAL_UART_GETCLOCKSOURCE       UART_GETCLOCKSOURCE
2056 #define __HAL_UART_MASK_COMPUTATION     UART_MASK_COMPUTATION
2057 #define __UART_GETCLOCKSOURCE           UART_GETCLOCKSOURCE
2058 #define __UART_MASK_COMPUTATION         UART_MASK_COMPUTATION
2059
2060 #define IS_UART_WAKEUPMETHODE           IS_UART_WAKEUPMETHOD
2061
2062 #define IS_UART_ONEBIT_SAMPLE           IS_UART_ONE_BIT_SAMPLE
2063 #define IS_UART_ONEBIT_SAMPLING         IS_UART_ONE_BIT_SAMPLE
2064
2065 /**
2066   * @}
2067   */
2068
2069
2070 /** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
2071   * @{
2072   */
2073
2074 #define __USART_ENABLE_IT               __HAL_USART_ENABLE_IT
2075 #define __USART_DISABLE_IT              __HAL_USART_DISABLE_IT
2076 #define __USART_ENABLE                  __HAL_USART_ENABLE
2077 #define __USART_DISABLE                 __HAL_USART_DISABLE
2078
2079 #define __HAL_USART_GETCLOCKSOURCE      USART_GETCLOCKSOURCE
2080 #define __USART_GETCLOCKSOURCE          USART_GETCLOCKSOURCE
2081
2082 /**
2083   * @}
2084   */
2085
2086 /** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
2087   * @{
2088   */
2089 #define USB_EXTI_LINE_WAKEUP                               USB_WAKEUP_EXTI_LINE
2090
2091 #define USB_FS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
2092 #define USB_FS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
2093 #define USB_FS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
2094 #define USB_FS_EXTI_LINE_WAKEUP                            USB_OTG_FS_WAKEUP_EXTI_LINE
2095
2096 #define USB_HS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
2097 #define USB_HS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
2098 #define USB_HS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
2099 #define USB_HS_EXTI_LINE_WAKEUP                            USB_OTG_HS_WAKEUP_EXTI_LINE
2100
2101 #define __HAL_USB_EXTI_ENABLE_IT                           __HAL_USB_WAKEUP_EXTI_ENABLE_IT
2102 #define __HAL_USB_EXTI_DISABLE_IT                          __HAL_USB_WAKEUP_EXTI_DISABLE_IT
2103 #define __HAL_USB_EXTI_GET_FLAG                            __HAL_USB_WAKEUP_EXTI_GET_FLAG
2104 #define __HAL_USB_EXTI_CLEAR_FLAG                          __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
2105 #define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER             __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
2106 #define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER            __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
2107 #define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER           __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
2108
2109 #define __HAL_USB_FS_EXTI_ENABLE_IT                        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
2110 #define __HAL_USB_FS_EXTI_DISABLE_IT                       __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
2111 #define __HAL_USB_FS_EXTI_GET_FLAG                         __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
2112 #define __HAL_USB_FS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
2113 #define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
2114 #define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
2115 #define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
2116 #define __HAL_USB_FS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
2117
2118 #define __HAL_USB_HS_EXTI_ENABLE_IT                        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
2119 #define __HAL_USB_HS_EXTI_DISABLE_IT                       __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
2120 #define __HAL_USB_HS_EXTI_GET_FLAG                         __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
2121 #define __HAL_USB_HS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
2122 #define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
2123 #define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
2124 #define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
2125 #define __HAL_USB_HS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
2126
2127 #define HAL_PCD_ActiveRemoteWakeup                         HAL_PCD_ActivateRemoteWakeup
2128 #define HAL_PCD_DeActiveRemoteWakeup                       HAL_PCD_DeActivateRemoteWakeup
2129
2130 #define HAL_PCD_SetTxFiFo                                  HAL_PCDEx_SetTxFiFo
2131 #define HAL_PCD_SetRxFiFo                                  HAL_PCDEx_SetRxFiFo
2132 /**
2133   * @}
2134   */
2135
2136 /** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
2137   * @{
2138   */
2139 #define __HAL_TIM_SetICPrescalerValue   TIM_SET_ICPRESCALERVALUE
2140 #define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
2141
2142 #define TIM_GET_ITSTATUS                __HAL_TIM_GET_IT_SOURCE
2143 #define TIM_GET_CLEAR_IT                __HAL_TIM_CLEAR_IT
2144
2145 #define __HAL_TIM_DIRECTION_STATUS      __HAL_TIM_IS_TIM_COUNTING_DOWN
2146 #define __HAL_TIM_PRESCALER             __HAL_TIM_SET_PRESCALER
2147 #define __HAL_TIM_SetCounter            __HAL_TIM_SET_COUNTER
2148 #define __HAL_TIM_GetCounter            __HAL_TIM_GET_COUNTER
2149 #define __HAL_TIM_SetAutoreload         __HAL_TIM_SET_AUTORELOAD
2150 #define __HAL_TIM_GetAutoreload         __HAL_TIM_GET_AUTORELOAD
2151 #define __HAL_TIM_SetClockDivision      __HAL_TIM_SET_CLOCKDIVISION
2152 #define __HAL_TIM_GetClockDivision      __HAL_TIM_GET_CLOCKDIVISION
2153 #define __HAL_TIM_SetICPrescaler        __HAL_TIM_SET_ICPRESCALER
2154 #define __HAL_TIM_GetICPrescaler        __HAL_TIM_GET_ICPRESCALER
2155 #define __HAL_TIM_SetCompare            __HAL_TIM_SET_COMPARE
2156 #define __HAL_TIM_GetCompare            __HAL_TIM_GET_COMPARE
2157
2158 #define TIM_TS_ITR0                        ((uint32_t)0x0000)
2159 #define TIM_TS_ITR1                        ((uint32_t)0x0010)
2160 #define TIM_TS_ITR2                        ((uint32_t)0x0020)
2161 #define TIM_TS_ITR3                        ((uint32_t)0x0030)
2162 #define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
2163                                                       ((SELECTION) == TIM_TS_ITR1) || \
2164                                                       ((SELECTION) == TIM_TS_ITR2) || \
2165                                                       ((SELECTION) == TIM_TS_ITR3))
2166
2167 #define TIM_CHANNEL_1                      ((uint32_t)0x0000)
2168 #define TIM_CHANNEL_2                      ((uint32_t)0x0004)
2169 #define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
2170                                        ((CHANNEL) == TIM_CHANNEL_2))
2171
2172 #define TIM_OUTPUTNSTATE_DISABLE            ((uint32_t)0x0000)
2173 #define TIM_OUTPUTNSTATE_ENABLE             (TIM_CCER_CC1NE)
2174
2175 #define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \
2176                                      ((STATE) == TIM_OUTPUTNSTATE_ENABLE))
2177
2178 #define TIM_OUTPUTSTATE_DISABLE            ((uint32_t)0x0000)
2179 #define TIM_OUTPUTSTATE_ENABLE             (TIM_CCER_CC1E)
2180
2181 #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \
2182                                     ((STATE) == TIM_OUTPUTSTATE_ENABLE))
2183 /**
2184   * @}
2185   */
2186
2187 /** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
2188   * @{
2189   */
2190
2191 #define __HAL_ETH_EXTI_ENABLE_IT                   __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
2192 #define __HAL_ETH_EXTI_DISABLE_IT                  __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
2193 #define __HAL_ETH_EXTI_GET_FLAG                    __HAL_ETH_WAKEUP_EXTI_GET_FLAG
2194 #define __HAL_ETH_EXTI_CLEAR_FLAG                  __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
2195 #define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER     __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
2196 #define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER    __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
2197 #define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER   __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
2198
2199 #define ETH_PROMISCIOUSMODE_ENABLE   ETH_PROMISCUOUS_MODE_ENABLE
2200 #define ETH_PROMISCIOUSMODE_DISABLE  ETH_PROMISCUOUS_MODE_DISABLE
2201 #define IS_ETH_PROMISCIOUS_MODE      IS_ETH_PROMISCUOUS_MODE
2202 /**
2203   * @}
2204   */
2205
2206 /** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
2207   * @{
2208   */
2209 #define __HAL_LTDC_LAYER LTDC_LAYER
2210 /**
2211   * @}
2212   */
2213
2214 /** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
2215   * @{
2216   */
2217 #define SAI_OUTPUTDRIVE_DISABLED          SAI_OUTPUTDRIVE_DISABLE
2218 #define SAI_OUTPUTDRIVE_ENABLED           SAI_OUTPUTDRIVE_ENABLE
2219 #define SAI_MASTERDIVIDER_ENABLED         SAI_MASTERDIVIDER_ENABLE
2220 #define SAI_MASTERDIVIDER_DISABLED        SAI_MASTERDIVIDER_DISABLE
2221 #define SAI_STREOMODE                     SAI_STEREOMODE
2222 #define SAI_FIFOStatus_Empty              SAI_FIFOSTATUS_EMPTY
2223 #define SAI_FIFOStatus_Less1QuarterFull   SAI_FIFOSTATUS_LESS1QUARTERFULL
2224 #define SAI_FIFOStatus_1QuarterFull       SAI_FIFOSTATUS_1QUARTERFULL
2225 #define SAI_FIFOStatus_HalfFull           SAI_FIFOSTATUS_HALFFULL
2226 #define SAI_FIFOStatus_3QuartersFull      SAI_FIFOSTATUS_3QUARTERFULL
2227 #define SAI_FIFOStatus_Full               SAI_FIFOSTATUS_FULL
2228 #define IS_SAI_BLOCK_MONO_STREO_MODE     IS_SAI_BLOCK_MONO_STEREO_MODE
2229
2230 /**
2231   * @}
2232   */
2233
2234
2235 /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
2236   * @{
2237   */
2238
2239 /**
2240   * @}
2241   */
2242
2243 #ifdef __cplusplus
2244 }
2245 #endif
2246
2247 #endif /* ___STM32_HAL_LEGACY */
2248
2249 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
2250