tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_dma.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32l0xx_hal_dma.h
   4   * @author  MCD Application Team
   5   * @version V1.2.0
   6   * @date    06-February-2015
   7   * @brief   Header file of DMA HAL module.
   8   ******************************************************************************
   9   * @attention
  10   *
  11   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
  12   *
  13   * Redistribution and use in source and binary forms, with or without modification,
  14   * are permitted provided that the following conditions are met:
  15   *   1. Redistributions of source code must retain the above copyright notice,
  16   *      this list of conditions and the following disclaimer.
  17   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18   *      this list of conditions and the following disclaimer in the documentation
  19   *      and/or other materials provided with the distribution.
  20   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21   *      may be used to endorse or promote products derived from this software
  22   *      without specific prior written permission.
  23   *
  24   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34   *
  35   ******************************************************************************
  36   */
  37
  38 /* Define to prevent recursive inclusion -------------------------------------*/
  39 #ifndef __STM32L0xx_HAL_DMA_H
  40 #define __STM32L0xx_HAL_DMA_H
  41
  42 #ifdef __cplusplus
  43  extern "C" {
  44 #endif
  45
  46 /* Includes ------------------------------------------------------------------*/
  47 #include "stm32l0xx_hal_def.h"
  48
  49 /** @addtogroup STM32L0xx_HAL_Driver
  50   * @{
  51   */
  52
  53 /** @defgroup DMA DMA
  54   * @{
  55   */
  56
  57 /* Exported types ------------------------------------------------------------*/
  58
  59 /**
  60   * @brief  DMA Configuration Structure definition
  61   */
  62 typedef struct
  63 {
  64   uint32_t Request;                   /*!< Specifies the request selected for the specified channel.
  65                                            This parameter can be a value of @ref DMA_request */
  66
  67   uint32_t Direction;                 /*!< Specifies if the data will be transferred from memory to peripheral,
  68                                            from memory to memory or from peripheral to memory.
  69                                            This parameter can be a value of @ref DMA_Data_transfer_direction */
  70
  71   uint32_t PeriphInc;                 /*!< Specifies whether the Peripheral address register should be incremented or not.
  72                                            When Memory to Memory transfer is used, this is the Source Increment mode
  73                                            This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
  74
  75   uint32_t MemInc;                    /*!< Specifies whether the memory address register should be incremented or not.
  76                                            When Memory to Memory transfer is used, this is the Destination Increment mode
  77                                            This parameter can be a value of @ref DMA_Memory_incremented_mode */
  78
  79   uint32_t PeriphDataAlignment;       /*!< Specifies the Peripheral data width.
  80                                            When Memory to Memory transfer is used, this is the Source Alignment format
  81                                            This parameter can be a value of @ref DMA_Peripheral_data_size */
  82
  83   uint32_t MemDataAlignment;          /*!< Specifies the Memory data width.
  84                                            When Memory to Memory transfer is used, this is the Destination Alignment format
  85                                            This parameter can be a value of @ref DMA_Memory_data_size */
  86
  87   uint32_t Mode;                      /*!< Specifies the operation mode of the DMAy Channelx (Normal or Circular).
  88                                            This parameter can be a value of @ref DMA_mode
  89                                            @note The circular buffer mode cannot be used if the memory-to-memory
  90                                                  data transfer is configured on the selected Channel */
  91
  92   uint32_t Priority;                   /*!< Specifies the software priority for the DMAy Channelx.
  93                                             This parameter can be a value of @ref DMA_Priority_level */
  94 } DMA_InitTypeDef;
  95
  96 /**
  97   * @brief DMA Configuration enumeration values definition
  98   */
  99 typedef enum
 100 {
 101   DMA_MODE            = 0,      /*!< Control related DMA mode Parameter in DMA_InitTypeDef        */
 102   DMA_PRIORITY        = 1,      /*!< Control related priority level Parameter in DMA_InitTypeDef  */
 103
 104 } DMA_ControlTypeDef;
 105
 106 /**
 107   * @brief  HAL DMA State structures definition
 108   */
 109 typedef enum
 110 {
 111   HAL_DMA_STATE_RESET             = 0x00,  /*!< DMA not yet initialized or disabled */
 112   HAL_DMA_STATE_READY             = 0x01,  /*!< DMA process success and ready for use   */
 113   HAL_DMA_STATE_BUSY              = 0x02,  /*!< DMA process is ongoing              */
 114   HAL_DMA_STATE_TIMEOUT           = 0x03,  /*!< DMA timeout state                   */
 115   HAL_DMA_STATE_ERROR             = 0x04,  /*!< DMA error state                     */
 116   HAL_DMA_STATE_READY_HALF        = 0x05,  /*!< DMA Half process success            */
 117 }HAL_DMA_StateTypeDef;
 118
 119 /**
 120   * @brief  HAL DMA Error Code structure definition
 121   */
 122 typedef enum
 123 {
 124   HAL_DMA_FULL_TRANSFER      = 0x00,    /*!< Full transfer     */
 125   HAL_DMA_HALF_TRANSFER      = 0x01,    /*!< Half Transfer     */
 126
 127 }HAL_DMA_LevelCompleteTypeDef;
 128
 129
 130 /**
 131   * @brief  DMA handle Structure definition
 132   */
 133 typedef struct __DMA_HandleTypeDef
 134 {
 135   DMA_Channel_TypeDef    *Instance;                                                   /*!< Register base address                  */
 136
 137   DMA_InitTypeDef       Init;                                                         /*!< DMA communication parameters           */
 138
 139   HAL_LockTypeDef       Lock;                                                         /*!< DMA locking object                     */
 140
 141   __IO HAL_DMA_StateTypeDef  State;                                                   /*!< DMA transfer state                     */
 142
 143   void                  *Parent;                                                      /*!< Parent object state                    */
 144
 145   void                  (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma);     /*!< DMA transfer complete callback         */
 146
 147   void                  (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback    */
 148
 149   void                  (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer error callback            */
 150
 151   __IO uint32_t          ErrorCode;                                                    /*!< DMA Error code                         */
 152
 153 } DMA_HandleTypeDef;
 154
 155 /* Exported constants --------------------------------------------------------*/
 156
 157 /** @defgroup DMA_Exported_Constants DMA Exported Constants
 158   * @{
 159   */
 160
 161 /** @defgroup DMA_Error_Code DMA Error Codes
 162   * @{
 163   */
 164 #define HAL_DMA_ERROR_NONE      ((uint32_t)0x00000000)    /*!< No error             */
 165 #define HAL_DMA_ERROR_TE        ((uint32_t)0x00000001)    /*!< Transfer error       */
 166 #define HAL_DMA_ERROR_TIMEOUT   ((uint32_t)0x00000020)    /*!< Timeout error        */
 167
 168 #define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
 169                                    ((PERIPH) == DMA1_Channel2) || \
 170                                    ((PERIPH) == DMA1_Channel3) || \
 171                                    ((PERIPH) == DMA1_Channel4) || \
 172                                    ((PERIPH) == DMA1_Channel5) || \
 173                                    ((PERIPH) == DMA1_Channel6) || \
 174                                    ((PERIPH) == DMA1_Channel7))
 175
 176 #define IS_DMA_ALL_CONTROLLER(CONTROLLER) (((CONTROLLER) == DMA1))
 177
 178 /**
 179   * @}
 180   */
 181
 182 /** @defgroup DMA_request DMA request defintiions
 183   * @{
 184   */
 185
 186 #if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
 187
 188 #define DMA_REQUEST_0                     ((uint32_t)0x00000000)
 189 #define DMA_REQUEST_1                     ((uint32_t)0x00000001)
 190 #define DMA_REQUEST_2                     ((uint32_t)0x00000002)
 191 #define DMA_REQUEST_3                     ((uint32_t)0x00000003)
 192 #define DMA_REQUEST_4                     ((uint32_t)0x00000004)
 193 #define DMA_REQUEST_5                     ((uint32_t)0x00000005)
 194 #define DMA_REQUEST_6                     ((uint32_t)0x00000006)
 195 #define DMA_REQUEST_7                     ((uint32_t)0x00000007)
 196 #define DMA_REQUEST_8                     ((uint32_t)0x00000008)
 197 #define DMA_REQUEST_9                     ((uint32_t)0x00000009)
 198 #define DMA_REQUEST_10                    ((uint32_t)0x0000000A)
 199 #define DMA_REQUEST_11                    ((uint32_t)0x0000000B)
 200 #define DMA_REQUEST_12                    ((uint32_t)0x0000000C)
 201 #define DMA_REQUEST_13                    ((uint32_t)0x0000000D)
 202 #define DMA_REQUEST_14                    ((uint32_t)0x0000000E)
 203 #define DMA_REQUEST_15                    ((uint32_t)0x0000000F)
 204
 205 #define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \
 206                                      ((REQUEST) == DMA_REQUEST_1) || \
 207                                      ((REQUEST) == DMA_REQUEST_2) || \
 208                                      ((REQUEST) == DMA_REQUEST_3) || \
 209                                      ((REQUEST) == DMA_REQUEST_4) || \
 210                                      ((REQUEST) == DMA_REQUEST_5) || \
 211                                      ((REQUEST) == DMA_REQUEST_6) || \
 212                                      ((REQUEST) == DMA_REQUEST_7) || \
 213                                      ((REQUEST) == DMA_REQUEST_8) || \
 214                                      ((REQUEST) == DMA_REQUEST_9) || \
 215                                      ((REQUEST) == DMA_REQUEST_10) || \
 216                                      ((REQUEST) == DMA_REQUEST_11) || \
 217                                      ((REQUEST) == DMA_REQUEST_12) || \
 218                                      ((REQUEST) == DMA_REQUEST_13) || \
 219                                      ((REQUEST) == DMA_REQUEST_14) || \
 220                                      ((REQUEST) == DMA_REQUEST_15))
 221
 222 #else /* #if STM32L071xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx */
 223
 224 #define DMA_REQUEST_0                     ((uint32_t)0x00000000)
 225 #define DMA_REQUEST_1                     ((uint32_t)0x00000001)
 226 #define DMA_REQUEST_2                     ((uint32_t)0x00000002)
 227 #define DMA_REQUEST_3                     ((uint32_t)0x00000003)
 228 #define DMA_REQUEST_4                     ((uint32_t)0x00000004)
 229 #define DMA_REQUEST_5                     ((uint32_t)0x00000005)
 230 #define DMA_REQUEST_6                     ((uint32_t)0x00000006)
 231 #define DMA_REQUEST_7                     ((uint32_t)0x00000007)
 232 #define DMA_REQUEST_8                     ((uint32_t)0x00000008)
 233 #define DMA_REQUEST_9                     ((uint32_t)0x00000009)
 234 #define DMA_REQUEST_11                    ((uint32_t)0x0000000B)
 235
 236 #define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \
 237                                      ((REQUEST) == DMA_REQUEST_1) || \
 238                                      ((REQUEST) == DMA_REQUEST_2) || \
 239                                      ((REQUEST) == DMA_REQUEST_3) || \
 240                                      ((REQUEST) == DMA_REQUEST_4) || \
 241                                      ((REQUEST) == DMA_REQUEST_5) || \
 242                                      ((REQUEST) == DMA_REQUEST_6) || \
 243                                      ((REQUEST) == DMA_REQUEST_7) || \
 244                                      ((REQUEST) == DMA_REQUEST_8) || \
 245                                      ((REQUEST) == DMA_REQUEST_9) || \
 246                                      ((REQUEST) == DMA_REQUEST_11))
 247 #endif /* #if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx) */
 248
 249 /**
 250   * @}
 251   */
 252
 253 /** @defgroup DMA_Data_transfer_direction DMA Data Transfer directions
 254   * @{
 255   */
 256 #define DMA_PERIPH_TO_MEMORY         ((uint32_t)0x00000000)        /*!< Peripheral to memory direction */
 257 #define DMA_MEMORY_TO_PERIPH         ((uint32_t)DMA_CCR_DIR)       /*!< Memory to peripheral direction */
 258 #define DMA_MEMORY_TO_MEMORY         ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction     */
 259
 260 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
 261                                      ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
 262                                      ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
 263 /**
 264   * @}
 265   */
 266
 267 /** @defgroup DMA_Data_buffer_size
 268   * @{
 269   */
 270 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
 271 /**
 272   * @}
 273   */
 274
 275 /** @defgroup DMA_Peripheral_incremented_mode
 276   * @{
 277   */
 278 #define DMA_PINC_ENABLE        ((uint32_t)DMA_CCR_PINC)  /*!< Peripheral increment mode Enable */
 279 #define DMA_PINC_DISABLE       ((uint32_t)0x00000000)    /*!< Peripheral increment mode Disable */
 280
 281 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
 282                                             ((STATE) == DMA_PINC_DISABLE))
 283 /**
 284   * @}
 285   */
 286
 287 /** @defgroup DMA_Memory_incremented_mode
 288   * @{
 289   */
 290 #define DMA_MINC_ENABLE         ((uint32_t)DMA_CCR_MINC)  /*!< Memory increment mode Enable  */
 291 #define DMA_MINC_DISABLE        ((uint32_t)0x00000000)    /*!< Memory increment mode Disable */
 292
 293 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \
 294                                         ((STATE) == DMA_MINC_DISABLE))
 295 /**
 296   * @}
 297   */
 298
 299 /** @defgroup DMA_Peripheral_data_size
 300   * @{
 301   */
 302 #define DMA_PDATAALIGN_BYTE          ((uint32_t)0x00000000)       /*!< Peripheral data alignment : Byte     */
 303 #define DMA_PDATAALIGN_HALFWORD      ((uint32_t)DMA_CCR_PSIZE_0)  /*!< Peripheral data alignment : HalfWord */
 304 #define DMA_PDATAALIGN_WORD          ((uint32_t)DMA_CCR_PSIZE_1)  /*!< Peripheral data alignment : Word     */
 305
 306 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
 307                                            ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
 308                                            ((SIZE) == DMA_PDATAALIGN_WORD))
 309 /**
 310   * @}
 311   */
 312
 313
 314 /** @defgroup DMA_Memory_data_size
 315   * @{
 316   */
 317 #define DMA_MDATAALIGN_BYTE          ((uint32_t)0x00000000)       /*!< Memory data alignment : Byte     */
 318 #define DMA_MDATAALIGN_HALFWORD      ((uint32_t)DMA_CCR_MSIZE_0)  /*!< Memory data alignment : HalfWord */
 319 #define DMA_MDATAALIGN_WORD          ((uint32_t)DMA_CCR_MSIZE_1)  /*!< Memory data alignment : Word     */
 320
 321 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
 322                                        ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
 323                                        ((SIZE) == DMA_MDATAALIGN_WORD ))
 324 /**
 325   * @}
 326   */
 327
 328 /** @defgroup DMA_mode
 329   * @{
 330   */
 331 #define DMA_NORMAL         ((uint32_t)0x00000000)       /*!< Normal Mode                  */
 332 #define DMA_CIRCULAR       ((uint32_t)DMA_CCR_CIRC)    /*!< Circular Mode                */
 333
 334 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \
 335                            ((MODE) == DMA_CIRCULAR))
 336 /**
 337   * @}
 338   */
 339
 340 /** @defgroup DMA_Priority_level
 341   * @{
 342   */
 343 #define DMA_PRIORITY_LOW             ((uint32_t)0x00000000)    /*!< Priority level : Low       */
 344 #define DMA_PRIORITY_MEDIUM          ((uint32_t)DMA_CCR_PL_0)  /*!< Priority level : Medium    */
 345 #define DMA_PRIORITY_HIGH            ((uint32_t)DMA_CCR_PL_1)  /*!< Priority level : High      */
 346 #define DMA_PRIORITY_VERY_HIGH       ((uint32_t)DMA_CCR_PL)    /*!< Priority level : Very_High */
 347
 348 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \
 349                                    ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
 350                                    ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
 351                                    ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
 352 /**
 353   * @}
 354   */
 355
 356
 357 /** @defgroup DMA_interrupt_enable_definitions
 358   * @{
 359   */
 360
 361 #define DMA_IT_TC                         ((uint32_t)DMA_CCR_TCIE)
 362 #define DMA_IT_HT                         ((uint32_t)DMA_CCR_HTIE)
 363 #define DMA_IT_TE                         ((uint32_t)DMA_CCR_TEIE)
 364
 365 /**
 366   * @}
 367   */
 368
 369 /** @defgroup DMA_flag_definitions
 370   * @{
 371   */
 372
 373 #define DMA_FLAG_GL1                      ((uint32_t)0x00000001)
 374 #define DMA_FLAG_TC1                      ((uint32_t)0x00000002)
 375 #define DMA_FLAG_HT1                      ((uint32_t)0x00000004)
 376 #define DMA_FLAG_TE1                      ((uint32_t)0x00000008)
 377 #define DMA_FLAG_GL2                      ((uint32_t)0x00000010)
 378 #define DMA_FLAG_TC2                      ((uint32_t)0x00000020)
 379 #define DMA_FLAG_HT2                      ((uint32_t)0x00000040)
 380 #define DMA_FLAG_TE2                      ((uint32_t)0x00000080)
 381 #define DMA_FLAG_GL3                      ((uint32_t)0x00000100)
 382 #define DMA_FLAG_TC3                      ((uint32_t)0x00000200)
 383 #define DMA_FLAG_HT3                      ((uint32_t)0x00000400)
 384 #define DMA_FLAG_TE3                      ((uint32_t)0x00000800)
 385 #define DMA_FLAG_GL4                      ((uint32_t)0x00001000)
 386 #define DMA_FLAG_TC4                      ((uint32_t)0x00002000)
 387 #define DMA_FLAG_HT4                      ((uint32_t)0x00004000)
 388 #define DMA_FLAG_TE4                      ((uint32_t)0x00008000)
 389 #define DMA_FLAG_GL5                      ((uint32_t)0x00010000)
 390 #define DMA_FLAG_TC5                      ((uint32_t)0x00020000)
 391 #define DMA_FLAG_HT5                      ((uint32_t)0x00040000)
 392 #define DMA_FLAG_TE5                      ((uint32_t)0x00080000)
 393 #define DMA_FLAG_GL6                      ((uint32_t)0x00100000)
 394 #define DMA_FLAG_TC6                      ((uint32_t)0x00200000)
 395 #define DMA_FLAG_HT6                      ((uint32_t)0x00400000)
 396 #define DMA_FLAG_TE6                      ((uint32_t)0x00800000)
 397 #define DMA_FLAG_GL7                      ((uint32_t)0x01000000)
 398 #define DMA_FLAG_TC7                      ((uint32_t)0x02000000)
 399 #define DMA_FLAG_HT7                      ((uint32_t)0x04000000)
 400 #define DMA_FLAG_TE7                      ((uint32_t)0x08000000)
 401
 402
 403 /**
 404   * @}
 405   */
 406
 407 /**
 408   * @}
 409   */
 410
 411 /* Exported macro ------------------------------------------------------------*/
 412
 413 /** @defgroup DMA_Exported_Macros DMA Exported Macros
 414  * @{
 415  */
 416
 417 /** @brief Reset DMA handle state
 418   * @param  __HANDLE__: DMA handle
 419   * @retval None
 420   */
 421 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
 422
 423 /**
 424   * @brief  Enable the specified DMA Channel.
 425   * @param  __HANDLE__: DMA handle
 426   * @retval None.
 427   */
 428 #define __HAL_DMA_ENABLE(__HANDLE__)        ((__HANDLE__)->Instance->CCR |=  DMA_CCR_EN)
 429
 430 /**
 431   * @brief  Disable the specified DMA Channel.
 432   * @param  __HANDLE__: DMA handle
 433   * @retval None.
 434   */
 435 #define __HAL_DMA_DISABLE(__HANDLE__)       ((__HANDLE__)->Instance->CCR &=  ~DMA_CCR_EN)
 436
 437
 438 /* Interrupt & Flag management */
 439
 440 /**
 441   * @brief  Returns the current DMA Channel transfer complete flag.
 442   * @param  __HANDLE__: DMA handle
 443   * @retval The specified transfer complete flag index.
 444   */
 445
 446 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
 447 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
 448  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
 449  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
 450  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
 451  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
 452  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
 453    DMA_FLAG_TC7)
 454
 455 /**
 456   * @brief  Returns the current DMA Channel half transfer complete flag.
 457   * @param  __HANDLE__: DMA handle
 458   * @retval The specified half transfer complete flag index.
 459   */
 460 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
 461 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
 462  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
 463  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
 464  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
 465  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
 466  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
 467    DMA_FLAG_HT7)
 468
 469 /**
 470   * @brief  Returns the current DMA Channel transfer error flag.
 471   * @param  __HANDLE__: DMA handle
 472   * @retval The specified transfer error flag index.
 473   */
 474 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
 475 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
 476  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
 477  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
 478  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
 479  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
 480  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
 481    DMA_FLAG_TE7)
 482
 483 /**
 484   * @brief  Returns the current DMA Channel Global interrupt flag.
 485   * @param  __HANDLE__: DMA handle
 486   * @retval The specified transfer error flag index.
 487   */
 488 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
 489 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
 490  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
 491  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
 492  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
 493  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
 494  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
 495    DMA_ISR_GIF7)
 496 /**
 497   * @brief  Get the DMA Channel pending flags.
 498   * @param  __HANDLE__: DMA handle
 499   * @param  __FLAG__: Get the specified flag.
 500   *          This parameter can be any combination of the following values:
 501   *            @arg DMA_FLAG_TCIFx:  Transfer complete flag
 502   *            @arg DMA_FLAG_HTIFx:  Half transfer complete flag
 503   *            @arg DMA_FLAG_TEIFx:  Transfer error flag
 504   *            @arg DMA_ISR_GIFx: Global interrupt flag
 505   *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
 506   * @retval The state of FLAG (SET or RESET).
 507   */
 508 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
 509
 510 /**
 511   * @brief  Clears the DMA Channel pending flags.
 512   * @param  __HANDLE__: DMA handle
 513   * @param  __FLAG__: specifies the flag to clear.
 514   *          This parameter can be any combination of the following values:
 515   *            @arg DMA_FLAG_TCIFx:  Transfer complete flag
 516   *            @arg DMA_FLAG_HTIFx:  Half transfer complete flag
 517   *            @arg DMA_FLAG_TEIFx:  Transfer error flag
 518   *            @arg DMA_ISR_GIFx: Global interrupt flag
 519   *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
 520   * @retval None
 521   */
 522 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
 523
 524 /**
 525   * @brief  Enables the specified DMA Channel interrupts.
 526   * @param  __HANDLE__: DMA handle
 527   * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
 528   *          This parameter can be any combination of the following values:
 529   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
 530   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
 531   *            @arg DMA_IT_TE:  Transfer error interrupt mask
 532   * @retval None
 533   */
 534 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
 535
 536 /**
 537   * @brief  Disables the specified DMA Channel interrupts.
 538   * @param  __HANDLE__: DMA handle
 539   * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
 540   *          This parameter can be any combination of the following values:
 541   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
 542   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
 543   *            @arg DMA_IT_TE:  Transfer error interrupt mask
 544   * @retval None
 545   */
 546 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
 547
 548 /**
 549   * @brief  Checks whether the specified DMA Channel interrupt has occurred or not.
 550   * @param  __HANDLE__: DMA handle
 551   * @param  __INTERRUPT__: specifies the DMA interrupt source to check.
 552   *          This parameter can be one of the following values:
 553   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
 554   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
 555   *            @arg DMA_IT_TE:  Transfer error interrupt mask
 556   * @retval The state of DMA_IT (SET or RESET).
 557   */
 558 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
 559
 560 /**
 561   * @}
 562   */
 563
 564 /* Exported functions --------------------------------------------------------*/
 565
 566 /** @defgroup DMA_Exported_Functions DMA Exported Functions
 567   * @{
 568   */
 569
 570 /** @defgroup DMA_Exported_Functions_Group1 Initialization/de-initialization functions
 571   * @{
 572   */
 573
 574 /* Initialization and de-initialization functions *****************************/
 575 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
 576 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
 577
 578 /**
 579   * @}
 580   */
 581
 582 /** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
 583   * @{
 584   */
 585
 586 /* IO operation functions *****************************************************/
 587 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
 588 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
 589 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
 590 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
 591 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
 592 /**
 593   * @}
 594   */
 595
 596 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
 597   * @{
 598   */
 599
 600 /* Peripheral State and Error functions ***************************************/
 601 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
 602 uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
 603
 604 /**
 605   * @}
 606   */
 607
 608 /**
 609   * @}
 610   */
 611
 612 /**
 613   * @}
 614   */
 615
 616 /**
 617   * @}
 618   */
 619
 620 #ifdef __cplusplus
 621 }
 622 #endif
 623
 624 #endif /* __STM32L0xx_HAL_DMA_H */
 625
 626 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
 627