tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32l0xx_hal_rcc.h
   4   * @author  MCD Application Team
   5   * @version V1.2.0
   6   * @date    06-February-2015
   7   * @brief   Header file of RCC HAL module.
   8   ******************************************************************************
   9   * @attention
  10   *
  11   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
  12   *
  13   * Redistribution and use in source and binary forms, with or without modification,
  14   * are permitted provided that the following conditions are met:
  15   *   1. Redistributions of source code must retain the above copyright notice,
  16   *      this list of conditions and the following disclaimer.
  17   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18   *      this list of conditions and the following disclaimer in the documentation
  19   *      and/or other materials provided with the distribution.
  20   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21   *      may be used to endorse or promote products derived from this software
  22   *      without specific prior written permission.
  23   *
  24   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34   *
  35   ******************************************************************************
  36   */
  37
  38 /* Define to prevent recursive inclusion -------------------------------------*/
  39 #ifndef __STM32L0xx_HAL_RCC_H
  40 #define __STM32L0xx_HAL_RCC_H
  41
  42 #ifdef __cplusplus
  43  extern "C" {
  44 #endif
  45
  46 /* Includes ------------------------------------------------------------------*/
  47 #include "stm32l0xx_hal_def.h"
  48
  49 /** @addtogroup STM32L0xx_HAL_Driver
  50   * @{
  51   */
  52
  53 /** @defgroup RCC RCC
  54   * @{
  55   */
  56
  57 /* Exported types ------------------------------------------------------------*/
  58
  59 /**
  60   * @brief  RCC PLL configuration structure definition
  61   */
  62 typedef struct
  63 {
  64   uint32_t PLLState;   /*!< The new state of the PLL.
  65                             This parameter can be a value of @ref RCC_PLL_Config */
  66
  67   uint32_t PLLSource;  /*!< RCC_PLLSource: PLL entry clock source.
  68                             This parameter must be a value of @ref RCC_PLL_Clock_Source */
  69
  70   uint32_t PLLMUL;       /*!< PLLMUL: Multiplication factor for PLL VCO output clock
  71                               This parameter must of @ref RCC_PLLMultiplication_Factor */
  72
  73   uint32_t PLLDIV;       /*!< PLLDIV: Division factor for main system clock (SYSCLK)
  74                             This parameter must be a value of @ref RCC_PLLDivider_Factor */
  75
  76 }RCC_PLLInitTypeDef;
  77
  78 /**
  79   * @brief  RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
  80   */
  81 typedef struct
  82 {
  83   uint32_t OscillatorType;       /*!< The oscillators to be configured.
  84                                       This parameter can be a value of @ref RCC_Oscillator_Type */
  85
  86   uint32_t HSEState;             /*!< The new state of the HSE.
  87                                       This parameter can be a value of @ref RCC_HSE_Config */
  88
  89   uint32_t LSEState;             /*!< The new state of the LSE.
  90                                       This parameter can be a value of @ref RCC_LSE_Config */
  91
  92   uint32_t HSIState;             /*!< The new state of the HSI.
  93                                       This parameter can be a value of @ref RCC_HSI_Config */
  94
  95   uint32_t HSICalibrationValue;  /*!< The calibration trimming value.
  96                                       This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
  97
  98   uint32_t LSIState;             /*!< The new state of the LSI.
  99                                       This parameter can be a value of @ref RCC_LSI_Config */
 100
 101 #if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx)  && !defined(STM32L081xx)
 102   uint32_t HSI48State;             /*!< The new state of the HSI48.
 103                                       This parameter can be a value of @ref RCC_HSI48_Config */
 104 #endif
 105
 106   uint32_t MSIState;             /*!< The new state of the MSI.
 107                                       This parameter can be a value of @ref RCC_MSI_Config */
 108
 109   uint32_t MSICalibrationValue;  /*!< The calibration trimming value.
 110                                       This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
 111
 112   uint32_t MSIClockRange;         /*!< The MSI  frequency  range.
 113                                       This parameter can be a value of @ref RCC_MSI_Clock_Range  */
 114
 115   RCC_PLLInitTypeDef PLL;        /*!< PLL structure parameters */
 116
 117 }RCC_OscInitTypeDef;
 118
 119 /**
 120   * @brief  RCC System, AHB and APB busses clock configuration structure definition
 121   */
 122 typedef struct
 123 {
 124   uint32_t ClockType;             /*!< The clock to be configured.
 125                                        This parameter can be a value of @ref RCC_System_Clock_Type */
 126
 127   uint32_t SYSCLKSource;          /*!< The clock source (SYSCLKS) used as system clock.
 128                                        This parameter can be a value of @ref RCC_System_Clock_Source */
 129
 130   uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
 131                                        This parameter can be a value of @ref RCC_AHB_Clock_Source */
 132
 133   uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
 134                                        This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
 135
 136   uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
 137                                        This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
 138
 139 }RCC_ClkInitTypeDef;
 140
 141
 142 /** @defgroup RCC_Private_Constants RCC Private constatnts
 143   * @brief RCC registers bit address in the alias region
 144   * @{
 145   */
 146 #define RCC_OFFSET                (RCC_BASE - PERIPH_BASE)
 147 /* --- CR Register ---*/
 148 /* Alias word address of HSION bit */
 149 #define RCC_CR_OFFSET             (RCC_OFFSET + 0x00)
 150 /* --- CFGR Register ---*/
 151 /* Alias word address of I2SSRC bit */
 152 #define RCC_CFGR_OFFSET           (RCC_OFFSET + 0x08)
 153 /* --- CSR Register ---*/
 154 #define RCC_CSR_OFFSET            (RCC_OFFSET + 0x74)
 155
 156 /* CR register byte 3 (Bits[23:16]) base address */
 157 #define RCC_CR_BYTE2_ADDRESS          ((uint32_t)0x40023802)
 158
 159 /* CIER register byte 0 (Bits[0:8]) base address */
 160 #define CIER_BYTE0_ADDRESS         ((uint32_t)(RCC_BASE + 0x10 + 0x00))
 161
 162 #define RCC_LSE_TIMEOUT_VALUE          LSE_STARTUP_TIMEOUT
 163 #define RCC_DBP_TIMEOUT_VALUE          ((uint32_t)100)  /* 100 ms */
 164
 165 /**
 166   * @}
 167   */
 168
 169 /** @defgroup RCC_Exported_Constants RCC Exported Constants
 170   * @{
 171   */
 172
 173 /** @defgroup RCC_Oscillator_Type RCC Oscillator Type
 174   * @{
 175   */
 176 #define RCC_OSCILLATORTYPE_NONE            ((uint32_t)0x00000000)
 177 #define RCC_OSCILLATORTYPE_HSE             ((uint32_t)0x00000001)
 178 #define RCC_OSCILLATORTYPE_HSI             ((uint32_t)0x00000002)
 179 #define RCC_OSCILLATORTYPE_LSE             ((uint32_t)0x00000004)
 180 #define RCC_OSCILLATORTYPE_LSI             ((uint32_t)0x00000008)
 181 #define RCC_OSCILLATORTYPE_MSI             ((uint32_t)0x00000010)
 182 #if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx)  && !defined(STM32L081xx)
 183 #define RCC_OSCILLATORTYPE_HSI48           ((uint32_t)0x00000020)
 184 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) ((__OSCILLATOR__) <= 0x3F)
 185 #else
 186 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) ((__OSCILLATOR__) <= 0x1F)
 187 #endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx)  && !defined(STM32L081xx) */
 188
 189 /**
 190   * @}
 191   */
 192
 193 /** @defgroup RCC_HSE_Config RCC HSE Config
 194   * @{
 195   */
 196 #define RCC_HSE_OFF                     ((uint32_t)0x00000000)
 197 #define RCC_HSE_ON                      RCC_CR_HSEON
 198 #define RCC_HSE_BYPASS                  ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
 199
 200 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
 201                              ((__HSE__) == RCC_HSE_BYPASS))
 202 /**
 203   * @}
 204   */
 205
 206 /** @defgroup RCC_LSE_Config RCC LSE Config
 207   * @{
 208   */
 209 #define RCC_LSE_OFF                      ((uint32_t)0x00000000)
 210 #define RCC_LSE_ON                       RCC_CSR_LSEON
 211 #define RCC_LSE_BYPASS                   ((uint32_t)(RCC_CSR_LSEBYP | RCC_CSR_LSEON))
 212
 213 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
 214                              ((__LSE__) == RCC_LSE_BYPASS))
 215 /**
 216   * @}
 217   */
 218
 219
 220
 221 /** @defgroup RCC_MSI_Clock_Range RCC MSI Clock Range
 222   * @{
 223   */
 224
 225 #define RCC_MSIRANGE_0                   RCC_ICSCR_MSIRANGE_0 /*!< MSI = 65.536 KHz  */
 226 #define RCC_MSIRANGE_1                   RCC_ICSCR_MSIRANGE_1 /*!< MSI = 131.072 KHz */
 227 #define RCC_MSIRANGE_2                   RCC_ICSCR_MSIRANGE_2 /*!< MSI = 262.144 KHz */
 228 #define RCC_MSIRANGE_3                   RCC_ICSCR_MSIRANGE_3 /*!< MSI = 524.288 KHz */
 229 #define RCC_MSIRANGE_4                   RCC_ICSCR_MSIRANGE_4 /*!< MSI = 1.048 MHz   */
 230 #define RCC_MSIRANGE_5                   RCC_ICSCR_MSIRANGE_5 /*!< MSI = 2.097 MHz   */
 231 #define RCC_MSIRANGE_6                   RCC_ICSCR_MSIRANGE_6 /*!< MSI = 4.194 MHz   */
 232
 233 #define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \
 234                                           ((__RANGE__) == RCC_MSIRANGE_1) || \
 235                                           ((__RANGE__) == RCC_MSIRANGE_2) || \
 236                                           ((__RANGE__) == RCC_MSIRANGE_3) || \
 237                                           ((__RANGE__) == RCC_MSIRANGE_4) || \
 238                                           ((__RANGE__) == RCC_MSIRANGE_5) || \
 239                                           ((__RANGE__) == RCC_MSIRANGE_6))
 240
 241 /**
 242   * @}
 243   */
 244
 245 /** @defgroup RCC_LSI_Config RCC LSI Config
 246   * @{
 247   */
 248 #define RCC_LSI_OFF                      ((uint8_t)0x00)
 249 #define RCC_LSI_ON                       ((uint8_t)0x01)
 250
 251 #define RCC_MSICALIBRATION_DEFAULT     ((uint32_t)0)   /* Default MSI calibration trimming value */
 252
 253 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
 254 /**
 255   * @}
 256   */
 257
 258
 259 /** @defgroup RCC_MSI_Config RCC MSI Config
 260   * @{
 261   */
 262 #define RCC_MSI_OFF                      ((uint8_t)0x00)
 263 #define RCC_MSI_ON                       ((uint8_t)0x01)
 264
 265 #define RCC_HSICALIBRATION_DEFAULT     ((uint32_t)0x10)   /* Default HSI calibration trimming value */
 266
 267 #define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON))
 268 /**
 269   * @}
 270   */
 271
 272 #if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx)  && !defined(STM32L081xx)
 273 /** @defgroup RCC_HSI48_Config
 274   * @{
 275   */
 276 #define RCC_HSI48_OFF                      ((uint8_t)0x00)
 277 #define RCC_HSI48_ON                       ((uint8_t)0x01)
 278
 279 #define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON))
 280 /**
 281   * @}
 282   */
 283 #endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx)  && !defined(STM32L081xx) */
 284
 285 /** @defgroup RCC_PLL_Config RCC PLL Config
 286   * @{
 287   */
 288 #define RCC_PLL_NONE                      ((uint8_t)0x00)
 289 #define RCC_PLL_OFF                       ((uint8_t)0x01)
 290 #define RCC_PLL_ON                        ((uint8_t)0x02)
 291
 292 #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || ((__PLL__) == RCC_PLL_ON))
 293 /**
 294   * @}
 295   */
 296
 297 /** @defgroup RCC_PLL_Clock_Source PCC PLL Clock Source
 298   * @{
 299   */
 300 #define RCC_PLLSOURCE_HSI                RCC_CFGR_PLLSRC_HSI
 301 #define RCC_PLLSOURCE_HSE                RCC_CFGR_PLLSRC_HSE
 302
 303 #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) || \
 304                                       ((__SOURCE__) == RCC_PLLSOURCE_HSE))
 305
 306 /**
 307   * @}
 308   */
 309
 310 /** @defgroup RCC_PLLMultiplication_Factor RCC PLL Multipliers
 311   * @{
 312   */
 313
 314 #define RCC_PLLMUL_3                     RCC_CFGR_PLLMUL3
 315 #define RCC_PLLMUL_4                     RCC_CFGR_PLLMUL4
 316 #define RCC_PLLMUL_6                     RCC_CFGR_PLLMUL6
 317 #define RCC_PLLMUL_8                     RCC_CFGR_PLLMUL8
 318 #define RCC_PLLMUL_12                    RCC_CFGR_PLLMUL12
 319 #define RCC_PLLMUL_16                    RCC_CFGR_PLLMUL16
 320 #define RCC_PLLMUL_24                    RCC_CFGR_PLLMUL24
 321 #define RCC_PLLMUL_32                    RCC_CFGR_PLLMUL32
 322 #define RCC_PLLMUL_48                    RCC_CFGR_PLLMUL48
 323 #define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLLMUL_3) || ((__MUL__) == RCC_PLLMUL_4) || \
 324                                  ((__MUL__) == RCC_PLLMUL_6) || ((__MUL__) == RCC_PLLMUL_8) || \
 325                                  ((__MUL__) == RCC_PLLMUL_12) || ((__MUL__) == RCC_PLLMUL_16) || \
 326                                  ((__MUL__) == RCC_PLLMUL_24) || ((__MUL__) == RCC_PLLMUL_32) || \
 327                                  ((__MUL__) == RCC_PLLMUL_48))
 328 /**
 329   * @}
 330   */
 331
 332 /** @defgroup RCC_PLLDivider_Factor RCC PLL Dividers
 333   * @{
 334   */
 335
 336 #define RCC_PLLDIV_2                     RCC_CFGR_PLLDIV2
 337 #define RCC_PLLDIV_3                     RCC_CFGR_PLLDIV3
 338 #define RCC_PLLDIV_4                     RCC_CFGR_PLLDIV4
 339 #define IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLLDIV_2) || ((__DIV__) == RCC_PLLDIV_3) || \
 340                                  ((__DIV__) == RCC_PLLDIV_4))
 341 /**
 342   * @}
 343   */
 344
 345 /** @defgroup RCC_System_Clock_Type RCC System Clock Type
 346   * @{
 347   */
 348 #define RCC_CLOCKTYPE_SYSCLK             ((uint32_t)0x00000001)
 349 #define RCC_CLOCKTYPE_HCLK               ((uint32_t)0x00000002)
 350 #define RCC_CLOCKTYPE_PCLK1              ((uint32_t)0x00000004)
 351 #define RCC_CLOCKTYPE_PCLK2              ((uint32_t)0x00000008)
 352
 353 #define IS_RCC_CLOCKTYPE(__CLK__) ((1 <= (__CLK__)) && ((__CLK__) <= 15))
 354 /**
 355   * @}
 356   */
 357
 358 /** @defgroup RCC_System_Clock_Source RCC System Clock Source
 359   * @{
 360   */
 361 #define RCC_SYSCLKSOURCE_MSI             RCC_CFGR_SW_MSI
 362 #define RCC_SYSCLKSOURCE_HSI             RCC_CFGR_SW_HSI
 363 #define RCC_SYSCLKSOURCE_HSE             RCC_CFGR_SW_HSE
 364 #define RCC_SYSCLKSOURCE_PLLCLK          RCC_CFGR_SW_PLL
 365
 366 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
 367                                          ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
 368                                          ((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \
 369                                          ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
 370 /**
 371   * @}
 372   */
 373
 374 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
 375   * @{
 376   */
 377 #define RCC_SYSCLKSOURCE_STATUS_HSI      RCC_CFGR_SWS_HSI
 378 #define RCC_SYSCLKSOURCE_STATUS_HSE      RCC_CFGR_SWS_HSE
 379 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK   RCC_CFGR_SWS_PLL
 380
 381 /**
 382   * @}
 383   */
 384
 385 /** @defgroup RCC_AHB_Clock_Source RCC AHB Clock SOurce
 386   * @{
 387   */
 388 #define RCC_SYSCLK_DIV1                  RCC_CFGR_HPRE_DIV1
 389 #define RCC_SYSCLK_DIV2                  RCC_CFGR_HPRE_DIV2
 390 #define RCC_SYSCLK_DIV4                  RCC_CFGR_HPRE_DIV4
 391 #define RCC_SYSCLK_DIV8                  RCC_CFGR_HPRE_DIV8
 392 #define RCC_SYSCLK_DIV16                 RCC_CFGR_HPRE_DIV16
 393 #define RCC_SYSCLK_DIV64                 RCC_CFGR_HPRE_DIV64
 394 #define RCC_SYSCLK_DIV128                RCC_CFGR_HPRE_DIV128
 395 #define RCC_SYSCLK_DIV256                RCC_CFGR_HPRE_DIV256
 396 #define RCC_SYSCLK_DIV512                RCC_CFGR_HPRE_DIV512
 397
 398 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1)   || ((__HCLK__) == RCC_SYSCLK_DIV2)   || \
 399                                ((__HCLK__) == RCC_SYSCLK_DIV4)   || ((__HCLK__) == RCC_SYSCLK_DIV8)   || \
 400                                ((__HCLK__) == RCC_SYSCLK_DIV16)  || ((__HCLK__) == RCC_SYSCLK_DIV64)  || \
 401                                ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
 402                                ((__HCLK__) == RCC_SYSCLK_DIV512))
 403 /**
 404   * @}
 405   */
 406
 407 /** @defgroup RCC_APB1_APB2_Clock_Source RCC APB1 Clock Source
 408   * @{
 409   */
 410 #define RCC_HCLK_DIV1                    RCC_CFGR_PPRE1_DIV1
 411 #define RCC_HCLK_DIV2                    RCC_CFGR_PPRE1_DIV2
 412 #define RCC_HCLK_DIV4                    RCC_CFGR_PPRE1_DIV4
 413 #define RCC_HCLK_DIV8                    RCC_CFGR_PPRE1_DIV8
 414 #define RCC_HCLK_DIV16                   RCC_CFGR_PPRE1_DIV16
 415
 416 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
 417                                ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
 418                                ((__PCLK__) == RCC_HCLK_DIV16))
 419 /**
 420   * @}
 421   */
 422
 423 /** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source
 424   * @{
 425   */
 426 #define RCC_RTCCLKSOURCE_NO_CLK          ((uint32_t)0x00000000)
 427 #define RCC_RTCCLKSOURCE_LSE             RCC_CSR_RTCSEL_LSE
 428 #define RCC_RTCCLKSOURCE_LSI             RCC_CSR_RTCSEL_LSI
 429 #define RCC_RTCCLKSOURCE_HSE_DIV2        RCC_CSR_RTCSEL_HSE
 430 #define RCC_RTCCLKSOURCE_HSE_DIV4        ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE_0)
 431 #define RCC_RTCCLKSOURCE_HSE_DIV8        ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE_1)
 432 #define RCC_RTCCLKSOURCE_HSE_DIV16       ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE)
 433 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
 434                                           ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
 435                                           ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || \
 436                                           ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || \
 437                                           ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || \
 438                                           ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16))
 439 /**
 440   * @}
 441   */
 442
 443 /** @defgroup RCC_MCO_Clock_Source RCC MCo Clock Source
 444   * @{
 445   */
 446
 447 #define RCC_MCO1SOURCE_NOCLOCK            RCC_CFGR_MCO_NOCLOCK
 448 #define RCC_MCO1SOURCE_SYSCLK             RCC_CFGR_MCO_SYSCLK
 449 #define RCC_MCO1SOURCE_HSI                RCC_CFGR_MCO_HSI
 450 #define RCC_MCO1SOURCE_MSI                RCC_CFGR_MCO_MSI
 451 #define RCC_MCO1SOURCE_HSE                RCC_CFGR_MCO_HSE
 452 #define RCC_MCO1SOURCE_PLLCLK             RCC_CFGR_MCO_PLL
 453 #define RCC_MCO1SOURCE_LSI                RCC_CFGR_MCO_LSI
 454 #define RCC_MCO1SOURCE_LSE                RCC_CFGR_MCO_LSE
 455 #if  !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx)  && !defined(STM32L081xx)
 456 #define RCC_MCO1SOURCE_HSI48              RCC_CFGR_MCO_HSI48
 457 #endif
 458
 459 #if  !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx)  && !defined(STM32L081xx)
 460 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
 461                                       ((__SOURCE__) == RCC_MCO1SOURCE_HSI)  || ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \
 462                                       ((__SOURCE__) == RCC_MCO1SOURCE_HSE)  || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
 463                                       ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \
 464                                       ((__SOURCE__) == RCC_MCO1SOURCE_HSI48))
 465 #else
 466 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
 467                                       ((__SOURCE__) == RCC_MCO1SOURCE_HSI)  || ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \
 468                                       ((__SOURCE__) == RCC_MCO1SOURCE_HSE)  || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
 469                                       ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || ((__SOURCE__) == RCC_MCO1SOURCE_LSE))
 470 #endif
 471
 472 /**
 473   * @}
 474   */
 475
 476 /** @defgroup RCC_MCOPrescaler RCC MCO Prescaler
 477   * @{
 478   */
 479
 480 #define RCC_MCODIV_1            RCC_CFGR_MCO_PRE_1
 481 #define RCC_MCODIV_2            RCC_CFGR_MCO_PRE_2
 482 #define RCC_MCODIV_4            RCC_CFGR_MCO_PRE_4
 483 #define RCC_MCODIV_8            RCC_CFGR_MCO_PRE_8
 484 #define RCC_MCODIV_16           RCC_CFGR_MCO_PRE_16
 485
 486 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1)  || \
 487                                 ((__DIV__) == RCC_MCODIV_2)  || \
 488                                 ((__DIV__) == RCC_MCODIV_4)  || \
 489                                 ((__DIV__) == RCC_MCODIV_8)  || \
 490                                 ((__DIV__) == RCC_MCODIV_16))
 491 /**
 492   * @}
 493   */
 494
 495 /** @defgroup RCC_MCO_Index RCC MCO Index
 496   * @{
 497   */
 498 #define RCC_MCO1                         ((uint32_t)0x00000000)
 499 #define RCC_MCO2                         ((uint32_t)0x00000001)
 500
 501 #define IS_RCC_MCO(__MCOx__) (((__MCOx__) == RCC_MCO1) || ((__MCOx__) == RCC_MCO2))
 502 /**
 503   * @}
 504   */
 505
 506 /** @defgroup RCC_Interrupt RCC Interruptions
 507   * @{
 508   */
 509 #define RCC_IT_LSIRDY                    RCC_CIFR_LSIRDYF
 510 #define RCC_IT_LSERDY                    RCC_CIFR_LSERDYF
 511 #define RCC_IT_HSIRDY                    RCC_CIFR_HSIRDYF
 512 #define RCC_IT_HSERDY                    RCC_CIFR_HSERDYF
 513 #define RCC_IT_PLLRDY                    RCC_CIFR_PLLRDYF
 514 #define RCC_IT_MSIRDY                    RCC_CIFR_MSIRDYF
 515
 516 #define RCC_IT_LSECSS                    RCC_CIFR_LSECSSF
 517 #define RCC_IT_CSS                       RCC_CIFR_CSSF
 518 #if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx)  && !defined(STM32L081xx)
 519 #define RCC_IT_HSI48RDY                  RCC_CIFR_HSI48RDYF
 520
 521 #define IS_RCC_IT(__IT__) (((__IT__) == RCC_IT_LSIRDY) || ((__IT__) == RCC_IT_LSERDY) || \
 522                            ((__IT__) == RCC_IT_HSIRDY) || ((__IT__) == RCC_IT_HSERDY) || \
 523                            ((__IT__) == RCC_IT_PLLRDY) || ((__IT__) == RCC_IT_MSIRDY) || \
 524                            ((__IT__) == RCC_IT_HSI48RDY)  || ((__IT__) == RCC_IT_LSECSS))
 525
 526 #define IS_RCC_GET_IT(__IT__) (((__IT__) == RCC_IT_LSIRDY) || ((__IT__) == RCC_IT_LSERDY) || \
 527                                ((__IT__) == RCC_IT_HSIRDY) || ((__IT__) == RCC_IT_HSERDY) || \
 528                                ((__IT__) == RCC_IT_PLLRDY) || ((__IT__) == RCC_IT_MSIRDY) || \
 529                                ((__IT__) == RCC_IT_CSS)    || ((__IT__) == RCC_IT_HSI48RDY) || \
 530                                ((__IT__) == RCC_IT_LSECSS))
 531
 532 #define IS_RCC_CLEAR_IT(__IT__) (((__IT__) == RCC_IT_LSIRDY) || ((__IT__) == RCC_IT_LSERDY) || \
 533                                  ((__IT__) == RCC_IT_HSIRDY) || ((__IT__) == RCC_IT_HSERDY) || \
 534                                  ((__IT__) == RCC_IT_PLLRDY) || ((__IT__) == RCC_IT_MSIRDY) || \
 535                                  ((__IT__) == RCC_IT_CSS)    || ((__IT__) == RCC_IT_HSI48RDY) || \
 536                                  ((__IT__) == RCC_IT_LSECSS))
 537 #else
 538 #define IS_RCC_IT(__IT__) (((__IT__) == RCC_IT_LSIRDY) || ((__IT__) == RCC_IT_LSERDY) || \
 539                            ((__IT__) == RCC_IT_HSIRDY) || ((__IT__) == RCC_IT_HSERDY) || \
 540                            ((__IT__) == RCC_IT_PLLRDY) || ((__IT__) == RCC_IT_MSIRDY) || \
 541                            ((__IT__) == RCC_IT_LSECSS))
 542
 543 #define IS_RCC_GET_IT(__IT__) (((__IT__) == RCC_IT_LSIRDY) || ((__IT__) == RCC_IT_LSERDY) || \
 544                                ((__IT__) == RCC_IT_HSIRDY) || ((__IT__) == RCC_IT_HSERDY) || \
 545                                ((__IT__) == RCC_IT_PLLRDY) || ((__IT__) == RCC_IT_MSIRDY) || \
 546                                ((__IT__) == RCC_IT_CSS)    ||  ((__IT__) == RCC_IT_LSECSS))
 547
 548
 549 #define IS_RCC_CLEAR_IT(__IT__) (((__IT__) == RCC_IT_LSIRDY) || ((__IT__) == RCC_IT_LSERDY) || \
 550                                  ((__IT__) == RCC_IT_HSIRDY) || ((__IT__) == RCC_IT_HSERDY) || \
 551                                  ((__IT__) == RCC_IT_PLLRDY) || ((__IT__) == RCC_IT_MSIRDY) || \
 552                                  ((__IT__) == RCC_IT_CSS)    || ((__IT__) == RCC_IT_LSECSS))
 553
 554 #endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx)  && !defined(STM32L081xx) */
 555 /**
 556   * @}
 557   */
 558
 559 /** @defgroup RCC_Flag
 560   *        Elements values convention: 0XXYYYYYb
 561   *           - YYYYY  : Flag position in the register
 562   *           - 0XX  : Register index
 563   *                 - 01: CR register
 564   *                 - 10: CSR register
 565   *                 - 11: CRRCR register
 566   * @{
 567   */
 568 /* Flags in the CR register */
 569 #define RCC_FLAG_HSIRDY                  ((uint8_t)0x22)
 570 #define RCC_FLAG_HSIDIV                  ((uint8_t)0x24)
 571 #define RCC_FLAG_MSIRDY                  ((uint8_t)0x29)
 572 #define RCC_FLAG_HSERDY                  ((uint8_t)0x31)
 573 #define RCC_FLAG_PLLRDY                  ((uint8_t)0x39)
 574
 575 /* Flags in the CSR register */
 576 #define RCC_FLAG_LSERDY                  ((uint8_t)0x49)
 577 #define RCC_FLAG_LSECSS                  ((uint8_t)0x4E)
 578 #define RCC_FLAG_LSIRDY                  ((uint8_t)0x41)
 579 #define RCC_FLAG_FWRST                   ((uint8_t)0x58)
 580 #define RCC_FLAG_OBLRST                  ((uint8_t)0x59)
 581 #define RCC_FLAG_PINRST                  ((uint8_t)0x5A)
 582 #define RCC_FLAG_PORRST                  ((uint8_t)0x5B)
 583 #define RCC_FLAG_SFTRST                  ((uint8_t)0x5C)
 584 #define RCC_FLAG_IWDGRST                 ((uint8_t)0x5D)
 585 #define RCC_FLAG_WWDGRST                 ((uint8_t)0x5E)
 586 #define RCC_FLAG_LPWRRST                 ((uint8_t)0x5F)
 587
 588 #if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx)  && !defined(STM32L081xx)
 589 /* Flags in the CRRCR register */
 590 #define RCC_FLAG_HSI48RDY                ((uint8_t)0x61)
 591 #endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx)  && !defined(STM32L081xx) */
 592
 593 #define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F)
 594 #define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0xFF)
 595
 596 /**
 597   * @}
 598   */
 599
 600 /**
 601   * @}
 602   */
 603 /* Exported macro ------------------------------------------------------------*/
 604 /** @defgroup RCC_Exported_Macros RCC Exported Macros
 605  * @{
 606  */
 607
 608 /** @brief  Enable or disable the AHB peripheral clock.
 609   * @note   After reset, the peripheral clock (used for registers read/write access)
 610   *         is disabled and the application software has to enable this clock before
 611   *         using it.
 612   */
 613 #define __HAL_RCC_DMA1_CLK_ENABLE()   do { \
 614                                         __IO uint32_t tmpreg; \
 615                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
 616                                         /* Delay after an RCC peripheral clock enabling */ \
 617                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
 618                                         UNUSED(tmpreg); \
 619                                       } while(0)
 620
 621 #define __HAL_RCC_MIF_CLK_ENABLE()   do { \
 622                                         __IO uint32_t tmpreg; \
 623                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN);\
 624                                         /* Delay after an RCC peripheral clock enabling */ \
 625                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN);\
 626                                         UNUSED(tmpreg); \
 627                                       } while(0)
 628
 629 #define __HAL_RCC_CRC_CLK_ENABLE()   do { \
 630                                         __IO uint32_t tmpreg; \
 631                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
 632                                         /* Delay after an RCC peripheral clock enabling */ \
 633                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
 634                                         UNUSED(tmpreg); \
 635                                       } while(0)
 636
 637
 638 #define __HAL_RCC_DMA1_CLK_DISABLE()          (RCC->AHBENR  &= ~ (RCC_AHBENR_DMA1EN))
 639 #define __HAL_RCC_MIF_CLK_DISABLE()           (RCC->AHBENR  &= ~ (RCC_AHBENR_MIFEN))
 640 #define __HAL_RCC_CRC_CLK_DISABLE()           (RCC->AHBENR  &= ~ (RCC_AHBENR_CRCEN))
 641
 642
 643 /** @brief  Enable or disable the IOPORT peripheral clock.
 644   * @note   After reset, the peripheral clock (used for registers read/write access)
 645   *         is disabled and the application software has to enable this clock before
 646   *         using it.
 647   */
 648 #define __HAL_RCC_GPIOA_CLK_ENABLE()   do { \
 649                                         __IO uint32_t tmpreg; \
 650                                         SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN);\
 651                                         /* Delay after an RCC peripheral clock enabling */ \
 652                                         tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN);\
 653                                         UNUSED(tmpreg); \
 654                                       } while(0)
 655
 656 #define __HAL_RCC_GPIOB_CLK_ENABLE()   do { \
 657                                         __IO uint32_t tmpreg; \
 658                                         SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN);\
 659                                         /* Delay after an RCC peripheral clock enabling */ \
 660                                         tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN);\
 661                                         UNUSED(tmpreg); \
 662                                       } while(0)
 663
 664 #define __HAL_RCC_GPIOC_CLK_ENABLE()   do { \
 665                                         __IO uint32_t tmpreg; \
 666                                         SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN);\
 667                                         /* Delay after an RCC peripheral clock enabling */ \
 668                                         tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN);\
 669                                         UNUSED(tmpreg); \
 670                                       } while(0)
 671
 672 #define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
 673                                         __IO uint32_t tmpreg; \
 674                                         SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN);\
 675                                         /* Delay after an RCC peripheral clock enabling */ \
 676                                         tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN);\
 677                                         UNUSED(tmpreg); \
 678                                       } while(0)
 679
 680 #define __HAL_RCC_GPIOH_CLK_ENABLE()   do { \
 681                                         __IO uint32_t tmpreg; \
 682                                         SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN);\
 683                                         /* Delay after an RCC peripheral clock enabling */ \
 684                                         tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN);\
 685                                         UNUSED(tmpreg); \
 686                                       } while(0)
 687
 688
 689 #define __HAL_RCC_GPIOA_CLK_DISABLE()        (RCC->IOPENR &= ~(RCC_IOPENR_GPIOAEN))
 690 #define __HAL_RCC_GPIOB_CLK_DISABLE()        (RCC->IOPENR &= ~(RCC_IOPENR_GPIOBEN))
 691 #define __HAL_RCC_GPIOC_CLK_DISABLE()        (RCC->IOPENR &= ~(RCC_IOPENR_GPIOCEN))
 692 #define __HAL_RCC_GPIOD_CLK_DISABLE()        (RCC->IOPENR &= ~(RCC_IOPENR_GPIODEN))
 693 #define __HAL_RCC_GPIOH_CLK_DISABLE()        (RCC->IOPENR &= ~(RCC_IOPENR_GPIOHEN))
 694
 695
 696 /** @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
 697   * @note   After reset, the peripheral clock (used for registers read/write access)
 698   *         is disabled and the application software has to enable this clock before
 699   *         using it.
 700   */
 701 #define __HAL_RCC_WWDG_CLK_ENABLE()    (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN))
 702 #define __HAL_RCC_PWR_CLK_ENABLE()     (RCC->APB1ENR |= (RCC_APB1ENR_PWREN))
 703
 704 #define __HAL_RCC_WWDG_CLK_DISABLE()    (RCC->APB1ENR &= ~ (RCC_APB1ENR_WWDGEN))
 705 #define __HAL_RCC_PWR_CLK_DISABLE()     (RCC->APB1ENR &= ~ (RCC_APB1ENR_PWREN))
 706
 707 /** @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
 708   * @note   After reset, the peripheral clock (used for registers read/write access)
 709   *         is disabled and the application software has to enable this clock before
 710   *         using it.
 711   */
 712 #define __HAL_RCC_SYSCFG_CLK_ENABLE()   (RCC->APB2ENR |= (RCC_APB2ENR_SYSCFGEN))
 713 #define __HAL_RCC_DBGMCU_CLK_ENABLE()   (RCC->APB2ENR |= (RCC_APB2ENR_DBGMCUEN))
 714
 715 #define __HAL_RCC_SYSCFG_CLK_DISABLE()   (RCC->APB2ENR &= ~  (RCC_APB2ENR_SYSCFGEN))
 716 #define __HAL_RCC_DBGMCU_CLK_DISABLE()   (RCC->APB2ENR &= ~  (RCC_APB2ENR_DBGMCUEN))
 717
 718 /** @brief  Force or release AHB peripheral reset.
 719   */
 720 #define __HAL_RCC_AHB_FORCE_RESET()     (RCC->AHBRSTR = 0xFFFFFFFF)
 721 #define __HAL_RCC_DMA1_FORCE_RESET()    (RCC->AHBRSTR |= (RCC_AHBRSTR_DMA1RST))
 722 #define __HAL_RCC_MIF_FORCE_RESET()     (RCC->AHBRSTR |= (RCC_AHBRSTR_MIFRST))
 723 #define __HAL_RCC_CRC_FORCE_RESET()     (RCC->AHBRSTR |= (RCC_AHBRSTR_CRCRST))
 724
 725 #define __HAL_RCC_AHB_RELEASE_RESET()     (RCC->AHBRSTR = 0x00)
 726 #define __HAL_RCC_CRC_RELEASE_RESET()     (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_CRCRST))
 727 #define __HAL_RCC_DMA1_RELEASE_RESET()    (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_DMA1RST))
 728 #define __HAL_RCC_MIF_RELEASE_RESET()     (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_MIFRST))
 729
 730
 731 /** @brief  Force or release IOPORT peripheral reset.
 732   */
 733 #define __HAL_RCC_IOP_FORCE_RESET()     (RCC->IOPRSTR = 0xFFFFFFFF)
 734 #define __HAL_RCC_GPIOA_FORCE_RESET()   (RCC->IOPRSTR |= (RCC_IOPRSTR_GPIOARST))
 735 #define __HAL_RCC_GPIOB_FORCE_RESET()   (RCC->IOPRSTR |= (RCC_IOPRSTR_GPIOBRST))
 736 #define __HAL_RCC_GPIOC_FORCE_RESET()   (RCC->IOPRSTR |= (RCC_IOPRSTR_GPIOCRST))
 737 #define __HAL_RCC_GPIOD_FORCE_RESET()   (RCC->IOPRSTR |= (RCC_IOPRSTR_GPIODRST))
 738 #define __HAL_RCC_GPIOH_FORCE_RESET()   (RCC->IOPRSTR |= (RCC_IOPRSTR_GPIOHRST))
 739
 740 #define __HAL_RCC_IOP_RELEASE_RESET()   (RCC->IOPRSTR = 0x00)
 741 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOARST))
 742 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOBRST))
 743 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOCRST))
 744 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIODRST))
 745 #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOHRST))
 746
 747 /** @brief  Force or release APB1 peripheral reset.
 748   */
 749 #define __HAL_RCC_APB1_FORCE_RESET()     (RCC->APB1RSTR = 0xFFFFFFFF)
 750 #define __HAL_RCC_WWDG_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
 751 #define __HAL_RCC_PWR_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
 752
 753 #define __HAL_RCC_APB1_RELEASE_RESET()   (RCC->APB1RSTR = 0x00)
 754 #define __HAL_RCC_WWDG_RELEASE_RESET()   (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_WWDGRST))
 755 #define __HAL_RCC_PWR_RELEASE_RESET()    (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_PWRRST))
 756
 757 /** @brief  Force or release APB2 peripheral reset.
 758   */
 759 #define __HAL_RCC_APB2_FORCE_RESET()     (RCC->APB2RSTR = 0xFFFFFFFF)
 760 #define __HAL_RCC_DBGMCU_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_DBGMCURST))
 761 #define __HAL_RCC_SYSCFG_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
 762
 763 #define __HAL_RCC_APB2_RELEASE_RESET()   (RCC->APB2RSTR = 0x00)
 764 #define __HAL_RCC_DBGMCU_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_DBGMCURST))
 765 #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_SYSCFGRST))
 766
 767 /** @brief  Enable or disable the AHB peripheral clock during Low Power (Sleep) mode.
 768   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
 769   *         power consumption.
 770   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
 771   * @note   By default, all peripheral activated clocks remain enabled during SLEEP mode.
 772   */
 773 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()      (RCC->AHBSMENR |= (RCC_AHBSMENR_CRCSMEN))
 774 #define __HAL_RCC_MIF_CLK_SLEEP_ENABLE()      (RCC->AHBSMENR |= (RCC_AHBSMENR_MIFSMEN))
 775 #define __HAL_RCC_SRAM_CLK_SLEEP_ENABLE()     (RCC->AHBSMENR |= (RCC_AHBSMENR_SRAMSMEN))
 776 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE()     (RCC->AHBSMENR |= (RCC_AHBSMENR_DMA1SMEN))
 777
 778 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()     (RCC->AHBSMENR  &= ~ (RCC_AHBSMENR_CRCSMEN))
 779 #define __HAL_RCC_MIF_CLK_SLEEP_DISABLE()     (RCC->AHBSMENR  &= ~ (RCC_AHBSMENR_MIFSMEN))
 780 #define __HAL_RCC_SRAM_CLK_SLEEP_DISABLE()    (RCC->AHBSMENR  &= ~ (RCC_AHBSMENR_SRAMSMEN))
 781 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE()    (RCC->AHBSMENR  &= ~ (RCC_AHBSMENR_DMA1SMEN))
 782
 783 /** @brief  Enable or disable the IOPORT peripheral clock during Low Power (Sleep) mode.
 784   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
 785   *         power consumption.
 786   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
 787   * @note   By default, all peripheral activated clocks remain enabled during SLEEP mode.
 788   */
 789
 790 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE()    (RCC->IOPSMENR |= (RCC_IOPSMENR_GPIOASMEN))
 791 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE()    (RCC->IOPSMENR |= (RCC_IOPSMENR_GPIOBSMEN))
 792 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE()    (RCC->IOPSMENR |= (RCC_IOPSMENR_GPIOCSMEN))
 793 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()    (RCC->IOPSMENR |= (RCC_IOPSMENR_GPIODSMEN))
 794 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE()    (RCC->IOPSMENR |= (RCC_IOPSMENR_GPIOHSMEN))
 795
 796 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE()   (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOASMEN))
 797 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE()   (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOBSMEN))
 798 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE()   (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOCSMEN))
 799 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()   (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIODSMEN))
 800 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE()   (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOHSMEN))
 801
 802 /** @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
 803   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
 804   *         power consumption.
 805   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
 806   * @note   By default, all peripheral activated clocks remain enabled during SLEEP mode.
 807   */
 808 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE()    (RCC->APB1SMENR |= (RCC_APB1SMENR_WWDGSMEN))
 809 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE()     (RCC->APB1SMENR |= (RCC_APB1SMENR_PWRSMEN))
 810
 811 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE()   (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_WWDGSMEN))
 812 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE()    (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_PWRSMEN))
 813
 814 /** @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
 815   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
 816   *         power consumption.
 817   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
 818   * @note   By default, all peripheral actiated clocks remain enabled during SLEEP mode.
 819   */
 820 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE()   (RCC->APB2SMENR |= (RCC_APB2SMENR_SYSCFGSMEN))
 821 #define __HAL_RCC_DBGMCU_CLK_SLEEP_ENABLE()   (RCC->APB2SMENR |= (RCC_APB2SMENR_DBGMCUSMEN))
 822
 823 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE()   (RCC->APB2SMENR &= ~  (RCC_APB2SMENR_SYSCFGSMEN))
 824 #define __HAL_RCC_DBGMCU_CLK_SLEEP_DISABLE()   (RCC->APB2SMENR &= ~  (RCC_APB2SMENR_DBGMCUSMEN))
 825
 826 /** @brief  Macro to enable or disable the Internal High Speed oscillator (HSI).
 827   * @note     After enabling the HSI, the application software should wait on
 828   *           HSIRDY flag to be set indicating that HSI clock is stable and can
 829   *           be used to clock the PLL and/or system clock.
 830   * @note     HSI can not be stopped if it is used directly or through the PLL
 831   *           as system clock. In this case, you have to select another source
 832   *           of the system clock then stop the HSI.
 833   * @note     The HSI is stopped by hardware when entering STOP and STANDBY modes.
 834   * @param    __STATE__: specifies the new state of the HSI.
 835   *           This parameter can be one of the following values:
 836   *            @arg RCC_HSI_OFF: turn OFF the HSI oscillator
 837   *            @arg RCC_HSI_ON: turn ON the HSI oscillator
 838   *            @arg RCC_HSI_DIV4: turn ON the HSI oscillator and divide it by 4
 839   * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
 840   *         clock cycles.
 841   */
 842 #define __HAL_RCC_HSI_CONFIG(__STATE__) \
 843                   MODIFY_REG(RCC->CR, RCC_CR_HSION | RCC_CR_HSIDIVEN , (uint32_t)(__STATE__))
 844
 845 /** @brief  Macros to enable or disable the Internal High Speed oscillator (HSI).
 846   * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.
 847   *         It is used (enabled by hardware) as system clock source after startup
 848   *         from Reset, wakeup from STOP and STANDBY mode, or in case of failure
 849   *         of the HSE used directly or indirectly as system clock (if the Clock
 850   *         Security System CSS is enabled).
 851   * @note   HSI can not be stopped if it is used as system clock source. In this case,
 852   *         you have to select another source of the system clock then stop the HSI.
 853   * @note   After enabling the HSI, the application software should wait on HSIRDY
 854   *         flag to be set indicating that HSI clock is stable and can be used as
 855   *         system clock source.
 856   * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
 857   *         clock cycles.
 858   */
 859 #define __HAL_RCC_HSI_ENABLE()  SET_BIT(RCC->CR, RCC_CR_HSION)
 860 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
 861
 862 /**
 863   * @brief  Macros to enable or disable the Internal Multi Speed oscillator (MSI).
 864   * @note     The MSI is stopped by hardware when entering STOP and STANDBY modes.
 865   *           It is used (enabled by hardware) as system clock source after
 866   *           startup from Reset, wakeup from STOP and STANDBY mode, or in case
 867   *           of failure of the HSE used directly or indirectly as system clock
 868   *           (if the Clock Security System CSS is enabled).
 869   * @note     MSI can not be stopped if it is used as system clock source.
 870   *           In this case, you have to select another source of the system
 871   *           clock then stop the MSI.
 872   * @note     After enabling the MSI, the application software should wait on
 873   *           MSIRDY flag to be set indicating that MSI clock is stable and can
 874   *           be used as system clock source.
 875   * @note   When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator
 876   *         clock cycles.
 877   */
 878 #define __HAL_RCC_MSI_ENABLE()  SET_BIT(RCC->CR, RCC_CR_MSION)
 879 #define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION)
 880
 881 /** @brief  Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
 882   * @note   The calibration is used to compensate for the variations in voltage
 883   *         and temperature that influence the frequency of the internal HSI RC.
 884   * @param  __HSICalibrationValue__: specifies the calibration trimming value.
 885   *         This parameter must be a number between 0 and 0x1F.
 886   */
 887 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->ICSCR,\
 888         RCC_ICSCR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << 8))
 889
 890 /** @brief  Macro Adjusts the Internal Multi Speed oscillator (MSI) calibration value.
 891   * @note   The calibration is used to compensate for the variations in voltage
 892   *         and temperature that influence the frequency of the internal MSI RC.
 893   *         Refer to the Application Note AN3300 for more details on how to
 894   *         calibrate the MSI.
 895   * @param  __MSICalibrationValue__: specifies the calibration trimming value.
 896   *         This parameter must be a number between 0 and 0xFF.
 897   */
 898 #define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICalibrationValue__) (MODIFY_REG(RCC->ICSCR,\
 899         RCC_ICSCR_MSITRIM, (uint32_t)(__MSICalibrationValue__) << 24))
 900
 901 /**
 902   * @brief  Macro to configures the Internal Multi Speed oscillator (MSI) clock range.
 903   * @note     After restart from Reset or wakeup from STANDBY, the MSI clock is
 904   *           around 2.097 MHz. The MSI clock does not change after wake-up from
 905   *           STOP mode.
 906   * @note    The MSI clock range can be modified on the fly.
 907   * @param  RCC_MSIRange: specifies the MSI Clock range.
 908   *   This parameter must be one of the following values:
 909   *     @arg RCC_MSIRANGE_0: MSI clock is around 65.536 KHz
 910   *     @arg RCC_MSIRANGE_1: MSI clock is around 131.072 KHz
 911   *     @arg RCC_MSIRANGE_2: MSI clock is around 262.144 KHz
 912   *     @arg RCC_MSIRANGE_3: MSI clock is around 524.288 KHz
 913   *     @arg RCC_MSIRANGE_4: MSI clock is around 1.048 MHz
 914   *     @arg RCC_MSIRANGE_5: MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)
 915   *     @arg RCC_MSIRANGE_6: MSI clock is around 4.194 MHz
 916   */
 917 #define __HAL_RCC_MSI_RANGE_CONFIG(__RCC_MSIRange__) (MODIFY_REG(RCC->ICSCR,\
 918         RCC_ICSCR_MSIRANGE, (uint32_t)(__RCC_MSIRange__) ))
 919
 920 /** @brief  Macros to enable or disable the Internal Low Speed oscillator (LSI).
 921   * @note   After enabling the LSI, the application software should wait on
 922   *         LSIRDY flag to be set indicating that LSI clock is stable and can
 923   *         be used to clock the IWDG and/or the RTC.
 924   * @note   LSI can not be disabled if the IWDG is running.
 925   * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
 926   *         clock cycles.
 927   */
 928 #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
 929 #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
 930
 931 /**
 932   * @brief  Macro to configure the External High Speed oscillator (HSE).
 933   * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
 934   *         software should wait on HSERDY flag to be set indicating that HSE clock
 935   *         is stable and can be used to clock the PLL and/or system clock.
 936   * @note   HSE state can not be changed if it is used directly or through the
 937   *         PLL as system clock. In this case, you have to select another source
 938   *         of the system clock then change the HSE state (ex. disable it).
 939   * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.
 940   * @note   This function reset the CSSON bit, so if the clock security system(CSS)
 941   *         was previously enabled you have to enable it again after calling this
 942   *         function.
 943   * @param  __STATE__: specifies the new state of the HSE.
 944   *         This parameter can be one of the following values:
 945   *            @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
 946   *                              6 HSE oscillator clock cycles.
 947   *            @arg RCC_HSE_ON: turn ON the HSE oscillator.
 948   *            @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
 949   */
 950 #define __HAL_RCC_HSE_CONFIG(__STATE__) \
 951                     do {                                     \
 952                       CLEAR_BIT(RCC->CR, RCC_CR_HSEON);      \
 953                       if((__STATE__) == RCC_HSE_ON)          \
 954                       {                                      \
 955                         CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);   \
 956                         SET_BIT(RCC->CR, RCC_CR_HSEON);      \
 957                       }                                      \
 958                       else if((__STATE__) == RCC_HSE_BYPASS) \
 959                       {                                      \
 960                         SET_BIT(RCC->CR, RCC_CR_HSEBYP);     \
 961                         SET_BIT(RCC->CR, RCC_CR_HSEON);      \
 962                       }                                      \
 963                       else                                   \
 964                       {                                      \
 965                         CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);   \
 966                       }                                      \
 967                     } while(0)
 968
 969 /**
 970   * @brief  Macro to configure the External Low Speed oscillator (LSE).
 971   * @note   As the LSE is in the Backup domain and write access is denied to
 972   *         this domain after reset, you have to enable write access using
 973   *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE
 974   *         (to be done once after reset).
 975   * @note   After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
 976   *         software should wait on LSERDY flag to be set indicating that LSE clock
 977   *         is stable and can be used to clock the RTC.
 978   * @param  __STATE__: specifies the new state of the LSE.
 979   *         This parameter can be one of the following values:
 980   *            @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
 981   *                              6 LSE oscillator clock cycles.
 982   *            @arg RCC_LSE_ON: turn ON the LSE oscillator.
 983   *            @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
 984   */
 985 #define __HAL_RCC_LSE_CONFIG(__STATE__) \
 986                     do {                                       \
 987                       if((__STATE__) == RCC_LSE_ON)            \
 988                       {                                        \
 989                         SET_BIT(RCC->CSR, RCC_CSR_LSEON);      \
 990                       }                                        \
 991                       else if((__STATE__) == RCC_LSE_OFF)      \
 992                       {                                        \
 993                         CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON);    \
 994                       }                                        \
 995                       else if((__STATE__) == RCC_LSE_BYPASS)   \
 996                       {                                        \
 997                         CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON);    \
 998                         SET_BIT(RCC->CSR, RCC_CSR_LSEBYP);     \
 999                         SET_BIT(RCC->CSR, RCC_CSR_LSEON);      \
1000                       }                                        \
1001                       else                                     \
1002                       {                                        \
1003                         CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON);    \
1004                         CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP);   \
1005                       }                                        \
1006                     } while(0)
1007
1008 /** @brief  Macros to enable or disable the the RTC clock.
1009   * @note   These macros must be used only after the RTC clock source was selected.
1010   */
1011 #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_RTCEN)
1012 #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_RTCEN)
1013
1014 /**
1015   * @brief  Configures  or  Get the RTC and LCD clock (RTCCLK / LCDCLK).
1016   * @note     As the RTC clock configuration bits are in the RTC domain and write
1017   *           access is denied to this domain after reset, you have to enable write
1018   *           access using PWR_RTCAccessCmd(ENABLE) function before to configure
1019   *           the RTC clock source (to be done once after reset).
1020   * @note     Once the RTC clock is configured it cannot be changed unless the RTC
1021   *           is reset using RCC_RTCResetCmd function, or by a Power On Reset (POR)
1022   * @note     The RTC clock (RTCCLK) is used also to clock the LCD (LCDCLK).
1023   *
1024   * @param  RCC_RTCCLKSource: specifies the RTC clock source.
1025   *   This parameter can be one of the following values:
1026   *     @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
1027   *     @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
1028   *     @arg RCC_RTCCLKSOURCE_HSE_DIV2: HSE divided by 2 selected as RTC clock
1029   *     @arg RCC_RTCCLKSOURCE_HSE_DIV4: HSE divided by 4 selected as RTC clock
1030   *     @arg RCC_RTCCLKSOURCE_HSE_DIV8: HSE divided by 8 selected as RTC clock
1031   *     @arg RCC_RTCCLKSOURCE_HSE_DIV16: HSE divided by 16 selected as RTC clock
1032   *
1033   * @note     If the LSE or LSI is used as RTC clock source, the RTC continues to
1034   *           work in STOP and STANDBY modes, and can be used as wakeup source.
1035   *           However, when the HSE clock is used as RTC clock source, the RTC
1036   *           cannot be used in STOP and STANDBY modes.
1037   * @note     The maximum input clock frequency for RTC is 1MHz (when using HSE as
1038   *           RTC clock source).
1039   */
1040 #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_CSR_RTCSEL) == RCC_CSR_RTCSEL) ?    \
1041                                                  MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, ((__RTCCLKSource__) & 0xFFFCFFFF)) : CLEAR_BIT(RCC->CR, RCC_CR_RTCPRE)
1042
1043 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__);    \
1044                                                    MODIFY_REG( RCC->CSR, RCC_CSR_RTCSEL, (uint32_t)(__RTCCLKSource__));  \
1045                                                    } while (0)
1046
1047 #define  __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_RTCSEL)))
1048
1049 /** @brief  Macros to force or release the Backup domain reset.
1050   * @note   This function resets the RTC peripheral (including the backup registers)
1051   *         and the RTC clock source selection in RCC_CSR register.
1052   * @note   The BKPSRAM is not affected by this reset.
1053   */
1054 #define __HAL_RCC_BACKUPRESET_FORCE()  SET_BIT(RCC->CSR, RCC_CSR_RTCRST)
1055 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->CSR, RCC_CSR_RTCRST)
1056
1057 /** @brief  Macros to enable or disable the main PLL.
1058   * @note   After enabling the main PLL, the application software should wait on
1059   *         PLLRDY flag to be set indicating that PLL clock is stable and can
1060   *         be used as system clock source.
1061   * @note   The main PLL can not be disabled if it is used as system clock source
1062   * @note   The main PLL is disabled by hardware when entering STOP and STANDBY modes.
1063   */
1064 #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
1065 #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
1066
1067 /** @brief  Macro to configure the main PLL clock source, multiplication and division factors.
1068   * @note   This function must be used only when the main PLL is disabled.
1069   * @param  __RCC_PLLSource__: specifies the PLL entry clock source.
1070   *         This parameter can be one of the following values:
1071   *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
1072   *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
1073   * @param  __PLLMUL__: specifies the multiplication factor to generate the PLL VCO clock
1074   *         This parameter must be one of the following values:
1075   *            @arg RCC_CFGR_PLLMUL3: PLLVCO = PLL clock entry x 3
1076   *            @arg RCC_CFGR_PLLMUL4: PLLVCO = PLL clock entry x 4
1077   *            @arg RCC_CFGR_PLLMUL6: PLLVCO = PLL clock entry x 6
1078   *            @arg RCC_CFGR_PLLMUL8: PLLVCO = PLL clock entry x 8
1079   *            @arg RCC_CFGR_PLLMUL12: PLLVCO = PLL clock entry x 12
1080   *            @arg RCC_CFGR_PLLMUL16: PLLVCO = PLL clock entry x 16
1081   *            @arg RCC_CFGR_PLLMUL24: PLLVCO = PLL clock entry x 24
1082   *            @arg RCC_CFGR_PLLMUL32: PLLVCO = PLL clock entry x 32
1083   *            @arg RCC_CFGR_PLLMUL48: PLLVCO = PLL clock entry x 48
1084   * @note   The PLL VCO clock frequency must not exceed 96 MHz when the product is in
1085   *         Range 1, 48 MHz when the product is in Range 2 and 24 MHz when the product is
1086   *         in Range 3.
1087   * @param  __PLLDIV__: specifies the PLL output clock division from PLL VCO clock
1088   *         This parameter must be one of the following values:
1089   *            @arg RCC_PLLDIV_2: PLL clock output = PLLVCO / 2
1090   *            @arg RCC_PLLDIV_3: PLL clock output = PLLVCO / 3
1091   *            @arg RCC_PLLDIV_4: PLL clock output = PLLVCO / 4
1092   */
1093
1094 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PLLMUL__ ,__PLLDIV__ ) \
1095             MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLDIV | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)| (__PLLDIV__)| (__RCC_PLLSource__)))
1096
1097 /** @brief  Macro to get the clock source used as system clock.
1098   * @retval The clock source used as system clock. The returned value can be one
1099   *         of the following:
1100   *              - RCC_CFGR_SWS_HSI: HSI used as system clock.
1101   *              - RCC_CFGR_SWS_HSE: HSE used as system clock.
1102   *              - RCC_CFGR_SWS_PLL: PLL used as system clock.
1103   */
1104 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
1105
1106 /** @brief  Macro to get the oscillator used as PLL clock source.
1107   * @retval The oscillator used as PLL clock source. The returned value can be one
1108   *         of the following:
1109   *              - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
1110   *              - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
1111   */
1112 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC))
1113
1114 /** @defgroup RCC_Flags_Interrupts_Management
1115   * @brief macros to manage the specified RCC Flags and interrupts.
1116   * @{
1117   */
1118
1119 /** @brief  Enable RCC interrupt (Perform Byte access to RCC_CIER[0:7] bits to enable
1120   *         the selected interrupts).
1121   * @note   The CSS interrupt doesn't have an enable bit; once the CSS is enabled
1122   *         and if the HSE clock fails, the CSS interrupt occurs and an NMI is
1123   *         automatically generated. The NMI will be executed indefinitely, and
1124   *         since NMI has higher priority than any other IRQ (and main program)
1125   *         the application will be stacked in the NMI ISR unless the CSS interrupt
1126   *         pending bit is cleared.
1127   * @param  __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
1128   *         This parameter can be any combination of the following values:
1129   *     @arg RCC_IT_LSIRDY: LSI ready interrupt
1130   *     @arg RCC_IT_LSERDY: LSE ready interrupt
1131   *     @arg RCC_IT_HSIRDY: HSI ready interrupt
1132   *     @arg RCC_IT_HSERDY: HSE ready interrupt
1133   *     @arg RCC_IT_PLLRDY: PLL ready interrupt
1134   *     @arg RCC_IT_MSIRDY: MSI ready interrupt
1135   *     @arg RCC_IT_LSECSS: LSE CSS interrupt
1136   *     @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
1137   */
1138 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (RCC->CIER |= (__INTERRUPT__))
1139
1140 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIER[0:7] bits to disable
1141   *        the selected interrupts).
1142   * @note   The CSS interrupt doesn't have an enable bit; once the CSS is enabled
1143   *         and if the HSE clock fails, the CSS interrupt occurs and an NMI is
1144   *         automatically generated. The NMI will be executed indefinitely, and
1145   *         since NMI has higher priority than any other IRQ (and main program)
1146   *         the application will be stacked in the NMI ISR unless the CSS interrupt
1147   *         pending bit is cleared.
1148   * @param  __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
1149   *         This parameter can be any combination of the following values:
1150   *     @arg RCC_IT_LSIRDY: LSI ready interrupt
1151   *     @arg RCC_IT_LSERDY: LSE ready interrupt
1152   *     @arg RCC_IT_HSIRDY: HSI ready interrupt
1153   *     @arg RCC_IT_HSERDY: HSE ready interrupt
1154   *     @arg RCC_IT_PLLRDY: PLL ready interrupt
1155   *     @arg RCC_IT_MSIRDY: MSI ready interrupt
1156   *     @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
1157   *     @arg RCC_IT_LSECSS: LSE CSS interrupt
1158
1159   */
1160 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (RCC->CIER &= ~(__INTERRUPT__))
1161
1162 /** @brief  Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
1163   *         bits to clear the selected interrupt pending bits.
1164   * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
1165   *         This parameter can be any combination of the following values:
1166   *     @arg RCC_IT_LSIRDY: LSI ready interrupt
1167   *     @arg RCC_IT_LSERDY: LSE ready interrupt
1168   *     @arg RCC_IT_HSIRDY: HSI ready interrupt
1169   *     @arg RCC_IT_HSERDY: HSE ready interrupt
1170   *     @arg RCC_IT_PLLRDY: PLL ready interrupt
1171   *     @arg RCC_IT_MSIRDY: MSI ready interrupt
1172   *     @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
1173   *     @arg RCC_IT_LSECSS: LSE CSS interrupt
1174   *     @arg RCC_IT_CSS: Clock Security System interrupt
1175   */
1176  #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
1177
1178 /** @brief  Check the RCC's interrupt has occurred or not.
1179   * @param  __INTERRUPT__: specifies the RCC interrupt source to check.
1180   *         This parameter can be one of the following values:
1181   *     @arg RCC_IT_LSIRDY: LSI ready interrupt
1182   *     @arg RCC_IT_LSERDY: LSE ready interrupt
1183   *     @arg RCC_IT_HSIRDY: HSI ready interrupt
1184   *     @arg RCC_IT_HSERDY: HSE ready interrupt
1185   *     @arg RCC_IT_PLLRDY: PLL ready interrupt
1186   *     @arg RCC_IT_MSIRDY: MSI ready interrupt
1187   *     @arg RCC_IT_LSECSS: LSE CSS interrupt
1188   *     @arg RCC_IT_CSS: Clock Security System interrupt
1189   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
1190   */
1191 #define __HAL_RCC_GET_IT_SOURCE(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
1192
1193 /** @brief Set RMVF bit to clear the reset flags.
1194   *         The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST,
1195   *         RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.
1196   */
1197 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
1198
1199 /** @brief  Check RCC flag is set or not.
1200   * @param  __FLAG__: specifies the flag to check.
1201   *         This parameter can be one of the following values:
1202   *     @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
1203   *     @arg RCC_FLAG_MSIRDY: MSI oscillator clock ready
1204   *     @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
1205   *     @arg RCC_FLAG_PLLRDY: PLL clock ready
1206   *     @arg RCC_FLAG_LSECSS: LSE oscillator clock CSS detected
1207   *     @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
1208   *     @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
1209   *     @arg RCC_FLAG_FWRST: Firewall reset
1210   *     @arg RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset
1211   *     @arg RCC_FLAG_PINRST: Pin reset
1212   *     @arg RCC_FLAG_PORRST: POR/PDR reset
1213   *     @arg RCC_FLAG_SFTRST: Software reset
1214   *     @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
1215   *     @arg RCC_FLAG_WWDGRST: Window Watchdog reset
1216   *     @arg RCC_FLAG_LPWRRST: Low Power reset
1217   * @retval The new state of __FLAG__ (TRUE or FALSE).
1218   */
1219 #define RCC_FLAG_MASK  ((uint8_t)0x1F)
1220 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->CSR :((((__FLAG__) >> 5) == 3)? \
1221               RCC->CRRCR :RCC->CIFR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) != 0 ) ? 1 : 0 )
1222
1223 /**
1224   * @}
1225   */
1226
1227 /**
1228  * @}
1229  */
1230
1231 /* Include RCC HAL Extension module */
1232 #include "stm32l0xx_hal_rcc_ex.h"
1233
1234 /** @defgroup RCC_Exported_Functions RCC Exported Functions
1235   * @{
1236   */
1237
1238 /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
1239   * @{
1240   */
1241 void HAL_RCC_DeInit(void);
1242 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
1243 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
1244 /**
1245   * @}
1246   */
1247
1248 /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
1249   * @{
1250   */
1251 void     HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
1252 void     HAL_RCC_EnableCSS(void);
1253 uint32_t HAL_RCC_GetSysClockFreq(void);
1254 uint32_t HAL_RCC_GetHCLKFreq(void);
1255 uint32_t HAL_RCC_GetPCLK1Freq(void);
1256 uint32_t HAL_RCC_GetPCLK2Freq(void);
1257 void     HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
1258 void     HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
1259 /* CSS NMI IRQ handler */
1260 void HAL_RCC_NMI_IRQHandler(void);
1261
1262 /* User Callbacks in non blocking mode (IT mode) */
1263 void HAL_RCC_CSSCallback(void);
1264 /**
1265   * @}
1266   */
1267
1268 /**
1269   * @}
1270   */
1271
1272 /**
1273   * @}
1274   */
1275
1276 /**
1277   * @}
1278   */
1279
1280 #ifdef __cplusplus
1281 }
1282 #endif
1283
1284 #endif /* __STM32l0xx_HAL_RCC_H */
1285
1286 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1287