tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_smbus.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32l0xx_hal_smbus.h
   4   * @author  MCD Application Team
   5   * @version V1.2.0
   6   * @date    06-February-2015
   7   * @brief   Header file of SMBUS HAL module.
   8   ******************************************************************************
   9   * @attention
  10   *
  11   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
  12   *
  13   * Redistribution and use in source and binary forms, with or without modification,
  14   * are permitted provided that the following conditions are met:
  15   *   1. Redistributions of source code must retain the above copyright notice,
  16   *      this list of conditions and the following disclaimer.
  17   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18   *      this list of conditions and the following disclaimer in the documentation
  19   *      and/or other materials provided with the distribution.
  20   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21   *      may be used to endorse or promote products derived from this software
  22   *      without specific prior written permission.
  23   *
  24   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34   *
  35   ******************************************************************************
  36   */
  37
  38 /* Define to prevent recursive inclusion -------------------------------------*/
  39 #ifndef __STM32L0xx_HAL_SMBUS_H
  40 #define __STM32L0xx_HAL_SMBUS_H
  41
  42 #ifdef __cplusplus
  43  extern "C" {
  44 #endif
  45
  46 /* Includes ------------------------------------------------------------------*/
  47 #include "stm32l0xx_hal_def.h"
  48
  49 /** @addtogroup STM32L0xx_HAL_Driver
  50   * @{
  51   */
  52
  53 /** @addtogroup SMBUS
  54   * @{
  55   */
  56
  57 /* Exported types ------------------------------------------------------------*/
  58
  59 /**
  60   * @brief  SMBUS Configuration Structure definition
  61   */
  62 typedef struct
  63 {
  64   uint32_t Timing;                 /*!< Specifies the SMBUS_TIMINGR_register value.
  65                                         This parameter calculated by referring to SMBUS initialization
  66                                         section in Reference manual */
  67
  68   uint32_t AnalogFilter;           /*!< Specifies if Analog Filter is enable or not.
  69                                      This parameter can be a a value of @ref SMBUS_Analog_Filter */
  70
  71   uint32_t OwnAddress1;            /*!< Specifies the first device own address.
  72                                      This parameter can be a 7-bit or 10-bit address. */
  73
  74   uint32_t AddressingMode;         /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected.
  75                                      This parameter can be a value of @ref SMBUS_addressing_mode */
  76
  77   uint32_t DualAddressMode;        /*!< Specifies if dual addressing mode is selected.
  78                                      This parameter can be a value of @ref SMBUS_dual_addressing_mode */
  79
  80   uint32_t OwnAddress2;            /*!< Specifies the second device own address if dual addressing mode is selected
  81                                      This parameter can be a 7-bit address. */
  82
  83   uint32_t OwnAddress2Masks;       /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected
  84                                      This parameter can be a value of @ref SMBUS_own_address2_masks */
  85
  86   uint32_t GeneralCallMode;        /*!< Specifies if general call mode is selected.
  87                                      This parameter can be a value of @ref SMBUS_general_call_addressing_mode */
  88
  89   uint32_t NoStretchMode;          /*!< Specifies if nostretch mode is selected.
  90                                      This parameter can be a value of @ref SMBUS_nostretch_mode */
  91
  92   uint32_t PacketErrorCheckMode;   /*!< Specifies if Packet Error Check mode is selected.
  93                                      This parameter can be a value of @ref SMBUS_packet_error_check_mode */
  94
  95   uint32_t PeripheralMode;         /*!< Specifies which mode of Periphal is selected.
  96                                      This parameter can be a value of @ref SMBUS_peripheral_mode */
  97
  98   uint32_t SMBusTimeout;           /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value.
  99                                      (Enable bits and different timeout values)
 100                                      This parameter calculated by referring to SMBUS initialization
 101                                          section in Reference manual */
 102 } SMBUS_InitTypeDef;
 103
 104 /** @defgroup SMBUS_State SMBUS State
 105   * @brief  HAL States definition
 106    * @{
 107    */
 108
 109 #define  HAL_SMBUS_STATE_RESET           0x00  /*!< SMBUS not yet initialized or disabled         */
 110 #define  HAL_SMBUS_STATE_READY           0x01  /*!< SMBUS initialized and ready for use           */
 111 #define  HAL_SMBUS_STATE_BUSY            0x02  /*!< SMBUS internal process is ongoing             */
 112 #define  HAL_SMBUS_STATE_MASTER_BUSY_TX  0x12  /*!< Master Data Transmission process is ongoing   */
 113 #define  HAL_SMBUS_STATE_MASTER_BUSY_RX  0x22  /*!< Master Data Reception process is ongoing      */
 114 #define  HAL_SMBUS_STATE_SLAVE_BUSY_TX   0x32  /*!< Slave Data Transmission process is ongoing    */
 115 #define  HAL_SMBUS_STATE_SLAVE_BUSY_RX   0x42  /*!< Slave Data Reception process is ongoing       */
 116 #define  HAL_SMBUS_STATE_TIMEOUT         0x03  /*!< Timeout state                                 */
 117 #define  HAL_SMBUS_STATE_ERROR           0x04  /*!< Reception process is ongoing                  */
 118 #define  HAL_SMBUS_STATE_LISTEN          0x08   /*!< Address Listen Mode is ongoing                */
 119 /**
 120   * @}
 121   */
 122
 123 /** @defgroup SMBUS_Error_Code SMBUS Error Code
 124   * @brief  SMBUS Error Code
 125   * @{
 126   */
 127 #define HAL_SMBUS_ERROR_NONE       0x00 /*!< No error             */
 128 #define HAL_SMBUS_ERROR_BERR       0x01 /*!< BERR error           */
 129 #define HAL_SMBUS_ERROR_ARLO       0x02 /*!< ARLO error           */
 130 #define HAL_SMBUS_ERROR_ACKF       0x04 /*!< ACKF error           */
 131 #define HAL_SMBUS_ERROR_OVR        0x08 /*!< OVR error            */
 132 #define HAL_SMBUS_ERROR_HALTIMEOUT 0x10 /*!< Timeout error        */
 133 #define HAL_SMBUS_ERROR_BUSTIMEOUT 0x20 /*!< Bus Timeout error    */
 134 #define HAL_SMBUS_ERROR_ALERT      0x40 /*!< Alert error          */
 135 #define HAL_SMBUS_ERROR_PECERR     0x80 /*!< PEC error            */
 136 /**
 137   * @}
 138   */
 139
 140 /**
 141   * @brief  SMBUS handle Structure definition
 142   */
 143 typedef struct
 144 {
 145   I2C_TypeDef                  *Instance;       /*!< SMBUS registers base address            */
 146
 147   SMBUS_InitTypeDef            Init;            /*!< SMBUS communication parameters          */
 148
 149   uint8_t                      *pBuffPtr;       /*!< Pointer to SMBUS transfer buffer        */
 150
 151   uint16_t                     XferSize;        /*!< SMBUS transfer size                     */
 152
 153   __IO uint16_t                XferCount;       /*!< SMBUS transfer counter                  */
 154
 155   __IO uint32_t                XferOptions;     /*!< SMBUS transfer options                  */
 156
 157   __IO uint32_t                PreviousState;   /*!< SMBUS communication Previous tate       */
 158
 159   HAL_LockTypeDef              Lock;            /*!< SMBUS locking object                    */
 160
 161   __IO uint32_t                State;           /*!< SMBUS communication state               */
 162
 163   __IO uint32_t                ErrorCode;       /*!< SMBUS Error code , see SMBUS_Error_Code */
 164
 165 }SMBUS_HandleTypeDef;
 166
 167 /* Exported constants --------------------------------------------------------*/
 168
 169 /** @defgroup SMBUS_Exported_Constants
 170   * @{
 171   */
 172
 173 /** @defgroup SMBUS_Analog_Filter
 174   * @{
 175   */
 176 #define SMBUS_ANALOGFILTER_ENABLE              ((uint32_t)0x00000000)
 177 #define SMBUS_ANALOGFILTER_DISABLE             I2C_CR1_ANFOFF
 178
 179 #define IS_SMBUS_ANALOG_FILTER(FILTER)          (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \
 180                                                  ((FILTER) == SMBUS_ANALOGFILTER_DISABLE))
 181 /**
 182   * @}
 183   */
 184
 185 /** @defgroup SMBUS_addressing_mode
 186   * @{
 187   */
 188 #define SMBUS_ADDRESSINGMODE_7BIT               ((uint32_t)0x00000001)
 189 #define SMBUS_ADDRESSINGMODE_10BIT              ((uint32_t)0x00000002)
 190
 191 #define IS_SMBUS_ADDRESSING_MODE(MODE)          (((MODE) == SMBUS_ADDRESSINGMODE_7BIT)  || \
 192                                                  ((MODE) == SMBUS_ADDRESSINGMODE_10BIT))
 193 /**
 194   * @}
 195   */
 196
 197 /** @defgroup SMBUS_dual_addressing_mode
 198   * @{
 199   */
 200
 201 #define SMBUS_DUALADDRESS_DISABLE              ((uint32_t)0x00000000)
 202 #define SMBUS_DUALADDRESS_ENABLE               I2C_OAR2_OA2EN
 203
 204 #define IS_SMBUS_DUAL_ADDRESS(ADDRESS)          (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \
 205                                                  ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))
 206 /**
 207   * @}
 208   */
 209
 210 /** @defgroup SMBUS_own_address2_masks
 211   * @{
 212   */
 213
 214 #define SMBUS_OA2_NOMASK                        ((uint8_t)0x00)
 215 #define SMBUS_OA2_MASK01                        ((uint8_t)0x01)
 216 #define SMBUS_OA2_MASK02                        ((uint8_t)0x02)
 217 #define SMBUS_OA2_MASK03                        ((uint8_t)0x03)
 218 #define SMBUS_OA2_MASK04                        ((uint8_t)0x04)
 219 #define SMBUS_OA2_MASK05                        ((uint8_t)0x05)
 220 #define SMBUS_OA2_MASK06                        ((uint8_t)0x06)
 221 #define SMBUS_OA2_MASK07                        ((uint8_t)0x07)
 222
 223 #define IS_SMBUS_OWN_ADDRESS2_MASK(MASK)        (((MASK) == SMBUS_OA2_NOMASK)   || \
 224                                                  ((MASK) == SMBUS_OA2_MASK01)    || \
 225                                                  ((MASK) == SMBUS_OA2_MASK02)    || \
 226                                                  ((MASK) == SMBUS_OA2_MASK03)    || \
 227                                                  ((MASK) == SMBUS_OA2_MASK04)    || \
 228                                                  ((MASK) == SMBUS_OA2_MASK05)    || \
 229                                                  ((MASK) == SMBUS_OA2_MASK06)    || \
 230                                                  ((MASK) == SMBUS_OA2_MASK07))
 231 /**
 232   * @}
 233   */
 234
 235
 236 /** @defgroup SMBUS_general_call_addressing_mode
 237   * @{
 238   */
 239 #define SMBUS_GENERALCALL_DISABLE              ((uint32_t)0x00000000)
 240 #define SMBUS_GENERALCALL_ENABLE               I2C_CR1_GCEN
 241
 242 #define IS_SMBUS_GENERAL_CALL(CALL)             (((CALL) == SMBUS_GENERALCALL_DISABLE) || \
 243                                                  ((CALL) == SMBUS_GENERALCALL_ENABLE))
 244 /**
 245   * @}
 246   */
 247
 248 /** @defgroup SMBUS_nostretch_mode
 249   * @{
 250   */
 251 #define SMBUS_NOSTRETCH_DISABLE                ((uint32_t)0x00000000)
 252 #define SMBUS_NOSTRETCH_ENABLE                 I2C_CR1_NOSTRETCH
 253
 254 #define IS_SMBUS_NO_STRETCH(STRETCH)            (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \
 255                                                  ((STRETCH) == SMBUS_NOSTRETCH_ENABLE))
 256 /**
 257   * @}
 258   */
 259
 260 /** @defgroup SMBUS_packet_error_check_mode
 261   * @{
 262   */
 263 #define SMBUS_PEC_DISABLE                       ((uint32_t)0x00000000)
 264 #define SMBUS_PEC_ENABLE                        I2C_CR1_PECEN
 265
 266 #define IS_SMBUS_PEC(PEC)                       (((PEC) == SMBUS_PEC_DISABLE) || \
 267                                                  ((PEC) == SMBUS_PEC_ENABLE))
 268 /**
 269   * @}
 270   */
 271
 272 /** @defgroup SMBUS_peripheral_mode
 273   * @{
 274   */
 275 #define SMBUS_PERIPHERAL_MODE_SMBUS_HOST        (uint32_t)(I2C_CR1_SMBHEN)
 276 #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE       (uint32_t)(0x00000000)
 277 #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP   (uint32_t)(I2C_CR1_SMBDEN)
 278
 279 #define IS_SMBUS_PERIPHERAL_MODE(MODE)          (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST)   || \
 280                                                  ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE)  || \
 281                                                  ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
 282 /**
 283   * @}
 284   */
 285
 286 /** @defgroup SMBUS_ReloadEndMode_definition
 287   * @{
 288   */
 289
 290 #define  SMBUS_SOFTEND_MODE                     ((uint32_t)0x00000000)
 291 #define  SMBUS_RELOAD_MODE                      I2C_CR2_RELOAD
 292 #define  SMBUS_AUTOEND_MODE                     I2C_CR2_AUTOEND
 293 #define  SMBUS_SENDPEC_MODE                     I2C_CR2_PECBYTE
 294
 295 #define IS_SMBUS_TRANSFER_MODE(MODE)            (((MODE) == SMBUS_RELOAD_MODE)                          || \
 296                                                  ((MODE) == SMBUS_AUTOEND_MODE)                         || \
 297                                                  ((MODE) == SMBUS_SOFTEND_MODE)                         || \
 298                                                  ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))  || \
 299                                                  ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE))   || \
 300                                                  ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE )))
 301
 302 /**
 303   * @}
 304   */
 305
 306 /** @defgroup SMBUS_StartStopMode_definition
 307   * @{
 308   */
 309
 310 #define  SMBUS_NO_STARTSTOP                     ((uint32_t)0x00000000)
 311 #define  SMBUS_GENERATE_STOP                    I2C_CR2_STOP
 312 #define  SMBUS_GENERATE_START_READ              (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
 313 #define  SMBUS_GENERATE_START_WRITE             I2C_CR2_START
 314
 315 #define IS_SMBUS_TRANSFER_REQUEST(REQUEST)      (((REQUEST) == SMBUS_GENERATE_STOP)             || \
 316                                                  ((REQUEST) == SMBUS_GENERATE_START_READ)       || \
 317                                                  ((REQUEST) == SMBUS_GENERATE_START_WRITE)      || \
 318                                                  ((REQUEST) == SMBUS_NO_STARTSTOP))
 319 /**
 320   * @}
 321   */
 322
 323 /** @defgroup SMBUS_XferOptions_definition
 324   * @{
 325   */
 326
 327 #define  SMBUS_FIRST_FRAME                      ((uint32_t)(SMBUS_SOFTEND_MODE))
 328 #define  SMBUS_NEXT_FRAME                       ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
 329 #define  SMBUS_FIRST_AND_LAST_FRAME_NO_PEC      SMBUS_AUTOEND_MODE
 330 #define  SMBUS_LAST_FRAME_NO_PEC                SMBUS_AUTOEND_MODE
 331 #define  SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC    ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
 332 #define  SMBUS_LAST_FRAME_WITH_PEC              ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
 333
 334 #define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST)    (((REQUEST) == SMBUS_FIRST_FRAME)                       || \
 335                                                        ((REQUEST) == SMBUS_NEXT_FRAME)                        || \
 336                                                        ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC)       || \
 337                                                        ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC)                 || \
 338                                                        ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC)     || \
 339                                                        ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))
 340
 341 /**
 342   * @}
 343   */
 344
 345 /** @defgroup SMBUS_Interrupt_configuration_definition
 346   * @brief SMBUS Interrupt definition
 347   *        Elements values convention: 0xXXXXXXXX
 348   *           - XXXXXXXX  : Interrupt control mask
 349   * @{
 350   */
 351 #define SMBUS_IT_ERRI                     I2C_CR1_ERRIE
 352 #define SMBUS_IT_TCI                      I2C_CR1_TCIE
 353 #define SMBUS_IT_STOPI                    I2C_CR1_STOPIE
 354 #define SMBUS_IT_NACKI                    I2C_CR1_NACKIE
 355 #define SMBUS_IT_ADDRI                    I2C_CR1_ADDRIE
 356 #define SMBUS_IT_RXI                      I2C_CR1_RXIE
 357 #define SMBUS_IT_TXI                      I2C_CR1_TXIE
 358 #define SMBUS_IT_TX                       (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)
 359 #define SMBUS_IT_RX                       (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI)
 360 #define SMBUS_IT_ALERT                    (SMBUS_IT_ERRI)
 361 #define SMBUS_IT_ADDR                     (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
 362 /**
 363   * @}
 364   */
 365
 366 /** @defgroup SMBUS_Flag_definition
 367   * @brief Flag definition
 368   *        Elements values convention: 0xXXXXYYYY
 369   *           - XXXXXXXX  : Flag mask
 370   * @{
 371   */
 372
 373 #define  SMBUS_FLAG_TXE                   I2C_ISR_TXE
 374 #define  SMBUS_FLAG_TXIS                  I2C_ISR_TXIS
 375 #define  SMBUS_FLAG_RXNE                  I2C_ISR_RXNE
 376 #define  SMBUS_FLAG_ADDR                  I2C_ISR_ADDR
 377 #define  SMBUS_FLAG_AF                    I2C_ISR_NACKF
 378 #define  SMBUS_FLAG_STOPF                 I2C_ISR_STOPF
 379 #define  SMBUS_FLAG_TC                    I2C_ISR_TC
 380 #define  SMBUS_FLAG_TCR                   I2C_ISR_TCR
 381 #define  SMBUS_FLAG_BERR                  I2C_ISR_BERR
 382 #define  SMBUS_FLAG_ARLO                  I2C_ISR_ARLO
 383 #define  SMBUS_FLAG_OVR                   I2C_ISR_OVR
 384 #define  SMBUS_FLAG_PECERR                I2C_ISR_PECERR
 385 #define  SMBUS_FLAG_TIMEOUT               I2C_ISR_TIMEOUT
 386 #define  SMBUS_FLAG_ALERT                 I2C_ISR_ALERT
 387 #define  SMBUS_FLAG_BUSY                  I2C_ISR_BUSY
 388 #define  SMBUS_FLAG_DIR                   I2C_ISR_DIR
 389 /**
 390   * @}
 391   */
 392
 393 /**
 394   * @}
 395   */
 396
 397 /* Exported macro ------------------------------------------------------------*/
 398
 399 /** @brief Reset SMBUS handle state
 400   * @param  __HANDLE__: specifies the SMBUS Handle.
 401   *         This parameter can be SMBUSx where x: 1 or 2 to select the SMBUS peripheral.
 402   * @retval None
 403   */
 404 #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
 405
 406 /** @brief  Enable or disable the specified SMBUS interrupts.
 407   * @param  __HANDLE__: specifies the SMBUS Handle.
 408   *         This parameter can be SMBUSx where x: 1 or 2 to select the SMBUS peripheral.
 409   * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
 410   *        This parameter can be one of the following values:
 411   *            @arg SMBUS_IT_ERRI: Errors interrupt enable
 412   *            @arg SMBUS_IT_TCI: Transfer complete interrupt enable
 413   *            @arg SMBUS_IT_STOPI: STOP detection interrupt enable
 414   *            @arg SMBUS_IT_NACKI: NACK received interrupt enable
 415   *            @arg SMBUS_IT_ADDRI: Address match interrupt enable
 416   *            @arg SMBUS_IT_RXI: RX interrupt enable
 417   *            @arg SMBUS_IT_TXI: TX interrupt enable
 418   *
 419   * @retval None
 420   */
 421
 422 #define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
 423 #define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
 424
 425 /** @brief  Checks if the specified SMBUS interrupt source is enabled or disabled.
 426   * @param  __HANDLE__: specifies the SMBUS Handle.
 427   *         This parameter can be SMBUSx where x: 1 or 2 to select the SMBUS peripheral.
 428   * @param  __INTERRUPT__: specifies the SMBUS interrupt source to check.
 429   *          This parameter can be one of the following values:
 430   *            @arg SMBUS_IT_ERRI: Errors interrupt enable
 431   *            @arg SMBUS_IT_TCI: Transfer complete interrupt enable
 432   *            @arg SMBUS_IT_STOPI: STOP detection interrupt enable
 433   *            @arg SMBUS_IT_NACKI: NACK received interrupt enable
 434   *            @arg SMBUS_IT_ADDRI: Address match interrupt enable
 435   *            @arg SMBUS_IT_RXI: RX interrupt enable
 436   *            @arg SMBUS_IT_TXI: TX interrupt enable
 437   *
 438   * @retval The new state of __IT__ (TRUE or FALSE).
 439   */
 440 #define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
 441
 442 /** @brief  Checks whether the specified SMBUS flag is set or not.
 443   * @param  __HANDLE__: specifies the SMBUS Handle.
 444   *         This parameter can be SMBUSx where x: 1 or 2 to select the SMBUS peripheral.
 445   * @param  __FLAG__: specifies the flag to check.
 446   *        This parameter can be one of the following values:
 447   *            @arg SMBUS_FLAG_TXE:     Transmit data register empty
 448   *            @arg SMBUS_FLAG_TXIS:    Transmit interrupt status
 449   *            @arg SMBUS_FLAG_RXNE:    Receive data register not empty
 450   *            @arg SMBUS_FLAG_ADDR:    Address matched (slave mode)
 451   *            @arg SMBUS_FLAG_AF       NACK received flag
 452   *            @arg SMBUS_FLAG_STOPF:   STOP detection flag
 453   *            @arg SMBUS_FLAG_TC:      Transfer complete (master mode)
 454   *            @arg SMBUS_FLAG_TCR:     Transfer complete reload
 455   *            @arg SMBUS_FLAG_BERR:    Bus error
 456   *            @arg SMBUS_FLAG_ARLO:    Arbitration lost
 457   *            @arg SMBUS_FLAG_OVR:     Overrun/Underrun
 458   *            @arg SMBUS_FLAG_PECERR:  PEC error in reception
 459   *            @arg SMBUS_FLAG_TIMEOUT: Timeout or Tlow detection flag
 460   *            @arg SMBUS_FLAG_ALERT:   SMBus alert
 461   *            @arg SMBUS_FLAG_BUSY:    Bus busy
 462   *            @arg SMBUS_FLAG_DIR:     Transfer direction (slave mode)
 463   * @retval The new state of __FLAG__ (TRUE or FALSE).
 464   */
 465 #define SMBUS_FLAG_MASK  ((uint32_t)0x0001FFFF)
 466 #define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
 467
 468 /** @brief  Clears the SMBUS pending flags which are cleared by writing 1 in a specific bit.
 469   * @param  __HANDLE__: specifies the SMBUS Handle.
 470   *         This parameter can be SMBUSx where x: 1 or 2 to select the SMBUS peripheral.
 471   * @param  __FLAG__: specifies the flag to clear.
 472   *          This parameter can be any combination of the following values:
 473   *            @arg SMBUS_FLAG_ADDR:    Address matched (slave mode)
 474   *            @arg SMBUS_FLAG_AF:      NACK received flag
 475   *            @arg SMBUS_FLAG_STOPF:   STOP detection flag
 476   *            @arg SMBUS_FLAG_BERR:    Bus error
 477   *            @arg SMBUS_FLAG_ARLO:    Arbitration lost
 478   *            @arg SMBUS_FLAG_OVR:     Overrun/Underrun
 479   *            @arg SMBUS_FLAG_PECERR:  PEC error in reception
 480   *            @arg SMBUS_FLAG_TIMEOUT: Timeout or Tlow detection flag
 481   *            @arg SMBUS_FLAG_ALERT:           SMBus alert
 482   * @retval None
 483   */
 484 #define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = ((__FLAG__) & SMBUS_FLAG_MASK))
 485
 486
 487 #define __HAL_SMBUS_ENABLE(__HANDLE__)                          ((__HANDLE__)->Instance->CR1 |=  I2C_CR1_PE)
 488 #define __HAL_SMBUS_DISABLE(__HANDLE__)                         ((__HANDLE__)->Instance->CR1 &=  ~I2C_CR1_PE)
 489
 490 #define __SMBUS_RESET_CR1(__HANDLE__)                       ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))
 491 #define __SMBUS_RESET_CR2(__HANDLE__)                       ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
 492
 493 #define __SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__)     (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
 494                                                                   (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
 495
 496 #define __SMBUS_GET_ADDR_MATCH(__HANDLE__)                  (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17)
 497 #define __SMBUS_GET_DIR(__HANDLE__)                         (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16)
 498 #define __SMBUS_GET_STOP_MODE(__HANDLE__)                   ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
 499 #define __SMBUS_GET_PEC_MODE(__HANDLE__)                    ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
 500 #define __SMBUS_GET_ALERT_ENABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
 501 #define __HAL_SMBUS_GENERATE_NACK(__HANDLE__)                   ((__HANDLE__)->Instance->CR2 |= I2C_CR2_NACK)
 502
 503 #define IS_SMBUS_OWN_ADDRESS1(ADDRESS1)                         ((ADDRESS1) <= (uint32_t)0x000003FF)
 504 #define IS_SMBUS_OWN_ADDRESS2(ADDRESS2)                         ((ADDRESS2) <= (uint16_t)0x00FF)
 505
 506 /* Exported functions --------------------------------------------------------*/
 507 /* Initialization and de-initialization functions  ****************************/
 508 HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
 509 HAL_StatusTypeDef HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus);
 510 void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus);
 511 void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus);
 512
 513 /* IO operation functions  ****************************************************/
 514 HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
 515 HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
 516 HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus);
 517 HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus);
 518 /* Aliases for inter STM32 series compatibility */
 519 #define HAL_SMBUS_EnableListen_IT   HAL_SMBUS_EnableListen_IT
 520
 521 /******* Blocking mode: Polling */
 522 HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
 523
 524 /******* Non-Blocking mode: Interrupt */
 525 HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
 526 HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
 527 HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress);
 528 HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
 529 HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
 530
 531 /******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
 532 void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
 533 void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
 534 void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
 535 void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
 536 void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
 537 void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
 538 void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
 539 void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus);
 540 /* Aliases for inter STM32 series compatibility */
 541 #define HAL_SMBUS_AddrCallback         HAL_SMBUS_AddrCallback
 542 #define HAL_SMBUS_ListenCpltCallback   HAL_SMBUS_ListenCpltCallback
 543
 544 void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
 545
 546 /* Peripheral State and Errors functions  *************************************/
 547 uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus);
 548 uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus);
 549
 550 /**
 551   * @}
 552   */
 553
 554 /**
 555   * @}
 556   */
 557
 558 #ifdef __cplusplus
 559 }
 560 #endif
 561
 562
 563 #endif /* __STM32L0xx_HAL_SMBUS_H */
 564
 565 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
 566
 567