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[tmk_keyboard.git] / tool / mbed / mbed-sdk / libraries / mbed / targets / cmsis / TARGET_STM / TARGET_STM32L0 / stm32l0xx_hal_spi.c
1 /**
2 ******************************************************************************
3 * @file stm32l0xx_hal_spi.c
4 * @author MCD Application Team
5 * @version V1.2.0
6 * @date 06-February-2015
7 * @brief SPI HAL module driver.
8 *
9 * This file provides firmware functions to manage the following
10 * functionalities of the Serial Peripheral Interface (SPI) peripheral:
11 * + Initialization and de-initialization functions
12 * + IO operation functions
13 * + Peripheral Control functions
14 * + Peripheral State functions
15 @verbatim
16 ==============================================================================
17 ##### How to use this driver #####
18 ==============================================================================
19 [..]
20 The SPI HAL driver can be used as follows:
21
22 (#) Declare a SPI_HandleTypeDef handle structure, for example:
23 SPI_HandleTypeDef hspi;
24
25 (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit ()API:
26 (##) Enable the SPIx interface clock
27 (##) SPI pins configuration
28 (+++) Enable the clock for the SPI GPIOs
29 (+++) Configure these SPI pins as alternate function push-pull
30 (##) NVIC configuration if you need to use interrupt process
31 (+++) Configure the SPIx interrupt priority
32 (+++) Enable the NVIC SPI IRQ handle
33 (##) DMA Configuration if you need to use DMA process
34 (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Channel
35 (+++) Enable the DMAx clock
36 (+++) Configure the DMA handle parameters
37 (+++) Configure the DMA Tx or Rx Channel
38 (+++) Associate the initilalized hdma_tx(or _rx) handle to the hspi DMA Tx (or Rx) handle
39 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Channel
40
41 (#) Program the Mode, Direction , Data size, Baudrate Prescaler, NSS
42 management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
43
44 (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
45 (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
46 by calling the customed HAL_SPI_MspInit() API.
47 [..]
48 Circular mode restriction:
49 (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
50 (##) Master 2Lines RxOnly
51 (##) Master 1Line Rx
52 (#) The CRC feature is not managed when the DMA circular mode is enabled
53 (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
54 the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
55
56 [..]
57 Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes,
58 the following table resume the max SPI frequency reached with data size 8bits/16bits,
59 according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance :
60
61 DataSize = SPI_DATASIZE_8BIT:
62 +----------------------------------------------------------------------------------------------+
63 | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
64 | Process | Tranfert mode |---------------------|----------------------|----------------------|
65 | | | Master | Slave | Master | Slave | Master | Slave |
66 |==============================================================================================|
67 | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
68 | X |----------------|----------|----------|-----------|----------|-----------|----------|
69 | / | Interrupt | Fpclk/64 | Fpclk/64 | NA | NA | NA | NA |
70 | R |----------------|----------|----------|-----------|----------|-----------|----------|
71 | X | DMA | Fpclk/2 | Fpclk/4 | NA | NA | NA | NA |
72 |=========|================|==========|==========|===========|==========|===========|==========|
73 | | Polling | Fpclk/2 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/8 |
74 | |----------------|----------|----------|-----------|----------|-----------|----------|
75 | R | Interrupt | Fpclk/64 | Fpclk/32 | Fpclk/32 | Fpclk/16 | Fpclk/32 | Fpclk/32 |
76 | X |----------------|----------|----------|-----------|----------|-----------|----------|
77 | | DMA | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 | Fpclk/2 |
78 |=========|================|==========|==========|===========|==========|===========|==========|
79 | | Polling | Fpclk/8 | Fpclk/8 | NA | NA | Fpclk/4 | Fpclk/16 |
80 | |----------------|----------|----------|-----------|----------|-----------|----------|
81 | T | Interrupt | Fpclk/8 | Fpclk/32 | NA | NA | Fpclk/8 | Fpclk/16 |
82 | X |----------------|----------|----------|-----------|----------|-----------|----------|
83 | | DMA | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/2 | Fpclk/2 |
84 +----------------------------------------------------------------------------------------------+
85
86 DataSize = SPI_DATASIZE_16BIT:
87 +----------------------------------------------------------------------------------------------+
88 | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
89 | Process | Tranfert mode |---------------------|----------------------|----------------------|
90 | | | Master | Slave | Master | Slave | Master | Slave |
91 |==============================================================================================|
92 | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
93 | X |----------------|----------|----------|-----------|----------|-----------|----------|
94 | / | Interrupt | Fpclk/32 | Fpclk/16 | NA | NA | NA | NA |
95 | R |----------------|----------|----------|-----------|----------|-----------|----------|
96 | X | DMA | Fpclk/2 | Fpclk/4 | NA | NA | NA | NA |
97 |=========|================|==========|==========|===========|==========|===========|==========|
98 | | Polling | Fpclk/2 | Fpclk/4 | Fpclk/8 | Fpclk/4 | Fpclk/2 | Fpclk/8 |
99 | |----------------|----------|----------|-----------|----------|-----------|----------|
100 | R | Interrupt | Fpclk/32 | Fpclk/8 | Fpclk/16 | Fpclk/16 | Fpclk/16 | Fpclk/8 |
101 | X |----------------|----------|----------|-----------|----------|-----------|----------|
102 | | DMA | Fpclk/2 | Fpclk/2 | Fpclk/8 | Fpclk/2 | Fpclk/8 | Fpclk/2 |
103 |=========|================|==========|==========|===========|==========|===========|==========|
104 | | Polling | Fpclk/4 | Fpclk/4 | NA | NA | Fpclk/4 | Fpclk/8 |
105 | |----------------|----------|----------|-----------|----------|-----------|----------|
106 | T | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | Fpclk/8 | Fpclk/8 |
107 | X |----------------|----------|----------|-----------|----------|-----------|----------|
108 | | DMA | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/2 | Fpclk/2 |
109 +----------------------------------------------------------------------------------------------+
110 @note The max SPI frequency depend on SPI data size (8bits, 16bits),
111 SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
112 @note
113 (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
114 (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
115 (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
116
117 @endverbatim
118 ******************************************************************************
119 * @attention
120 *
121 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
122 *
123 * Redistribution and use in source and binary forms, with or without modification,
124 * are permitted provided that the following conditions are met:
125 * 1. Redistributions of source code must retain the above copyright notice,
126 * this list of conditions and the following disclaimer.
127 * 2. Redistributions in binary form must reproduce the above copyright notice,
128 * this list of conditions and the following disclaimer in the documentation
129 * and/or other materials provided with the distribution.
130 * 3. Neither the name of STMicroelectronics nor the names of its contributors
131 * may be used to endorse or promote products derived from this software
132 * without specific prior written permission.
133 *
134 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
135 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
136 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
137 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
138 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
139 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
140 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
141 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
142 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
143 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
144 *
145 ******************************************************************************
146 */
147
148 /* Includes ------------------------------------------------------------------*/
149 #include "stm32l0xx_hal.h"
150
151 /** @addtogroup STM32L0xx_HAL_Driver
152 * @{
153 */
154
155 /** @defgroup SPI SPI
156 * @brief SPI HAL module driver
157 * @{
158 */
159
160 #ifdef HAL_SPI_MODULE_ENABLED
161
162 /* Private typedef -----------------------------------------------------------*/
163 /* Private define ------------------------------------------------------------*/
164 /** @defgroup SPI_Private_Constants SPI Private Constants
165 * @{
166 */
167 #define SPI_TIMEOUT_VALUE 10
168 /**
169 * @}
170 */
171
172 /* Private macro -------------------------------------------------------------*/
173 /* Private variables ---------------------------------------------------------*/
174 /* Private function prototypes -----------------------------------------------*/
175 /** @defgroup SPI_Private_Functions SPI Private Functions
176 * @{
177 */
178 static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi);
179 static void SPI_TxISR(SPI_HandleTypeDef *hspi);
180 static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi);
181 static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi);
182 static void SPI_RxISR(SPI_HandleTypeDef *hspi);
183 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
184 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
185 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
186 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
187 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
188 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
189 static void SPI_DMAError(DMA_HandleTypeDef *hdma);
190 static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
191 /**
192 * @}
193 */
194
195 /* Exported functions ---------------------------------------------------------*/
196
197 /** @defgroup SPI_Exported_Functions SPI Exported Functions
198 * @{
199 */
200
201 /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
202 * @brief Initialization and Configuration functions
203 *
204 @verbatim
205 ===============================================================================
206 ##### Initialization and de-initialization functions #####
207 ===============================================================================
208 [..] This subsection provides a set of functions allowing to initialize and
209 de-initialiaze the SPIx peripheral:
210
211 (+) User must implement HAL_SPI_MspInit() function in which he configures
212 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
213
214 (+) Call the function HAL_SPI_Init() to configure the selected device with
215 the selected configuration:
216 (++) Mode
217 (++) Direction
218 (++) Data Size
219 (++) Clock Polarity and Phase
220 (++) NSS Management
221 (++) BaudRate Prescaler
222 (++) FirstBit
223 (++) TIMode
224 (++) CRC Calculation
225 (++) CRC Polynomial if CRC enabled
226
227 (+) Call the function HAL_SPI_DeInit() to restore the default configuration
228 of the selected SPIx periperal.
229
230 @endverbatim
231 * @{
232 */
233
234 /**
235 * @brief Initializes the SPI according to the specified parameters
236 * in the SPI_InitTypeDef and create the associated handle.
237 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
238 * the configuration information for SPI module.
239 * @retval HAL status
240 */
241 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
242 {
243 /* Check the SPI handle allocation */
244 if(hspi == NULL)
245 {
246 return HAL_ERROR;
247 }
248
249 /* Check the parameters */
250 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
251 assert_param(IS_SPI_MODE(hspi->Init.Mode));
252 assert_param(IS_SPI_DIRECTION_MODE(hspi->Init.Direction));
253 assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
254 assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
255 assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
256 assert_param(IS_SPI_NSS(hspi->Init.NSS));
257 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
258 assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
259 assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
260 assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
261 assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
262
263 if(hspi->State == HAL_SPI_STATE_RESET)
264 {
265 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
266 HAL_SPI_MspInit(hspi);
267 }
268
269 hspi->State = HAL_SPI_STATE_BUSY;
270
271 /* Disble the selected SPI peripheral */
272 __HAL_SPI_DISABLE(hspi);
273
274 /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
275 /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
276 Communication speed, First bit and CRC calculation state */
277 WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize |
278 hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
279 hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation) );
280
281 /* Configure : NSS management */
282 WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode));
283
284 /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
285 /* Configure : CRC Polynomial */
286 WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
287
288 /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
289 CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
290
291 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
292 hspi->State = HAL_SPI_STATE_READY;
293
294 return HAL_OK;
295 }
296
297 /**
298 * @brief DeInitializes the SPI peripheral
299 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
300 * the configuration information for SPI module.
301 * @retval HAL status
302 */
303 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
304 {
305 /* Check the SPI handle allocation */
306 if(hspi == NULL)
307 {
308 return HAL_ERROR;
309 }
310
311 hspi->State = HAL_SPI_STATE_BUSY;
312
313 /* Disable the SPI Peripheral Clock */
314 __HAL_SPI_DISABLE(hspi);
315
316 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
317 HAL_SPI_MspDeInit(hspi);
318
319 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
320 hspi->State = HAL_SPI_STATE_RESET;
321
322 /* Release Lock */
323 __HAL_UNLOCK(hspi);
324
325 return HAL_OK;
326 }
327
328 /**
329 * @brief SPI MSP Init
330 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
331 * the configuration information for SPI module.
332 * @retval None
333 */
334 __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
335 {
336 /* NOTE : This function Should not be modified, when the callback is needed,
337 the HAL_SPI_MspInit could be implenetd in the user file
338 */
339 }
340
341 /**
342 * @brief SPI MSP DeInit
343 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
344 * the configuration information for SPI module.
345 * @retval None
346 */
347 __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
348 {
349 /* NOTE : This function Should not be modified, when the callback is needed,
350 the HAL_SPI_MspDeInit could be implenetd in the user file
351 */
352 }
353
354 /**
355 * @}
356 */
357
358 /** @defgroup SPI_Exported_Functions_Group2 IO operation functions
359 * @brief Data transfers functions
360 *
361 @verbatim
362 ==============================================================================
363 ##### IO operation functions #####
364 ===============================================================================
365 This subsection provides a set of functions allowing to manage the SPI
366 data transfers.
367
368 [..] The SPI supports master and slave mode :
369
370 (#) There are two modes of transfer:
371 (++) Blocking mode: The communication is performed in polling mode.
372 The HAL status of all data processing is returned by the same function
373 after finishing transfer.
374 (++) No-Blocking mode: The communication is performed using Interrupts
375 or DMA, These APIs return the HAL status.
376 The end of the data processing will be indicated through the
377 dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
378 using DMA mode.
379 The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
380 will be executed respectivelly at the end of the transmit or Receive process
381 The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
382
383 (#) Blocking mode APIs are :
384 (++) HAL_SPI_Transmit()in 1Line (simplex) and 2Lines (full duplex) mode
385 (++) HAL_SPI_Receive() in 1Line (simplex) and 2Lines (full duplex) mode
386 (++) HAL_SPI_TransmitReceive() in full duplex mode
387
388 (#) Non Blocking mode API's with Interrupt are :
389 (++) HAL_SPI_Transmit_IT()in 1Line (simplex) and 2Lines (full duplex) mode
390 (++) HAL_SPI_Receive_IT() in 1Line (simplex) and 2Lines (full duplex) mode
391 (++) HAL_SPI_TransmitReceive_IT()in full duplex mode
392 (++) HAL_SPI_IRQHandler()
393
394 (#) Non Blocking mode functions with DMA are :
395 (++) HAL_SPI_Transmit_DMA()in 1Line (simplex) and 2Lines (full duplex) mode
396 (++) HAL_SPI_Receive_DMA() in 1Line (simplex) and 2Lines (full duplex) mode
397 (++) HAL_SPI_TransmitReceive_DMA() in full duplex mode
398
399 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
400 (++) HAL_SPI_TxCpltCallback()
401 (++) HAL_SPI_RxCpltCallback()
402 (++) HAL_SPI_TxRxCpltCallback()
403 (++) HAL_SPI_TxHalfCpltCallback()
404 (++) HAL_SPI_RxHalfCpltCallback()
405 (++) HAL_SPI_TxRxHalfCpltCallback()
406 (++) HAL_SPI_ErrorCallback()
407
408 @endverbatim
409 * @{
410 */
411
412 /**
413 * @brief Transmit an amount of data in blocking mode
414 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
415 * the configuration information for SPI module.
416 * @param pData: pointer to data buffer
417 * @param Size: amount of data to be sent
418 * @param Timeout: Timeout duration
419 * @retval HAL status
420 */
421 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
422 {
423
424 if(hspi->State == HAL_SPI_STATE_READY)
425 {
426 if((pData == NULL ) || (Size == 0))
427 {
428 return HAL_ERROR;
429 }
430
431 /* Check the parameters */
432 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
433
434 /* Process Locked */
435 __HAL_LOCK(hspi);
436
437 /* Configure communication */
438 hspi->State = HAL_SPI_STATE_BUSY_TX;
439 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
440
441 hspi->pTxBuffPtr = pData;
442 hspi->TxXferSize = Size;
443 hspi->TxXferCount = Size;
444
445 /*Init field not used in handle to zero */
446 hspi->TxISR = 0;
447 hspi->RxISR = 0;
448 hspi->pRxBuffPtr = NULL;
449 hspi->RxXferSize = 0;
450 hspi->RxXferCount = 0;
451
452 /* Reset CRC Calculation */
453 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
454 {
455 SPI_RESET_CRC(hspi);
456 }
457
458 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
459 {
460 /* Configure communication direction : 1Line */
461 SPI_1LINE_TX(hspi);
462 }
463
464 /* Check if the SPI is already enabled */
465 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
466 {
467 /* Enable SPI peripheral */
468 __HAL_SPI_ENABLE(hspi);
469 }
470
471 /* Transmit data in 8 Bit mode */
472 if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
473 {
474 if((hspi->Init.Mode == SPI_MODE_SLAVE)|| (hspi->TxXferCount == 0x01))
475 {
476 hspi->Instance->DR = (*hspi->pTxBuffPtr++);
477 hspi->TxXferCount--;
478 }
479
480 while(hspi->TxXferCount > 0)
481 {
482 /* Wait until TXE flag is set to send data */
483 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
484 {
485 return HAL_TIMEOUT;
486 }
487 hspi->Instance->DR = (*hspi->pTxBuffPtr++);
488 hspi->TxXferCount--;
489 }
490 /* Enable CRC Transmission */
491 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
492 {
493 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
494 }
495 }
496 /* Transmit data in 16 Bit mode */
497 else
498 {
499 if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01))
500 {
501 hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
502 hspi->pTxBuffPtr+=2;
503 hspi->TxXferCount--;
504 }
505
506 while(hspi->TxXferCount > 0)
507 {
508 /* Wait until TXE flag is set to send data */
509 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
510 {
511 return HAL_TIMEOUT;
512 }
513 hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
514 hspi->pTxBuffPtr+=2;
515 hspi->TxXferCount--;
516 }
517 /* Enable CRC Transmission */
518 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
519 {
520 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
521 }
522 }
523
524 /* Wait until TXE flag is set to send data */
525 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
526 {
527 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
528 return HAL_TIMEOUT;
529 }
530
531 /* Wait until Busy flag is reset before disabling SPI */
532 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
533 {
534 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
535 return HAL_TIMEOUT;
536 }
537
538 /* Clear OVERUN flag in 2 Lines communication mode because received is not read */
539 if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
540 {
541 __HAL_SPI_CLEAR_OVRFLAG(hspi);
542 }
543
544 hspi->State = HAL_SPI_STATE_READY;
545
546 /* Process Unlocked */
547 __HAL_UNLOCK(hspi);
548
549 return HAL_OK;
550 }
551 else
552 {
553 return HAL_BUSY;
554 }
555 }
556
557 /**
558 * @brief Receive an amount of data in blocking mode
559 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
560 * the configuration information for SPI module.
561 * @param pData: pointer to data buffer
562 * @param Size: amount of data to be sent
563 * @param Timeout: Timeout duration
564 * @retval HAL status
565 */
566 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
567 {
568 __IO uint16_t tmpreg = 0;
569
570 if(hspi->State == HAL_SPI_STATE_READY)
571 {
572 if((pData == NULL ) || (Size == 0))
573 {
574 return HAL_ERROR;
575 }
576
577 /* Process Locked */
578 __HAL_LOCK(hspi);
579
580 /* Configure communication */
581 hspi->State = HAL_SPI_STATE_BUSY_RX;
582 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
583
584 hspi->pRxBuffPtr = pData;
585 hspi->RxXferSize = Size;
586 hspi->RxXferCount = Size;
587
588 /*Init field not used in handle to zero */
589 hspi->RxISR = 0;
590 hspi->TxISR = 0;
591 hspi->pTxBuffPtr = NULL;
592 hspi->TxXferSize = 0;
593 hspi->TxXferCount = 0;
594
595 /* Configure communication direction : 1Line */
596 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
597 {
598 SPI_1LINE_RX(hspi);
599 }
600
601 /* Reset CRC Calculation */
602 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
603 {
604 SPI_RESET_CRC(hspi);
605 }
606
607 if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
608 {
609 /* Process Unlocked */
610 __HAL_UNLOCK(hspi);
611
612 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
613 return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
614 }
615
616 /* Check if the SPI is already enabled */
617 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
618 {
619 /* Enable SPI peripheral */
620 __HAL_SPI_ENABLE(hspi);
621 }
622
623 /* Receive data in 8 Bit mode */
624 if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
625 {
626 while(hspi->RxXferCount > 1)
627 {
628 /* Wait until RXNE flag is set */
629 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
630 {
631 return HAL_TIMEOUT;
632 }
633
634 (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
635 hspi->RxXferCount--;
636 }
637 /* Enable CRC Reception */
638 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
639 {
640 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
641 }
642 }
643 /* Receive data in 16 Bit mode */
644 else
645 {
646 while(hspi->RxXferCount > 1)
647 {
648 /* Wait until RXNE flag is set to read data */
649 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
650 {
651 return HAL_TIMEOUT;
652 }
653
654 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
655 hspi->pRxBuffPtr+=2;
656 hspi->RxXferCount--;
657 }
658 /* Enable CRC Reception */
659 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
660 {
661 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
662 }
663 }
664
665 /* Wait until RXNE flag is set */
666 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
667 {
668 return HAL_TIMEOUT;
669 }
670
671 /* Receive last data in 8 Bit mode */
672 if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
673 {
674 (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
675 }
676 /* Receive last data in 16 Bit mode */
677 else
678 {
679 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
680 hspi->pRxBuffPtr+=2;
681 }
682 hspi->RxXferCount--;
683
684 /* If CRC computation is enabled */
685 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
686 {
687 /* Wait until RXNE flag is set: CRC Received */
688 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
689 {
690 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
691 return HAL_TIMEOUT;
692 }
693
694 /* Read CRC to clear RXNE flag */
695 tmpreg = hspi->Instance->DR;
696 UNUSED(tmpreg); /* avoid warning on tmpreg affectation with stupid compiler */
697 }
698
699 if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
700 {
701 /* Disable SPI peripheral */
702 __HAL_SPI_DISABLE(hspi);
703 }
704
705 hspi->State = HAL_SPI_STATE_READY;
706
707 /* Check if CRC error occurred */
708 if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET))
709 {
710 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
711
712 /* Reset CRC Calculation */
713 SPI_RESET_CRC(hspi);
714
715 /* Process Unlocked */
716 __HAL_UNLOCK(hspi);
717
718 return HAL_ERROR;
719 }
720
721 /* Process Unlocked */
722 __HAL_UNLOCK(hspi);
723
724 return HAL_OK;
725 }
726 else
727 {
728 return HAL_BUSY;
729 }
730 }
731
732 /**
733 * @brief Transmit and Receive an amount of data in blocking mode
734 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
735 * the configuration information for SPI module.
736 * @param pTxData: pointer to transmission data buffer
737 * @param pRxData: pointer to reception data buffer to be
738 * @param Size: amount of data to be sent
739 * @param Timeout: Timeout duration
740 * @retval HAL status
741 */
742 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
743 {
744 __IO uint16_t tmpreg = 0;
745
746 if((hspi->State == HAL_SPI_STATE_READY) || (hspi->State == HAL_SPI_STATE_BUSY_RX))
747 {
748 if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
749 {
750 return HAL_ERROR;
751 }
752
753 /* Check the parameters */
754 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
755
756 /* Process Locked */
757 __HAL_LOCK(hspi);
758
759 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
760 if(hspi->State == HAL_SPI_STATE_READY)
761 {
762 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
763 }
764
765 /* Configure communication */
766 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
767
768 hspi->pRxBuffPtr = pRxData;
769 hspi->RxXferSize = Size;
770 hspi->RxXferCount = Size;
771
772 hspi->pTxBuffPtr = pTxData;
773 hspi->TxXferSize = Size;
774 hspi->TxXferCount = Size;
775
776 /*Init field not used in handle to zero */
777 hspi->RxISR = 0;
778 hspi->TxISR = 0;
779
780 /* Reset CRC Calculation */
781 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
782 {
783 SPI_RESET_CRC(hspi);
784 }
785
786 /* Check if the SPI is already enabled */
787 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
788 {
789 /* Enable SPI peripheral */
790 __HAL_SPI_ENABLE(hspi);
791 }
792
793 /* Transmit and Receive data in 16 Bit mode */
794 if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
795 {
796 if((hspi->Init.Mode == SPI_MODE_SLAVE) || ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01)))
797 {
798 hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
799 hspi->pTxBuffPtr+=2;
800 hspi->TxXferCount--;
801 }
802 if(hspi->TxXferCount == 0)
803 {
804 /* Enable CRC Transmission */
805 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
806 {
807 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
808 }
809
810 /* Wait until RXNE flag is set */
811 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
812 {
813 return HAL_TIMEOUT;
814 }
815
816 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
817 hspi->pRxBuffPtr+=2;
818 hspi->RxXferCount--;
819 }
820 else
821 {
822 while(hspi->TxXferCount > 0)
823 {
824 /* Wait until TXE flag is set to send data */
825 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
826 {
827 return HAL_TIMEOUT;
828 }
829
830 hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
831 hspi->pTxBuffPtr+=2;
832 hspi->TxXferCount--;
833
834 /* Enable CRC Transmission */
835 if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
836 {
837 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
838 }
839
840 /* Wait until RXNE flag is set */
841 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
842 {
843 return HAL_TIMEOUT;
844 }
845
846 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
847 hspi->pRxBuffPtr+=2;
848 hspi->RxXferCount--;
849 }
850 /* Receive the last byte */
851 if(hspi->Init.Mode == SPI_MODE_SLAVE)
852 {
853 /* Wait until RXNE flag is set */
854 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
855 {
856 return HAL_TIMEOUT;
857 }
858
859 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
860 hspi->pRxBuffPtr+=2;
861 hspi->RxXferCount--;
862 }
863 }
864 }
865 /* Transmit and Receive data in 8 Bit mode */
866 else
867 {
868 if((hspi->Init.Mode == SPI_MODE_SLAVE) || ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01)))
869 {
870 hspi->Instance->DR = (*hspi->pTxBuffPtr++);
871 hspi->TxXferCount--;
872 }
873 if(hspi->TxXferCount == 0)
874 {
875 /* Enable CRC Transmission */
876 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
877 {
878 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
879 }
880
881 /* Wait until RXNE flag is set */
882 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
883 {
884 return HAL_TIMEOUT;
885 }
886
887 (*hspi->pRxBuffPtr) = hspi->Instance->DR;
888 hspi->RxXferCount--;
889 }
890 else
891 {
892 while(hspi->TxXferCount > 0)
893 {
894 /* Wait until TXE flag is set to send data */
895 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
896 {
897 return HAL_TIMEOUT;
898 }
899
900 hspi->Instance->DR = (*hspi->pTxBuffPtr++);
901 hspi->TxXferCount--;
902
903 /* Enable CRC Transmission */
904 if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
905 {
906 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
907 }
908
909 /* Wait until RXNE flag is set */
910 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
911 {
912 return HAL_TIMEOUT;
913 }
914
915 (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
916 hspi->RxXferCount--;
917 }
918 if(hspi->Init.Mode == SPI_MODE_SLAVE)
919 {
920 /* Wait until RXNE flag is set */
921 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
922 {
923 return HAL_TIMEOUT;
924 }
925
926 (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
927 hspi->RxXferCount--;
928 }
929 }
930 }
931
932 /* Read CRC from DR to close CRC calculation process */
933 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
934 {
935 /* Wait until RXNE flag is set */
936 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
937 {
938 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
939 return HAL_TIMEOUT;
940 }
941 /* Read CRC */
942 tmpreg = hspi->Instance->DR;
943 UNUSED(tmpreg); /* avoid warning on tmpreg affectation with stupid compiler */
944 }
945
946 /* Wait until Busy flag is reset before disabling SPI */
947 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
948 {
949 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
950 return HAL_TIMEOUT;
951 }
952
953 hspi->State = HAL_SPI_STATE_READY;
954
955 /* Check if CRC error occurred */
956 if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET))
957 {
958 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
959
960 SPI_RESET_CRC(hspi);
961
962 /* Process Unlocked */
963 __HAL_UNLOCK(hspi);
964
965 return HAL_ERROR;
966 }
967
968 /* Process Unlocked */
969 __HAL_UNLOCK(hspi);
970
971 return HAL_OK;
972 }
973 else
974 {
975 return HAL_BUSY;
976 }
977 }
978
979 /**
980 * @brief Transmit an amount of data in no-blocking mode with Interrupt
981 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
982 * the configuration information for SPI module.
983 * @param pData: pointer to data buffer
984 * @param Size: amount of data to be sent
985 * @retval HAL status
986 */
987 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
988 {
989 if(hspi->State == HAL_SPI_STATE_READY)
990 {
991 if((pData == NULL) || (Size == 0))
992 {
993 return HAL_ERROR;
994 }
995
996 /* Check the parameters */
997 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
998
999 /* Process Locked */
1000 __HAL_LOCK(hspi);
1001
1002 /* Configure communication */
1003 hspi->State = HAL_SPI_STATE_BUSY_TX;
1004 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1005
1006 hspi->TxISR = &SPI_TxISR;
1007 hspi->pTxBuffPtr = pData;
1008 hspi->TxXferSize = Size;
1009 hspi->TxXferCount = Size;
1010
1011 /*Init field not used in handle to zero */
1012 hspi->RxISR = 0;
1013 hspi->pRxBuffPtr = NULL;
1014 hspi->RxXferSize = 0;
1015 hspi->RxXferCount = 0;
1016
1017 /* Configure communication direction : 1Line */
1018 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
1019 {
1020 SPI_1LINE_TX(hspi);
1021 }
1022
1023 /* Reset CRC Calculation */
1024 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1025 {
1026 SPI_RESET_CRC(hspi);
1027 }
1028
1029 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
1030 {
1031 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE));
1032 }
1033 else
1034 {
1035 /* Enable TXE and ERR interrupt */
1036 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
1037 }
1038 /* Process Unlocked */
1039 __HAL_UNLOCK(hspi);
1040
1041 /* Check if the SPI is already enabled */
1042 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
1043 {
1044 /* Enable SPI peripheral */
1045 __HAL_SPI_ENABLE(hspi);
1046 }
1047
1048 return HAL_OK;
1049 }
1050 else
1051 {
1052 return HAL_BUSY;
1053 }
1054 }
1055
1056 /**
1057 * @brief Receive an amount of data in no-blocking mode with Interrupt
1058 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
1059 * the configuration information for SPI module.
1060 * @param pData: pointer to data buffer
1061 * @param Size: amount of data to be sent
1062 * @retval HAL status
1063 */
1064 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1065 {
1066 if(hspi->State == HAL_SPI_STATE_READY)
1067 {
1068 if((pData == NULL) || (Size == 0))
1069 {
1070 return HAL_ERROR;
1071 }
1072
1073 /* Process Locked */
1074 __HAL_LOCK(hspi);
1075
1076 /* Configure communication */
1077 hspi->State = HAL_SPI_STATE_BUSY_RX;
1078 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1079
1080 hspi->RxISR = &SPI_RxISR;
1081 hspi->pRxBuffPtr = pData;
1082 hspi->RxXferSize = Size;
1083 hspi->RxXferCount = Size ;
1084
1085 /*Init field not used in handle to zero */
1086 hspi->TxISR = 0;
1087 hspi->pTxBuffPtr = NULL;
1088 hspi->TxXferSize = 0;
1089 hspi->TxXferCount = 0;
1090
1091 /* Configure communication direction : 1Line */
1092 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
1093 {
1094 SPI_1LINE_RX(hspi);
1095 }
1096 else if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
1097 {
1098 /* Process Unlocked */
1099 __HAL_UNLOCK(hspi);
1100
1101 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
1102 return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
1103 }
1104
1105 /* Reset CRC Calculation */
1106 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1107 {
1108 SPI_RESET_CRC(hspi);
1109 }
1110
1111 /* Enable TXE and ERR interrupt */
1112 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
1113
1114 /* Process Unlocked */
1115 __HAL_UNLOCK(hspi);
1116
1117 /* Note : The SPI must be enabled after unlocking current process
1118 to avoid the risk of SPI interrupt handle execution before current
1119 process unlock */
1120
1121 /* Check if the SPI is already enabled */
1122 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
1123 {
1124 /* Enable SPI peripheral */
1125 __HAL_SPI_ENABLE(hspi);
1126 }
1127
1128 return HAL_OK;
1129 }
1130 else
1131 {
1132 return HAL_BUSY;
1133 }
1134 }
1135
1136 /**
1137 * @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt
1138 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
1139 * the configuration information for SPI module.
1140 * @param pTxData: pointer to transmission data buffer
1141 * @param pRxData: pointer to reception data buffer to be
1142 * @param Size: amount of data to be sent
1143 * @retval HAL status
1144 */
1145 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
1146 {
1147
1148 if((hspi->State == HAL_SPI_STATE_READY) || \
1149 ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
1150 {
1151 if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
1152 {
1153 return HAL_ERROR;
1154 }
1155
1156 /* Check the parameters */
1157 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
1158
1159 /* Process locked */
1160 __HAL_LOCK(hspi);
1161
1162 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
1163 if(hspi->State != HAL_SPI_STATE_BUSY_RX)
1164 {
1165 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
1166 }
1167
1168 /* Configure communication */
1169 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1170
1171 hspi->TxISR = &SPI_TxISR;
1172 hspi->pTxBuffPtr = pTxData;
1173 hspi->TxXferSize = Size;
1174 hspi->TxXferCount = Size;
1175
1176 hspi->RxISR = &SPI_2LinesRxISR;
1177 hspi->pRxBuffPtr = pRxData;
1178 hspi->RxXferSize = Size;
1179 hspi->RxXferCount = Size;
1180
1181 /* Reset CRC Calculation */
1182 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1183 {
1184 SPI_RESET_CRC(hspi);
1185 }
1186
1187 /* Enable TXE, RXNE and ERR interrupt */
1188 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
1189
1190 /* Process Unlocked */
1191 __HAL_UNLOCK(hspi);
1192
1193 /* Check if the SPI is already enabled */
1194 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
1195 {
1196 /* Enable SPI peripheral */
1197 __HAL_SPI_ENABLE(hspi);
1198 }
1199
1200 return HAL_OK;
1201 }
1202 else
1203 {
1204 return HAL_BUSY;
1205 }
1206 }
1207
1208 /**
1209 * @brief Transmit an amount of data in no-blocking mode with DMA
1210 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
1211 * the configuration information for SPI module.
1212 * @param pData: pointer to data buffer
1213 * @param Size: amount of data to be sent
1214 * @retval HAL status
1215 */
1216 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1217 {
1218 if(hspi->State == HAL_SPI_STATE_READY)
1219 {
1220 if((pData == NULL) || (Size == 0))
1221 {
1222 /* Process Unlocked */
1223 __HAL_UNLOCK(hspi);
1224 return HAL_ERROR;
1225 }
1226
1227 /* Check the parameters */
1228 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
1229
1230 /* Process Locked */
1231 __HAL_LOCK(hspi);
1232
1233 /* Configure communication */
1234 hspi->State = HAL_SPI_STATE_BUSY_TX;
1235 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1236
1237 hspi->pTxBuffPtr = (uint8_t*)pData;
1238 hspi->TxXferSize = Size;
1239 hspi->TxXferCount = Size;
1240
1241 /*Init field not used in handle to zero */
1242 hspi->TxISR = 0;
1243 hspi->RxISR = 0;
1244
1245 hspi->pRxBuffPtr = NULL;
1246 hspi->RxXferSize = 0;
1247 hspi->RxXferCount = 0;
1248
1249 /* Configure communication direction : 1Line */
1250 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
1251 {
1252 SPI_1LINE_TX(hspi);
1253 }
1254
1255 /* Reset CRC Calculation */
1256 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1257 {
1258 SPI_RESET_CRC(hspi);
1259 }
1260
1261 /* Set the SPI TxDMA Half transfer complete callback */
1262 hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
1263
1264 /* Set the SPI TxDMA transfer complete callback */
1265 hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
1266
1267 /* Set the DMA error callback */
1268 hspi->hdmatx->XferErrorCallback = SPI_DMAError;
1269
1270 /* Reset content of SPI RxDMA descriptor */
1271 hspi->hdmarx->XferHalfCpltCallback = (void (*)(DMA_HandleTypeDef *))NULL;
1272 hspi->hdmarx->XferCpltCallback = (void (*)(DMA_HandleTypeDef *))NULL;
1273 hspi->hdmarx->XferErrorCallback = (void (*)(DMA_HandleTypeDef *))NULL;
1274
1275 /* Enable the Tx DMA Channel */
1276 HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
1277
1278 /* Enable Tx DMA Request */
1279 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
1280
1281 /* Process Unlocked */
1282 __HAL_UNLOCK(hspi);
1283
1284 /* Check if the SPI is already enabled */
1285 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
1286 {
1287 /* Enable SPI peripheral */
1288 __HAL_SPI_ENABLE(hspi);
1289 }
1290
1291 return HAL_OK;
1292 }
1293 else
1294 {
1295 /* Process Unlocked */
1296 __HAL_UNLOCK(hspi);
1297 return HAL_BUSY;
1298 }
1299 }
1300
1301 /**
1302 * @brief Receive an amount of data in no-blocking mode with DMA
1303 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
1304 * the configuration information for SPI module.
1305 * @param pData: pointer to data buffer
1306 * @note When the CRC feature is enabled the pData Length must be Size + 1.
1307 * @param Size: amount of data to be sent
1308 * @retval HAL status
1309 */
1310 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1311 {
1312 if(hspi->State == HAL_SPI_STATE_READY)
1313 {
1314 if((pData == NULL) || (Size == 0))
1315 {
1316 /* Process Unlocked */
1317 __HAL_UNLOCK(hspi);
1318 return HAL_ERROR;
1319 }
1320
1321 /* Process Locked */
1322 __HAL_LOCK(hspi);
1323
1324 /* Configure communication */
1325 hspi->State = HAL_SPI_STATE_BUSY_RX;
1326 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1327
1328 hspi->pRxBuffPtr = (uint8_t*)pData;
1329 hspi->RxXferSize = Size;
1330 hspi->RxXferCount = Size;
1331
1332 /*Init field not used in handle to zero */
1333 hspi->RxISR = 0;
1334 hspi->TxISR = 0;
1335
1336 hspi->pTxBuffPtr = NULL;
1337 hspi->TxXferSize = 0;
1338 hspi->TxXferCount = 0;
1339
1340 /* Configure communication direction : 1Line */
1341 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
1342 {
1343 SPI_1LINE_RX(hspi);
1344 }
1345 else if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER))
1346 {
1347 /* Process Unlocked */
1348 __HAL_UNLOCK(hspi);
1349
1350 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
1351 return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
1352 }
1353
1354 /* Reset CRC Calculation */
1355 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1356 {
1357 SPI_RESET_CRC(hspi);
1358 }
1359
1360 /* Set the SPI RxDMA Half transfer complete callback */
1361 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
1362
1363 /* Set the SPI Rx DMA transfer complete callback */
1364 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
1365
1366 /* Set the DMA error callback */
1367 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
1368
1369 /* Reset content of SPI TxDMA descriptor */
1370 hspi->hdmatx->XferHalfCpltCallback = (void (*)(DMA_HandleTypeDef *))NULL;
1371 hspi->hdmatx->XferCpltCallback = (void (*)(DMA_HandleTypeDef *))NULL;
1372 hspi->hdmatx->XferErrorCallback = (void (*)(DMA_HandleTypeDef *))NULL;
1373
1374 /* Enable the Rx DMA Channel */
1375 HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
1376
1377 /* Enable Rx DMA Request */
1378 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
1379
1380 /* Process Unlocked */
1381 __HAL_UNLOCK(hspi);
1382
1383 /* Check if the SPI is already enabled */
1384 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
1385 {
1386 /* Enable SPI peripheral */
1387 __HAL_SPI_ENABLE(hspi);
1388 }
1389
1390 return HAL_OK;
1391 }
1392 else
1393 {
1394 /* Process Unlocked */
1395 __HAL_UNLOCK(hspi);
1396 return HAL_BUSY;
1397 }
1398 }
1399
1400 /**
1401 * @brief Transmit and Receive an amount of data in no-blocking mode with DMA
1402 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
1403 * the configuration information for SPI module.
1404 * @param pTxData: pointer to transmission data buffer
1405 * @param pRxData: pointer to reception data buffer
1406 * @note When the CRC feature is enabled the pRxData Length must be Size + 1
1407 * @param Size: amount of data to be sent
1408 * @retval HAL status
1409 */
1410 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
1411 {
1412 if((hspi->State == HAL_SPI_STATE_READY) || \
1413 ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
1414 {
1415 if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
1416 {
1417 return HAL_ERROR;
1418 }
1419
1420 /* Check the parameters */
1421 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
1422
1423 /* Process locked */
1424 __HAL_LOCK(hspi);
1425
1426 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
1427 if(hspi->State != HAL_SPI_STATE_BUSY_RX)
1428 {
1429 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
1430 }
1431
1432 /* Configure communication */
1433 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1434
1435 hspi->pTxBuffPtr = (uint8_t*)pTxData;
1436 hspi->TxXferSize = Size;
1437 hspi->TxXferCount = Size;
1438
1439 hspi->pRxBuffPtr = (uint8_t*)pRxData;
1440 hspi->RxXferSize = Size;
1441 hspi->RxXferCount = Size;
1442
1443 /*Init field not used in handle to zero */
1444 hspi->RxISR = 0;
1445 hspi->TxISR = 0;
1446
1447 /* Reset CRC Calculation */
1448 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1449 {
1450 SPI_RESET_CRC(hspi);
1451 }
1452
1453 /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
1454 if(hspi->State == HAL_SPI_STATE_BUSY_RX)
1455 {
1456 /* Set the SPI Rx DMA Half transfer complete callback */
1457 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
1458
1459 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
1460 }
1461 else
1462 {
1463 /* Set the SPI Tx/Rx DMA Half transfer complete callback */
1464 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
1465
1466 hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
1467 }
1468
1469 /* Set the DMA error callback */
1470 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
1471
1472 /* Enable the Rx DMA Channel */
1473 HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
1474
1475 /* Enable Rx DMA Request */
1476 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
1477
1478 /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
1479 is performed in DMA reception complete callback */
1480 hspi->hdmatx->XferHalfCpltCallback = (void (*)(DMA_HandleTypeDef *))NULL;
1481 hspi->hdmatx->XferCpltCallback = (void (*)(DMA_HandleTypeDef *))NULL;
1482
1483 /* Set the DMA error callback */
1484 hspi->hdmatx->XferErrorCallback = SPI_DMAError;
1485
1486 /* Enable the Tx DMA Channel */
1487 HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
1488
1489 /* Check if the SPI is already enabled */
1490 if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1491 {
1492 /* Enable SPI peripheral */
1493 __HAL_SPI_ENABLE(hspi);
1494 }
1495
1496 /* Enable Tx DMA Request */
1497 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
1498
1499 /* Process Unlocked */
1500 __HAL_UNLOCK(hspi);
1501
1502 return HAL_OK;
1503 }
1504 else
1505 {
1506 return HAL_BUSY;
1507 }
1508 }
1509
1510
1511 /**
1512 * @brief Pauses the DMA Transfer.
1513 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
1514 * the configuration information for the specified SPI module.
1515 * @retval HAL status
1516 */
1517 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
1518 {
1519 /* Process Locked */
1520 __HAL_LOCK(hspi);
1521
1522 /* Disable the SPI DMA Tx & Rx requests */
1523 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
1524 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
1525
1526 /* Process Unlocked */
1527 __HAL_UNLOCK(hspi);
1528
1529 return HAL_OK;
1530 }
1531
1532 /**
1533 * @brief Resumes the DMA Transfer.
1534 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
1535 * the configuration information for the specified SPI module.
1536 * @retval HAL status
1537 */
1538 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
1539 {
1540 /* Process Locked */
1541 __HAL_LOCK(hspi);
1542
1543 /* Enable the SPI DMA Tx & Rx requests */
1544 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
1545 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
1546
1547 /* Process Unlocked */
1548 __HAL_UNLOCK(hspi);
1549
1550 return HAL_OK;
1551 }
1552
1553 /**
1554 * @brief Stops the DMA Transfer.
1555 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
1556 * the configuration information for the specified SPI module.
1557 * @retval HAL status
1558 */
1559 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
1560 {
1561 /* The Lock is not implemented on this API to allow the user application
1562 to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
1563 when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
1564 and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
1565 */
1566
1567 /* Abort the SPI DMA tx Channel */
1568 if(hspi->hdmatx != NULL)
1569 {
1570 HAL_DMA_Abort(hspi->hdmatx);
1571 }
1572 /* Abort the SPI DMA rx Channel */
1573 if(hspi->hdmarx != NULL)
1574 {
1575 HAL_DMA_Abort(hspi->hdmarx);
1576 }
1577
1578 /* Disable the SPI DMA Tx & Rx requests */
1579 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
1580 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
1581
1582 hspi->State = HAL_SPI_STATE_READY;
1583
1584 return HAL_OK;
1585 }
1586
1587 /**
1588 * @brief This function handles SPI interrupt request.
1589 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
1590 * the configuration information for SPI module.
1591 * @retval HAL status
1592 */
1593 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
1594 {
1595 /* SPI in mode Receiver and Overrun not occurred ---------------------------*/
1596 if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) == RESET))
1597 {
1598 hspi->RxISR(hspi);
1599 return;
1600 }
1601
1602 /* SPI in mode Tramitter ---------------------------------------------------*/
1603 if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE) != RESET))
1604 {
1605 hspi->TxISR(hspi);
1606 return;
1607 }
1608
1609 if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_ERR) != RESET)
1610 {
1611 /* SPI CRC error interrupt occurred ---------------------------------------*/
1612 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
1613 {
1614 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1615 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
1616 }
1617 /* SPI Mode Fault error interrupt occurred --------------------------------*/
1618 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET)
1619 {
1620 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
1621 __HAL_SPI_CLEAR_MODFFLAG(hspi);
1622 }
1623
1624 /* SPI Overrun error interrupt occurred -----------------------------------*/
1625 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET)
1626 {
1627 if(hspi->State != HAL_SPI_STATE_BUSY_TX)
1628 {
1629 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
1630 __HAL_SPI_CLEAR_OVRFLAG(hspi);
1631 }
1632 }
1633
1634 /* SPI Frame error interrupt occurred -------------------------------------*/
1635 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_FRE) != RESET)
1636 {
1637 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
1638 __HAL_SPI_CLEAR_FREFLAG(hspi);
1639 }
1640
1641 /* Call the Error call Back in case of Errors */
1642 if(hspi->ErrorCode!=HAL_SPI_ERROR_NONE)
1643 {
1644 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
1645 hspi->State = HAL_SPI_STATE_READY;
1646 HAL_SPI_ErrorCallback(hspi);
1647 }
1648 }
1649 }
1650
1651 /**
1652 * @brief Tx Transfer completed callbacks
1653 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
1654 * the configuration information for SPI module.
1655 * @retval None
1656 */
1657 __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
1658 {
1659 /* NOTE : This function Should not be modified, when the callback is needed,
1660 the HAL_SPI_TxCpltCallback could be implenetd in the user file
1661 */
1662 }
1663
1664 /**
1665 * @brief Rx Transfer completed callbacks
1666 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
1667 * the configuration information for SPI module.
1668 * @retval None
1669 */
1670 __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
1671 {
1672 /* NOTE : This function Should not be modified, when the callback is needed,
1673 the HAL_SPI_RxCpltCallback() could be implenetd in the user file
1674 */
1675 }
1676
1677 /**
1678 * @brief Tx and Rx Transfer completed callbacks
1679 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
1680 * the configuration information for SPI module.
1681 * @retval None
1682 */
1683 __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
1684 {
1685 /* NOTE : This function Should not be modified, when the callback is needed,
1686 the HAL_SPI_TxRxCpltCallback() could be implenetd in the user file
1687 */
1688 }
1689
1690 /**
1691 * @brief Tx Half Transfer completed callbacks
1692 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
1693 * the configuration information for SPI module.
1694 * @retval None
1695 */
1696 __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
1697 {
1698 /* NOTE : This function Should not be modified, when the callback is needed,
1699 the HAL_SPI_TxHalfCpltCallback could be implenetd in the user file
1700 */
1701 }
1702
1703 /**
1704 * @brief Rx Half Transfer completed callbacks
1705 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
1706 * the configuration information for SPI module.
1707 * @retval None
1708 */
1709 __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
1710 {
1711 /* NOTE : This function Should not be modified, when the callback is needed,
1712 the HAL_SPI_RxHalfCpltCallback() could be implenetd in the user file
1713 */
1714 }
1715
1716 /**
1717 * @brief Tx and Rx Transfer completed callbacks
1718 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
1719 * the configuration information for SPI module.
1720 * @retval None
1721 */
1722 __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
1723 {
1724 /* NOTE : This function Should not be modified, when the callback is needed,
1725 the HAL_SPI_TxRxHalfCpltCallback() could be implenetd in the user file
1726 */
1727 }
1728
1729 /**
1730 * @brief SPI error callbacks
1731 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
1732 * the configuration information for SPI module.
1733 * @retval None
1734 */
1735 __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
1736 {
1737 /* NOTE : - This function Should not be modified, when the callback is needed,
1738 the HAL_SPI_ErrorCallback() could be implenetd in the user file.
1739 - The ErrorCode parameter in the hspi handle is updated by the SPI processes
1740 and user can use HAL_SPI_GetError() API to check the latest error occurred.
1741 */
1742 }
1743
1744 /**
1745 * @}
1746 */
1747
1748 /** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
1749 * @brief SPI control functions
1750 *
1751 @verbatim
1752 ===============================================================================
1753 ##### Peripheral State and Errors functions #####
1754 ===============================================================================
1755 [..]
1756 This subsection provides a set of functions allowing to control the SPI.
1757 (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
1758 (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
1759 @endverbatim
1760 * @{
1761 */
1762
1763 /**
1764 * @brief Return the SPI state
1765 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
1766 * the configuration information for SPI module.
1767 * @retval SPI state
1768 */
1769 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
1770 {
1771 return hspi->State;
1772 }
1773
1774 /**
1775 * @brief Return the SPI error code
1776 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
1777 * the configuration information for SPI module.
1778 * @retval SPI Error Code
1779 */
1780 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
1781 {
1782 return hspi->ErrorCode;
1783 }
1784
1785 /**
1786 * @}
1787 */
1788
1789 /**
1790 * @}
1791 */
1792
1793
1794
1795 /** @addtogroup SPI_Private_Functions
1796 * @{
1797 */
1798
1799
1800 /**
1801 * @brief Interrupt Handler to close Tx transfer
1802 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
1803 * the configuration information for SPI module.
1804 * @retval void
1805 */
1806 static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi)
1807 {
1808 /* Wait until TXE flag is set to send data */
1809 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
1810 {
1811 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
1812 }
1813
1814 /* Disable TXE interrupt */
1815 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE));
1816
1817 /* Disable ERR interrupt if Receive process is finished */
1818 if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) == RESET)
1819 {
1820 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR));
1821
1822 /* Wait until Busy flag is reset before disabling SPI */
1823 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
1824 {
1825 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
1826 }
1827
1828 /* Clear OVERUN flag in 2 Lines communication mode because received is not read */
1829 if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
1830 {
1831 __HAL_SPI_CLEAR_OVRFLAG(hspi);
1832 }
1833
1834 /* Check if Errors has been detected during transfer */
1835 if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
1836 {
1837 /* Check if we are in Tx or in Rx/Tx Mode */
1838 if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
1839 {
1840 /* Set state to READY before run the Callback Complete */
1841 hspi->State = HAL_SPI_STATE_READY;
1842 HAL_SPI_TxRxCpltCallback(hspi);
1843 }
1844 else
1845 {
1846 /* Set state to READY before run the Callback Complete */
1847 hspi->State = HAL_SPI_STATE_READY;
1848 HAL_SPI_TxCpltCallback(hspi);
1849 }
1850 }
1851 else
1852 {
1853 /* Set state to READY before run the Callback Complete */
1854 hspi->State = HAL_SPI_STATE_READY;
1855 /* Call Error call back in case of Error */
1856 HAL_SPI_ErrorCallback(hspi);
1857 }
1858 }
1859 }
1860
1861 /**
1862 * @brief Interrupt Handler to transmit amount of data in no-blocking mode
1863 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
1864 * the configuration information for SPI module.
1865 * @retval void
1866 */
1867 static void SPI_TxISR(SPI_HandleTypeDef *hspi)
1868 {
1869 /* Transmit data in 8 Bit mode */
1870 if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
1871 {
1872 hspi->Instance->DR = (*hspi->pTxBuffPtr++);
1873 }
1874 /* Transmit data in 16 Bit mode */
1875 else
1876 {
1877 hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
1878 hspi->pTxBuffPtr+=2;
1879 }
1880 hspi->TxXferCount--;
1881
1882 if(hspi->TxXferCount == 0)
1883 {
1884 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1885 {
1886 /* calculate and transfer CRC on Tx line */
1887 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1888 }
1889 SPI_TxCloseIRQHandler(hspi);
1890 }
1891 }
1892
1893 /**
1894 * @brief Interrupt Handler to close Rx transfer
1895 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
1896 * the configuration information for SPI module.
1897 * @retval void
1898 */
1899 static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi)
1900 {
1901 __IO uint16_t tmpreg = 0;
1902
1903 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1904 {
1905 /* Wait until RXNE flag is set to read CRC data */
1906 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
1907 {
1908 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
1909 }
1910
1911 /* Read CRC to reset RXNE flag */
1912 tmpreg = hspi->Instance->DR;
1913 UNUSED(tmpreg); /* avoid warning on tmpreg affectation with some compiler */
1914
1915 /* Wait until RXNE flag is reset */
1916 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
1917 {
1918 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
1919 }
1920
1921 /* Check if CRC error occurred */
1922 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
1923 {
1924 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1925
1926 /* Reset CRC Calculation */
1927 SPI_RESET_CRC(hspi);
1928 }
1929 }
1930
1931 /* Disable RXNE interrupt */
1932 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE));
1933
1934 /* if Transmit process is finished */
1935 if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) == RESET)
1936 {
1937 /* Disable ERR interrupt */
1938 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR));
1939
1940 if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
1941 {
1942 /* Disable SPI peripheral */
1943 __HAL_SPI_DISABLE(hspi);
1944 }
1945
1946 /* Check if Errors has been detected during transfer */
1947 if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
1948 {
1949 /* Check if we are in Rx or in Rx/Tx Mode */
1950 if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
1951 {
1952 /* Set state to READY before run the Callback Complete */
1953 hspi->State = HAL_SPI_STATE_READY;
1954 HAL_SPI_TxRxCpltCallback(hspi);
1955 }
1956 else
1957 {
1958 /* Set state to READY before run the Callback Complete */
1959 hspi->State = HAL_SPI_STATE_READY;
1960 HAL_SPI_RxCpltCallback(hspi);
1961 }
1962 }
1963 else
1964 {
1965 /* Set state to READY before run the Callback Complete */
1966 hspi->State = HAL_SPI_STATE_READY;
1967 /* Call Error call back in case of Error */
1968 HAL_SPI_ErrorCallback(hspi);
1969 }
1970 }
1971 }
1972
1973 /**
1974 * @brief Interrupt Handler to receive amount of data in 2Lines mode
1975 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
1976 * the configuration information for SPI module.
1977 * @retval void
1978 */
1979 static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi)
1980 {
1981 /* Receive data in 8 Bit mode */
1982 if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
1983 {
1984 (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
1985 }
1986 /* Receive data in 16 Bit mode */
1987 else
1988 {
1989 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
1990 hspi->pRxBuffPtr+=2;
1991 }
1992 hspi->RxXferCount--;
1993
1994 if(hspi->RxXferCount==0)
1995 {
1996 SPI_RxCloseIRQHandler(hspi);
1997 }
1998 }
1999
2000 /**
2001 * @brief Interrupt Handler to receive amount of data in no-blocking mode
2002 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
2003 * the configuration information for SPI module.
2004 * @retval void
2005 */
2006 static void SPI_RxISR(SPI_HandleTypeDef *hspi)
2007 {
2008 /* Receive data in 8 Bit mode */
2009 if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
2010 {
2011 (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
2012 }
2013 /* Receive data in 16 Bit mode */
2014 else
2015 {
2016 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
2017 hspi->pRxBuffPtr+=2;
2018 }
2019 hspi->RxXferCount--;
2020
2021 /* Enable CRC Transmission */
2022 if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
2023 {
2024 /* Set CRC Next to calculate CRC on Rx side */
2025 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
2026 }
2027
2028 if(hspi->RxXferCount == 0)
2029 {
2030 SPI_RxCloseIRQHandler(hspi);
2031 }
2032 }
2033
2034 /**
2035 * @brief DMA SPI transmit process complete callback
2036 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
2037 * the configuration information for the specified DMA module.
2038 * @retval None
2039 */
2040 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
2041 {
2042 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2043
2044
2045 /* DMA Normal Mode */
2046 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
2047 {
2048 /* Wait until TXE flag is set to send data */
2049 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
2050 {
2051 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
2052 }
2053
2054 /* Disable Tx DMA Request */
2055 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
2056
2057 /* Wait until Busy flag is reset before disabling SPI */
2058 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
2059 {
2060 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
2061 }
2062
2063 hspi->TxXferCount = 0;
2064 hspi->State = HAL_SPI_STATE_READY;
2065 }
2066
2067 /* Clear OVERUN flag in 2 Lines communication mode because received is not read */
2068 if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
2069 {
2070 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2071 }
2072
2073 /* Check if Errors has been detected during transfer */
2074 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
2075 {
2076 HAL_SPI_ErrorCallback(hspi);
2077 }
2078 else
2079 {
2080 HAL_SPI_TxCpltCallback(hspi);
2081 }
2082 }
2083
2084 /**
2085 * @brief DMA SPI receive process complete callback
2086 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
2087 * the configuration information for the specified DMA module.
2088 * @retval None
2089 */
2090 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
2091 {
2092 __IO uint16_t tmpreg = 0;
2093
2094 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2095
2096 /* DMA Normal mode */
2097 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
2098 {
2099 /* Disable Rx DMA Request */
2100 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
2101
2102 /* Disable Tx DMA Request (done by default to handle the case Master RX direction 2 lines) */
2103 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
2104
2105 /* CRC Calculation handling */
2106 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2107 {
2108 /* Wait until RXNE flag is set (CRC ready) */
2109 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
2110 {
2111 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
2112 }
2113
2114 /* Read CRC */
2115 tmpreg = hspi->Instance->DR;
2116 UNUSED(tmpreg); /* avoid warning on tmpreg affectation with some compiler */
2117
2118 /* Wait until RXNE flag is reset */
2119 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
2120 {
2121 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
2122 }
2123
2124 /* Check if CRC error occurred */
2125 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
2126 {
2127 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
2128 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
2129 }
2130 }
2131
2132 if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
2133 {
2134 /* Disable SPI peripheral */
2135 __HAL_SPI_DISABLE(hspi);
2136 }
2137
2138 hspi->RxXferCount = 0;
2139 hspi->State = HAL_SPI_STATE_READY;
2140
2141 /* Check if Errors has been detected during transfer */
2142 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
2143 {
2144 HAL_SPI_ErrorCallback(hspi);
2145 }
2146 else
2147 {
2148 HAL_SPI_RxCpltCallback(hspi);
2149 }
2150 }
2151 else
2152 {
2153 HAL_SPI_RxCpltCallback(hspi);
2154 }
2155 }
2156
2157 /**
2158 * @brief DMA SPI transmit receive process complete callback
2159 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
2160 * the configuration information for the specified DMA module.
2161 * @retval None
2162 */
2163 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
2164 {
2165 __IO uint16_t tmpreg = 0;
2166
2167 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2168 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
2169 {
2170 /* CRC Calculation handling */
2171 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2172 {
2173 /* Check if CRC is done on going (RXNE flag set) */
2174 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) == HAL_OK)
2175 {
2176 /* Wait until RXNE flag is set to send data */
2177 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
2178 {
2179 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
2180 }
2181 }
2182 /* Read CRC */
2183 tmpreg = hspi->Instance->DR;
2184 UNUSED(tmpreg); /* avoid warning on tmpreg affectation with some compiler */
2185
2186 /* Check if CRC error occurred */
2187 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
2188 {
2189 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
2190 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
2191 }
2192 }
2193
2194 /* Wait until TXE flag is set to send data */
2195 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
2196 {
2197 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
2198 }
2199
2200 /* Disable Tx DMA Request */
2201 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
2202
2203 /* Wait until Busy flag is reset before disabling SPI */
2204 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
2205 {
2206 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
2207 }
2208
2209 /* Disable Rx DMA Request */
2210 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
2211
2212 hspi->TxXferCount = 0;
2213 hspi->RxXferCount = 0;
2214
2215 hspi->State = HAL_SPI_STATE_READY;
2216
2217 /* Check if Errors has been detected during transfer */
2218 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
2219 {
2220 HAL_SPI_ErrorCallback(hspi);
2221 }
2222 else
2223 {
2224 HAL_SPI_TxRxCpltCallback(hspi);
2225 }
2226 }
2227 else
2228 {
2229 HAL_SPI_TxRxCpltCallback(hspi);
2230 }
2231 }
2232
2233 /**
2234 * @brief DMA SPI half transmit process complete callback
2235 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
2236 * the configuration information for the specified DMA module.
2237 * @retval None
2238 */
2239 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
2240 {
2241 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2242
2243 HAL_SPI_TxHalfCpltCallback(hspi);
2244 }
2245
2246 /**
2247 * @brief DMA SPI half receive process complete callback
2248 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
2249 * the configuration information for the specified DMA module.
2250 * @retval None
2251 */
2252 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
2253 {
2254 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2255
2256 HAL_SPI_RxHalfCpltCallback(hspi);
2257 }
2258
2259 /**
2260 * @brief DMA SPI Half transmit receive process complete callback
2261 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
2262 * the configuration information for the specified DMA module.
2263 * @retval None
2264 */
2265 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
2266 {
2267 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2268
2269 HAL_SPI_TxRxHalfCpltCallback(hspi);
2270 }
2271
2272 /**
2273 * @brief DMA SPI communication error callback
2274 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
2275 * the configuration information for the specified DMA module.
2276 * @retval None
2277 */
2278 static void SPI_DMAError(DMA_HandleTypeDef *hdma)
2279 {
2280 SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2281 hspi->TxXferCount = 0;
2282 hspi->RxXferCount = 0;
2283 hspi->State= HAL_SPI_STATE_READY;
2284 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2285 HAL_SPI_ErrorCallback(hspi);
2286 }
2287
2288 /**
2289 * @brief This function handles SPI Communication Timeout.
2290 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
2291 * the configuration information for SPI module.
2292 * @param Flag: SPI flag to check
2293 * @param Status: Flag status to check: RESET or set
2294 * @param Timeout: Timeout duration
2295 * @retval HAL status
2296 */
2297 static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
2298 {
2299 uint32_t tickstart = 0;
2300
2301 /* Get tick */
2302 tickstart = HAL_GetTick();
2303
2304 /* Wait until flag is set */
2305 if(Status == RESET)
2306 {
2307 while(__HAL_SPI_GET_FLAG(hspi, Flag) == RESET)
2308 {
2309 if(Timeout != HAL_MAX_DELAY)
2310 {
2311 if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
2312 {
2313 /* Disable the SPI and reset the CRC: the CRC value should be cleared
2314 on both master and slave sides in order to resynchronize the master
2315 and slave for their respective CRC calculation */
2316
2317 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
2318 __HAL_SPI_DISABLE_IT(hspi, (uint32_t)(SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
2319
2320 /* Disable SPI peripheral */
2321 __HAL_SPI_DISABLE(hspi);
2322
2323 /* Reset CRC Calculation */
2324 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2325 {
2326 SPI_RESET_CRC(hspi);
2327 }
2328
2329 hspi->State= HAL_SPI_STATE_READY;
2330
2331 /* Process Unlocked */
2332 __HAL_UNLOCK(hspi);
2333
2334 return HAL_TIMEOUT;
2335 }
2336 }
2337 }
2338 }
2339 else
2340 {
2341 while(__HAL_SPI_GET_FLAG(hspi, Flag) != RESET)
2342 {
2343 if(Timeout != HAL_MAX_DELAY)
2344 {
2345 if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
2346 {
2347 /* Disable the SPI and reset the CRC: the CRC value should be cleared
2348 on both master and slave sides in order to resynchronize the master
2349 and slave for their respective CRC calculation */
2350
2351 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
2352 __HAL_SPI_DISABLE_IT(hspi, (uint32_t)(SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
2353
2354 /* Disable SPI peripheral */
2355 __HAL_SPI_DISABLE(hspi);
2356
2357 /* Reset CRC Calculation */
2358 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2359 {
2360 SPI_RESET_CRC(hspi);
2361 }
2362
2363 hspi->State= HAL_SPI_STATE_READY;
2364
2365 /* Process Unlocked */
2366 __HAL_UNLOCK(hspi);
2367
2368 return HAL_TIMEOUT;
2369 }
2370 }
2371 }
2372 }
2373 return HAL_OK;
2374 }
2375 /**
2376 * @}
2377 */
2378
2379 #endif /* HAL_SPI_MODULE_ENABLED */
2380 /**
2381 * @}
2382 */
2383
2384 /**
2385 * @}
2386 */
2387
2388 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
2389
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