tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_tsc.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32l0xx_hal_tsc.h
   4   * @author  MCD Application Team
   5   * @version V1.2.0
   6   * @date    06-February-2015
   7   * @brief   This file contains all the functions prototypes for the TSC firmware
   8   *          library.
   9   ******************************************************************************
  10   * @attention
  11   *
  12   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
  13   *
  14   * Redistribution and use in source and binary forms, with or without modification,
  15   * are permitted provided that the following conditions are met:
  16   *   1. Redistributions of source code must retain the above copyright notice,
  17   *      this list of conditions and the following disclaimer.
  18   *   2. Redistributions in binary form must reproduce the above copyright notice,
  19   *      this list of conditions and the following disclaimer in the documentation
  20   *      and/or other materials provided with the distribution.
  21   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  22   *      may be used to endorse or promote products derived from this software
  23   *      without specific prior written permission.
  24   *
  25   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  26   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  27   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  28   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  29   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  30   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  31   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  32   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  33   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  34   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35   *
  36   ******************************************************************************
  37   */
  38
  39 #if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx)
  40 /* Define to prevent recursive inclusion -------------------------------------*/
  41 #ifndef __STM32L0xx_TSC_H
  42 #define __STM32L0xx_TSC_H
  43
  44 #ifdef __cplusplus
  45  extern "C" {
  46 #endif
  47
  48 /* Includes ------------------------------------------------------------------*/
  49 #include "stm32l0xx_hal_def.h"
  50
  51 /** @addtogroup STM32L0xx_HAL_Driver
  52   * @{
  53   */
  54
  55 /** @addtogroup TSC
  56   * @{
  57   */
  58
  59 /* Exported types ------------------------------------------------------------*/
  60
  61 /**
  62   * @brief TSC state structure definition
  63   */
  64 typedef enum
  65 {
  66   HAL_TSC_STATE_RESET  = 0x00, /*!< TSC registers have their reset value */
  67   HAL_TSC_STATE_READY  = 0x01, /*!< TSC registers are initialized or acquisition is completed with success */
  68   HAL_TSC_STATE_BUSY   = 0x02, /*!< TSC initialization or acquisition is on-going */
  69   HAL_TSC_STATE_ERROR  = 0x03  /*!< Acquisition is completed with max count error */
  70 } HAL_TSC_StateTypeDef;
  71
  72 /**
  73   * @brief TSC group status structure definition
  74   */
  75 typedef enum
  76 {
  77   TSC_GROUP_ONGOING   = 0x00, /*!< Acquisition on group is on-going or not started */
  78   TSC_GROUP_COMPLETED = 0x01  /*!< Acquisition on group is completed with success (no max count error) */
  79 } TSC_GroupStatusTypeDef;
  80
  81 /**
  82   * @brief TSC init structure definition
  83   */
  84 typedef struct
  85 {
  86   uint32_t CTPulseHighLength;       /*!< Charge-transfer high pulse length */
  87   uint32_t CTPulseLowLength;        /*!< Charge-transfer low pulse length */
  88   uint32_t SpreadSpectrum;          /*!< Spread spectrum activation */
  89   uint32_t SpreadSpectrumDeviation; /*!< Spread spectrum deviation */
  90   uint32_t SpreadSpectrumPrescaler; /*!< Spread spectrum prescaler */
  91   uint32_t PulseGeneratorPrescaler; /*!< Pulse generator prescaler */
  92   uint32_t MaxCountValue;           /*!< Max count value */
  93   uint32_t IODefaultMode;           /*!< IO default mode */
  94   uint32_t SynchroPinPolarity;      /*!< Synchro pin polarity */
  95   uint32_t AcquisitionMode;         /*!< Acquisition mode */
  96   uint32_t MaxCountInterrupt;       /*!< Max count interrupt activation */
  97   uint32_t ChannelIOs;              /*!< Channel IOs mask */
  98   uint32_t ShieldIOs;               /*!< Shield IOs mask */
  99   uint32_t SamplingIOs;             /*!< Sampling IOs mask */
 100 } TSC_InitTypeDef;
 101
 102 /**
 103   * @brief TSC IOs configuration structure definition
 104   */
 105 typedef struct
 106 {
 107   uint32_t ChannelIOs;  /*!< Channel IOs mask */
 108   uint32_t ShieldIOs;   /*!< Shield IOs mask */
 109   uint32_t SamplingIOs; /*!< Sampling IOs mask */
 110 } TSC_IOConfigTypeDef;
 111
 112 /**
 113   * @brief  TSC handle Structure definition
 114   */
 115 typedef struct
 116 {
 117   TSC_TypeDef               *Instance; /*!< Register base address */
 118   TSC_InitTypeDef           Init;      /*!< Initialization parameters */
 119   __IO HAL_TSC_StateTypeDef State;     /*!< Peripheral state */
 120   HAL_LockTypeDef           Lock;      /*!< Lock feature */
 121 } TSC_HandleTypeDef;
 122
 123 /* Exported constants --------------------------------------------------------*/
 124
 125 /** @defgroup TSC_Exported_Constants
 126   * @{
 127   */
 128
 129 #define IS_TSC_ALL_INSTANCE(PERIPH) ((PERIPH) == TSC)
 130
 131 #define TSC_CTPH_1CYCLE   ((uint32_t)((uint32_t) 0 << 28))
 132 #define TSC_CTPH_2CYCLES  ((uint32_t)((uint32_t) 1 << 28))
 133 #define TSC_CTPH_3CYCLES  ((uint32_t)((uint32_t) 2 << 28))
 134 #define TSC_CTPH_4CYCLES  ((uint32_t)((uint32_t) 3 << 28))
 135 #define TSC_CTPH_5CYCLES  ((uint32_t)((uint32_t) 4 << 28))
 136 #define TSC_CTPH_6CYCLES  ((uint32_t)((uint32_t) 5 << 28))
 137 #define TSC_CTPH_7CYCLES  ((uint32_t)((uint32_t) 6 << 28))
 138 #define TSC_CTPH_8CYCLES  ((uint32_t)((uint32_t) 7 << 28))
 139 #define TSC_CTPH_9CYCLES  ((uint32_t)((uint32_t) 8 << 28))
 140 #define TSC_CTPH_10CYCLES ((uint32_t)((uint32_t) 9 << 28))
 141 #define TSC_CTPH_11CYCLES ((uint32_t)((uint32_t)10 << 28))
 142 #define TSC_CTPH_12CYCLES ((uint32_t)((uint32_t)11 << 28))
 143 #define TSC_CTPH_13CYCLES ((uint32_t)((uint32_t)12 << 28))
 144 #define TSC_CTPH_14CYCLES ((uint32_t)((uint32_t)13 << 28))
 145 #define TSC_CTPH_15CYCLES ((uint32_t)((uint32_t)14 << 28))
 146 #define TSC_CTPH_16CYCLES ((uint32_t)((uint32_t)15 << 28))
 147 #define IS_TSC_CTPH(VAL) (((VAL) == TSC_CTPH_1CYCLE) || \
 148                           ((VAL) == TSC_CTPH_2CYCLES) || \
 149                           ((VAL) == TSC_CTPH_3CYCLES) || \
 150                           ((VAL) == TSC_CTPH_4CYCLES) || \
 151                           ((VAL) == TSC_CTPH_5CYCLES) || \
 152                           ((VAL) == TSC_CTPH_6CYCLES) || \
 153                           ((VAL) == TSC_CTPH_7CYCLES) || \
 154                           ((VAL) == TSC_CTPH_8CYCLES) || \
 155                           ((VAL) == TSC_CTPH_9CYCLES) || \
 156                           ((VAL) == TSC_CTPH_10CYCLES) || \
 157                           ((VAL) == TSC_CTPH_11CYCLES) || \
 158                           ((VAL) == TSC_CTPH_12CYCLES) || \
 159                           ((VAL) == TSC_CTPH_13CYCLES) || \
 160                           ((VAL) == TSC_CTPH_14CYCLES) || \
 161                           ((VAL) == TSC_CTPH_15CYCLES) || \
 162                           ((VAL) == TSC_CTPH_16CYCLES))
 163
 164 #define TSC_CTPL_1CYCLE   ((uint32_t)((uint32_t) 0 << 24))
 165 #define TSC_CTPL_2CYCLES  ((uint32_t)((uint32_t) 1 << 24))
 166 #define TSC_CTPL_3CYCLES  ((uint32_t)((uint32_t) 2 << 24))
 167 #define TSC_CTPL_4CYCLES  ((uint32_t)((uint32_t) 3 << 24))
 168 #define TSC_CTPL_5CYCLES  ((uint32_t)((uint32_t) 4 << 24))
 169 #define TSC_CTPL_6CYCLES  ((uint32_t)((uint32_t) 5 << 24))
 170 #define TSC_CTPL_7CYCLES  ((uint32_t)((uint32_t) 6 << 24))
 171 #define TSC_CTPL_8CYCLES  ((uint32_t)((uint32_t) 7 << 24))
 172 #define TSC_CTPL_9CYCLES  ((uint32_t)((uint32_t) 8 << 24))
 173 #define TSC_CTPL_10CYCLES ((uint32_t)((uint32_t) 9 << 24))
 174 #define TSC_CTPL_11CYCLES ((uint32_t)((uint32_t)10 << 24))
 175 #define TSC_CTPL_12CYCLES ((uint32_t)((uint32_t)11 << 24))
 176 #define TSC_CTPL_13CYCLES ((uint32_t)((uint32_t)12 << 24))
 177 #define TSC_CTPL_14CYCLES ((uint32_t)((uint32_t)13 << 24))
 178 #define TSC_CTPL_15CYCLES ((uint32_t)((uint32_t)14 << 24))
 179 #define TSC_CTPL_16CYCLES ((uint32_t)((uint32_t)15 << 24))
 180 #define IS_TSC_CTPL(VAL) (((VAL) == TSC_CTPL_1CYCLE) || \
 181                           ((VAL) == TSC_CTPL_2CYCLES) || \
 182                           ((VAL) == TSC_CTPL_3CYCLES) || \
 183                           ((VAL) == TSC_CTPL_4CYCLES) || \
 184                           ((VAL) == TSC_CTPL_5CYCLES) || \
 185                           ((VAL) == TSC_CTPL_6CYCLES) || \
 186                           ((VAL) == TSC_CTPL_7CYCLES) || \
 187                           ((VAL) == TSC_CTPL_8CYCLES) || \
 188                           ((VAL) == TSC_CTPL_9CYCLES) || \
 189                           ((VAL) == TSC_CTPL_10CYCLES) || \
 190                           ((VAL) == TSC_CTPL_11CYCLES) || \
 191                           ((VAL) == TSC_CTPL_12CYCLES) || \
 192                           ((VAL) == TSC_CTPL_13CYCLES) || \
 193                           ((VAL) == TSC_CTPL_14CYCLES) || \
 194                           ((VAL) == TSC_CTPL_15CYCLES) || \
 195                           ((VAL) == TSC_CTPL_16CYCLES))
 196
 197 #define IS_TSC_SS(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE))
 198
 199 #define IS_TSC_SSD(VAL) (((VAL) == 0) || (((VAL) > 0) && ((VAL) < 128)))
 200
 201 #define TSC_SS_PRESC_DIV1 ((uint32_t)0)
 202 #define TSC_SS_PRESC_DIV2  (TSC_CR_SSPSC)
 203 #define IS_TSC_SS_PRESC(VAL) (((VAL) == TSC_SS_PRESC_DIV1) || ((VAL) == TSC_SS_PRESC_DIV2))
 204
 205 #define TSC_PG_PRESC_DIV1   ((uint32_t)(0 << 12))
 206 #define TSC_PG_PRESC_DIV2   ((uint32_t)(1 << 12))
 207 #define TSC_PG_PRESC_DIV4   ((uint32_t)(2 << 12))
 208 #define TSC_PG_PRESC_DIV8   ((uint32_t)(3 << 12))
 209 #define TSC_PG_PRESC_DIV16  ((uint32_t)(4 << 12))
 210 #define TSC_PG_PRESC_DIV32  ((uint32_t)(5 << 12))
 211 #define TSC_PG_PRESC_DIV64  ((uint32_t)(6 << 12))
 212 #define TSC_PG_PRESC_DIV128 ((uint32_t)(7 << 12))
 213 #define IS_TSC_PG_PRESC(VAL) (((VAL) == TSC_PG_PRESC_DIV1) || \
 214                               ((VAL) == TSC_PG_PRESC_DIV2) || \
 215                               ((VAL) == TSC_PG_PRESC_DIV4) || \
 216                               ((VAL) == TSC_PG_PRESC_DIV8) || \
 217                               ((VAL) == TSC_PG_PRESC_DIV16) || \
 218                               ((VAL) == TSC_PG_PRESC_DIV32) || \
 219                               ((VAL) == TSC_PG_PRESC_DIV64) || \
 220                               ((VAL) == TSC_PG_PRESC_DIV128))
 221
 222 #define TSC_MCV_255   ((uint32_t)(0 << 5))
 223 #define TSC_MCV_511   ((uint32_t)(1 << 5))
 224 #define TSC_MCV_1023  ((uint32_t)(2 << 5))
 225 #define TSC_MCV_2047  ((uint32_t)(3 << 5))
 226 #define TSC_MCV_4095  ((uint32_t)(4 << 5))
 227 #define TSC_MCV_8191  ((uint32_t)(5 << 5))
 228 #define TSC_MCV_16383 ((uint32_t)(6 << 5))
 229 #define IS_TSC_MCV(VAL) (((VAL) == TSC_MCV_255) || \
 230                          ((VAL) == TSC_MCV_511) || \
 231                          ((VAL) == TSC_MCV_1023) || \
 232                          ((VAL) == TSC_MCV_2047) || \
 233                          ((VAL) == TSC_MCV_4095) || \
 234                          ((VAL) == TSC_MCV_8191) || \
 235                          ((VAL) == TSC_MCV_16383))
 236
 237 #define TSC_IODEF_OUT_PP_LOW ((uint32_t)0)
 238 #define TSC_IODEF_IN_FLOAT   (TSC_CR_IODEF)
 239 #define IS_TSC_IODEF(VAL) (((VAL) == TSC_IODEF_OUT_PP_LOW) || ((VAL) == TSC_IODEF_IN_FLOAT))
 240
 241 #define TSC_SYNC_POLARITY_FALLING      ((uint32_t)0)
 242 #define TSC_SYNC_POLARITY_RISING (TSC_CR_SYNCPOL)
 243 #define IS_TSC_SYNC_POL(VAL) (((VAL) == TSC_SYNC_POL_FALL) || ((VAL) == TSC_SYNC_POL_RISE_HIGH))
 244
 245 #define TSC_ACQ_MODE_NORMAL  ((uint32_t)0)
 246 #define TSC_ACQ_MODE_SYNCHRO (TSC_CR_AM)
 247 #define IS_TSC_ACQ_MODE(VAL) (((VAL) == TSC_ACQ_MODE_NORMAL) || ((VAL) == TSC_ACQ_MODE_SYNCHRO))
 248
 249 #define TSC_IOMODE_UNUSED   ((uint32_t)0)
 250 #define TSC_IOMODE_CHANNEL  ((uint32_t)1)
 251 #define TSC_IOMODE_SHIELD   ((uint32_t)2)
 252 #define TSC_IOMODE_SAMPLING ((uint32_t)3)
 253 #define IS_TSC_IOMODE(VAL) (((VAL) == TSC_IOMODE_UNUSED) || \
 254                             ((VAL) == TSC_IOMODE_CHANNEL) || \
 255                             ((VAL) == TSC_IOMODE_SHIELD) || \
 256                             ((VAL) == TSC_IOMODE_SAMPLING))
 257
 258 /** @defgroup TSC_interrupts_definition
 259   * @{
 260   */
 261 #define TSC_IT_EOA ((uint32_t)TSC_IER_EOAIE)
 262 #define TSC_IT_MCE ((uint32_t)TSC_IER_MCEIE)
 263 #define IS_TSC_MCE_IT(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE))
 264 /**
 265   * @}
 266   */
 267
 268 /** @defgroup TSC_flags_definition
 269   * @{
 270   */
 271 #define TSC_FLAG_EOA ((uint32_t)TSC_ISR_EOAF)
 272 #define TSC_FLAG_MCE ((uint32_t)TSC_ISR_MCEF)
 273 /**
 274   * @}
 275   */
 276
 277 #define TSC_NB_OF_GROUPS (8)
 278
 279 #define TSC_GROUP1 ((uint32_t)0x00000001)
 280 #define TSC_GROUP2 ((uint32_t)0x00000002)
 281 #define TSC_GROUP3 ((uint32_t)0x00000004)
 282 #define TSC_GROUP4 ((uint32_t)0x00000008)
 283 #define TSC_GROUP5 ((uint32_t)0x00000010)
 284 #define TSC_GROUP6 ((uint32_t)0x00000020)
 285 #define TSC_GROUP7 ((uint32_t)0x00000040)
 286 #define TSC_GROUP8 ((uint32_t)0x00000080)
 287 #define TSC_ALL_GROUPS ((uint32_t)0x000000FF)
 288
 289 #define TSC_GROUP1_IDX ((uint32_t)0)
 290 #define TSC_GROUP2_IDX ((uint32_t)1)
 291 #define TSC_GROUP3_IDX ((uint32_t)2)
 292 #define TSC_GROUP4_IDX ((uint32_t)3)
 293 #define TSC_GROUP5_IDX ((uint32_t)4)
 294 #define TSC_GROUP6_IDX ((uint32_t)5)
 295 #define TSC_GROUP7_IDX ((uint32_t)6)
 296 #define TSC_GROUP8_IDX ((uint32_t)7)
 297 #define IS_GROUP_INDEX(VAL) (((VAL) == 0) || (((VAL) > 0) && ((VAL) < TSC_NB_OF_GROUPS)))
 298
 299 #define TSC_GROUP1_IO1 ((uint32_t)0x00000001)
 300 #define TSC_GROUP1_IO2 ((uint32_t)0x00000002)
 301 #define TSC_GROUP1_IO3 ((uint32_t)0x00000004)
 302 #define TSC_GROUP1_IO4 ((uint32_t)0x00000008)
 303 #define TSC_GROUP1_ALL_IOS ((uint32_t)0x0000000F)
 304
 305 #define TSC_GROUP2_IO1 ((uint32_t)0x00000010)
 306 #define TSC_GROUP2_IO2 ((uint32_t)0x00000020)
 307 #define TSC_GROUP2_IO3 ((uint32_t)0x00000040)
 308 #define TSC_GROUP2_IO4 ((uint32_t)0x00000080)
 309 #define TSC_GROUP2_ALL_IOS ((uint32_t)0x000000F0)
 310
 311 #define TSC_GROUP3_IO1 ((uint32_t)0x00000100)
 312 #define TSC_GROUP3_IO2 ((uint32_t)0x00000200)
 313 #define TSC_GROUP3_IO3 ((uint32_t)0x00000400)
 314 #define TSC_GROUP3_IO4 ((uint32_t)0x00000800)
 315 #define TSC_GROUP3_ALL_IOS ((uint32_t)0x00000F00)
 316
 317 #define TSC_GROUP4_IO1 ((uint32_t)0x00001000)
 318 #define TSC_GROUP4_IO2 ((uint32_t)0x00002000)
 319 #define TSC_GROUP4_IO3 ((uint32_t)0x00004000)
 320 #define TSC_GROUP4_IO4 ((uint32_t)0x00008000)
 321 #define TSC_GROUP4_ALL_IOS ((uint32_t)0x0000F000)
 322
 323 #define TSC_GROUP5_IO1 ((uint32_t)0x00010000)
 324 #define TSC_GROUP5_IO2 ((uint32_t)0x00020000)
 325 #define TSC_GROUP5_IO3 ((uint32_t)0x00040000)
 326 #define TSC_GROUP5_IO4 ((uint32_t)0x00080000)
 327 #define TSC_GROUP5_ALL_IOS ((uint32_t)0x000F0000)
 328
 329 #define TSC_GROUP6_IO1 ((uint32_t)0x00100000)
 330 #define TSC_GROUP6_IO2 ((uint32_t)0x00200000)
 331 #define TSC_GROUP6_IO3 ((uint32_t)0x00400000)
 332 #define TSC_GROUP6_IO4 ((uint32_t)0x00800000)
 333 #define TSC_GROUP6_ALL_IOS ((uint32_t)0x00F00000)
 334
 335 #define TSC_GROUP7_IO1 ((uint32_t)0x01000000)
 336 #define TSC_GROUP7_IO2 ((uint32_t)0x02000000)
 337 #define TSC_GROUP7_IO3 ((uint32_t)0x04000000)
 338 #define TSC_GROUP7_IO4 ((uint32_t)0x08000000)
 339 #define TSC_GROUP7_ALL_IOS ((uint32_t)0x0F000000)
 340
 341 #define TSC_GROUP8_IO1 ((uint32_t)0x10000000)
 342 #define TSC_GROUP8_IO2 ((uint32_t)0x20000000)
 343 #define TSC_GROUP8_IO3 ((uint32_t)0x40000000)
 344 #define TSC_GROUP8_IO4 ((uint32_t)0x80000000)
 345 #define TSC_GROUP8_ALL_IOS ((uint32_t)0xF0000000)
 346
 347 #define TSC_ALL_GROUPS_ALL_IOS ((uint32_t)0xFFFFFFFF)
 348
 349 /**
 350   * @}
 351   */
 352
 353 /* Exported macro ------------------------------------------------------------*/
 354
 355 /** @brief Reset TSC handle state
 356   * @param  __HANDLE__: TSC handle
 357   * @retval None
 358   */
 359 #define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET)
 360
 361 /**
 362   * @brief Enable the TSC peripheral.
 363   * @param  __HANDLE__: TSC handle
 364   * @retval None
 365   */
 366 #define __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE)
 367
 368 /**
 369   * @brief Disable the TSC peripheral.
 370   * @param  __HANDLE__: TSC handle
 371   * @retval None
 372   */
 373 #define __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_TSCE))
 374
 375 /**
 376   * @brief Start acquisition
 377   * @param  __HANDLE__: TSC handle
 378   * @retval None
 379   */
 380 #define __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START)
 381
 382 /**
 383   * @brief Stop acquisition
 384   * @param  __HANDLE__: TSC handle
 385   * @retval None
 386   */
 387 #define __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_START))
 388
 389 /**
 390   * @brief Set IO default mode to output push-pull low
 391   * @param  __HANDLE__: TSC handle
 392   * @retval None
 393   */
 394 #define __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_IODEF))
 395
 396 /**
 397   * @brief Set IO default mode to input floating
 398   * @param  __HANDLE__: TSC handle
 399   * @retval None
 400   */
 401 #define __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF)
 402
 403 /**
 404   * @brief Set synchronization polarity to falling edge
 405   * @param  __HANDLE__: TSC handle
 406   * @retval None
 407   */
 408 #define __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_SYNCPOL))
 409
 410 /**
 411   * @brief Set synchronization polarity to rising edge and high level
 412   * @param  __HANDLE__: TSC handle
 413   * @retval None
 414   */
 415 #define __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL)
 416
 417 /**
 418   * @brief Enable TSC interrupt.
 419   * @param  __HANDLE__: TSC handle
 420   * @param  __INTERRUPT__: TSC interrupt
 421   * @retval None
 422   */
 423 #define __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
 424
 425 /**
 426   * @brief Disable TSC interrupt.
 427   * @param  __HANDLE__: TSC handle
 428   * @param  __INTERRUPT__: TSC interrupt
 429   * @retval None
 430   */
 431 #define __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (uint32_t)(~(__INTERRUPT__)))
 432
 433 /** @brief Check if the specified TSC interrupt source is enabled or disabled.
 434   * @param  __HANDLE__: TSC Handle
 435   * @param  __INTERRUPT__: TSC interrupt
 436   * @retval SET or RESET
 437   */
 438 #define __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
 439
 440 /**
 441   * @brief Get the selected TSC's flag status.
 442   * @param  __HANDLE__: TSC handle
 443   * @param  __FLAG__: TSC flag
 444   * @retval SET or RESET
 445   */
 446 #define __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
 447
 448 /**
 449   * @brief Clear the TSC's pending flag.
 450   * @param  __HANDLE__: TSC handle
 451   * @param  __FLAG__: TSC flag
 452   * @retval None
 453   */
 454 #define __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
 455
 456 /**
 457   * @brief Enable schmitt trigger hysteresis on a group of IOs
 458   * @param  __HANDLE__: TSC handle
 459   * @param  __GX_IOY_MASK__: IOs mask
 460   * @retval None
 461   */
 462 #define __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__))
 463
 464 /**
 465   * @brief Disable schmitt trigger hysteresis on a group of IOs
 466   * @param  __HANDLE__: TSC handle
 467   * @param  __GX_IOY_MASK__: IOs mask
 468   * @retval None
 469   */
 470 #define __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR &= (uint32_t)(~(__GX_IOY_MASK__)))
 471
 472 /**
 473   * @brief Open analog switch on a group of IOs
 474   * @param  __HANDLE__: TSC handle
 475   * @param  __GX_IOY_MASK__: IOs mask
 476   * @retval None
 477   */
 478 #define __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR &= (uint32_t)(~(__GX_IOY_MASK__)))
 479
 480 /**
 481   * @brief Close analog switch on a group of IOs
 482   * @param  __HANDLE__: TSC handle
 483   * @param  __GX_IOY_MASK__: IOs mask
 484   * @retval None
 485   */
 486 #define __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__))
 487
 488 /**
 489   * @brief Enable a group of IOs in channel mode
 490   * @param  __HANDLE__: TSC handle
 491   * @param  __GX_IOY_MASK__: IOs mask
 492   * @retval None
 493   */
 494 #define __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__))
 495
 496 /**
 497   * @brief Disable a group of channel IOs
 498   * @param  __HANDLE__: TSC handle
 499   * @param  __GX_IOY_MASK__: IOs mask
 500   * @retval None
 501   */
 502 #define __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR &= (uint32_t)(~(__GX_IOY_MASK__)))
 503
 504 /**
 505   * @brief Enable a group of IOs in sampling mode
 506   * @param  __HANDLE__: TSC handle
 507   * @param  __GX_IOY_MASK__: IOs mask
 508   * @retval None
 509   */
 510 #define __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__))
 511
 512 /**
 513   * @brief Disable a group of sampling IOs
 514   * @param  __HANDLE__: TSC handle
 515   * @param  __GX_IOY_MASK__: IOs mask
 516   * @retval None
 517   */
 518 #define __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (uint32_t)(~(__GX_IOY_MASK__)))
 519
 520 /**
 521   * @brief Enable acquisition groups
 522   * @param  __HANDLE__: TSC handle
 523   * @param  __GX_MASK__: Groups mask
 524   * @retval None
 525   */
 526 #define __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__))
 527
 528 /**
 529   * @brief Disable acquisition groups
 530   * @param  __HANDLE__: TSC handle
 531   * @param  __GX_MASK__: Groups mask
 532   * @retval None
 533   */
 534 #define __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (uint32_t)(~(__GX_MASK__)))
 535
 536 /** @brief Gets acquisition group status
 537   * @param  __HANDLE__: TSC Handle
 538   * @param  __GX_INDEX__: Group index
 539   * @retval SET or RESET
 540   */
 541 #define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \
 542 ((((__HANDLE__)->Instance->IOGCSR & (uint32_t)((uint32_t)1 << ((__GX_INDEX__) + (uint32_t)16))) == (uint32_t)((uint32_t)1 << ((__GX_INDEX__) + (uint32_t)16))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING)
 543
 544 /* Exported functions --------------------------------------------------------*/
 545
 546 /* Initialization and de-initialization functions *****************************/
 547 HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc);
 548 HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc);
 549 void HAL_TSC_MspInit(TSC_HandleTypeDef* htsc);
 550 void HAL_TSC_MspDeInit(TSC_HandleTypeDef* htsc);
 551
 552 /* IO operation functions *****************************************************/
 553 HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef* htsc);
 554 HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef* htsc);
 555 HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef* htsc);
 556 HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef* htsc);
 557 TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef* htsc, uint32_t gx_index);
 558 uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef* htsc, uint32_t gx_index);
 559
 560 /* Peripheral Control functions ***********************************************/
 561 HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef* htsc, TSC_IOConfigTypeDef* config);
 562 HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef* htsc, uint32_t choice);
 563
 564 /* Peripheral State and Error functions ***************************************/
 565 HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef* htsc);
 566 HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef* htsc);
 567 void HAL_TSC_IRQHandler(TSC_HandleTypeDef* htsc);
 568
 569 /* Callback functions *********************************************************/
 570 void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef* htsc);
 571 void HAL_TSC_ErrorCallback(TSC_HandleTypeDef* htsc);
 572
 573 /**
 574   * @}
 575   */
 576
 577 /**
 578   * @}
 579   */
 580
 581 #ifdef __cplusplus
 582 }
 583 #endif
 584
 585 #endif /*__STM32L0xx_TSC_H */
 586 #endif /* #if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx) */
 587
 588 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
 589