tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/system_stm32l1xx.c

   1 /**
   2   ******************************************************************************
   3   * @file    system_stm32l1xx.c
   4   * @author  MCD Application Team
   5   * @version V2.0.0
   6   * @date    5-September-2014
   7   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
   8   *
   9   *   This file provides two functions and one global variable to be called from
  10   *   user application:
  11   *      - SystemInit(): This function is called at startup just after reset and
  12   *                      before branch to main program. This call is made inside
  13   *                      the "startup_stm32l1xx.s" file.
  14   *
  15   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
  16   *                                  by the user application to setup the SysTick
  17   *                                  timer or configure other parameters.
  18   *
  19   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
  20   *                                 be called whenever the core clock is changed
  21   *                                 during program execution.
  22   *
  23   * This file configures the system clock as follows:
  24   *-----------------------------------------------------------------------------
  25   * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
  26   *                                    | (external 8 MHz clock) | (internal 16 MHz)
  27   *                                    | 2- PLL_HSE_XTAL        |
  28   *                                    | (external 8 MHz xtal)  |
  29   *-----------------------------------------------------------------------------
  30   * SYSCLK(MHz)                        | 24                     | 32
  31   *-----------------------------------------------------------------------------
  32   * AHBCLK (MHz)                       | 24                     | 32
  33   *-----------------------------------------------------------------------------
  34   * APB1CLK (MHz)                      | 24                     | 32
  35   *-----------------------------------------------------------------------------
  36   * APB2CLK (MHz)                      | 24                     | 32
  37   *-----------------------------------------------------------------------------
  38   * USB capable (48 MHz precise clock) | YES                    | NO
  39   *-----------------------------------------------------------------------------
  40   ******************************************************************************
  41   * @attention
  42   *
  43   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
  44   *
  45   * Redistribution and use in source and binary forms, with or without modification,
  46   * are permitted provided that the following conditions are met:
  47   *   1. Redistributions of source code must retain the above copyright notice,
  48   *      this list of conditions and the following disclaimer.
  49   *   2. Redistributions in binary form must reproduce the above copyright notice,
  50   *      this list of conditions and the following disclaimer in the documentation
  51   *      and/or other materials provided with the distribution.
  52   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  53   *      may be used to endorse or promote products derived from this software
  54   *      without specific prior written permission.
  55   *
  56   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  57   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  58   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  59   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  60   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  61   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  62   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  63   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  64   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  65   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  66   *
  67   ******************************************************************************
  68   */
  69
  70 /** @addtogroup CMSIS
  71   * @{
  72   */
  73
  74 /** @addtogroup stm32l1xx_system
  75   * @{
  76   */
  77
  78 /** @addtogroup STM32L1xx_System_Private_Includes
  79   * @{
  80   */
  81
  82 #include "stm32l1xx.h"
  83 #include "hal_tick.h"
  84
  85 /**
  86   * @}
  87   */
  88
  89 /** @addtogroup STM32L1xx_System_Private_TypesDefinitions
  90   * @{
  91   */
  92
  93 /**
  94   * @}
  95   */
  96
  97 /** @addtogroup STM32L1xx_System_Private_Defines
  98   * @{
  99   */
 100 #if !defined  (HSE_VALUE)
 101   #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
 102                                                 This value can be provided and adapted by the user application. */
 103 #endif /* HSE_VALUE */
 104
 105 #if !defined  (HSI_VALUE)
 106   #define HSI_VALUE    ((uint32_t)16000000) /*!< Default value of the Internal oscillator in Hz.
 107                                                 This value can be provided and adapted by the user application. */
 108 #endif /* HSI_VALUE */
 109
 110 /*!< Uncomment the following line if you need to use external SRAM mounted
 111      on STM32L152D_EVAL board as data memory  */
 112 /* #define DATA_IN_ExtSRAM */
 113
 114 /*!< Uncomment the following line if you need to relocate your vector Table in
 115      Internal SRAM. */
 116 /* #define VECT_TAB_SRAM */
 117 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
 118                                   This value must be a multiple of 0x200. */
 119 /**
 120   * @}
 121   */
 122
 123 /** @addtogroup STM32L1xx_System_Private_Macros
 124   * @{
 125   */
 126
 127 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
 128 #define USE_PLL_HSE_EXTC (1) /* Use external clock */
 129 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
 130
 131 /**
 132   * @}
 133   */
 134
 135 /** @addtogroup STM32L1xx_System_Private_Variables
 136   * @{
 137   */
 138   /* This variable is updated in three ways:
 139       1) by calling CMSIS function SystemCoreClockUpdate()
 140       2) by calling HAL API function HAL_RCC_GetHCLKFreq()
 141       3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
 142          Note: If you use this function to configure the system clock; then there
 143                is no need to call the 2 first functions listed above, since SystemCoreClock
 144                variable is updated automatically.
 145   */
 146 uint32_t SystemCoreClock = 32000000; /* Default with HSI. Will be updated if HSE is used */
 147 const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
 148 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
 149
 150 /**
 151   * @}
 152   */
 153
 154 /** @addtogroup STM32L1xx_System_Private_FunctionPrototypes
 155   * @{
 156   */
 157
 158 #if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
 159 #ifdef DATA_IN_ExtSRAM
 160   static void SystemInit_ExtMemCtl(void);
 161 #endif /* DATA_IN_ExtSRAM */
 162 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
 163
 164 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
 165 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
 166 #endif
 167
 168 uint8_t SetSysClock_PLL_HSI(void);
 169
 170 /**
 171   * @}
 172   */
 173
 174 /** @addtogroup STM32L1xx_System_Private_Functions
 175   * @{
 176   */
 177
 178 /**
 179   * @brief  Setup the microcontroller system.
 180   *         Initialize the Embedded Flash Interface, the PLL and update the
 181   *         SystemCoreClock variable.
 182   * @param  None
 183   * @retval None
 184   */
 185 void SystemInit (void)
 186 {
 187   /*!< Set MSION bit */
 188   RCC->CR |= (uint32_t)0x00000100;
 189
 190   /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
 191   RCC->CFGR &= (uint32_t)0x88FFC00C;
 192
 193   /*!< Reset HSION, HSEON, CSSON and PLLON bits */
 194   RCC->CR &= (uint32_t)0xEEFEFFFE;
 195
 196   /*!< Reset HSEBYP bit */
 197   RCC->CR &= (uint32_t)0xFFFBFFFF;
 198
 199   /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
 200   RCC->CFGR &= (uint32_t)0xFF02FFFF;
 201
 202   /*!< Disable all interrupts */
 203   RCC->CIR = 0x00000000;
 204
 205 #ifdef DATA_IN_ExtSRAM
 206   SystemInit_ExtMemCtl();
 207 #endif /* DATA_IN_ExtSRAM */
 208
 209 #ifdef VECT_TAB_SRAM
 210   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
 211 #else
 212   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
 213 #endif
 214
 215   /* Configure the Cube driver */
 216   SystemCoreClock = 16000000; // At this stage the HSI is used as system clock
 217   HAL_Init();
 218
 219   /* Configure the System clock source, PLL Multiplier and Divider factors,
 220      AHB/APBx prescalers and Flash settings */
 221   SetSysClock();
 222
 223   /* Reset the timer to avoid issues after the RAM initialization */
 224   TIM_MST_RESET_ON;
 225   TIM_MST_RESET_OFF;
 226 }
 227
 228 /**
 229   * @brief  Update SystemCoreClock according to Clock Register Values
 230   *         The SystemCoreClock variable contains the core clock (HCLK), it can
 231   *         be used by the user application to setup the SysTick timer or configure
 232   *         other parameters.
 233   *
 234   * @note   Each time the core clock (HCLK) changes, this function must be called
 235   *         to update SystemCoreClock variable value. Otherwise, any configuration
 236   *         based on this variable will be incorrect.
 237   *
 238   * @note   - The system frequency computed by this function is not the real
 239   *           frequency in the chip. It is calculated based on the predefined
 240   *           constant and the selected clock source:
 241   *
 242   *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
 243   *             value as defined by the MSI range.
 244   *
 245   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
 246   *
 247   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
 248   *
 249   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
 250   *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
 251   *
 252   *         (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value
 253   *             16 MHz) but the real value may vary depending on the variations
 254   *             in voltage and temperature.
 255   *
 256   *         (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value
 257   *              8 MHz), user has to ensure that HSE_VALUE is same as the real
 258   *              frequency of the crystal used. Otherwise, this function may
 259   *              have wrong result.
 260   *
 261   *         - The result of this function could be not correct when using fractional
 262   *           value for HSE crystal.
 263   * @param  None
 264   * @retval None
 265   */
 266 void SystemCoreClockUpdate (void)
 267 {
 268   uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
 269
 270   /* Get SYSCLK source -------------------------------------------------------*/
 271   tmp = RCC->CFGR & RCC_CFGR_SWS;
 272
 273   switch (tmp)
 274   {
 275     case 0x00:  /* MSI used as system clock */
 276       msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
 277       SystemCoreClock = (32768 * (1 << (msirange + 1)));
 278       break;
 279     case 0x04:  /* HSI used as system clock */
 280       SystemCoreClock = HSI_VALUE;
 281       break;
 282     case 0x08:  /* HSE used as system clock */
 283       SystemCoreClock = HSE_VALUE;
 284       break;
 285     case 0x0C:  /* PLL used as system clock */
 286       /* Get PLL clock source and multiplication factor ----------------------*/
 287       pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
 288       plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
 289       pllmul = PLLMulTable[(pllmul >> 18)];
 290       plldiv = (plldiv >> 22) + 1;
 291
 292       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
 293
 294       if (pllsource == 0x00)
 295       {
 296         /* HSI oscillator clock selected as PLL clock entry */
 297         SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
 298       }
 299       else
 300       {
 301         /* HSE selected as PLL clock entry */
 302         SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
 303       }
 304       break;
 305     default: /* MSI used as system clock */
 306       msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
 307       SystemCoreClock = (32768 * (1 << (msirange + 1)));
 308       break;
 309   }
 310   /* Compute HCLK clock frequency --------------------------------------------*/
 311   /* Get HCLK prescaler */
 312   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
 313   /* HCLK clock frequency */
 314   SystemCoreClock >>= tmp;
 315 }
 316
 317 #if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
 318 #ifdef DATA_IN_ExtSRAM
 319 /**
 320   * @brief  Setup the external memory controller.
 321   *         Called in SystemInit() function before jump to main.
 322   *         This function configures the external SRAM mounted on STM32L152D_EVAL board
 323   *         This SRAM will be used as program data memory (including heap and stack).
 324   * @param  None
 325   * @retval None
 326   */
 327 void SystemInit_ExtMemCtl(void)
 328 {
 329 /*-- GPIOs Configuration -----------------------------------------------------*/
 330 /*
 331  +-------------------+--------------------+------------------+------------------+
 332  +                       SRAM pins assignment                                   +
 333  +-------------------+--------------------+------------------+------------------+
 334  | PD0  <-> FSMC_D2  | PE0  <-> FSMC_NBL0 | PF0  <-> FSMC_A0 | PG0 <-> FSMC_A10 |
 335  | PD1  <-> FSMC_D3  | PE1  <-> FSMC_NBL1 | PF1  <-> FSMC_A1 | PG1 <-> FSMC_A11 |
 336  | PD4  <-> FSMC_NOE | PE7  <-> FSMC_D4   | PF2  <-> FSMC_A2 | PG2 <-> FSMC_A12 |
 337  | PD5  <-> FSMC_NWE | PE8  <-> FSMC_D5   | PF3  <-> FSMC_A3 | PG3 <-> FSMC_A13 |
 338  | PD8  <-> FSMC_D13 | PE9  <-> FSMC_D6   | PF4  <-> FSMC_A4 | PG4 <-> FSMC_A14 |
 339  | PD9  <-> FSMC_D14 | PE10 <-> FSMC_D7   | PF5  <-> FSMC_A5 | PG5 <-> FSMC_A15 |
 340  | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8   | PF12 <-> FSMC_A6 | PG10<-> FSMC_NE2 |
 341  | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9   | PF13 <-> FSMC_A7 |------------------+
 342  | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10  | PF14 <-> FSMC_A8 |
 343  | PD13 <-> FSMC_A18 | PE14 <-> FSMC_D11  | PF15 <-> FSMC_A9 |
 344  | PD14 <-> FSMC_D0  | PE15 <-> FSMC_D12  |------------------+
 345  | PD15 <-> FSMC_D1  |--------------------+
 346  +-------------------+
 347 */
 348
 349   /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
 350   RCC->AHBENR   = 0x000080D8;
 351
 352   /* Connect PDx pins to FSMC Alternate function */
 353   GPIOD->AFR[0]  = 0x00CC00CC;
 354   GPIOD->AFR[1]  = 0xCCCCCCCC;
 355   /* Configure PDx pins in Alternate function mode */
 356   GPIOD->MODER   = 0xAAAA0A0A;
 357   /* Configure PDx pins speed to 40 MHz */
 358   GPIOD->OSPEEDR = 0xFFFF0F0F;
 359   /* Configure PDx pins Output type to push-pull */
 360   GPIOD->OTYPER  = 0x00000000;
 361   /* No pull-up, pull-down for PDx pins */
 362   GPIOD->PUPDR   = 0x00000000;
 363
 364   /* Connect PEx pins to FSMC Alternate function */
 365   GPIOE->AFR[0]  = 0xC00000CC;
 366   GPIOE->AFR[1]  = 0xCCCCCCCC;
 367   /* Configure PEx pins in Alternate function mode */
 368   GPIOE->MODER   = 0xAAAA800A;
 369   /* Configure PEx pins speed to 40 MHz */
 370   GPIOE->OSPEEDR = 0xFFFFC00F;
 371   /* Configure PEx pins Output type to push-pull */
 372   GPIOE->OTYPER  = 0x00000000;
 373   /* No pull-up, pull-down for PEx pins */
 374   GPIOE->PUPDR   = 0x00000000;
 375
 376   /* Connect PFx pins to FSMC Alternate function */
 377   GPIOF->AFR[0]  = 0x00CCCCCC;
 378   GPIOF->AFR[1]  = 0xCCCC0000;
 379   /* Configure PFx pins in Alternate function mode */
 380   GPIOF->MODER   = 0xAA000AAA;
 381   /* Configure PFx pins speed to 40 MHz */
 382   GPIOF->OSPEEDR = 0xFF000FFF;
 383   /* Configure PFx pins Output type to push-pull */
 384   GPIOF->OTYPER  = 0x00000000;
 385   /* No pull-up, pull-down for PFx pins */
 386   GPIOF->PUPDR   = 0x00000000;
 387
 388   /* Connect PGx pins to FSMC Alternate function */
 389   GPIOG->AFR[0]  = 0x00CCCCCC;
 390   GPIOG->AFR[1]  = 0x00000C00;
 391   /* Configure PGx pins in Alternate function mode */
 392   GPIOG->MODER   = 0x00200AAA;
 393   /* Configure PGx pins speed to 40 MHz */
 394   GPIOG->OSPEEDR = 0x00300FFF;
 395   /* Configure PGx pins Output type to push-pull */
 396   GPIOG->OTYPER  = 0x00000000;
 397   /* No pull-up, pull-down for PGx pins */
 398   GPIOG->PUPDR   = 0x00000000;
 399
 400 /*-- FSMC Configuration ------------------------------------------------------*/
 401   /* Enable the FSMC interface clock */
 402   RCC->AHBENR    = 0x400080D8;
 403
 404   /* Configure and enable Bank1_SRAM3 */
 405   FSMC_Bank1->BTCR[4]  = 0x00001011;
 406   FSMC_Bank1->BTCR[5]  = 0x00000300;
 407   FSMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
 408 /*
 409   Bank1_SRAM3 is configured as follow:
 410
 411   p.FSMC_AddressSetupTime = 0;
 412   p.FSMC_AddressHoldTime = 0;
 413   p.FSMC_DataSetupTime = 3;
 414   p.FSMC_BusTurnAroundDuration = 0;
 415   p.FSMC_CLKDivision = 0;
 416   p.FSMC_DataLatency = 0;
 417   p.FSMC_AccessMode = FSMC_AccessMode_A;
 418
 419   FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3;
 420   FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
 421   FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
 422   FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
 423   FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
 424   FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
 425   FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
 426   FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
 427   FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
 428   FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
 429   FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
 430   FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
 431   FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
 432   FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
 433   FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
 434
 435   FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
 436
 437   FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
 438 */
 439
 440 }
 441 #endif /* DATA_IN_ExtSRAM */
 442 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
 443
 444 /**
 445   * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
 446   *               AHB/APBx prescalers and Flash settings
 447   * @note   This function should be called only once the RCC clock configuration
 448   *         is reset to the default reset state (done in SystemInit() function).
 449   * @param  None
 450   * @retval None
 451   */
 452 void SetSysClock(void)
 453 {
 454   /* 1- Try to start with HSE and external clock */
 455 #if USE_PLL_HSE_EXTC != 0
 456   if (SetSysClock_PLL_HSE(1) == 0)
 457 #endif
 458   {
 459     /* 2- If fail try to start with HSE and external xtal */
 460     #if USE_PLL_HSE_XTAL != 0
 461     if (SetSysClock_PLL_HSE(0) == 0)
 462     #endif
 463     {
 464       /* 3- If fail start with HSI clock */
 465       if (SetSysClock_PLL_HSI() == 0)
 466       {
 467         while(1)
 468         {
 469           // [TODO] Put something here to tell the user that a problem occured...
 470         }
 471       }
 472     }
 473   }
 474
 475   /* Output clock on MCO1 pin(PA8) for debugging purpose */
 476   //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
 477 }
 478
 479 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
 480 /******************************************************************************/
 481 /*            PLL (clocked by HSE) used as System clock source                */
 482 /******************************************************************************/
 483 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
 484 {
 485   RCC_ClkInitTypeDef RCC_ClkInitStruct;
 486   RCC_OscInitTypeDef RCC_OscInitStruct;
 487
 488   /* Used to gain time after DeepSleep in case HSI is used */
 489   if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
 490   {
 491     return 0;
 492   }
 493
 494   /* The voltage scaling allows optimizing the power consumption when the device is
 495      clocked below the maximum system frequency, to update the voltage scaling value
 496      regarding system frequency refer to product datasheet. */
 497   __PWR_CLK_ENABLE();
 498   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
 499
 500   /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */
 501   RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
 502   if (bypass == 0)
 503   {
 504     RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
 505   }
 506   else
 507   {
 508     RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
 509   }
 510   RCC_OscInitStruct.HSIState            = RCC_HSI_OFF;
 511   // SYSCLK = 24 MHz ((8 MHz * 6) / 2)
 512   // USBCLK = 48 MHz (8 MHz * 6) --> USB OK
 513   RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
 514   RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
 515   RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL6;
 516   RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLL_DIV2;
 517   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 518   {
 519     return 0; // FAIL
 520   }
 521
 522   /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
 523   RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
 524   RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 24 MHz
 525   RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 24 MHz
 526   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 24 MHz
 527   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 24 MHz
 528   if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
 529   {
 530     return 0; // FAIL
 531   }
 532
 533   /* Output clock on MCO1 pin(PA8) for debugging purpose */
 534   //if (bypass == 0)
 535     //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
 536   //else
 537     //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
 538
 539   return 1; // OK
 540 }
 541 #endif
 542
 543 /******************************************************************************/
 544 /*            PLL (clocked by HSI) used as System clock source                */
 545 /******************************************************************************/
 546 uint8_t SetSysClock_PLL_HSI(void)
 547 {
 548   RCC_ClkInitTypeDef RCC_ClkInitStruct;
 549   RCC_OscInitTypeDef RCC_OscInitStruct;
 550
 551   /* The voltage scaling allows optimizing the power consumption when the device is
 552      clocked below the maximum system frequency, to update the voltage scaling value
 553      regarding system frequency refer to product datasheet. */
 554   __PWR_CLK_ENABLE();
 555   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
 556
 557   /* Enable HSI oscillator and activate PLL with HSI as source */
 558   RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
 559   RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
 560   RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
 561   // SYSCLK = 32 MHz ((16 MHz * 4) / 2)
 562   // USBCLK = 64 MHz (16 MHz * 4) --> USB not possible
 563   RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
 564   RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
 565   RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL4;
 566   RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLL_DIV2;
 567   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 568   {
 569     return 0; // FAIL
 570   }
 571
 572   /* Poll VOSF bit of in PWR_CSR. Wait until it is reset to 0 */
 573   while (__HAL_PWR_GET_FLAG(PWR_FLAG_VOS) != RESET) {};
 574
 575   /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
 576   RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
 577   RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
 578   RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
 579   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
 580   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
 581   if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
 582   {
 583     return 0; // FAIL
 584   }
 585
 586   /* Output clock on MCO1 pin(PA8) for debugging purpose */
 587   //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
 588
 589   return 1; // OK
 590 }
 591
 592 /**
 593   * @}
 594   */
 595
 596 /**
 597   * @}
 598   */
 599
 600 /**
 601   * @}
 602   */
 603
 604 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/