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1 /**
2 ******************************************************************************
3 * @file stm32l1xx_hal_adc.h
4 * @author MCD Application Team
5 * @version V1.0.0
6 * @date 5-September-2014
7 * @brief Header file containing functions prototypes of ADC HAL library.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32L1xx_HAL_ADC_H
40 #define __STM32L1xx_HAL_ADC_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32l1xx_hal_def.h"
48 /** @addtogroup STM32L1xx_HAL_Driver
49 * @{
50 */
51
52 /** @addtogroup ADC
53 * @{
54 */
55
56 /* Exported types ------------------------------------------------------------*/
57 /** @defgroup ADC_Exported_Types ADC Exported Types
58 * @{
59 */
60
61 /**
62 * @brief Structure definition of ADC and regular group initialization
63 * @note Parameters of this structure are shared within 2 scopes:
64 * - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank.
65 * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
66 * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
67 * ADC state can be either:
68 * - For all parameters: ADC disabled
69 * - For all parameters except 'Resolution', 'ScanConvMode', 'LowPowerAutoWait', 'LowPowerAutoPowerOff', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group.
70 * - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going.
71 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
72 * without error reporting without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fullfills the ADC state condition) on the fly).
73 */
74 typedef struct
75 {
76 uint32_t ClockPrescaler; /*!< Select ADC clock source (asynchronous clock derived from HSI RC oscillator) and clock prescaler.
77 This parameter can be a value of @ref ADC_ClockPrescaler
78 Note: In case of usage of channels on injected group, ADC frequency should be low than AHB clock frequency /4 for resolution 12 or 10 bits,
79 AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits.
80 Note: HSI RC oscillator must be preliminarily enabled at RCC top level. */
81 uint32_t Resolution; /*!< Configures the ADC resolution.
82 This parameter can be a value of @ref ADC_Resolution */
83 uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
84 or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
85 This parameter can be a value of @ref ADC_Data_align */
86 uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
87 This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
88 If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
89 Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
90 If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
91 Scan direction is upward: from rank1 to rank 'n'.
92 This parameter can be a value of @ref ADC_Scan_mode */
93 uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
94 This parameter can be a value of @ref ADC_EOCSelection.
95 Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence.
96 Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT)
97 or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion.
98 Note: If overrun feature is intending to be used in ADC mode 'interruption' (function HAL_ADC_Start_IT() ), parameter EOCSelection must be set to each conversion (this is not needed for ADC mode 'transfer by DMA', with function HAL_ADC_Start_DMA()) */
99 uint32_t LowPowerAutoWait; /*!< Selects the dynamic low power Auto Delay: new conversion start only when the previous
100 conversion (for regular group) or previous sequence (for injected group) has been treated by user software.
101 This feature automatically adapts the speed of ADC to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications.
102 This parameter can be a value of @ref ADC_LowPowerAutoWait.
103 Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they have to clear immediately the EOC flag to free the IRQ vector sequencer.
104 Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed
105 and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion.
106 Note: ADC clock latency and some timing constraints depending on clock prescaler have to be taken into account: refer to reference manual (register ADC_CR2 bit DELS description). */
107 uint32_t LowPowerAutoPowerOff; /*!< Selects the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling).
108 This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait').
109 This parameter can be a value of @ref ADC_LowPowerAutoPowerOff. */
110 uint32_t ChannelsBank; /*!< Selects the ADC channels bank.
111 This parameter can be a value of @ref ADC_ChannelsBank.
112 Note: Banks availability depends on devices categories.
113 Note: To change bank selection on the fly, without going through execution of 'HAL_ADC_Init()', macro '__HAL_ADC_CHANNELS_BANK()' can be used directly. */
114 uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
115 after the selected trigger occurred (software start or external trigger).
116 This parameter can be set to ENABLE or DISABLE. */
117 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
118 uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
119 To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
120 This parameter must be a number between Min_Data = 1 and Max_Data = 28. */
121 #else
122 uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
123 To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
124 This parameter must be a number between Min_Data = 1 and Max_Data = 27. */
125 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
126 uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
127 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
128 Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
129 This parameter can be set to ENABLE or DISABLE. */
130 uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided.
131 If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
132 This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
133 uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
134 If set to ADC_SOFTWARE_START, external triggers are disabled.
135 If set to external trigger source, triggering is on event rising edge.
136 This parameter can be a value of @ref ADC_External_trigger_source_Regular */
137 uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group.
138 If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
139 This parameter can be a value of @ref ADC_External_trigger_edge_Regular */
140 uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
141 or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
142 Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
143 This parameter can be set to ENABLE or DISABLE.
144 Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could lauch a conversion). */
145 }ADC_InitTypeDef;
146
147 /**
148 * @brief Structure definition of ADC channel for regular group
149 * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
150 * ADC can be either disabled or enabled without conversion on going on regular group.
151 */
152 typedef struct
153 {
154 uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
155 This parameter can be a value of @ref ADC_channels
156 Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability.
157 Maximum number of channels by device category (without taking in account each device package constraints):
158 STM32L1 category 1, 2: 24 channels on external pins + 3 channels on internal measurement paths (VrefInt, Temp sensor, Vcomp): Channel 0 to channel 26.
159 STM32L1 category 3: 25 channels on external pins + 3 channels on internal measurement paths (VrefInt, Temp sensor, Vcomp): Channel 0 to channel 26, 1 additional channel in bank B. Note: OPAMP1 and OPAMP2 are connected internally but not increasing internal channels number: they are sharing ADC input with external channels ADC_IN3 and ADC_IN8.
160 STM32L1 category 4, 5: 40 channels on external pins + 3 channels on internal measurement paths (VrefInt, Temp sensor, Vcomp): Channel 0 to channel 31, 11 additional channels in bank B. Note: OPAMP1 and OPAMP2 are connected internally but not increasing internal channels number: they are sharing ADC input with external channels ADC_IN3 and ADC_IN8.
161 Note: In case of peripherals OPAMPx not used: 3 channels (3, 8, 13) can be configured as direct channels (fast channels). Refer to macro ' __HAL_ADC_CHANNEL_SPEED_FAST() '.
162 Note: In case of peripheral OPAMP3 and ADC channel OPAMP3 used (OPAMP3 available on STM32L1 devices Cat.4 only): the analog switch COMP1_SW1 must be closed. Refer to macro: ' __HAL_OPAMP_OPAMP3OUT_CONNECT_ADC_COMP1() '. */
163 uint32_t Rank; /*!< Specifies the rank in the regular group sequencer
164 This parameter can be a value of @ref ADC_regular_rank
165 Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
166 uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
167 Unit: ADC clock cycles
168 Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
169 This parameter can be a value of @ref ADC_sampling_times
170 Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
171 If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
172 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
173 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
174 Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
175 }ADC_ChannelConfTypeDef;
176
177 /**
178 * @brief ADC Configuration analog watchdog definition
179 * @note The setting of these parameters with function is conditioned to ADC state.
180 * ADC state can be either disabled or enabled without conversion on going on regular and injected groups.
181 */
182 typedef struct
183 {
184 uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all channels, regular/injected group.
185 This parameter can be a value of @ref ADC_analog_watchdog_mode. */
186 uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog.
187 This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode)
188 This parameter can be a value of @ref ADC_channels. */
189 uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
190 This parameter can be set to ENABLE or DISABLE */
191 uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
192 This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
193 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
194 This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
195 uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */
196 }ADC_AnalogWDGConfTypeDef;
197
198 /**
199 * @brief HAL ADC state machine: ADC States structure definition
200 */
201 typedef enum
202 {
203 HAL_ADC_STATE_RESET = 0x00, /*!< ADC not yet initialized or disabled */
204 HAL_ADC_STATE_READY = 0x01, /*!< ADC peripheral ready for use */
205 HAL_ADC_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
206 HAL_ADC_STATE_BUSY_REG = 0x12, /*!< Regular conversion is ongoing */
207 HAL_ADC_STATE_BUSY_INJ = 0x22, /*!< Injected conversion is ongoing */
208 HAL_ADC_STATE_BUSY_INJ_REG = 0x32, /*!< Injected and regular conversion are ongoing */
209 HAL_ADC_STATE_TIMEOUT = 0x03, /*!< Timeout state */
210 HAL_ADC_STATE_ERROR = 0x04, /*!< ADC state error */
211 HAL_ADC_STATE_EOC = 0x05, /*!< Conversion is completed */
212 HAL_ADC_STATE_EOC_REG = 0x15, /*!< Regular conversion is completed */
213 HAL_ADC_STATE_EOC_INJ = 0x25, /*!< Injected conversion is completed */
214 HAL_ADC_STATE_EOC_INJ_REG = 0x35, /*!< Injected and regular conversion are completed */
215 HAL_ADC_STATE_AWD = 0x06, /*!< ADC state analog watchdog */
216 HAL_ADC_STATE_AWD2 = 0x07, /*!< Not used on STM32L1xx devices (kept for compatibility with other devices featuring several AWD) */
217 HAL_ADC_STATE_AWD3 = 0x08, /*!< Not used on STM32l1xx devices (kept for compatibility with other devices featuring several AWD) */
218 }HAL_ADC_StateTypeDef;
219
220 /**
221 * @brief ADC handle Structure definition
222 */
223 typedef struct
224 {
225 ADC_TypeDef *Instance; /*!< Register base address */
226
227 ADC_InitTypeDef Init; /*!< ADC required parameters */
228
229 __IO uint32_t NbrOfConversionRank ; /*!< ADC conversion rank counter */
230
231 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
232
233 HAL_LockTypeDef Lock; /*!< ADC locking object */
234
235 __IO HAL_ADC_StateTypeDef State; /*!< ADC communication state */
236
237 __IO uint32_t ErrorCode; /*!< ADC Error code */
238 }ADC_HandleTypeDef;
239 /**
240 * @}
241 */
242
243
244
245 /* Exported constants --------------------------------------------------------*/
246
247 /** @defgroup ADC_Exported_Constants ADC Exported Constants
248 * @{
249 */
250
251 /** @defgroup ADC_Error_Code ADC Error Code
252 * @{
253 */
254 #define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */
255 #define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01) /*!< ADC IP internal error: if problem of clocking,
256 enable/disable, erroneous state */
257 #define HAL_ADC_ERROR_OVR ((uint32_t)0x02) /*!< Overrun error */
258 #define HAL_ADC_ERROR_DMA ((uint32_t)0x04) /*!< DMA transfer error */
259
260 /**
261 * @}
262 */
263
264 /** @defgroup ADC_ClockPrescaler ADC ClockPrescaler
265 * @{
266 */
267 #define ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000) /*!< ADC asynchronous clock derived from ADC dedicated HSI without prescaler */
268 #define ADC_CLOCK_ASYNC_DIV2 ((uint32_t)ADC_CCR_ADCPRE_0) /*!< ADC asynchronous clock derived from ADC dedicated HSI divided by a prescaler of 2 */
269 #define ADC_CLOCK_ASYNC_DIV4 ((uint32_t)ADC_CCR_ADCPRE_1) /*!< ADC asynchronous clock derived from ADC dedicated HSI divided by a prescaler of 4 */
270
271 #define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) || \
272 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2) || \
273 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4) )
274 /**
275 * @}
276 */
277
278 /** @defgroup ADC_Resolution ADC Resolution
279 * @{
280 */
281 #define ADC_RESOLUTION12b ((uint32_t)0x00000000) /*!< ADC 12-bit resolution */
282 #define ADC_RESOLUTION10b ((uint32_t)ADC_CR1_RES_0) /*!< ADC 10-bit resolution */
283 #define ADC_RESOLUTION8b ((uint32_t)ADC_CR1_RES_1) /*!< ADC 8-bit resolution */
284 #define ADC_RESOLUTION6b ((uint32_t)ADC_CR1_RES) /*!< ADC 6-bit resolution */
285
286 #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION12b) || \
287 ((RESOLUTION) == ADC_RESOLUTION10b) || \
288 ((RESOLUTION) == ADC_RESOLUTION8b) || \
289 ((RESOLUTION) == ADC_RESOLUTION6b) )
290
291 #define IS_ADC_RESOLUTION_8_6_BITS(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION8b) || \
292 ((RESOLUTION) == ADC_RESOLUTION6b) )
293 /**
294 * @}
295 */
296
297 /** @defgroup ADC_Data_align ADC Data_align
298 * @{
299 */
300 #define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000)
301 #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
302
303 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
304 ((ALIGN) == ADC_DATAALIGN_LEFT) )
305 /**
306 * @}
307 */
308
309 /** @defgroup ADC_Scan_mode ADC Scan mode
310 * @{
311 */
312 #define ADC_SCAN_DISABLE ((uint32_t)0x00000000)
313 #define ADC_SCAN_ENABLE ((uint32_t)0x00000001)
314
315 #define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \
316 ((SCAN_MODE) == ADC_SCAN_ENABLE) )
317 /**
318 * @}
319 */
320
321 /** @defgroup ADC_External_trigger_edge_Regular ADC External trigger edge Regular
322 * @{
323 */
324 #define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000)
325 #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0)
326 #define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1)
327 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN)
328
329 #define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
330 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
331 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
332 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) )
333 /**
334 * @}
335 */
336
337 /** @defgroup ADC_External_trigger_source_Regular ADC External trigger source Regular
338 * @{
339 */
340 /* List of external triggers with generic trigger name, sorted by trigger */
341 /* name: */
342
343 /* External triggers of regular group for ADC1 */
344 #define ADC_EXTERNALTRIGCONV_T2_CC3 ADC_EXTERNALTRIG_T2_CC3
345 #define ADC_EXTERNALTRIGCONV_T2_CC2 ADC_EXTERNALTRIG_T2_CC2
346 #define ADC_EXTERNALTRIGCONV_T2_TRGO ADC_EXTERNALTRIG_T2_TRGO
347 #define ADC_EXTERNALTRIGCONV_T3_CC1 ADC_EXTERNALTRIG_T3_CC1
348 #define ADC_EXTERNALTRIGCONV_T3_CC3 ADC_EXTERNALTRIG_T3_CC3
349 #define ADC_EXTERNALTRIGCONV_T3_TRGO ADC_EXTERNALTRIG_T3_TRGO
350 #define ADC_EXTERNALTRIGCONV_T4_CC4 ADC_EXTERNALTRIG_T4_CC4
351 #define ADC_EXTERNALTRIGCONV_T4_TRGO ADC_EXTERNALTRIG_T4_TRGO
352 #define ADC_EXTERNALTRIGCONV_T6_TRGO ADC_EXTERNALTRIG_T6_TRGO
353 #define ADC_EXTERNALTRIGCONV_T9_CC2 ADC_EXTERNALTRIG_T9_CC2
354 #define ADC_EXTERNALTRIGCONV_T9_TRGO ADC_EXTERNALTRIG_T9_TRGO
355 #define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC_EXTERNALTRIG_EXT_IT11
356
357 #define ADC_SOFTWARE_START ((uint32_t)0x00000010)
358
359 #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \
360 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
361 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
362 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \
363 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC3) || \
364 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
365 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
366 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO) || \
367 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \
368 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T9_CC2) || \
369 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T9_TRGO) || \
370 ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
371 ((REGTRIG) == ADC_SOFTWARE_START) )
372 /**
373 * @}
374 */
375
376 /** @defgroup ADC_Internal_HAL_driver_Ext_trig_src_Regular ADC Internal HAL driver Ext trig src Regular
377 * @{
378 */
379
380 /* List of external triggers of regular group for ADC1: */
381 /* (used internally by HAL driver. To not use into HAL structure parameters) */
382
383 /* External triggers of regular group for ADC1 */
384 #define ADC_EXTERNALTRIG_T9_CC2 ((uint32_t) 0x00000000)
385 #define ADC_EXTERNALTRIG_T9_TRGO ((uint32_t)( ADC_CR2_EXTSEL_0))
386 #define ADC_EXTERNALTRIG_T2_CC3 ((uint32_t)( ADC_CR2_EXTSEL_1 ))
387 #define ADC_EXTERNALTRIG_T2_CC2 ((uint32_t)( ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
388 #define ADC_EXTERNALTRIG_T3_TRGO ((uint32_t)( ADC_CR2_EXTSEL_2 ))
389 #define ADC_EXTERNALTRIG_T4_CC4 ((uint32_t)( ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
390 #define ADC_EXTERNALTRIG_T2_TRGO ((uint32_t)( ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 ))
391 #define ADC_EXTERNALTRIG_T3_CC1 ((uint32_t)( ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
392 #define ADC_EXTERNALTRIG_T3_CC3 ((uint32_t)(ADC_CR2_EXTSEL_3 ))
393 #define ADC_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0))
394 #define ADC_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 ))
395 #define ADC_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
396
397 /**
398 * @}
399 */
400
401 /** @defgroup ADC_EOCSelection ADC EOCSelection
402 * @{
403 */
404 #define EOC_SEQ_CONV ((uint32_t)0x00000000)
405 #define EOC_SINGLE_CONV ((uint32_t)ADC_CR2_EOCS)
406
407 #define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == EOC_SINGLE_CONV) || \
408 ((EOC_SELECTION) == EOC_SEQ_CONV) )
409 /**
410 * @}
411 */
412
413 /** @defgroup ADC_LowPowerAutoWait ADC LowPowerAutoWait
414 * @{
415 */
416 /*!< Note : For compatibility with other STM32 devices with ADC autowait */
417 /* feature limited to enable or disable settings: */
418 /* Setting "ADC_AUTOWAIT_UNTIL_DATA_READ" is equivalent to "ENABLE". */
419
420 #define ADC_AUTOWAIT_DISABLE ((uint32_t)0x00000000)
421 #define ADC_AUTOWAIT_UNTIL_DATA_READ ((uint32_t)( ADC_CR2_DELS_0)) /*!< Insert a delay between ADC conversions: infinite delay, until the result of previous conversion is read */
422 #define ADC_AUTOWAIT_7_APBCLOCKCYCLES ((uint32_t)( ADC_CR2_DELS_1 )) /*!< Insert a delay between ADC conversions: 7 APB clock cycles */
423 #define ADC_AUTOWAIT_15_APBCLOCKCYCLES ((uint32_t)( ADC_CR2_DELS_1 | ADC_CR2_DELS_0)) /*!< Insert a delay between ADC conversions: 15 APB clock cycles */
424 #define ADC_AUTOWAIT_31_APBCLOCKCYCLES ((uint32_t)(ADC_CR2_DELS_2 )) /*!< Insert a delay between ADC conversions: 31 APB clock cycles */
425 #define ADC_AUTOWAIT_63_APBCLOCKCYCLES ((uint32_t)(ADC_CR2_DELS_2 | ADC_CR2_DELS_0)) /*!< Insert a delay between ADC conversions: 63 APB clock cycles */
426 #define ADC_AUTOWAIT_127_APBCLOCKCYCLES ((uint32_t)(ADC_CR2_DELS_2 | ADC_CR2_DELS_1 )) /*!< Insert a delay between ADC conversions: 127 APB clock cycles */
427 #define ADC_AUTOWAIT_255_APBCLOCKCYCLES ((uint32_t)(ADC_CR2_DELS_2 | ADC_CR2_DELS_1 | ADC_CR2_DELS_0)) /*!< Insert a delay between ADC conversions: 255 APB clock cycles */
428
429 #define IS_ADC_AUTOWAIT(AUTOWAIT) (((AUTOWAIT) == ADC_AUTOWAIT_DISABLE) || \
430 ((AUTOWAIT) == ADC_AUTOWAIT_UNTIL_DATA_READ) || \
431 ((AUTOWAIT) == ADC_AUTOWAIT_7_APBCLOCKCYCLES) || \
432 ((AUTOWAIT) == ADC_AUTOWAIT_15_APBCLOCKCYCLES) || \
433 ((AUTOWAIT) == ADC_AUTOWAIT_31_APBCLOCKCYCLES) || \
434 ((AUTOWAIT) == ADC_AUTOWAIT_63_APBCLOCKCYCLES) || \
435 ((AUTOWAIT) == ADC_AUTOWAIT_127_APBCLOCKCYCLES) || \
436 ((AUTOWAIT) == ADC_AUTOWAIT_255_APBCLOCKCYCLES) )
437 /**
438 * @}
439 */
440
441 /** @defgroup ADC_LowPowerAutoPowerOff ADC LowPowerAutoPowerOff
442 * @{
443 */
444 #define ADC_AUTOPOWEROFF_DISABLE ((uint32_t)0x00000000)
445 #define ADC_AUTOPOWEROFF_IDLE_PHASE ((uint32_t)ADC_CR1_PDI) /*!< ADC power off when ADC is not converting (idle phase) */
446 #define ADC_AUTOPOWEROFF_DELAY_PHASE ((uint32_t)ADC_CR1_PDD) /*!< ADC power off when a delay is inserted between conversions (see parameter ADC_LowPowerAutoWait) */
447 #define ADC_AUTOPOWEROFF_IDLE_DELAY_PHASES ((uint32_t)(ADC_CR1_PDI | ADC_CR1_PDD)) /*!< ADC power off when ADC is not converting (idle phase) and when a delay is inserted between conversions */
448
449 #define IS_ADC_AUTOPOWEROFF(AUTOPOWEROFF) (((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_DISABLE) || \
450 ((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_IDLE_PHASE) || \
451 ((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_DELAY_PHASE) || \
452 ((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_IDLE_DELAY_PHASES) )
453 /**
454 * @}
455 */
456
457
458 /** @defgroup ADC_ChannelsBank ADC ChannelsBank
459 * @{
460 */
461 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
462 #define ADC_CHANNELS_BANK_A ((uint32_t)0x00000000)
463 #define ADC_CHANNELS_BANK_B ((uint32_t)ADC_CR2_CFG)
464
465 #define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A) || \
466 ((BANK) == ADC_CHANNELS_BANK_B) )
467 #else
468 #define ADC_CHANNELS_BANK_A ((uint32_t)0x00000000)
469
470 #define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A))
471 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
472 /**
473 * @}
474 */
475
476 /** @defgroup ADC_channels ADC channels
477 * @{
478 */
479 /* Note: Depending on devices, some channels may not be available on package */
480 /* pins. Refer to device datasheet for channels availability. */
481 #define ADC_CHANNEL_0 ((uint32_t)0x00000000) /* Channel different in bank A and bank B */
482 #define ADC_CHANNEL_1 ((uint32_t)( ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */
483 #define ADC_CHANNEL_2 ((uint32_t)( ADC_SQR5_SQ1_1 )) /* Channel different in bank A and bank B */
484 #define ADC_CHANNEL_3 ((uint32_t)( ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */
485 #define ADC_CHANNEL_4 ((uint32_t)( ADC_SQR5_SQ1_2 )) /* Direct (fast) channel */
486 #define ADC_CHANNEL_5 ((uint32_t)( ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_0)) /* Direct (fast) channel */
487 #define ADC_CHANNEL_6 ((uint32_t)( ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 )) /* Channel different in bank A and bank B */
488 #define ADC_CHANNEL_7 ((uint32_t)( ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */
489 #define ADC_CHANNEL_8 ((uint32_t)( ADC_SQR5_SQ1_3 )) /* Channel different in bank A and bank B */
490 #define ADC_CHANNEL_9 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */
491 #define ADC_CHANNEL_10 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_1 )) /* Channel different in bank A and bank B */
492 #define ADC_CHANNEL_11 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */
493 #define ADC_CHANNEL_12 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 )) /* Channel different in bank A and bank B */
494 #define ADC_CHANNEL_13 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
495 #define ADC_CHANNEL_14 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 )) /* Channel common to both bank A and bank B */
496 #define ADC_CHANNEL_15 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
497 #define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR5_SQ1_4 )) /* Channel common to both bank A and bank B */
498 #define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
499 #define ADC_CHANNEL_18 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_1 )) /* Channel common to both bank A and bank B */
500 #define ADC_CHANNEL_19 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
501 #define ADC_CHANNEL_20 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_2 )) /* Channel common to both bank A and bank B */
502 #define ADC_CHANNEL_21 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
503 #define ADC_CHANNEL_22 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 )) /* Direct (fast) channel */
504 #define ADC_CHANNEL_23 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Direct (fast) channel */
505 #define ADC_CHANNEL_24 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 )) /* Direct (fast) channel */
506 #define ADC_CHANNEL_25 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_0)) /* Direct (fast) channel */
507 #define ADC_CHANNEL_26 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_1 )) /* Channel common to both bank A and bank B */
508 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
509 #define ADC_CHANNEL_27 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
510 #define ADC_CHANNEL_28 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 )) /* Channel common to both bank A and bank B */
511 #define ADC_CHANNEL_29 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
512 #define ADC_CHANNEL_30 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 )) /* Channel common to both bank A and bank B */
513 #define ADC_CHANNEL_31 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
514 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
515
516 #define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 /* ADC internal channel (no connection on device pin). Channel common to both bank A and bank B. */
517 #define ADC_CHANNEL_VREFINT ADC_CHANNEL_17 /* ADC internal channel (no connection on device pin). Channel common to both bank A and bank B. */
518 #define ADC_CHANNEL_VCOMP ADC_CHANNEL_26 /* ADC internal channel (no connection on device pin). Channel common to both bank A and bank B. */
519
520 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
521 #define ADC_CHANNEL_VOPAMP1 ADC_CHANNEL_3 /* Internal connection from OPAMP1 output to ADC switch matrix */
522 #define ADC_CHANNEL_VOPAMP2 ADC_CHANNEL_8 /* Internal connection from OPAMP2 output to ADC switch matrix */
523 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD)
524 #define ADC_CHANNEL_VOPAMP3 ADC_CHANNEL_13 /* Internal connection from OPAMP3 output to ADC switch matrix */
525 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD */
526 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
527
528 #if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC)
529 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \
530 ((CHANNEL) == ADC_CHANNEL_1) || \
531 ((CHANNEL) == ADC_CHANNEL_2) || \
532 ((CHANNEL) == ADC_CHANNEL_3) || \
533 ((CHANNEL) == ADC_CHANNEL_4) || \
534 ((CHANNEL) == ADC_CHANNEL_5) || \
535 ((CHANNEL) == ADC_CHANNEL_6) || \
536 ((CHANNEL) == ADC_CHANNEL_7) || \
537 ((CHANNEL) == ADC_CHANNEL_8) || \
538 ((CHANNEL) == ADC_CHANNEL_9) || \
539 ((CHANNEL) == ADC_CHANNEL_10) || \
540 ((CHANNEL) == ADC_CHANNEL_11) || \
541 ((CHANNEL) == ADC_CHANNEL_12) || \
542 ((CHANNEL) == ADC_CHANNEL_13) || \
543 ((CHANNEL) == ADC_CHANNEL_14) || \
544 ((CHANNEL) == ADC_CHANNEL_15) || \
545 ((CHANNEL) == ADC_CHANNEL_16) || \
546 ((CHANNEL) == ADC_CHANNEL_17) || \
547 ((CHANNEL) == ADC_CHANNEL_18) || \
548 ((CHANNEL) == ADC_CHANNEL_19) || \
549 ((CHANNEL) == ADC_CHANNEL_20) || \
550 ((CHANNEL) == ADC_CHANNEL_21) || \
551 ((CHANNEL) == ADC_CHANNEL_22) || \
552 ((CHANNEL) == ADC_CHANNEL_23) || \
553 ((CHANNEL) == ADC_CHANNEL_24) || \
554 ((CHANNEL) == ADC_CHANNEL_25) || \
555 ((CHANNEL) == ADC_CHANNEL_26) )
556 #endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */
557 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
558 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \
559 ((CHANNEL) == ADC_CHANNEL_1) || \
560 ((CHANNEL) == ADC_CHANNEL_2) || \
561 ((CHANNEL) == ADC_CHANNEL_3) || \
562 ((CHANNEL) == ADC_CHANNEL_4) || \
563 ((CHANNEL) == ADC_CHANNEL_5) || \
564 ((CHANNEL) == ADC_CHANNEL_6) || \
565 ((CHANNEL) == ADC_CHANNEL_7) || \
566 ((CHANNEL) == ADC_CHANNEL_8) || \
567 ((CHANNEL) == ADC_CHANNEL_9) || \
568 ((CHANNEL) == ADC_CHANNEL_10) || \
569 ((CHANNEL) == ADC_CHANNEL_11) || \
570 ((CHANNEL) == ADC_CHANNEL_12) || \
571 ((CHANNEL) == ADC_CHANNEL_13) || \
572 ((CHANNEL) == ADC_CHANNEL_14) || \
573 ((CHANNEL) == ADC_CHANNEL_15) || \
574 ((CHANNEL) == ADC_CHANNEL_16) || \
575 ((CHANNEL) == ADC_CHANNEL_17) || \
576 ((CHANNEL) == ADC_CHANNEL_18) || \
577 ((CHANNEL) == ADC_CHANNEL_19) || \
578 ((CHANNEL) == ADC_CHANNEL_20) || \
579 ((CHANNEL) == ADC_CHANNEL_21) || \
580 ((CHANNEL) == ADC_CHANNEL_22) || \
581 ((CHANNEL) == ADC_CHANNEL_23) || \
582 ((CHANNEL) == ADC_CHANNEL_24) || \
583 ((CHANNEL) == ADC_CHANNEL_25) || \
584 ((CHANNEL) == ADC_CHANNEL_26) || \
585 ((CHANNEL) == ADC_CHANNEL_27) || \
586 ((CHANNEL) == ADC_CHANNEL_28) || \
587 ((CHANNEL) == ADC_CHANNEL_29) || \
588 ((CHANNEL) == ADC_CHANNEL_30) || \
589 ((CHANNEL) == ADC_CHANNEL_31) )
590 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
591 /**
592 * @}
593 */
594
595 /** @defgroup ADC_sampling_times ADC sampling times
596 * @{
597 */
598 #define ADC_SAMPLETIME_4CYCLES ((uint32_t)0x00000000) /*!< Sampling time 4 ADC clock cycles */
599 #define ADC_SAMPLETIME_9CYCLES ((uint32_t) ADC_SMPR3_SMP0_0) /*!< Sampling time 9 ADC clock cycles */
600 #define ADC_SAMPLETIME_16CYCLES ((uint32_t) ADC_SMPR3_SMP0_1) /*!< Sampling time 16 ADC clock cycles */
601 #define ADC_SAMPLETIME_24CYCLES ((uint32_t)(ADC_SMPR3_SMP0_1 | ADC_SMPR3_SMP0_0)) /*!< Sampling time 24 ADC clock cycles */
602 #define ADC_SAMPLETIME_48CYCLES ((uint32_t) ADC_SMPR3_SMP0_2) /*!< Sampling time 48 ADC clock cycles */
603 #define ADC_SAMPLETIME_96CYCLES ((uint32_t)(ADC_SMPR3_SMP0_2 | ADC_SMPR3_SMP0_0)) /*!< Sampling time 96 ADC clock cycles */
604 #define ADC_SAMPLETIME_192CYCLES ((uint32_t)(ADC_SMPR3_SMP0_2 | ADC_SMPR3_SMP0_1)) /*!< Sampling time 192 ADC clock cycles */
605 #define ADC_SAMPLETIME_384CYCLES ((uint32_t) ADC_SMPR3_SMP0) /*!< Sampling time 384 ADC clock cycles */
606
607 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_4CYCLES) || \
608 ((TIME) == ADC_SAMPLETIME_9CYCLES) || \
609 ((TIME) == ADC_SAMPLETIME_16CYCLES) || \
610 ((TIME) == ADC_SAMPLETIME_24CYCLES) || \
611 ((TIME) == ADC_SAMPLETIME_48CYCLES) || \
612 ((TIME) == ADC_SAMPLETIME_96CYCLES) || \
613 ((TIME) == ADC_SAMPLETIME_192CYCLES) || \
614 ((TIME) == ADC_SAMPLETIME_384CYCLES) )
615 /**
616 * @}
617 */
618
619 /** @defgroup ADC_sampling_times_all_channels ADC sampling times all channels
620 * @{
621 */
622 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT2 \
623 (ADC_SMPR3_SMP9_2 | ADC_SMPR3_SMP8_2 | ADC_SMPR3_SMP7_2 | ADC_SMPR3_SMP6_2 | \
624 ADC_SMPR3_SMP5_2 | ADC_SMPR3_SMP4_2 | ADC_SMPR3_SMP3_2 | ADC_SMPR3_SMP2_2 | \
625 ADC_SMPR3_SMP1_2 | ADC_SMPR3_SMP0_2)
626 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \
627 (ADC_SMPR2_SMP19_2 | ADC_SMPR2_SMP18_2 | ADC_SMPR2_SMP17_2 | ADC_SMPR2_SMP16_2 | \
628 ADC_SMPR2_SMP15_2 | ADC_SMPR2_SMP14_2 | ADC_SMPR2_SMP13_2 | ADC_SMPR2_SMP12_2 | \
629 ADC_SMPR2_SMP11_2 | ADC_SMPR2_SMP10_2)
630 #if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC)
631 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \
632 (ADC_SMPR1_SMP26_2 | ADC_SMPR1_SMP25_2 | ADC_SMPR1_SMP24_2 | ADC_SMPR1_SMP23_2 | \
633 ADC_SMPR1_SMP22_2 | ADC_SMPR1_SMP21_2 | ADC_SMPR1_SMP20_2)
634 #endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */
635 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
636 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \
637 (ADC_SMPR1_SMP29_2 | ADC_SMPR1_SMP28_2 | ADC_SMPR1_SMP27_2 | ADC_SMPR1_SMP26_2 | \
638 ADC_SMPR1_SMP25_2 | ADC_SMPR1_SMP24_2 | ADC_SMPR1_SMP23_2 | ADC_SMPR1_SMP22_2 | \
639 ADC_SMPR1_SMP21_2 | ADC_SMPR1_SMP20_2)
640 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT2 \
641 (ADC_SMPR0_SMP31_2 | ADC_SMPR0_SMP30_2 )
642 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
643
644 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT1 \
645 (ADC_SMPR3_SMP9_1 | ADC_SMPR3_SMP8_1 | ADC_SMPR3_SMP7_1 | ADC_SMPR3_SMP6_1 | \
646 ADC_SMPR3_SMP5_1 | ADC_SMPR3_SMP4_1 | ADC_SMPR3_SMP3_1 | ADC_SMPR3_SMP2_1 | \
647 ADC_SMPR3_SMP1_1 | ADC_SMPR3_SMP0_1)
648 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \
649 (ADC_SMPR2_SMP19_1 | ADC_SMPR2_SMP18_1 | ADC_SMPR2_SMP17_1 | ADC_SMPR2_SMP16_1 | \
650 ADC_SMPR2_SMP15_1 | ADC_SMPR2_SMP14_1 | ADC_SMPR2_SMP13_1 | ADC_SMPR2_SMP12_1 | \
651 ADC_SMPR2_SMP11_1 | ADC_SMPR2_SMP10_1)
652 #if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC)
653 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \
654 (ADC_SMPR1_SMP26_1 | ADC_SMPR1_SMP25_1 | ADC_SMPR1_SMP24_1 | ADC_SMPR1_SMP23_1 | \
655 ADC_SMPR1_SMP22_1 | ADC_SMPR1_SMP21_1 | ADC_SMPR1_SMP20_1)
656 #endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */
657 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
658 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \
659 (ADC_SMPR1_SMP29_1 | ADC_SMPR1_SMP28_1 | ADC_SMPR1_SMP27_1 | ADC_SMPR1_SMP26_1 | \
660 ADC_SMPR1_SMP25_1 | ADC_SMPR1_SMP24_1 | ADC_SMPR1_SMP23_1 | ADC_SMPR1_SMP22_1 | \
661 ADC_SMPR1_SMP21_1 | ADC_SMPR1_SMP20_1)
662 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT1 \
663 (ADC_SMPR0_SMP31_1 | ADC_SMPR0_SMP30_1 )
664 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
665
666 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT0 \
667 (ADC_SMPR3_SMP9_0 | ADC_SMPR3_SMP8_0 | ADC_SMPR3_SMP7_0 | ADC_SMPR3_SMP6_0 | \
668 ADC_SMPR3_SMP5_0 | ADC_SMPR3_SMP4_0 | ADC_SMPR3_SMP3_0 | ADC_SMPR3_SMP2_0 | \
669 ADC_SMPR3_SMP1_0 | ADC_SMPR3_SMP0_0)
670 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0 \
671 (ADC_SMPR2_SMP19_0 | ADC_SMPR2_SMP18_0 | ADC_SMPR2_SMP17_0 | ADC_SMPR2_SMP16_0 | \
672 ADC_SMPR2_SMP15_0 | ADC_SMPR2_SMP14_0 | ADC_SMPR2_SMP13_0 | ADC_SMPR2_SMP12_0 | \
673 ADC_SMPR2_SMP11_0 | ADC_SMPR2_SMP10_0)
674 #if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC)
675 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \
676 (ADC_SMPR1_SMP26_0 | ADC_SMPR1_SMP25_0 | ADC_SMPR1_SMP24_0 | ADC_SMPR1_SMP23_0 | \
677 ADC_SMPR1_SMP22_0 | ADC_SMPR1_SMP21_0 | ADC_SMPR1_SMP20_0)
678 #endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */
679 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
680 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \
681 (ADC_SMPR1_SMP29_0 | ADC_SMPR1_SMP28_0 | ADC_SMPR1_SMP27_0 | ADC_SMPR1_SMP26_0 | \
682 ADC_SMPR1_SMP25_0 | ADC_SMPR1_SMP24_0 | ADC_SMPR1_SMP23_0 | ADC_SMPR1_SMP22_0 | \
683 ADC_SMPR1_SMP21_0 | ADC_SMPR1_SMP20_0)
684 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT0 \
685 (ADC_SMPR0_SMP31_0 | ADC_SMPR0_SMP30_0 )
686 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
687 /**
688 * @}
689 */
690
691 /** @defgroup ADC_regular_rank ADC regular rank
692 * @{
693 */
694 #define ADC_REGULAR_RANK_1 ((uint32_t)0x00000001)
695 #define ADC_REGULAR_RANK_2 ((uint32_t)0x00000002)
696 #define ADC_REGULAR_RANK_3 ((uint32_t)0x00000003)
697 #define ADC_REGULAR_RANK_4 ((uint32_t)0x00000004)
698 #define ADC_REGULAR_RANK_5 ((uint32_t)0x00000005)
699 #define ADC_REGULAR_RANK_6 ((uint32_t)0x00000006)
700 #define ADC_REGULAR_RANK_7 ((uint32_t)0x00000007)
701 #define ADC_REGULAR_RANK_8 ((uint32_t)0x00000008)
702 #define ADC_REGULAR_RANK_9 ((uint32_t)0x00000009)
703 #define ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A)
704 #define ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B)
705 #define ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C)
706 #define ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D)
707 #define ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E)
708 #define ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F)
709 #define ADC_REGULAR_RANK_16 ((uint32_t)0x00000010)
710 #define ADC_REGULAR_RANK_17 ((uint32_t)0x00000011)
711 #define ADC_REGULAR_RANK_18 ((uint32_t)0x00000012)
712 #define ADC_REGULAR_RANK_19 ((uint32_t)0x00000013)
713 #define ADC_REGULAR_RANK_20 ((uint32_t)0x00000014)
714 #define ADC_REGULAR_RANK_21 ((uint32_t)0x00000015)
715 #define ADC_REGULAR_RANK_22 ((uint32_t)0x00000016)
716 #define ADC_REGULAR_RANK_23 ((uint32_t)0x00000017)
717 #define ADC_REGULAR_RANK_24 ((uint32_t)0x00000018)
718 #define ADC_REGULAR_RANK_25 ((uint32_t)0x00000019)
719 #define ADC_REGULAR_RANK_26 ((uint32_t)0x0000001A)
720 #define ADC_REGULAR_RANK_27 ((uint32_t)0x0000001B)
721 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
722 #define ADC_REGULAR_RANK_28 ((uint32_t)0x0000001C)
723
724 #define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \
725 ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \
726 ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \
727 ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \
728 ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \
729 ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \
730 ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \
731 ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \
732 ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \
733 ((CHANNEL) == ADC_REGULAR_RANK_10) || \
734 ((CHANNEL) == ADC_REGULAR_RANK_11) || \
735 ((CHANNEL) == ADC_REGULAR_RANK_12) || \
736 ((CHANNEL) == ADC_REGULAR_RANK_13) || \
737 ((CHANNEL) == ADC_REGULAR_RANK_14) || \
738 ((CHANNEL) == ADC_REGULAR_RANK_15) || \
739 ((CHANNEL) == ADC_REGULAR_RANK_16) || \
740 ((CHANNEL) == ADC_REGULAR_RANK_17) || \
741 ((CHANNEL) == ADC_REGULAR_RANK_18) || \
742 ((CHANNEL) == ADC_REGULAR_RANK_19) || \
743 ((CHANNEL) == ADC_REGULAR_RANK_20) || \
744 ((CHANNEL) == ADC_REGULAR_RANK_21) || \
745 ((CHANNEL) == ADC_REGULAR_RANK_22) || \
746 ((CHANNEL) == ADC_REGULAR_RANK_23) || \
747 ((CHANNEL) == ADC_REGULAR_RANK_24) || \
748 ((CHANNEL) == ADC_REGULAR_RANK_25) || \
749 ((CHANNEL) == ADC_REGULAR_RANK_26) || \
750 ((CHANNEL) == ADC_REGULAR_RANK_27) || \
751 ((CHANNEL) == ADC_REGULAR_RANK_28) )
752 #else
753
754 #define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \
755 ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \
756 ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \
757 ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \
758 ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \
759 ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \
760 ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \
761 ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \
762 ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \
763 ((CHANNEL) == ADC_REGULAR_RANK_10) || \
764 ((CHANNEL) == ADC_REGULAR_RANK_11) || \
765 ((CHANNEL) == ADC_REGULAR_RANK_12) || \
766 ((CHANNEL) == ADC_REGULAR_RANK_13) || \
767 ((CHANNEL) == ADC_REGULAR_RANK_14) || \
768 ((CHANNEL) == ADC_REGULAR_RANK_15) || \
769 ((CHANNEL) == ADC_REGULAR_RANK_16) || \
770 ((CHANNEL) == ADC_REGULAR_RANK_17) || \
771 ((CHANNEL) == ADC_REGULAR_RANK_18) || \
772 ((CHANNEL) == ADC_REGULAR_RANK_19) || \
773 ((CHANNEL) == ADC_REGULAR_RANK_20) || \
774 ((CHANNEL) == ADC_REGULAR_RANK_21) || \
775 ((CHANNEL) == ADC_REGULAR_RANK_22) || \
776 ((CHANNEL) == ADC_REGULAR_RANK_23) || \
777 ((CHANNEL) == ADC_REGULAR_RANK_24) || \
778 ((CHANNEL) == ADC_REGULAR_RANK_25) || \
779 ((CHANNEL) == ADC_REGULAR_RANK_26) || \
780 ((CHANNEL) == ADC_REGULAR_RANK_27) )
781 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
782 /**
783 * @}
784 */
785
786 /** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode
787 * @{
788 */
789 #define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000)
790 #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
791 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
792 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
793 #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CR1_AWDEN)
794 #define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t) ADC_CR1_JAWDEN)
795 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
796
797 #define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \
798 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
799 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
800 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
801 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \
802 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
803 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
804 /**
805 * @}
806 */
807
808 /** @defgroup ADC_conversion_group ADC conversion group
809 * @{
810 */
811 #define REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC))
812 #define INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC))
813 #define REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_JEOC))
814
815 #define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == REGULAR_GROUP) || \
816 ((CONVERSION) == INJECTED_GROUP) || \
817 ((CONVERSION) == REGULAR_INJECTED_GROUP) )
818 /**
819 * @}
820 */
821
822 /** @defgroup ADC_Event_type ADC Event type
823 * @{
824 */
825 #define AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /*!< ADC Analog watchdog event */
826 #define OVR_EVENT ((uint32_t)ADC_FLAG_OVR) /*!< ADC overrun event */
827
828 #define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == AWD_EVENT) || \
829 ((EVENT) == ADC_FLAG_OVR) )
830 /**
831 * @}
832 */
833
834 /** @defgroup ADC_interrupts_definition ADC interrupts definition
835 * @{
836 */
837 #define ADC_IT_EOC ADC_CR1_EOCIE /*!< ADC End of Regular Conversion interrupt source */
838 #define ADC_IT_JEOC ADC_CR1_JEOCIE /*!< ADC End of Injected Conversion interrupt source */
839 #define ADC_IT_AWD ADC_CR1_AWDIE /*!< ADC Analog watchdog interrupt source */
840 #define ADC_IT_OVR ADC_CR1_OVRIE /*!< ADC overrun interrupt source */
841 /**
842 * @}
843 */
844
845 /** @defgroup ADC_flags_definition ADC flags definition
846 * @{
847 */
848 #define ADC_FLAG_AWD ADC_SR_AWD /*!< ADC Analog watchdog flag */
849 #define ADC_FLAG_EOC ADC_SR_EOC /*!< ADC End of Regular conversion flag */
850 #define ADC_FLAG_JEOC ADC_SR_JEOC /*!< ADC End of Injected conversion flag */
851 #define ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC Injected group start flag */
852 #define ADC_FLAG_STRT ADC_SR_STRT /*!< ADC Regular group start flag */
853 #define ADC_FLAG_OVR ADC_SR_OVR /*!< ADC overrun flag */
854 #define ADC_FLAG_ADONS ADC_SR_ADONS /*!< ADC ready status flag */
855 #define ADC_FLAG_RCNR ADC_SR_RCNR /*!< ADC Regular group ready status flag */
856 #define ADC_FLAG_JCNR ADC_SR_JCNR /*!< ADC Regular group ready status flag */
857
858 /* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */
859 #define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_JEOC | ADC_FLAG_AWD | \
860 ADC_FLAG_OVR)
861 /**
862 * @}
863 */
864
865 /** @defgroup ADC_range_verification ADC range verification
866 * For a unique ADC resolution: 12 bits
867 * @{
868 */
869 #define IS_ADC_RANGE(ADC_VALUE) ((ADC_VALUE) <= ((uint32_t)0x0FFF))
870 /**
871 * @}
872 */
873
874 /** @defgroup ADC_regular_nb_conv_verification ADC regular nb conv verification
875 * @{
876 */
877 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
878 #define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)28)))
879 #else
880 #define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)27)))
881 #endif
882 /**
883 * @}
884 */
885
886 /** @defgroup ADC_regular_discontinuous_mode_number_verification ADC regular discontinuous mode number verification
887 * @{
888 */
889 #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8)))
890 /**
891 * @}
892 */
893
894 /**
895 * @}
896 */
897
898 /* Exported macro ------------------------------------------------------------*/
899
900 /** @defgroup ADC_Exported_Macros ADC Exported Macros
901 * @{
902 */
903 /* Macro for internal HAL driver usage, and possibly can be used into code of */
904 /* final user. */
905
906 /**
907 * @brief Verification of ADC state: enabled or disabled
908 * @param __HANDLE__: ADC handle
909 * @retval SET (ADC enabled) or RESET (ADC disabled)
910 */
911 #define __HAL_ADC_IS_ENABLED(__HANDLE__) \
912 ((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS ) \
913 ) ? SET : RESET)
914
915 /**
916 * @brief Test if conversion trigger of regular group is software start
917 * or external trigger.
918 * @param __HANDLE__: ADC handle
919 * @retval SET (software start) or RESET (external trigger)
920 */
921 #define __HAL_ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
922 (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
923
924 /**
925 * @brief Test if conversion trigger of injected group is software start
926 * or external trigger.
927 * @param __HANDLE__: ADC handle
928 * @retval SET (software start) or RESET (external trigger)
929 */
930 #define __HAL_ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
931 (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET)
932
933 /** @brief Checks if the specified ADC interrupt source is enabled or disabled.
934 * @param __HANDLE__: ADC handle
935 * @param __INTERRUPT__: ADC interrupt source to check
936 * @retval State of interruption (SET or RESET)
937 */
938 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
939 (( ((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__) \
940 )? SET : RESET \
941 )
942
943 /**
944 * @brief Enable the ADC end of conversion interrupt.
945 * @param __HANDLE__: ADC handle
946 * @param __INTERRUPT__: ADC Interrupt
947 * @retval None
948 */
949 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
950 (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
951
952 /**
953 * @brief Disable the ADC end of conversion interrupt.
954 * @param __HANDLE__: ADC handle
955 * @param __INTERRUPT__: ADC Interrupt
956 * @retval None
957 */
958 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
959 (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
960
961 /**
962 * @brief Get the selected ADC's flag status.
963 * @param __HANDLE__: ADC handle
964 * @param __FLAG__: ADC flag
965 * @retval None
966 */
967 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
968 ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
969
970 /**
971 * @brief Clear the ADC's pending flags
972 * @param __HANDLE__: ADC handle
973 * @param __FLAG__: ADC flag
974 * @retval None
975 */
976 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
977
978 /**
979 * @brief Clear ADC error code (set it to error code: "no error")
980 * @param __HANDLE__: ADC handle
981 * @retval None
982 */
983 #define __HAL_ADC_CLEAR_ERRORCODE(__HANDLE__) \
984 ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
985
986 /** @brief Reset ADC handle state
987 * @param __HANDLE__: ADC handle
988 * @retval None
989 */
990 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
991
992 /**
993 * @}
994 */
995
996 /* Include ADC HAL Extension module */
997 #include "stm32l1xx_hal_adc_ex.h"
998
999 /* Exported functions --------------------------------------------------------*/
1000 /** @addtogroup ADC_Exported_Functions
1001 * @{
1002 */
1003
1004 /** @addtogroup ADC_Exported_Functions_Group1
1005 * @{
1006 */
1007
1008
1009 /* Initialization and de-initialization functions **********************************/
1010 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
1011 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
1012 void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
1013 void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
1014 /**
1015 * @}
1016 */
1017
1018 /* IO operation functions *****************************************************/
1019
1020 /** @addtogroup ADC_Exported_Functions_Group2
1021 * @{
1022 */
1023
1024
1025 /* Blocking mode: Polling */
1026 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
1027 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
1028 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
1029 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
1030
1031 /* Non-blocking mode: Interruption */
1032 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
1033 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
1034
1035 /* Non-blocking mode: DMA */
1036 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
1037 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
1038
1039 /* ADC retrieve conversion value intended to be used with polling or interruption */
1040 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
1041
1042 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
1043 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
1044 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
1045 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
1046 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
1047 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
1048 /**
1049 * @}
1050 */
1051
1052
1053 /* Peripheral Control functions ***********************************************/
1054 /** @addtogroup ADC_Exported_Functions_Group3
1055 * @{
1056 */
1057 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
1058 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
1059 /**
1060 * @}
1061 */
1062
1063
1064 /* Peripheral State functions *************************************************/
1065 /** @addtogroup ADC_Exported_Functions_Group4
1066 * @{
1067 */
1068 HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
1069 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
1070 /**
1071 * @}
1072 */
1073
1074
1075 /**
1076 * @}
1077 */
1078
1079
1080 /* Internal HAL driver functions **********************************************/
1081 /** @addtogroup ADC_Private_Functions
1082 * @{
1083 */
1084
1085 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
1086 HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc);
1087 /**
1088 * @}
1089 */
1090
1091
1092 /**
1093 * @}
1094 */
1095
1096 /**
1097 * @}
1098 */
1099
1100 #ifdef __cplusplus
1101 }
1102 #endif
1103
1104
1105 #endif /* __STM32L1xx_HAL_ADC_H */
1106
1107 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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