tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_adc_ex.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32l1xx_hal_adc_ex.h
   4   * @author  MCD Application Team
   5   * @version V1.0.0
   6   * @date    5-September-2014
   7   * @brief   Header file of ADC HAL Extension module.
   8   ******************************************************************************
   9   * @attention
  10   *
  11   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
  12   *
  13   * Redistribution and use in source and binary forms, with or without modification,
  14   * are permitted provided that the following conditions are met:
  15   *   1. Redistributions of source code must retain the above copyright notice,
  16   *      this list of conditions and the following disclaimer.
  17   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18   *      this list of conditions and the following disclaimer in the documentation
  19   *      and/or other materials provided with the distribution.
  20   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21   *      may be used to endorse or promote products derived from this software
  22   *      without specific prior written permission.
  23   *
  24   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34   *
  35   ******************************************************************************
  36   */
  37
  38 /* Define to prevent recursive inclusion -------------------------------------*/
  39 #ifndef __STM32L1xx_HAL_ADC_EX_H
  40 #define __STM32L1xx_HAL_ADC_EX_H
  41
  42 #ifdef __cplusplus
  43  extern "C" {
  44 #endif
  45
  46 /* Includes ------------------------------------------------------------------*/
  47 #include "stm32l1xx_hal_def.h"
  48
  49 /** @addtogroup STM32L1xx_HAL_Driver
  50   * @{
  51   */
  52
  53 /** @addtogroup ADCEx
  54   * @{
  55   */
  56
  57 /* Exported types ------------------------------------------------------------*/
  58 /** @defgroup ADCEx_Exported_Types ADCEx Exported Types
  59   * @{
  60   */
  61
  62 /**
  63   * @brief  ADC Configuration injected Channel structure definition
  64   * @note   Parameters of this structure are shared within 2 scopes:
  65   *          - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset
  66   *          - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
  67   *            AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv.
  68   * @note   The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
  69   *         ADC state can be either:
  70   *          - For all parameters: ADC disabled
  71   *          - For all except parameters 'InjectedDiscontinuousConvMode' and 'AutoInjectedConv': ADC enabled without conversion on going on injected group.
  72   *          - For parameters 'ExternalTrigInjecConv' and 'ExternalTrigInjecConvEdge': ADC enabled, even with conversion on going on injected group.
  73   */
  74 typedef struct
  75 {
  76   uint32_t InjectedChannel;               /*!< Selection of ADC channel to configure
  77                                                This parameter can be a value of @ref ADC_channels
  78                                                Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
  79   uint32_t InjectedRank;                  /*!< Rank in the injected group sequencer
  80                                                This parameter must be a value of @ref ADCEx_injected_rank
  81                                                Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
  82   uint32_t InjectedSamplingTime;          /*!< Sampling time value to be set for the selected channel.
  83                                                Unit: ADC clock cycles
  84                                                Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
  85                                                This parameter can be a value of @ref ADC_sampling_times
  86                                                Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
  87                                                         If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
  88                                                Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
  89                                                      sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
  90                                                      Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
  91   uint32_t InjectedOffset;                /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only).
  92                                                Offset value must be a positive number.
  93                                                Depending of ADC resolution selected (12, 10, 8 or 6 bits),
  94                                                this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
  95   uint32_t InjectedNbrOfConversion;       /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
  96                                                To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
  97                                                This parameter must be a number between Min_Data = 1 and Max_Data = 4.
  98                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
  99                                                         configure a channel on injected group can impact the configuration of other channels previously set. */
 100   uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
 101                                                Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
 102                                                Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
 103                                                This parameter can be set to ENABLE or DISABLE.
 104                                                Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one.
 105                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
 106                                                         configure a channel on injected group can impact the configuration of other channels previously set. */
 107   uint32_t AutoInjectedConv;              /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
 108                                                This parameter can be set to ENABLE or DISABLE.
 109                                                Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
 110                                                Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START)
 111                                                Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
 112                                                      To maintain JAUTO always enabled, DMA must be configured in circular mode.
 113                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
 114                                                         configure a channel on injected group can impact the configuration of other channels previously set. */
 115   uint32_t ExternalTrigInjecConv;         /*!< Selects the external event used to trigger the conversion start of injected group.
 116                                                If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled.
 117                                                If set to external trigger source, triggering is on event rising edge.
 118                                                This parameter can be a value of @ref ADCEx_External_trigger_source_Injected
 119                                                Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
 120                                                      If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly)
 121                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
 122                                                         configure a channel on injected group can impact the configuration of other channels previously set. */
 123   uint32_t ExternalTrigInjecConvEdge;     /*!< Selects the external trigger edge of injected group.
 124                                                This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected.
 125                                                If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded.
 126                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
 127                                                         configure a channel on injected group can impact the configuration of other channels previously set. */
 128 }ADC_InjectionConfTypeDef;
 129 /**
 130   * @}
 131   */
 132
 133
 134 /* Exported constants --------------------------------------------------------*/
 135
 136 /** @defgroup ADCEx_Exported_Constants ADCEx Exported Constants
 137   * @{
 138   */
 139
 140 /** @defgroup ADCEx_injected_rank ADCEx injected rank
 141   * @{
 142   */
 143 #define ADC_INJECTED_RANK_1    ((uint32_t)0x00000001)
 144 #define ADC_INJECTED_RANK_2    ((uint32_t)0x00000002)
 145 #define ADC_INJECTED_RANK_3    ((uint32_t)0x00000003)
 146 #define ADC_INJECTED_RANK_4    ((uint32_t)0x00000004)
 147
 148 #define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || \
 149                                        ((CHANNEL) == ADC_INJECTED_RANK_2) || \
 150                                        ((CHANNEL) == ADC_INJECTED_RANK_3) || \
 151                                        ((CHANNEL) == ADC_INJECTED_RANK_4)   )
 152 /**
 153   * @}
 154   */
 155
 156 /** @defgroup ADCEx_External_trigger_edge_Injected ADCEx External trigger edge Injected
 157   * @{
 158   */
 159 #define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE           ((uint32_t)0x00000000)
 160 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING         ((uint32_t)ADC_CR2_JEXTEN_0)
 161 #define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING        ((uint32_t)ADC_CR2_JEXTEN_1)
 162 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING  ((uint32_t)ADC_CR2_JEXTEN)
 163
 164 #define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE)         || \
 165                                         ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING)       || \
 166                                         ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING)      || \
 167                                         ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING)  )
 168 /**
 169   * @}
 170   */
 171
 172 /** @defgroup ADCEx_External_trigger_source_Injected ADCEx External trigger source Injected
 173   * @{
 174   */
 175 /* External triggers for injected groups of ADC1 */
 176 #define ADC_EXTERNALTRIGINJECCONV_T2_CC1      ADC_EXTERNALTRIGINJEC_T2_CC1
 177 #define ADC_EXTERNALTRIGINJECCONV_T2_TRGO     ADC_EXTERNALTRIGINJEC_T2_TRGO
 178 #define ADC_EXTERNALTRIGINJECCONV_T3_CC4      ADC_EXTERNALTRIGINJEC_T3_CC4
 179 #define ADC_EXTERNALTRIGINJECCONV_T4_TRGO     ADC_EXTERNALTRIGINJEC_T4_TRGO
 180 #define ADC_EXTERNALTRIGINJECCONV_T4_CC1      ADC_EXTERNALTRIGINJEC_T4_CC1
 181 #define ADC_EXTERNALTRIGINJECCONV_T4_CC2      ADC_EXTERNALTRIGINJEC_T4_CC2
 182 #define ADC_EXTERNALTRIGINJECCONV_T4_CC3      ADC_EXTERNALTRIGINJEC_T4_CC3
 183 #define ADC_EXTERNALTRIGINJECCONV_T7_TRGO     ADC_EXTERNALTRIGINJEC_T7_TRGO
 184 #define ADC_EXTERNALTRIGINJECCONV_T9_CC1      ADC_EXTERNALTRIGINJEC_T9_CC1
 185 #define ADC_EXTERNALTRIGINJECCONV_T9_TRGO     ADC_EXTERNALTRIGINJEC_T9_TRGO
 186 #define ADC_EXTERNALTRIGINJECCONV_T10_CC1     ADC_EXTERNALTRIGINJEC_T10_CC1
 187 #define ADC_EXTERNALTRIGINJECCONV_EXT_IT15    ADC_EXTERNALTRIGINJEC_EXT_IT15
 188
 189 #define ADC_INJECTED_SOFTWARE_START      ((uint32_t)0x00000010)
 190
 191 #define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1)   || \
 192                                       ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO)  || \
 193                                       ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4)   || \
 194                                       ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO)  || \
 195                                       ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC1)   || \
 196                                       ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC2)   || \
 197                                       ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3)   || \
 198                                       ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T7_TRGO)  || \
 199                                       ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T9_CC1)   || \
 200                                       ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T9_TRGO)  || \
 201                                       ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T10_CC1)  || \
 202                                       ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
 203                                       ((REGTRIG) == ADC_SOFTWARE_START)              )
 204 /**
 205   * @}
 206   */
 207
 208 /** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Injected ADCEx Internal HAL driver Ext trig src Injected
 209   * @{
 210   */
 211
 212 /* List of external triggers of injected group for ADC1:                      */
 213 /* (used internally by HAL driver. To not use into HAL structure parameters)  */
 214 #define ADC_EXTERNALTRIGINJEC_T9_CC1         ((uint32_t) 0x00000000)
 215 #define ADC_EXTERNALTRIGINJEC_T9_TRGO        ((uint32_t)(                                                         ADC_CR2_JEXTSEL_0))
 216 #define ADC_EXTERNALTRIGINJEC_T2_TRGO        ((uint32_t)(                                      ADC_CR2_JEXTSEL_1                   ))
 217 #define ADC_EXTERNALTRIGINJEC_T2_CC1         ((uint32_t)(                                      ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
 218 #define ADC_EXTERNALTRIGINJEC_T3_CC4         ((uint32_t)(                   ADC_CR2_JEXTSEL_2                                      ))
 219 #define ADC_EXTERNALTRIGINJEC_T4_TRGO        ((uint32_t)(                   ADC_CR2_JEXTSEL_2 |                    ADC_CR2_JEXTSEL_0))
 220 #define ADC_EXTERNALTRIGINJEC_T4_CC1         ((uint32_t)(                   ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1                   ))
 221 #define ADC_EXTERNALTRIGINJEC_T4_CC2         ((uint32_t)(                   ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
 222 #define ADC_EXTERNALTRIGINJEC_T4_CC3         ((uint32_t)(ADC_CR2_JEXTSEL_3                                                         ))
 223 #define ADC_EXTERNALTRIGINJEC_T10_CC1        ((uint32_t)(ADC_CR2_JEXTSEL_3                                       | ADC_CR2_JEXTSEL_0))
 224 #define ADC_EXTERNALTRIGINJEC_T7_TRGO        ((uint32_t)(ADC_CR2_JEXTSEL_3                    | ADC_CR2_JEXTSEL_1                   ))
 225 #define ADC_EXTERNALTRIGINJEC_EXT_IT15       ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
 226
 227 /**
 228   * @}
 229   */
 230
 231
 232 /** @defgroup ADCEx_injected_nb_conv_verification ADCEx injected nb conv verification
 233   * @{
 234   */
 235 #define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)4)))
 236 /**
 237   * @}
 238   */
 239
 240 /**
 241   * @}
 242   */
 243
 244
 245 /* Exported macro ------------------------------------------------------------*/
 246
 247 /** @defgroup ADCEx_Exported_Macros ADCEx Exported Macros
 248   * @{
 249   */
 250 /* Macro for internal HAL driver usage, and possibly can be used into code of */
 251 /* final user.                                                                */
 252
 253 /**
 254   * @brief Selection of channels bank.
 255   * Note: Banks availability depends on devices categories.
 256   * This macro is intended to change bank selection quickly on the fly,
 257   * without going through ADC init structure update and execution of function
 258   * 'HAL_ADC_Init()'.
 259   * @param __HANDLE__: ADC handle
 260   * @param __BANK__: Bank selection. This parameter can be a value of @ref ADC_ChannelsBank.
 261   * @retval None
 262   */
 263 #define __HAL_ADC_CHANNELS_BANK(__HANDLE__, __BANK__)                          \
 264   MODIFY_REG((__HANDLE__)->Instance->CR2, ADC_CR2_CFG, (__BANK__))
 265
 266 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
 267 /**
 268  * @brief Configures the ADC channels speed.
 269  * Limited to channels 3, 8, 13 and to devices category Cat.3, Cat.4, Cat.5.
 270  *  - For ADC_CHANNEL_3: Used as ADC direct channel (fast channel) if OPAMP1 is
 271  *    in power down mode.
 272  *  - For ADC_CHANNEL_8: Used as ADC direct channel (fast channel) if OPAMP2 is
 273  *    in power down mode.
 274  *  - For ADC_CHANNEL_13: Used as ADC re-routed channel if OPAMP3 is in
 275  *    power down mode. Otherwise, channel 13 is connected to OPAMP3 output and
 276  *    routed through switches COMP1_SW1 and VCOMP to ADC switch matrix.
 277  *    (Note: OPAMP3 is available on STM32L1 Cat.4 only).
 278  * @param __CHANNEL__: ADC channel
 279  * This parameter can be one of the following values:
 280  * @arg ADC_CHANNEL_3: Channel 3 is selected.
 281  * @arg ADC_CHANNEL_8: Channel 8 is selected.
 282  * @arg ADC_CHANNEL_13: Channel 13 is selected.
 283  * @retval None
 284  */
 285 #define __HAL_ADC_CHANNEL_SPEED_FAST(__CHANNEL__)                              \
 286   ( ( ((__CHANNEL__) == ADC_CHANNEL_3)                                         \
 287     )?                                                                         \
 288      (SET_BIT(COMP->CSR, COMP_CSR_FCH3))                                       \
 289      :                                                                         \
 290      ( ( ((__CHANNEL__) == ADC_CHANNEL_8)                                      \
 291        )?                                                                      \
 292         (SET_BIT(COMP->CSR, COMP_CSR_FCH8))                                    \
 293         :                                                                      \
 294         ( ( ((__CHANNEL__) == ADC_CHANNEL_13)                                  \
 295           )?                                                                   \
 296            (SET_BIT(COMP->CSR, COMP_CSR_RCH13))                                \
 297            :                                                                   \
 298            (SET_BIT(COMP->CSR, 0x00000000))                                    \
 299         )                                                                      \
 300      )                                                                         \
 301   )
 302
 303 #define __HAL_ADC_CHANNEL_SPEED_SLOW(__CHANNEL__)                              \
 304   ( ( ((__CHANNEL__) == ADC_CHANNEL_3)                                         \
 305     )?                                                                         \
 306      (CLEAR_BIT(COMP->CSR, COMP_CSR_FCH3))                                     \
 307      :                                                                         \
 308      ( ( ((__CHANNEL__) == ADC_CHANNEL_8)                                      \
 309        )?                                                                      \
 310         (CLEAR_BIT(COMP->CSR, COMP_CSR_FCH8))                                  \
 311         :                                                                      \
 312         ( ( ((__CHANNEL__) == ADC_CHANNEL_13)                                  \
 313           )?                                                                   \
 314            (CLEAR_BIT(COMP->CSR, COMP_CSR_RCH13))                              \
 315            :                                                                   \
 316            (SET_BIT(COMP->CSR, 0x00000000))                                    \
 317         )                                                                      \
 318      )                                                                         \
 319   )
 320 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
 321
 322 /**
 323   * @}
 324   */
 325
 326 /* Private macro ------------------------------------------------------------*/
 327
 328 /** @defgroup ADCEx_Private_Macro ADCEx Private Macro
 329   * @{
 330   */
 331 /* Macro reserved for internal HAL driver usage, not intended to be used in   */
 332 /* code of final user.                                                        */
 333
 334 /**
 335   * @brief Set ADC number of ranks into regular channel sequence length.
 336   * @param _NbrOfConversion_: Regular channel sequence length
 337   * @retval None
 338   */
 339 #define __ADC_SQR1_L(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << POSITION_VAL(ADC_SQR1_L))
 340
 341 /**
 342   * @brief Set ADC ranks available in register SQR1.
 343   * Register SQR1 bits availability depends on device category.
 344   * @param _NbrOfConversion_: Regular channel sequence length
 345   * @retval None
 346   */
 347 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
 348 #define __ADC_SQR1_SQXX   ADC_SQR1_SQ28 | ADC_SQR1_SQ27 | ADC_SQR1_SQ26 | ADC_SQR1_SQ25
 349 #else
 350 #define __ADC_SQR1_SQXX   ADC_SQR1_SQ27 | ADC_SQR1_SQ26 | ADC_SQR1_SQ25
 351 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
 352
 353 /**
 354   * @brief Set the ADC's sample time for channel numbers between 30 and 31.
 355   * Register SMPR0 availability depends on device category. If register is not
 356   * available on the current device, this macro does nothing.
 357   * @retval None
 358   * @param _SAMPLETIME_: Sample time parameter.
 359   * @param _CHANNELNB_: Channel number.
 360   * @retval None
 361   */
 362 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
 363 #define __ADC_SMPR0(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 30)))
 364 #else
 365 #define __ADC_SMPR0(_SAMPLETIME_, _CHANNELNB_) ((uint32_t)0x00000000)
 366 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
 367
 368 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
 369 /**
 370   * @brief Set the ADC's sample time for channel numbers between 20 and 29.
 371   * @param _SAMPLETIME_: Sample time parameter.
 372   * @param _CHANNELNB_: Channel number.
 373   * @retval None
 374   */
 375 #define __ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 20)))
 376 #else
 377 /**
 378   * @brief Set the ADC's sample time for channel numbers between 20 and 26.
 379   * @param _SAMPLETIME_: Sample time parameter.
 380   * @param _CHANNELNB_: Channel number.
 381   * @retval None
 382   */
 383 #define __ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 20)))
 384 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
 385
 386 /**
 387   * @brief Defines the highest channel available in register SMPR1. Channels
 388   * availability depends on device category:
 389   * Highest channel in register SMPR1 is channel 26 for devices Cat.1, Cat.2, Cat.3
 390   * Highest channel in register SMPR1 is channel 29 for devices Cat.4, Cat.5
 391   * @param None
 392   * @retval None
 393   */
 394 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
 395 #define ADC_SMPR1_CHANNEL_MAX   ADC_CHANNEL_29
 396 #else
 397 #define ADC_SMPR1_CHANNEL_MAX   ADC_CHANNEL_26
 398 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
 399
 400 /**
 401   * @brief Set the ADC's sample time for channel numbers between 10 and 18.
 402   * @param _SAMPLETIME_: Sample time parameter.
 403   * @param _CHANNELNB_: Channel number.
 404   * @retval None
 405   */
 406 #define __ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 10)))
 407
 408 /**
 409   * @brief Set the ADC's sample time for channel numbers between 0 and 9.
 410   * @param _SAMPLETIME_: Sample time parameter.
 411   * @param _CHANNELNB_: Channel number.
 412   * @retval None
 413   */
 414 #define __ADC_SMPR3(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * (_CHANNELNB_)))
 415
 416 /**
 417   * @brief Set the selected regular channel rank for rank between 1 and 6.
 418   * @param _CHANNELNB_: Channel number.
 419   * @param _RANKNB_: Rank number.
 420   * @retval None
 421   */
 422 #define __ADC_SQR5_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 1)))
 423
 424 /**
 425   * @brief Set the selected regular channel rank for rank between 7 and 12.
 426   * @param _CHANNELNB_: Channel number.
 427   * @param _RANKNB_: Rank number.
 428   * @retval None
 429   */
 430 #define __ADC_SQR4_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 7)))
 431
 432 /**
 433   * @brief Set the selected regular channel rank for rank between 13 and 18.
 434   * @param _CHANNELNB_: Channel number.
 435   * @param _RANKNB_: Rank number.
 436   * @retval None
 437   */
 438 #define __ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 13)))
 439
 440 /**
 441   * @brief Set the selected regular channel rank for rank between 19 and 24.
 442   * @param _CHANNELNB_: Channel number.
 443   * @param _RANKNB_: Rank number.
 444   * @retval None
 445   */
 446 #define __ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 19)))
 447
 448 /**
 449   * @brief Set the selected regular channel rank for rank between 25 and 28.
 450   * @param _CHANNELNB_: Channel number.
 451   * @param _RANKNB_: Rank number.
 452   * @retval None
 453   */
 454 #define __ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 25)))
 455
 456 /**
 457   * @brief Set the injected sequence length.
 458   * @param _JSQR_JL_: Sequence length.
 459   * @retval None
 460   */
 461 #define __ADC_JSQR_JL(_JSQR_JL_)   (((_JSQR_JL_) -1) << 20)
 462
 463 /**
 464   * @brief Set the selected injected Channel rank (channels sequence starting from 4-JL)
 465   * @param _CHANNELNB_: Channel number.
 466   * @param _RANKNB_: Rank number.
 467   * @param _JSQR_JL_: Sequence length.
 468   * @retval None
 469   */
 470 #define __ADC_JSQR_RK(_CHANNELNB_, _RANKNB_, _JSQR_JL_)                        \
 471     ((_CHANNELNB_) << (5 * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1)))
 472
 473
 474 /**
 475   * @brief Enable the ADC DMA continuous request.
 476   * @param _DMACONTREQ_MODE_: DMA continuous request mode.
 477   * @retval None
 478   */
 479 #define __ADC_CR2_DMACONTREQ(_DMACONTREQ_MODE_) ((_DMACONTREQ_MODE_) << POSITION_VAL(ADC_CR2_DDS))
 480
 481 /**
 482   * @brief Enable ADC continuous conversion mode.
 483   * @param _CONTINUOUS_MODE_: Continuous mode.
 484   * @retval None
 485   */
 486 #define __ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << POSITION_VAL(ADC_CR2_CONT))
 487
 488 /**
 489   * @brief Define mask of configuration bits of ADC and regular group in
 490   * register CR2 (bits of ADC enable, conversion start and injected group are
 491   * excluded of this mask).
 492   * @retval None
 493   */
 494 #if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
 495 #define __ADC_CR2_MASK_ADCINIT()                                               \
 496   (ADC_CR2_EXTEN | ADC_CR2_EXTSEL | ADC_CR2_ALIGN | ADC_CR2_EOCS | ADC_CR2_DDS | ADC_CR2_DELS | ADC_CR2_CFG | ADC_CR2_CONT)
 497 #else
 498 #define __ADC_CR2_MASK_ADCINIT()                                               \
 499   (ADC_CR2_EXTEN | ADC_CR2_EXTSEL | ADC_CR2_ALIGN | ADC_CR2_EOCS | ADC_CR2_DDS | ADC_CR2_DELS | ADC_CR2_CONT)
 500 #endif
 501
 502 /**
 503   * @brief Configures the number of discontinuous conversions for the regular group channels.
 504   * @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions.
 505   * @retval None
 506   */
 507 #define __ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_) - 1) << POSITION_VAL(ADC_CR1_DISCNUM))
 508
 509 /**
 510   * @brief Enable ADC scan mode to convert multiple ranks with sequencer.
 511   * @param _SCAN_MODE_: Scan conversion mode.
 512   * @retval None
 513   */
 514 #define __ADC_CR1_SCAN(_SCAN_MODE_)                                            \
 515   ( ( (_SCAN_MODE_) == (ADC_SCAN_ENABLE)                                       \
 516     )? (ADC_CR1_SCAN) : (0x00000000)                                           \
 517   )
 518
 519 /**
 520   * @brief Get the maximum ADC conversion cycles on all channels.
 521   * Returns the selected sampling time + conversion time (12.5 ADC clock cycles)
 522   * Approximation of sampling time within 2 ranges, returns the higher value:
 523   *   below 24 cycles {4 cycles; 9 cycles; 16 cycles; 24 cycles}
 524   *   between 48 cycles and 384 cycles {48 cycles; 96 cycles; 192 cycles; 384 cycles}
 525   * Unit: ADC clock cycles
 526   * @param __HANDLE__: ADC handle
 527   * @retval ADC conversion cycles on all channels
 528   */
 529 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
 530 #define __ADC_CONVCYCLES_MAX_RANGE(__HANDLE__)                                                          \
 531     (( (((__HANDLE__)->Instance->SMPR3 & ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT2) == RESET)  &&            \
 532        (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET)  &&            \
 533        (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET)  &&            \
 534        (((__HANDLE__)->Instance->SMPR0 & ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT2) == RESET) ) ?            \
 535                                                                                                         \
 536         ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_24CYCLES : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_384CYCLES  \
 537      )
 538 #else
 539 #define __ADC_CONVCYCLES_MAX_RANGE(__HANDLE__)                                                          \
 540     (( (((__HANDLE__)->Instance->SMPR3 & ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT2) == RESET)  &&            \
 541        (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET)  &&            \
 542        (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) ) ?            \
 543                                                                                                         \
 544         ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_24CYCLES : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_384CYCLES  \
 545      )
 546 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
 547
 548 /**
 549   * @brief Get the ADC clock prescaler from ADC common control register
 550   * and convert it to its decimal number setting (refer to reference manual)
 551   * @retval None
 552   */
 553 #define __ADC_GET_CLOCK_PRESCALER_DECIMAL(__HANDLE__)                          \
 554     ((0x01) << ((ADC->CCR & ADC_CCR_ADCPRE) >> POSITION_VAL(ADC_CCR_ADCPRE)))
 555
 556 /**
 557   * @brief Clear register SMPR0.
 558   * Register SMPR0 availability depends on device category. If register is not
 559   * available on the current device, this macro performs no action.
 560   * @param __HANDLE__: ADC handle
 561   * @retval None
 562   */
 563 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
 564 #define __ADC_SMPR0_CLEAR(__HANDLE__)                                          \
 565   (CLEAR_BIT((__HANDLE__)->Instance->SMPR0, (ADC_SMPR0_SMP31 | ADC_SMPR0_SMP30)))
 566 #else
 567 #define __ADC_SMPR0_CLEAR(__HANDLE__) __NOP()
 568 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
 569
 570 /**
 571   * @brief Clear register CR2.
 572   * @param __HANDLE__: ADC handle
 573   * @retval None
 574   */
 575 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
 576 #define __ADC_CR2_CLEAR(__HANDLE__)                                                                \
 577   (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_SWSTART  | ADC_CR2_EXTEN  | ADC_CR2_EXTSEL  |   \
 578                                            ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL |   \
 579                                            ADC_CR2_ALIGN    | ADC_CR2_EOCS   | ADC_CR2_DDS     |   \
 580                                            ADC_CR2_DMA      | ADC_CR2_DELS   | ADC_CR2_CFG     |   \
 581                                            ADC_CR2_CONT     | ADC_CR2_ADON                      )) \
 582   )
 583 #else
 584 #define __ADC_CR2_CLEAR(__HANDLE__)                                                                \
 585   (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_SWSTART  | ADC_CR2_EXTEN  | ADC_CR2_EXTSEL  |   \
 586                                            ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL |   \
 587                                            ADC_CR2_ALIGN    | ADC_CR2_EOCS   | ADC_CR2_DDS     |   \
 588                                            ADC_CR2_DMA      | ADC_CR2_DELS   |                     \
 589                                            ADC_CR2_CONT     | ADC_CR2_ADON                      )) \
 590   )
 591 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
 592
 593 /**
 594   * @brief Set the sampling time of selected channel on register SMPR0
 595   * Register SMPR0 availability depends on device category. If register is not
 596   * available on the current device, this macro performs no action.
 597   * @param __HANDLE__: ADC handle
 598   * @param _SAMPLETIME_: Sample time parameter.
 599   * @param __CHANNEL__: Channel number.
 600   * @retval None
 601   */
 602 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
 603 #define __ADC_SMPR0_CHANNEL_SET(__HANDLE__, _SAMPLETIME_, __CHANNEL__)         \
 604     MODIFY_REG((__HANDLE__)->Instance->SMPR0,                                  \
 605                __ADC_SMPR0(ADC_SMPR0_SMP30, (__CHANNEL__)),                    \
 606                __ADC_SMPR0((_SAMPLETIME_), (__CHANNEL__))  )
 607 #else
 608 #define __ADC_SMPR0_CHANNEL_SET(__HANDLE__, _SAMPLETIME_, __CHANNEL__) __NOP()
 609 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
 610
 611
 612 /**
 613   * @brief Enable the ADC peripheral
 614   * @param __HANDLE__: ADC handle
 615   * @retval None
 616   */
 617 #define __ADC_ENABLE(__HANDLE__)                                               \
 618             (__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON
 619
 620 /**
 621   * @brief Disable the ADC peripheral
 622   * @param __HANDLE__: ADC handle
 623   * @retval None
 624   */
 625 #define __ADC_DISABLE(__HANDLE__)                                              \
 626             (__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON
 627
 628 /**
 629   * @}
 630   */
 631
 632
 633 /* Exported functions --------------------------------------------------------*/
 634 /** @addtogroup ADCEx_Exported_Functions
 635   * @{
 636   */
 637
 638 /* IO operation functions  *****************************************************/
 639 /** @addtogroup ADCEx_Exported_Functions_Group1
 640   * @{
 641   */
 642
 643 /* Blocking mode: Polling */
 644 HAL_StatusTypeDef       HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc);
 645 HAL_StatusTypeDef       HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc);
 646 HAL_StatusTypeDef       HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
 647
 648 /* Non-blocking mode: Interruption */
 649 HAL_StatusTypeDef       HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);
 650 HAL_StatusTypeDef       HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);
 651
 652 /* ADC retrieve conversion value intended to be used with polling or interruption */
 653 uint32_t                HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
 654
 655 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
 656 void                    HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);
 657 /**
 658   * @}
 659   */
 660
 661
 662 /* Peripheral Control functions ***********************************************/
 663 /** @addtogroup ADCEx_Exported_Functions_Group2
 664   * @{
 665   */
 666
 667 HAL_StatusTypeDef       HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
 668 /**
 669   * @}
 670   */
 671
 672
 673 /**
 674   * @}
 675   */
 676
 677
 678 /**
 679   * @}
 680   */
 681
 682 /**
 683   * @}
 684   */
 685
 686 #ifdef __cplusplus
 687 }
 688 #endif
 689
 690 #endif /* __STM32L1xx_HAL_ADC_EX_H */
 691
 692
 693 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/