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[tmk_keyboard.git] / tool / mbed / mbed-sdk / libraries / mbed / targets / cmsis / TARGET_STM / TARGET_STM32L1 / stm32l1xx_hal_cryp.c
1 /**
2 ******************************************************************************
3 * @file stm32l1xx_hal_cryp.c
4 * @author MCD Application Team
5 * @version V1.0.0
6 * @date 5-September-2014
7 * @brief CRYP HAL module driver.
8 *
9 * This file provides firmware functions to manage the following
10 * functionalities of the Cryptography (CRYP) peripheral:
11 * + Initialization and de-initialization functions
12 * + Processing functions by algorithm using polling mode
13 * + Processing functions by algorithm using interrupt mode
14 * + Processing functions by algorithm using DMA mode
15 * + Peripheral State functions
16 *
17 @verbatim
18 ==============================================================================
19 ##### How to use this driver #####
20 ==============================================================================
21 [..]
22 The CRYP HAL driver can be used as follows:
23
24 (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
25 (##) Enable the CRYP interface clock using __CRYP_CLK_ENABLE()
26 (##) In case of using interrupts (e.g. HAL_CRYP_AESECB_Encrypt_IT())
27 (+) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
28 (+) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
29 (+) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
30 (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_AESECB_Encrypt_DMA())
31 (+) Enable the DMA2 interface clock using
32 (++) __DMA2_CLK_ENABLE()
33 (+) Configure and enable two DMA Channels one for managing data transfer from
34 memory to peripheral (input channel) and another channel for managing data
35 transfer from peripheral to memory (output channel)
36 (+) Associate the initialized DMA handle to the CRYP DMA handle
37 using __HAL_LINKDMA()
38 (+) Configure the priority and enable the NVIC for the transfer complete
39 interrupt on the two DMA Streams. The output stream should have higher
40 priority than the input stream.
41 (++) HAL_NVIC_SetPriority()
42 (++) HAL_NVIC_EnableIRQ()
43
44 (#)Initialize the CRYP HAL using HAL_CRYP_Init(). This function configures mainly:
45 (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit
46 (##) The encryption/decryption key.
47 (##) The initialization vector (counter). It is not used ECB mode.
48
49 (#)Three processing (encryption/decryption) functions are available:
50 (##) Polling mode: encryption and decryption APIs are blocking functions
51 i.e. they process the data and wait till the processing is finished
52 e.g. HAL_CRYP_AESCBC_Encrypt()
53 (##) Interrupt mode: encryption and decryption APIs are not blocking functions
54 i.e. they process the data under interrupt
55 e.g. HAL_CRYP_AESCBC_Encrypt_IT()
56 (##) DMA mode: encryption and decryption APIs are not blocking functions
57 i.e. the data transfer is ensured by DMA
58 e.g. HAL_CRYP_AESCBC_Encrypt_DMA()
59
60 (#)When the processing function is called for the first time after HAL_CRYP_Init()
61 the CRYP peripheral is initialized and processes the buffer in input.
62 At second call, the processing function performs an append of the already
63 processed buffer.
64 When a new data block is to be processed, call HAL_CRYP_Init() then the
65 processing function.
66
67 (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
68
69 @endverbatim
70 ******************************************************************************
71 * @attention
72 *
73 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
74 *
75 * Redistribution and use in source and binary forms, with or without modification,
76 * are permitted provided that the following conditions are met:
77 * 1. Redistributions of source code must retain the above copyright notice,
78 * this list of conditions and the following disclaimer.
79 * 2. Redistributions in binary form must reproduce the above copyright notice,
80 * this list of conditions and the following disclaimer in the documentation
81 * and/or other materials provided with the distribution.
82 * 3. Neither the name of STMicroelectronics nor the names of its contributors
83 * may be used to endorse or promote products derived from this software
84 * without specific prior written permission.
85 *
86 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
87 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
88 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
89 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
90 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
91 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
92 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
93 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
94 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
95 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
96 *
97 ******************************************************************************
98 */
99
100 /* Includes ------------------------------------------------------------------*/
101 #include "stm32l1xx_hal.h"
102
103 #ifdef HAL_CRYP_MODULE_ENABLED
104
105 /** @addtogroup STM32L1xx_HAL_Driver
106 * @{
107 */
108
109 /** @defgroup CRYP CRYP
110 * @brief CRYP HAL module driver.
111 * @{
112 */
113
114 #if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE)
115
116 /* Private typedef -----------------------------------------------------------*/
117 /* Private define ------------------------------------------------------------*/
118
119 /** @defgroup CRYP_Private_Defines CRYP Private Defines
120 * @{
121 */
122
123 #define CRYP_ALGO_CHAIN_MASK (AES_CR_MODE | AES_CR_CHMOD)
124
125 /**
126 * @}
127 */
128
129 /* Private macro -------------------------------------------------------------*/
130 /* Private variables ---------------------------------------------------------*/
131 /* Private function prototypes -----------------------------------------------*/
132
133 /** @defgroup CRYP_Private_Functions CRYP Private Functions
134 * @{
135 */
136
137 static HAL_StatusTypeDef CRYP_EncryptDecrypt_IT(CRYP_HandleTypeDef *hcryp);
138 static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector);
139 static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key);
140 static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout);
141 static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);
142 static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma);
143 static void CRYP_DMAError(DMA_HandleTypeDef *hdma);
144 static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
145
146 /**
147 * @}
148 */
149
150 /* Private functions ---------------------------------------------------------*/
151
152 /** @defgroup CRYP_Exported_Functions CRYP Exported Functions
153 * @{
154 */
155
156 /** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions
157 * @brief Initialization and Configuration functions.
158 *
159 @verbatim
160 ==============================================================================
161 ##### Initialization and de-initialization functions #####
162 ==============================================================================
163 [..] This section provides functions allowing to:
164 (+) Initialize the CRYP according to the specified parameters
165 in the CRYP_InitTypeDef and creates the associated handle
166 (+) DeInitialize the CRYP peripheral
167 (+) Initialize the CRYP MSP
168 (+) DeInitialize CRYP MSP
169
170 @endverbatim
171 * @{
172 */
173
174 /**
175 * @brief Initializes the CRYP according to the specified
176 * parameters in the CRYP_InitTypeDef and creates the associated handle.
177 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
178 * the configuration information for CRYP module
179 * @retval HAL status
180 */
181 HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
182 {
183 /* Check the CRYP handle allocation */
184 if(hcryp == HAL_NULL)
185 {
186 return HAL_ERROR;
187 }
188
189 /* Check the parameters */
190 assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));
191
192 if(hcryp->State == HAL_CRYP_STATE_RESET)
193 {
194 /* Init the low level hardware */
195 HAL_CRYP_MspInit(hcryp);
196 }
197
198 /* Check if AES already enabled */
199 if (HAL_IS_BIT_CLR(AES->CR, AES_CR_EN))
200 {
201 /* Change the CRYP state */
202 hcryp->State = HAL_CRYP_STATE_BUSY;
203
204 /* Set the data type*/
205 MODIFY_REG(AES->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
206
207 /* Reset CrypInCount and CrypOutCount */
208 hcryp->CrypInCount = 0;
209 hcryp->CrypOutCount = 0;
210
211 /* Change the CRYP state */
212 hcryp->State = HAL_CRYP_STATE_READY;
213
214 /* Set the default CRYP phase */
215 hcryp->Phase = HAL_CRYP_PHASE_READY;
216
217 /* Return function status */
218 return HAL_OK;
219 }
220 else
221 {
222 /* The Datatype selection must be changed if the AES is disabled. Writing these bits while the AES is */
223 /* enabled is forbidden to avoid unpredictable AES behavior.*/
224
225 /* Return function status */
226 return HAL_ERROR;
227 }
228
229 }
230
231 /**
232 * @brief DeInitializes the CRYP peripheral.
233 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
234 * the configuration information for CRYP module
235 * @retval HAL status
236 */
237 HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
238 {
239 /* Check the CRYP handle allocation */
240 if(hcryp == HAL_NULL)
241 {
242 return HAL_ERROR;
243 }
244
245 /* Change the CRYP state */
246 hcryp->State = HAL_CRYP_STATE_BUSY;
247
248 /* Set the default CRYP phase */
249 hcryp->Phase = HAL_CRYP_PHASE_READY;
250
251 /* Reset CrypInCount and CrypOutCount */
252 hcryp->CrypInCount = 0;
253 hcryp->CrypOutCount = 0;
254
255 /* Disable the CRYP Peripheral Clock */
256 __HAL_CRYP_DISABLE();
257
258 /* DeInit the low level hardware: CLOCK, NVIC.*/
259 HAL_CRYP_MspDeInit(hcryp);
260
261 /* Change the CRYP state */
262 hcryp->State = HAL_CRYP_STATE_RESET;
263
264 /* Release Lock */
265 __HAL_UNLOCK(hcryp);
266
267 /* Return function status */
268 return HAL_OK;
269 }
270
271 /**
272 * @brief Initializes the CRYP MSP.
273 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
274 * the configuration information for CRYP module
275 * @retval None
276 */
277 __weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
278 {
279 /* NOTE : This function should not be modified; when the callback is needed,
280 the HAL_CRYP_MspInit can be implemented in the user file */
281 }
282
283 /**
284 * @brief DeInitializes CRYP MSP.
285 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
286 * the configuration information for CRYP module
287 * @retval None
288 */
289 __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
290 {
291 /* NOTE : This function should not be modified; when the callback is needed,
292 the HAL_CRYP_MspDeInit can be implemented in the user file */
293 }
294
295 /**
296 * @}
297 */
298
299 /** @defgroup CRYP_Exported_Functions_Group2 AES processing functions
300 * @brief processing functions.
301 *
302 @verbatim
303 ==============================================================================
304 ##### AES processing functions #####
305 ==============================================================================
306 [..] This section provides functions allowing to:
307 (+) Encrypt plaintext using AES algorithm in different chaining modes
308 (+) Decrypt cyphertext using AES algorithm in different chaining modes
309 [..] Three processing functions are available:
310 (+) Polling mode
311 (+) Interrupt mode
312 (+) DMA mode
313
314 @endverbatim
315 * @{
316 */
317
318 /**
319 * @brief Initializes the CRYP peripheral in AES ECB encryption mode
320 * then encrypt pPlainData. The cypher data are available in pCypherData
321 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
322 * the configuration information for CRYP module
323 * @param pPlainData: Pointer to the plaintext buffer (aligned on u32)
324 * @param Size: Length of the plaintext buffer, must be a multiple of 16.
325 * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32)
326 * @param Timeout: Specify Timeout value
327 * @retval HAL status
328 */
329 HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
330 {
331 /* Process Locked */
332 __HAL_LOCK(hcryp);
333
334 /* Check that data aligned on u32 and Size multiple of 16*/
335 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
336 {
337 /* Process Locked */
338 __HAL_UNLOCK(hcryp);
339
340 /* Return function status */
341 return HAL_ERROR;
342 }
343
344 /* Check if HAL_CRYP_Init has been called */
345 if(hcryp->State != HAL_CRYP_STATE_RESET)
346 {
347 /* Change the CRYP state */
348 hcryp->State = HAL_CRYP_STATE_BUSY;
349
350 /* Check if initialization phase has already been performed */
351 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
352 {
353 /* Set the key */
354 CRYP_SetKey(hcryp, hcryp->Init.pKey);
355
356 /* Reset the CHMOD & MODE bits */
357 CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK);
358
359 /* Set the CRYP peripheral in AES ECB mode */
360 __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT);
361
362 /* Enable CRYP */
363 __HAL_CRYP_ENABLE();
364
365 /* Set the phase */
366 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
367 }
368
369 /* Write Plain Data and Get Cypher Data */
370 if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
371 {
372 return HAL_TIMEOUT;
373 }
374
375 /* Change the CRYP state */
376 hcryp->State = HAL_CRYP_STATE_READY;
377
378 /* Process Unlocked */
379 __HAL_UNLOCK(hcryp);
380
381 /* Return function status */
382 return HAL_OK;
383 }
384 else
385 {
386 /* Return function status */
387 return HAL_ERROR;
388 }
389 }
390
391 /**
392 * @brief Initializes the CRYP peripheral in AES CBC encryption mode
393 * then encrypt pPlainData. The cypher data are available in pCypherData
394 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
395 * the configuration information for CRYP module
396 * @param pPlainData: Pointer to the plaintext buffer (aligned on u32)
397 * @param Size: Length of the plaintext buffer, must be a multiple of 16.
398 * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32)
399 * @param Timeout: Specify Timeout value
400 * @retval HAL status
401 */
402 HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
403 {
404 /* Process Locked */
405 __HAL_LOCK(hcryp);
406
407 /* Check that data aligned on u32 */
408 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
409 {
410 /* Process Locked */
411 __HAL_UNLOCK(hcryp);
412
413 /* Return function status */
414 return HAL_ERROR;
415 }
416
417 /* Check if HAL_CRYP_Init has been called */
418 if(hcryp->State != HAL_CRYP_STATE_RESET)
419 {
420 /* Change the CRYP state */
421 hcryp->State = HAL_CRYP_STATE_BUSY;
422
423 /* Check if initialization phase has already been performed */
424 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
425 {
426 /* Set the key */
427 CRYP_SetKey(hcryp, hcryp->Init.pKey);
428
429 /* Reset the CHMOD & MODE bits */
430 CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK);
431
432 /* Set the CRYP peripheral in AES CBC mode */
433 __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT);
434
435 /* Set the Initialization Vector */
436 CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
437
438 /* Enable CRYP */
439 __HAL_CRYP_ENABLE();
440
441 /* Set the phase */
442 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
443 }
444
445 /* Write Plain Data and Get Cypher Data */
446 if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
447 {
448 return HAL_TIMEOUT;
449 }
450
451 /* Change the CRYP state */
452 hcryp->State = HAL_CRYP_STATE_READY;
453
454 /* Process Unlocked */
455 __HAL_UNLOCK(hcryp);
456
457 /* Return function status */
458 return HAL_OK;
459 }
460 else
461 {
462 /* Return function status */
463 return HAL_ERROR;
464 }
465 }
466
467 /**
468 * @brief Initializes the CRYP peripheral in AES CTR encryption mode
469 * then encrypt pPlainData. The cypher data are available in pCypherData
470 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
471 * the configuration information for CRYP module
472 * @param pPlainData: Pointer to the plaintext buffer (aligned on u32)
473 * @param Size: Length of the plaintext buffer, must be a multiple of 16.
474 * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32)
475 * @param Timeout: Specify Timeout value
476 * @retval HAL status
477 */
478 HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
479 {
480 /* Process Locked */
481 __HAL_LOCK(hcryp);
482
483 /* Check that data aligned on u32 */
484 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
485 {
486 /* Process Locked */
487 __HAL_UNLOCK(hcryp);
488
489 /* Return function status */
490 return HAL_ERROR;
491 }
492
493 /* Check if HAL_CRYP_Init has been called */
494 if(hcryp->State != HAL_CRYP_STATE_RESET)
495 {
496 /* Change the CRYP state */
497 hcryp->State = HAL_CRYP_STATE_BUSY;
498
499 /* Check if initialization phase has already been performed */
500 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
501 {
502 /* Set the key */
503 CRYP_SetKey(hcryp, hcryp->Init.pKey);
504
505 /* Reset the CHMOD & MODE bits */
506 CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK);
507
508 /* Set the CRYP peripheral in AES CTR mode */
509 __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT);
510
511 /* Set the Initialization Vector */
512 CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
513
514 /* Enable CRYP */
515 __HAL_CRYP_ENABLE();
516
517 /* Set the phase */
518 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
519 }
520
521 /* Write Plain Data and Get Cypher Data */
522 if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
523 {
524 return HAL_TIMEOUT;
525 }
526
527 /* Change the CRYP state */
528 hcryp->State = HAL_CRYP_STATE_READY;
529
530 /* Process Unlocked */
531 __HAL_UNLOCK(hcryp);
532
533 /* Return function status */
534 return HAL_OK;
535 }
536 else
537 {
538 /* Return function status */
539 return HAL_ERROR;
540 }
541 }
542
543 /**
544 * @brief Initializes the CRYP peripheral in AES ECB decryption mode
545 * then decrypted pCypherData. The cypher data are available in pPlainData
546 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
547 * the configuration information for CRYP module
548 * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32)
549 * @param Size: Length of the plaintext buffer, must be a multiple of 16.
550 * @param pPlainData: Pointer to the plaintext buffer (aligned on u32)
551 * @param Timeout: Specify Timeout value
552 * @retval HAL status
553 */
554 HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
555 {
556 /* Process Locked */
557 __HAL_LOCK(hcryp);
558
559 /* Check that data aligned on u32 */
560 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
561 {
562 /* Process Locked */
563 __HAL_UNLOCK(hcryp);
564
565 /* Return function status */
566 return HAL_ERROR;
567 }
568
569 /* Check if HAL_CRYP_Init has been called */
570 if(hcryp->State != HAL_CRYP_STATE_RESET)
571 {
572 /* Change the CRYP state */
573 hcryp->State = HAL_CRYP_STATE_BUSY;
574
575 /* Check if initialization phase has already been performed */
576 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
577 {
578 /* Set the key */
579 CRYP_SetKey(hcryp, hcryp->Init.pKey);
580
581 /* Reset the CHMOD & MODE bits */
582 CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK);
583
584 /* Set the CRYP peripheral in AES ECB decryption mode (with key derivation) */
585 __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT);
586
587 /* Enable CRYP */
588 __HAL_CRYP_ENABLE();
589
590 /* Set the phase */
591 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
592 }
593
594 /* Write Cypher Data and Get Plain Data */
595 if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
596 {
597 return HAL_TIMEOUT;
598 }
599
600 /* Change the CRYP state */
601 hcryp->State = HAL_CRYP_STATE_READY;
602
603 /* Process Unlocked */
604 __HAL_UNLOCK(hcryp);
605
606 /* Return function status */
607 return HAL_OK;
608 }
609 else
610 {
611 /* Return function status */
612 return HAL_ERROR;
613 }
614 }
615
616 /**
617 * @brief Initializes the CRYP peripheral in AES ECB decryption mode
618 * then decrypted pCypherData. The cypher data are available in pPlainData
619 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
620 * the configuration information for CRYP module
621 * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32)
622 * @param Size: Length of the plaintext buffer, must be a multiple of 16.
623 * @param pPlainData: Pointer to the plaintext buffer (aligned on u32)
624 * @param Timeout: Specify Timeout value
625 * @retval HAL status
626 */
627 HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
628 {
629 /* Process Locked */
630 __HAL_LOCK(hcryp);
631
632 /* Check that data aligned on u32 */
633 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
634 {
635 /* Process Locked */
636 __HAL_UNLOCK(hcryp);
637
638 /* Return function status */
639 return HAL_ERROR;
640 }
641
642 /* Check if HAL_CRYP_Init has been called */
643 if(hcryp->State != HAL_CRYP_STATE_RESET)
644 {
645 /* Change the CRYP state */
646 hcryp->State = HAL_CRYP_STATE_BUSY;
647
648 /* Check if initialization phase has already been performed */
649 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
650 {
651 /* Set the key */
652 CRYP_SetKey(hcryp, hcryp->Init.pKey);
653
654 /* Reset the CHMOD & MODE bits */
655 CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK);
656
657 /* Set the CRYP peripheral in AES CBC decryption mode (with key derivation) */
658 __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT);
659
660 /* Set the Initialization Vector */
661 CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
662
663 /* Enable CRYP */
664 __HAL_CRYP_ENABLE();
665
666 /* Set the phase */
667 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
668 }
669
670 /* Write Cypher Data and Get Plain Data */
671 if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
672 {
673 return HAL_TIMEOUT;
674 }
675
676 /* Change the CRYP state */
677 hcryp->State = HAL_CRYP_STATE_READY;
678
679 /* Process Unlocked */
680 __HAL_UNLOCK(hcryp);
681
682 /* Return function status */
683 return HAL_OK;
684 }
685 else
686 {
687 /* Return function status */
688 return HAL_ERROR;
689 }
690 }
691
692 /**
693 * @brief Initializes the CRYP peripheral in AES CTR decryption mode
694 * then decrypted pCypherData. The cypher data are available in pPlainData
695 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
696 * the configuration information for CRYP module
697 * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32)
698 * @param Size: Length of the plaintext buffer, must be a multiple of 16.
699 * @param pPlainData: Pointer to the plaintext buffer (aligned on u32)
700 * @param Timeout: Specify Timeout value
701 * @retval HAL status
702 */
703 HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
704 {
705 /* Process Locked */
706 __HAL_LOCK(hcryp);
707
708 /* Check that data aligned on u32 */
709 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
710 {
711 /* Process Locked */
712 __HAL_UNLOCK(hcryp);
713
714 /* Return function status */
715 return HAL_ERROR;
716 }
717
718 /* Check if initialization phase has already been performed */
719 if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->Phase == HAL_CRYP_PHASE_READY))
720 {
721 /* Change the CRYP state */
722 hcryp->State = HAL_CRYP_STATE_BUSY;
723
724 /* Set the key */
725 CRYP_SetKey(hcryp, hcryp->Init.pKey);
726
727 /* Reset the CHMOD & MODE bits */
728 CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK);
729
730 /* Set the CRYP peripheral in AES CTR decryption mode */
731 __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR_DECRYPT);
732
733 /* Set the Initialization Vector */
734 CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
735
736 /* Enable CRYP */
737 __HAL_CRYP_ENABLE();
738
739 /* Set the phase */
740 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
741 }
742
743 /* Write Cypher Data and Get Plain Data */
744 if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
745 {
746 return HAL_TIMEOUT;
747 }
748
749 /* Change the CRYP state */
750 hcryp->State = HAL_CRYP_STATE_READY;
751
752 /* Process Unlocked */
753 __HAL_UNLOCK(hcryp);
754
755 /* Return function status */
756 return HAL_OK;
757 }
758
759 /**
760 * @brief Initializes the CRYP peripheral in AES ECB encryption mode using Interrupt.
761 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
762 * the configuration information for CRYP module
763 * @param pPlainData: Pointer to the plaintext buffer (aligned on u32)
764 * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes
765 * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32)
766 * @retval HAL status
767 */
768 HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
769 {
770 uint32_t inputaddr = 0;
771
772 /* Check that data aligned on u32 */
773 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
774 {
775 /* Process Locked */
776 __HAL_UNLOCK(hcryp);
777
778 /* Return function status */
779 return HAL_ERROR;
780 }
781
782 if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
783 {
784 /* Process Locked */
785 __HAL_LOCK(hcryp);
786
787 /* Get the buffer addresses and sizes */
788 hcryp->CrypInCount = Size;
789 hcryp->pCrypInBuffPtr = pPlainData;
790 hcryp->pCrypOutBuffPtr = pCypherData;
791 hcryp->CrypOutCount = Size;
792
793 /* Change the CRYP state */
794 hcryp->State = HAL_CRYP_STATE_BUSY;
795
796 /* Check if initialization phase has already been performed */
797 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
798 {
799 /* Set the key */
800 CRYP_SetKey(hcryp, hcryp->Init.pKey);
801
802 /* Reset the CHMOD & MODE bits */
803 CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK);
804
805 /* Set the CRYP peripheral in AES ECB mode */
806 __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT);
807
808 /* Set the phase */
809 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
810 }
811
812 /* Enable Interrupts */
813 __HAL_CRYP_ENABLE_IT(AES_IT_CC);
814
815 /* Enable CRYP */
816 __HAL_CRYP_ENABLE();
817
818 /* Get the last input data adress */
819 inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
820
821 /* Write the Input block in the Data Input register */
822 AES->DINR = *(uint32_t*)(inputaddr);
823 inputaddr+=4;
824 AES->DINR = *(uint32_t*)(inputaddr);
825 inputaddr+=4;
826 AES->DINR = *(uint32_t*)(inputaddr);
827 inputaddr+=4;
828 AES->DINR = *(uint32_t*)(inputaddr);
829 hcryp->pCrypInBuffPtr += 16;
830 hcryp->CrypInCount -= 16;
831
832 /* Return function status */
833 return HAL_OK;
834 }
835 else
836 {
837 /* Return function status */
838 return HAL_ERROR;
839 }
840 }
841
842 /**
843 * @brief Initializes the CRYP peripheral in AES CBC encryption mode using Interrupt.
844 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
845 * the configuration information for CRYP module
846 * @param pPlainData: Pointer to the plaintext buffer (aligned on u32)
847 * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes
848 * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32)
849 * @retval HAL status
850 */
851 HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
852 {
853 uint32_t inputaddr = 0;
854
855 /* Check that data aligned on u32 */
856 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
857 {
858 /* Process Locked */
859 __HAL_UNLOCK(hcryp);
860
861 /* Return function status */
862 return HAL_ERROR;
863 }
864
865 if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
866 {
867 /* Process Locked */
868 __HAL_LOCK(hcryp);
869
870 /* Get the buffer addresses and sizes */
871 hcryp->CrypInCount = Size;
872 hcryp->pCrypInBuffPtr = pPlainData;
873 hcryp->pCrypOutBuffPtr = pCypherData;
874 hcryp->CrypOutCount = Size;
875
876 /* Change the CRYP state */
877 hcryp->State = HAL_CRYP_STATE_BUSY;
878
879 /* Check if initialization phase has already been performed */
880 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
881 {
882 /* Set the key */
883 CRYP_SetKey(hcryp, hcryp->Init.pKey);
884
885 /* Reset the CHMOD & MODE bits */
886 CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK);
887
888 /* Set the CRYP peripheral in AES CBC mode */
889 __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT);
890
891 /* Set the Initialization Vector */
892 CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
893
894 /* Set the phase */
895 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
896 }
897
898 /* Enable Interrupts */
899 __HAL_CRYP_ENABLE_IT(AES_IT_CC);
900
901 /* Enable CRYP */
902 __HAL_CRYP_ENABLE();
903
904 /* Get the last input data adress */
905 inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
906
907 /* Write the Input block in the Data Input register */
908 AES->DINR = *(uint32_t*)(inputaddr);
909 inputaddr+=4;
910 AES->DINR = *(uint32_t*)(inputaddr);
911 inputaddr+=4;
912 AES->DINR = *(uint32_t*)(inputaddr);
913 inputaddr+=4;
914 AES->DINR = *(uint32_t*)(inputaddr);
915 hcryp->pCrypInBuffPtr += 16;
916 hcryp->CrypInCount -= 16;
917
918 /* Return function status */
919 return HAL_OK;
920 }
921 else
922 {
923 /* Return function status */
924 return HAL_ERROR;
925 }
926 }
927
928 /**
929 * @brief Initializes the CRYP peripheral in AES CTR encryption mode using Interrupt.
930 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
931 * the configuration information for CRYP module
932 * @param pPlainData: Pointer to the plaintext buffer (aligned on u32)
933 * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes
934 * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32)
935 * @retval HAL status
936 */
937 HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
938 {
939 uint32_t inputaddr = 0;
940
941 /* Check that data aligned on u32 */
942 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
943 {
944 /* Process Locked */
945 __HAL_UNLOCK(hcryp);
946
947 /* Return function status */
948 return HAL_ERROR;
949 }
950
951 if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
952 {
953 /* Process Locked */
954 __HAL_LOCK(hcryp);
955
956 /* Get the buffer addresses and sizes */
957 hcryp->CrypInCount = Size;
958 hcryp->pCrypInBuffPtr = pPlainData;
959 hcryp->pCrypOutBuffPtr = pCypherData;
960 hcryp->CrypOutCount = Size;
961
962 /* Change the CRYP state */
963 hcryp->State = HAL_CRYP_STATE_BUSY;
964
965 /* Check if initialization phase has already been performed */
966 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
967 {
968 /* Set the key */
969 CRYP_SetKey(hcryp, hcryp->Init.pKey);
970
971 /* Reset the CHMOD & MODE bits */
972 CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK);
973
974 /* Set the CRYP peripheral in AES CTR mode */
975 __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT);
976
977 /* Set the Initialization Vector */
978 CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
979
980 /* Set the phase */
981 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
982 }
983
984 /* Enable Interrupts */
985 __HAL_CRYP_ENABLE_IT(AES_IT_CC);
986
987 /* Enable CRYP */
988 __HAL_CRYP_ENABLE();
989
990 /* Get the last input data adress */
991 inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
992
993 /* Write the Input block in the Data Input register */
994 AES->DINR = *(uint32_t*)(inputaddr);
995 inputaddr+=4;
996 AES->DINR = *(uint32_t*)(inputaddr);
997 inputaddr+=4;
998 AES->DINR = *(uint32_t*)(inputaddr);
999 inputaddr+=4;
1000 AES->DINR = *(uint32_t*)(inputaddr);
1001 hcryp->pCrypInBuffPtr += 16;
1002 hcryp->CrypInCount -= 16;
1003
1004 /* Return function status */
1005 return HAL_OK;
1006 }
1007 else
1008 {
1009 /* Return function status */
1010 return HAL_ERROR;
1011 }
1012 }
1013
1014 /**
1015 * @brief Initializes the CRYP peripheral in AES ECB decryption mode using Interrupt.
1016 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1017 * the configuration information for CRYP module
1018 * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32)
1019 * @param Size: Length of the plaintext buffer, must be a multiple of 16.
1020 * @param pPlainData: Pointer to the plaintext buffer (aligned on u32)
1021 * @retval HAL status
1022 */
1023 HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
1024 {
1025 uint32_t inputaddr = 0;
1026
1027 /* Check that data aligned on u32 */
1028 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
1029 {
1030 /* Process Locked */
1031 __HAL_UNLOCK(hcryp);
1032
1033 /* Return function status */
1034 return HAL_ERROR;
1035 }
1036
1037 if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
1038 {
1039 /* Process Locked */
1040 __HAL_LOCK(hcryp);
1041
1042 /* Get the buffer addresses and sizes */
1043 hcryp->CrypInCount = Size;
1044 hcryp->pCrypInBuffPtr = pCypherData;
1045 hcryp->pCrypOutBuffPtr = pPlainData;
1046 hcryp->CrypOutCount = Size;
1047
1048 /* Change the CRYP state */
1049 hcryp->State = HAL_CRYP_STATE_BUSY;
1050
1051 /* Check if initialization phase has already been performed */
1052 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
1053 {
1054 /* Set the key */
1055 CRYP_SetKey(hcryp, hcryp->Init.pKey);
1056
1057 /* Reset the CHMOD & MODE bits */
1058 CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK);
1059
1060 /* Set the CRYP peripheral in AES ECB decryption mode (with key derivation) */
1061 __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT);
1062
1063 /* Set the phase */
1064 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
1065 }
1066
1067 /* Enable Interrupts */
1068 __HAL_CRYP_ENABLE_IT(AES_IT_CC);
1069
1070 /* Enable CRYP */
1071 __HAL_CRYP_ENABLE();
1072
1073 /* Get the last input data adress */
1074 inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
1075
1076 /* Write the Input block in the Data Input register */
1077 AES->DINR = *(uint32_t*)(inputaddr);
1078 inputaddr+=4;
1079 AES->DINR = *(uint32_t*)(inputaddr);
1080 inputaddr+=4;
1081 AES->DINR = *(uint32_t*)(inputaddr);
1082 inputaddr+=4;
1083 AES->DINR = *(uint32_t*)(inputaddr);
1084 hcryp->pCrypInBuffPtr += 16;
1085 hcryp->CrypInCount -= 16;
1086
1087 /* Return function status */
1088 return HAL_OK;
1089 }
1090 else
1091 {
1092 /* Return function status */
1093 return HAL_ERROR;
1094 }
1095 }
1096
1097 /**
1098 * @brief Initializes the CRYP peripheral in AES CBC decryption mode using IT.
1099 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1100 * the configuration information for CRYP module
1101 * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32)
1102 * @param Size: Length of the plaintext buffer, must be a multiple of 16
1103 * @param pPlainData: Pointer to the plaintext buffer (aligned on u32)
1104 * @retval HAL status
1105 */
1106 HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
1107 {
1108 uint32_t inputaddr = 0;
1109
1110 /* Check that data aligned on u32 */
1111 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
1112 {
1113 /* Process Locked */
1114 __HAL_UNLOCK(hcryp);
1115
1116 /* Return function status */
1117 return HAL_ERROR;
1118 }
1119
1120 if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
1121 {
1122 /* Process Locked */
1123 __HAL_LOCK(hcryp);
1124
1125 /* Get the buffer addresses and sizes */
1126 hcryp->CrypInCount = Size;
1127 hcryp->pCrypInBuffPtr = pCypherData;
1128 hcryp->pCrypOutBuffPtr = pPlainData;
1129 hcryp->CrypOutCount = Size;
1130
1131 /* Change the CRYP state */
1132 hcryp->State = HAL_CRYP_STATE_BUSY;
1133
1134 /* Check if initialization phase has already been performed */
1135 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
1136 {
1137 /* Set the key */
1138 CRYP_SetKey(hcryp, hcryp->Init.pKey);
1139
1140 /* Reset the CHMOD & MODE bits */
1141 CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK);
1142
1143 /* Set the CRYP peripheral in AES CBC decryption mode (with key derivation) */
1144 __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT);
1145
1146 /* Set the Initialization Vector */
1147 CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
1148
1149 /* Set the phase */
1150 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
1151 }
1152
1153 /* Enable Interrupts */
1154 __HAL_CRYP_ENABLE_IT(AES_IT_CC);
1155
1156 /* Enable CRYP */
1157 __HAL_CRYP_ENABLE();
1158
1159 /* Get the last input data adress */
1160 inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
1161
1162 /* Write the Input block in the Data Input register */
1163 AES->DINR = *(uint32_t*)(inputaddr);
1164 inputaddr+=4;
1165 AES->DINR = *(uint32_t*)(inputaddr);
1166 inputaddr+=4;
1167 AES->DINR = *(uint32_t*)(inputaddr);
1168 inputaddr+=4;
1169 AES->DINR = *(uint32_t*)(inputaddr);
1170 hcryp->pCrypInBuffPtr += 16;
1171 hcryp->CrypInCount -= 16;
1172
1173 /* Return function status */
1174 return HAL_OK;
1175 }
1176 else
1177 {
1178 /* Return function status */
1179 return HAL_ERROR;
1180 }
1181 }
1182
1183 /**
1184 * @brief Initializes the CRYP peripheral in AES CTR decryption mode using Interrupt.
1185 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1186 * the configuration information for CRYP module
1187 * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32)
1188 * @param Size: Length of the plaintext buffer, must be a multiple of 16
1189 * @param pPlainData: Pointer to the plaintext buffer (aligned on u32)
1190 * @retval HAL status
1191 */
1192 HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
1193 {
1194 uint32_t inputaddr = 0;
1195
1196 /* Check that data aligned on u32 */
1197 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
1198 {
1199 /* Process Locked */
1200 __HAL_UNLOCK(hcryp);
1201
1202 /* Return function status */
1203 return HAL_ERROR;
1204 }
1205
1206 if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
1207 {
1208 /* Process Locked */
1209 __HAL_LOCK(hcryp);
1210
1211 /* Get the buffer addresses and sizes */
1212 hcryp->CrypInCount = Size;
1213 hcryp->pCrypInBuffPtr = pCypherData;
1214 hcryp->pCrypOutBuffPtr = pPlainData;
1215 hcryp->CrypOutCount = Size;
1216
1217 /* Change the CRYP state */
1218 hcryp->State = HAL_CRYP_STATE_BUSY;
1219
1220 /* Check if initialization phase has already been performed */
1221 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
1222 {
1223 /* Set the key */
1224 CRYP_SetKey(hcryp, hcryp->Init.pKey);
1225
1226 /* Reset the CHMOD & MODE bits */
1227 CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK);
1228
1229 /* Set the CRYP peripheral in AES CTR decryption mode */
1230 __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR_DECRYPT);
1231
1232 /* Set the Initialization Vector */
1233 CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
1234
1235 /* Set the phase */
1236 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
1237 }
1238
1239 /* Enable Interrupts */
1240 __HAL_CRYP_ENABLE_IT(AES_IT_CC);
1241
1242 /* Enable CRYP */
1243 __HAL_CRYP_ENABLE();
1244
1245 /* Get the last input data adress */
1246 inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
1247
1248 /* Write the Input block in the Data Input register */
1249 AES->DINR = *(uint32_t*)(inputaddr);
1250 inputaddr+=4;
1251 AES->DINR = *(uint32_t*)(inputaddr);
1252 inputaddr+=4;
1253 AES->DINR = *(uint32_t*)(inputaddr);
1254 inputaddr+=4;
1255 AES->DINR = *(uint32_t*)(inputaddr);
1256 hcryp->pCrypInBuffPtr += 16;
1257 hcryp->CrypInCount -= 16;
1258
1259 /* Return function status */
1260 return HAL_OK;
1261 }
1262 else
1263 {
1264 /* Return function status */
1265 return HAL_ERROR;
1266 }
1267 }
1268
1269 /**
1270 * @brief Initializes the CRYP peripheral in AES ECB encryption mode using DMA.
1271 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1272 * the configuration information for CRYP module
1273 * @param pPlainData: Pointer to the plaintext buffer (aligned on u32)
1274 * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes
1275 * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32)
1276 * @retval HAL status
1277 */
1278 HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
1279 {
1280 uint32_t inputaddr = 0, outputaddr = 0;
1281
1282 /* Check that data aligned on u32 */
1283 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
1284 {
1285 /* Process Locked */
1286 __HAL_UNLOCK(hcryp);
1287
1288 /* Return function status */
1289 return HAL_ERROR;
1290 }
1291
1292 /* Check if HAL_CRYP_Init has been called */
1293 if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
1294 {
1295 /* Process Locked */
1296 __HAL_LOCK(hcryp);
1297
1298 inputaddr = (uint32_t)pPlainData;
1299 outputaddr = (uint32_t)pCypherData;
1300
1301 /* Change the CRYP state */
1302 hcryp->State = HAL_CRYP_STATE_BUSY;
1303
1304 /* Check if initialization phase has already been performed */
1305 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
1306 {
1307 /* Set the key */
1308 CRYP_SetKey(hcryp, hcryp->Init.pKey);
1309
1310 /* Set the CRYP peripheral in AES ECB mode */
1311 __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT);
1312
1313 /* Set the phase */
1314 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
1315 }
1316 /* Set the input and output addresses and start DMA transfer */
1317 CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
1318
1319 /* Process Unlocked */
1320 __HAL_UNLOCK(hcryp);
1321
1322 /* Return function status */
1323 return HAL_OK;
1324 }
1325 else
1326 {
1327 return HAL_ERROR;
1328 }
1329 }
1330
1331 /**
1332 * @brief Initializes the CRYP peripheral in AES CBC encryption mode using DMA.
1333 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1334 * the configuration information for CRYP module
1335 * @param pPlainData: Pointer to the plaintext buffer (aligned on u32)
1336 * @param Size: Length of the plaintext buffer, must be a multiple of 16.
1337 * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32)
1338 * @retval HAL status
1339 */
1340 HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
1341 {
1342 uint32_t inputaddr = 0, outputaddr = 0;
1343
1344 /* Check that data aligned on u32 */
1345 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
1346 {
1347 /* Process Locked */
1348 __HAL_UNLOCK(hcryp);
1349
1350 /* Return function status */
1351 return HAL_ERROR;
1352 }
1353
1354 /* Check if HAL_CRYP_Init has been called */
1355 if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
1356 {
1357 /* Process Locked */
1358 __HAL_LOCK(hcryp);
1359
1360 inputaddr = (uint32_t)pPlainData;
1361 outputaddr = (uint32_t)pCypherData;
1362
1363 /* Change the CRYP state */
1364 hcryp->State = HAL_CRYP_STATE_BUSY;
1365
1366 /* Check if initialization phase has already been performed */
1367 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
1368 {
1369 /* Set the key */
1370 CRYP_SetKey(hcryp, hcryp->Init.pKey);
1371
1372 /* Set the CRYP peripheral in AES CBC mode */
1373 __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT);
1374
1375 /* Set the Initialization Vector */
1376 CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
1377
1378 /* Set the phase */
1379 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
1380 }
1381 /* Set the input and output addresses and start DMA transfer */
1382 CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
1383
1384 /* Process Unlocked */
1385 __HAL_UNLOCK(hcryp);
1386
1387 /* Return function status */
1388 return HAL_OK;
1389 }
1390 else
1391 {
1392 return HAL_ERROR;
1393 }
1394 }
1395
1396 /**
1397 * @brief Initializes the CRYP peripheral in AES CTR encryption mode using DMA.
1398 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1399 * the configuration information for CRYP module
1400 * @param pPlainData: Pointer to the plaintext buffer (aligned on u32)
1401 * @param Size: Length of the plaintext buffer, must be a multiple of 16.
1402 * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32)
1403 * @retval HAL status
1404 */
1405 HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
1406 {
1407 uint32_t inputaddr = 0, outputaddr = 0;
1408
1409 /* Check that data aligned on u32 */
1410 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
1411 {
1412 /* Process Locked */
1413 __HAL_UNLOCK(hcryp);
1414
1415 /* Return function status */
1416 return HAL_ERROR;
1417 }
1418
1419 /* Check if HAL_CRYP_Init has been called */
1420 if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
1421 {
1422 /* Process Locked */
1423 __HAL_LOCK(hcryp);
1424
1425 inputaddr = (uint32_t)pPlainData;
1426 outputaddr = (uint32_t)pCypherData;
1427
1428 /* Change the CRYP state */
1429 hcryp->State = HAL_CRYP_STATE_BUSY;
1430
1431 /* Check if initialization phase has already been performed */
1432 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
1433 {
1434 /* Set the key */
1435 CRYP_SetKey(hcryp, hcryp->Init.pKey);
1436
1437 /* Set the CRYP peripheral in AES CTR mode */
1438 __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT);
1439
1440 /* Set the Initialization Vector */
1441 CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
1442
1443 /* Set the phase */
1444 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
1445 }
1446
1447 /* Set the input and output addresses and start DMA transfer */
1448 CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
1449
1450 /* Process Unlocked */
1451 __HAL_UNLOCK(hcryp);
1452
1453 /* Return function status */
1454 return HAL_OK;
1455 }
1456 else
1457 {
1458 return HAL_ERROR;
1459 }
1460 }
1461
1462 /**
1463 * @brief Initializes the CRYP peripheral in AES ECB decryption mode using DMA.
1464 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1465 * the configuration information for CRYP module
1466 * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32)
1467 * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes
1468 * @param pPlainData: Pointer to the plaintext buffer (aligned on u32)
1469 * @retval HAL status
1470 */
1471 HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
1472 {
1473 uint32_t inputaddr = 0, outputaddr = 0;
1474
1475 /* Check that data aligned on u32 */
1476 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
1477 {
1478 /* Process Locked */
1479 __HAL_UNLOCK(hcryp);
1480
1481 /* Return function status */
1482 return HAL_ERROR;
1483 }
1484
1485 /* Check if HAL_CRYP_Init has been called */
1486 if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
1487 {
1488 /* Process Locked */
1489 __HAL_LOCK(hcryp);
1490
1491 inputaddr = (uint32_t)pCypherData;
1492 outputaddr = (uint32_t)pPlainData;
1493
1494 /* Change the CRYP state */
1495 hcryp->State = HAL_CRYP_STATE_BUSY;
1496
1497 /* Check if initialization phase has already been performed */
1498 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
1499 {
1500 /* Set the key */
1501 CRYP_SetKey(hcryp, hcryp->Init.pKey);
1502
1503 /* Reset the CHMOD & MODE bits */
1504 CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK);
1505
1506 /* Set the CRYP peripheral in AES ECB decryption mode (with key derivation) */
1507 __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT);
1508
1509 /* Set the phase */
1510 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
1511 }
1512
1513 /* Set the input and output addresses and start DMA transfer */
1514 CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
1515
1516 /* Process Unlocked */
1517 __HAL_UNLOCK(hcryp);
1518
1519 /* Return function status */
1520 return HAL_OK;
1521 }
1522 else
1523 {
1524 return HAL_ERROR;
1525 }
1526 }
1527
1528 /**
1529 * @brief Initializes the CRYP peripheral in AES CBC encryption mode using DMA.
1530 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1531 * the configuration information for CRYP module
1532 * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32)
1533 * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes
1534 * @param pPlainData: Pointer to the plaintext buffer (aligned on u32)
1535 * @retval HAL status
1536 */
1537 HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
1538 {
1539 uint32_t inputaddr = 0, outputaddr = 0;
1540
1541 /* Check that data aligned on u32 */
1542 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
1543 {
1544 /* Process Locked */
1545 __HAL_UNLOCK(hcryp);
1546
1547 /* Return function status */
1548 return HAL_ERROR;
1549 }
1550
1551 /* Check if HAL_CRYP_Init has been called */
1552 if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
1553 {
1554 /* Process Locked */
1555 __HAL_LOCK(hcryp);
1556
1557 inputaddr = (uint32_t)pCypherData;
1558 outputaddr = (uint32_t)pPlainData;
1559
1560 /* Change the CRYP state */
1561 hcryp->State = HAL_CRYP_STATE_BUSY;
1562
1563 /* Check if initialization phase has already been performed */
1564 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
1565 {
1566 /* Set the key */
1567 CRYP_SetKey(hcryp, hcryp->Init.pKey);
1568
1569 /* Reset the CHMOD & MODE bits */
1570 CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK);
1571
1572 /* Set the CRYP peripheral in AES CBC decryption mode (with key derivation) */
1573 __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT);
1574
1575 /* Set the Initialization Vector */
1576 CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
1577
1578 /* Set the phase */
1579 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
1580 }
1581
1582 /* Set the input and output addresses and start DMA transfer */
1583 CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
1584
1585 /* Process Unlocked */
1586 __HAL_UNLOCK(hcryp);
1587
1588 /* Return function status */
1589 return HAL_OK;
1590 }
1591 else
1592 {
1593 return HAL_ERROR;
1594 }
1595 }
1596
1597 /**
1598 * @brief Initializes the CRYP peripheral in AES CTR decryption mode using DMA.
1599 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1600 * the configuration information for CRYP module
1601 * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32)
1602 * @param Size: Length of the plaintext buffer, must be a multiple of 16
1603 * @param pPlainData: Pointer to the plaintext buffer (aligned on u32)
1604 * @retval HAL status
1605 */
1606 HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
1607 {
1608 uint32_t inputaddr = 0, outputaddr = 0;
1609
1610 /* Check that data aligned on u32 */
1611 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
1612 {
1613 /* Process Locked */
1614 __HAL_UNLOCK(hcryp);
1615
1616 /* Return function status */
1617 return HAL_ERROR;
1618 }
1619
1620 /* Check if HAL_CRYP_Init has been called */
1621 if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
1622 {
1623 /* Process Locked */
1624 __HAL_LOCK(hcryp);
1625
1626 inputaddr = (uint32_t)pCypherData;
1627 outputaddr = (uint32_t)pPlainData;
1628
1629 /* Change the CRYP state */
1630 hcryp->State = HAL_CRYP_STATE_BUSY;
1631
1632 /* Check if initialization phase has already been performed */
1633 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
1634 {
1635 /* Set the key */
1636 CRYP_SetKey(hcryp, hcryp->Init.pKey);
1637
1638 /* Set the CRYP peripheral in AES CTR mode */
1639 __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR_DECRYPT);
1640
1641 /* Set the Initialization Vector */
1642 CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
1643
1644 /* Set the phase */
1645 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
1646 }
1647
1648 /* Set the input and output addresses and start DMA transfer */
1649 CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
1650
1651 /* Process Unlocked */
1652 __HAL_UNLOCK(hcryp);
1653
1654 /* Return function status */
1655 return HAL_OK;
1656 }
1657 else
1658 {
1659 return HAL_ERROR;
1660 }
1661 }
1662
1663 /**
1664 * @}
1665 */
1666
1667 /** @defgroup CRYP_Exported_Functions_Group3 DMA callback functions
1668 * @brief DMA callback functions.
1669 *
1670 @verbatim
1671 ==============================================================================
1672 ##### DMA callback functions #####
1673 ==============================================================================
1674 [..] This section provides DMA callback functions:
1675 (+) DMA Input data transfer complete
1676 (+) DMA Output data transfer complete
1677 (+) DMA error
1678
1679 @endverbatim
1680 * @{
1681 */
1682
1683 /**
1684 * @brief CRYP error callback.
1685 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1686 * the configuration information for CRYP module
1687 * @retval None
1688 */
1689 __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
1690 {
1691 /* NOTE : This function should not be modified; when the callback is needed,
1692 the HAL_CRYP_ErrorCallback can be implemented in the user file
1693 */
1694 }
1695
1696 /**
1697 * @brief Input transfer completed callback.
1698 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1699 * the configuration information for CRYP module
1700 * @retval None
1701 */
1702 __weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
1703 {
1704 /* NOTE : This function should not be modified; when the callback is needed,
1705 the HAL_CRYP_InCpltCallback can be implemented in the user file
1706 */
1707 }
1708
1709 /**
1710 * @brief Output transfer completed callback.
1711 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1712 * the configuration information for CRYP module
1713 * @retval None
1714 */
1715 __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
1716 {
1717 /* NOTE : This function should not be modified; when the callback is needed,
1718 the HAL_CRYP_OutCpltCallback can be implemented in the user file
1719 */
1720 }
1721
1722 /**
1723 * @}
1724 */
1725
1726 /** @defgroup CRYP_Exported_Functions_Group4 CRYP IRQ handler
1727 * @brief CRYP IRQ handler.
1728 *
1729 @verbatim
1730 ==============================================================================
1731 ##### CRYP IRQ handler management #####
1732 ==============================================================================
1733 [..] This section provides CRYP IRQ handler function.
1734
1735 @endverbatim
1736 * @{
1737 */
1738
1739 /**
1740 * @brief This function handles CRYP interrupt request.
1741 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1742 * the configuration information for CRYP module
1743 * @retval None
1744 */
1745 void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
1746 {
1747 /* Check if error occurred*/
1748 if (__HAL_CRYP_GET_IT_SOURCE(hcryp, AES_IT_ERR) != RESET)
1749 {
1750 if (__HAL_CRYP_GET_FLAG(AES_FLAG_RDERR) != RESET)
1751 {
1752 __HAL_CRYP_CLEAR_FLAG(hcryp, AES_CLEARFLAG_RDERR);
1753 }
1754
1755 if (__HAL_CRYP_GET_FLAG(AES_FLAG_WRERR) != RESET)
1756 {
1757 __HAL_CRYP_CLEAR_FLAG(hcryp, AES_CLEARFLAG_WRERR);
1758 }
1759
1760 if (__HAL_CRYP_GET_FLAG(AES_FLAG_CCF) != RESET)
1761 {
1762 __HAL_CRYP_CLEAR_FLAG(hcryp, AES_CLEARFLAG_CCF);
1763 }
1764
1765 hcryp->State= HAL_CRYP_STATE_ERROR;
1766 /* Disable Computation Complete Interrupt */
1767 __HAL_CRYP_DISABLE_IT(AES_IT_CC);
1768 __HAL_CRYP_DISABLE_IT(AES_IT_ERR);
1769
1770 HAL_CRYP_ErrorCallback(hcryp);
1771
1772 /* Process Unlocked */
1773 __HAL_UNLOCK(hcryp);
1774
1775 return;
1776 }
1777
1778 /* Check if computation complete interrupt was enabled*/
1779 if (__HAL_CRYP_GET_IT_SOURCE(hcryp, AES_IT_CC) != RESET)
1780 {
1781 /* Clear CCF Flag */
1782 __HAL_CRYP_CLEAR_FLAG(hcryp, AES_CLEARFLAG_CCF);
1783
1784 CRYP_EncryptDecrypt_IT(hcryp);
1785 }
1786 }
1787
1788 /**
1789 * @}
1790 */
1791
1792 /** @defgroup CRYP_Exported_Functions_Group5 Peripheral State functions
1793 * @brief Peripheral State functions.
1794 *
1795 @verbatim
1796 ==============================================================================
1797 ##### Peripheral State functions #####
1798 ==============================================================================
1799 [..]
1800 This subsection permits to get in run-time the status of the peripheral.
1801
1802 @endverbatim
1803 * @{
1804 */
1805
1806 /**
1807 * @brief Returns the CRYP state.
1808 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1809 * the configuration information for CRYP module
1810 * @retval HAL state
1811 */
1812 HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)
1813 {
1814 return hcryp->State;
1815 }
1816
1817 /**
1818 * @}
1819 */
1820
1821 /**
1822 * @}
1823 */
1824
1825 /** @addtogroup CRYP_Private_Functions
1826 * @{
1827 */
1828
1829 /**
1830 * @brief IT function called under interruption context to continue encryption or decryption
1831 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1832 * the configuration information for CRYP module
1833 * @retval HAL status
1834 */
1835 static HAL_StatusTypeDef CRYP_EncryptDecrypt_IT(CRYP_HandleTypeDef *hcryp)
1836 {
1837 uint32_t inputaddr = 0, outputaddr = 0;
1838
1839 /* Get the last Output data adress */
1840 outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
1841
1842 /* Read the Output block from the Output Register */
1843 *(uint32_t*)(outputaddr) = AES->DOUTR;
1844 outputaddr+=4;
1845 *(uint32_t*)(outputaddr) = AES->DOUTR;
1846 outputaddr+=4;
1847 *(uint32_t*)(outputaddr) = AES->DOUTR;
1848 outputaddr+=4;
1849 *(uint32_t*)(outputaddr) = AES->DOUTR;
1850
1851 hcryp->pCrypOutBuffPtr += 16;
1852 hcryp->CrypOutCount -= 16;
1853
1854 /* Check if all input text is encrypted or decrypted */
1855 if(hcryp->CrypOutCount == 0)
1856 {
1857 /* Disable Computation Complete Interrupt */
1858 __HAL_CRYP_DISABLE_IT(AES_IT_CC);
1859 __HAL_CRYP_DISABLE_IT(AES_IT_ERR);
1860
1861 /* Process Unlocked */
1862 __HAL_UNLOCK(hcryp);
1863
1864 /* Change the CRYP state */
1865 hcryp->State = HAL_CRYP_STATE_READY;
1866
1867 /* Call computation complete callback */
1868 HAL_CRYPEx_ComputationCpltCallback(hcryp);
1869 }
1870 else /* Process the rest of input text */
1871 {
1872 /* Get the last Intput data adress */
1873 inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
1874
1875 /* Write the Input block in the Data Input register */
1876 AES->DINR = *(uint32_t*)(inputaddr);
1877 inputaddr+=4;
1878 AES->DINR = *(uint32_t*)(inputaddr);
1879 inputaddr+=4;
1880 AES->DINR = *(uint32_t*)(inputaddr);
1881 inputaddr+=4;
1882 AES->DINR = *(uint32_t*)(inputaddr);
1883 hcryp->pCrypInBuffPtr += 16;
1884 hcryp->CrypInCount -= 16;
1885 }
1886 return HAL_OK;
1887 }
1888 /**
1889 * @brief DMA CRYP Input Data process complete callback.
1890 * @param hdma: DMA handle
1891 * @retval None
1892 */
1893 static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
1894 {
1895 CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
1896
1897 /* Disable the DMA transfer for input request */
1898 CLEAR_BIT(AES->CR, AES_CR_DMAINEN);
1899
1900 /* Call input data transfer complete callback */
1901 HAL_CRYP_InCpltCallback(hcryp);
1902 }
1903
1904 /**
1905 * @brief DMA CRYP Output Data process complete callback.
1906 * @param hdma: DMA handle
1907 * @retval None
1908 */
1909 static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
1910 {
1911 CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
1912
1913 /* Disable the DMA transfer for output request by resetting the DMAOUTEN bit
1914 in the DMACR register */
1915 CLEAR_BIT(AES->CR, AES_CR_DMAOUTEN);
1916
1917 /* Clear CCF Flag */
1918 __HAL_CRYP_CLEAR_FLAG(hcryp, AES_CLEARFLAG_CCF);
1919
1920 /* Disable CRYP */
1921 __HAL_CRYP_DISABLE();
1922
1923 /* Change the CRYP state to ready */
1924 hcryp->State = HAL_CRYP_STATE_READY;
1925
1926 /* Call output data transfer complete callback */
1927 HAL_CRYP_OutCpltCallback(hcryp);
1928 }
1929
1930 /**
1931 * @brief DMA CRYP communication error callback.
1932 * @param hdma: DMA handle
1933 * @retval None
1934 */
1935 static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
1936 {
1937 CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
1938 hcryp->State= HAL_CRYP_STATE_ERROR;
1939 HAL_CRYP_ErrorCallback(hcryp);
1940 }
1941
1942 /**
1943 * @brief Writes the Key in Key registers.
1944 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1945 * the configuration information for CRYP module
1946 * @param Key: Pointer to Key buffer
1947 * @note Key must be written as little endian.
1948 * If Key pointer points at address n,
1949 * n[15:0] contains key[96:127],
1950 * (n+4)[15:0] contains key[64:95],
1951 * (n+8)[15:0] contains key[32:63] and
1952 * (n+12)[15:0] contains key[0:31]
1953 * @retval None
1954 */
1955 static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key)
1956 {
1957 uint32_t keyaddr = (uint32_t)Key;
1958
1959 AES->KEYR3 = __REV(*(uint32_t*)(keyaddr));
1960 keyaddr+=4;
1961 AES->KEYR2 = __REV(*(uint32_t*)(keyaddr));
1962 keyaddr+=4;
1963 AES->KEYR1 = __REV(*(uint32_t*)(keyaddr));
1964 keyaddr+=4;
1965 AES->KEYR0 = __REV(*(uint32_t*)(keyaddr));
1966 }
1967
1968 /**
1969 * @brief Writes the InitVector/InitCounter in IV registers.
1970 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1971 * the configuration information for CRYP module
1972 * @param InitVector: Pointer to InitVector/InitCounter buffer
1973 * @note Init Vector must be written as little endian.
1974 * If Init Vector pointer points at address n,
1975 * n[15:0] contains Vector[96:127],
1976 * (n+4)[15:0] contains Vector[64:95],
1977 * (n+8)[15:0] contains Vector[32:63] and
1978 * (n+12)[15:0] contains Vector[0:31]
1979 * @retval None
1980 */
1981 static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector)
1982 {
1983 uint32_t ivaddr = (uint32_t)InitVector;
1984
1985 AES->IVR3 = __REV(*(uint32_t*)(ivaddr));
1986 ivaddr+=4;
1987 AES->IVR2 = __REV(*(uint32_t*)(ivaddr));
1988 ivaddr+=4;
1989 AES->IVR1 = __REV(*(uint32_t*)(ivaddr));
1990 ivaddr+=4;
1991 AES->IVR0 = __REV(*(uint32_t*)(ivaddr));
1992 }
1993
1994 /**
1995 * @brief Process Data: Writes Input data in polling mode and reads the output data
1996 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1997 * the configuration information for CRYP module
1998 * @param Input: Pointer to the Input buffer
1999 * @param Ilength: Length of the Input buffer, must be a multiple of 16.
2000 * @param Output: Pointer to the returned buffer
2001 * @param Timeout: Specify Timeout value
2002 * @retval None
2003 */
2004 static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout)
2005 {
2006 uint32_t tickstart = 0;
2007
2008 uint32_t index = 0;
2009 uint32_t inputaddr = (uint32_t)Input;
2010 uint32_t outputaddr = (uint32_t)Output;
2011
2012 for(index=0; (index < Ilength); index += 16)
2013 {
2014 /* Write the Input block in the Data Input register */
2015 AES->DINR = *(uint32_t*)(inputaddr);
2016 inputaddr+=4;
2017 AES->DINR = *(uint32_t*)(inputaddr);
2018 inputaddr+=4;
2019 AES->DINR = *(uint32_t*)(inputaddr);
2020 inputaddr+=4;
2021 AES->DINR = *(uint32_t*)(inputaddr);
2022 inputaddr+=4;
2023
2024 /* Get timeout */
2025 tickstart = HAL_GetTick();
2026
2027 while(HAL_IS_BIT_CLR(AES->SR, AES_SR_CCF))
2028 {
2029 /* Check for the Timeout */
2030 if(Timeout != HAL_MAX_DELAY)
2031 {
2032 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
2033 {
2034 /* Change state */
2035 hcryp->State = HAL_CRYP_STATE_TIMEOUT;
2036
2037 /* Process Unlocked */
2038 __HAL_UNLOCK(hcryp);
2039
2040 return HAL_TIMEOUT;
2041 }
2042 }
2043 }
2044 /* Clear CCF Flag */
2045 __HAL_CRYP_CLEAR_FLAG(hcryp, AES_CLEARFLAG_CCF);
2046
2047 /* Read the Output block from the Data Output Register */
2048 *(uint32_t*)(outputaddr) = AES->DOUTR;
2049 outputaddr+=4;
2050 *(uint32_t*)(outputaddr) = AES->DOUTR;
2051 outputaddr+=4;
2052 *(uint32_t*)(outputaddr) = AES->DOUTR;
2053 outputaddr+=4;
2054 *(uint32_t*)(outputaddr) = AES->DOUTR;
2055 outputaddr+=4;
2056 }
2057 /* Return function status */
2058 return HAL_OK;
2059 }
2060
2061 /**
2062 * @brief Set the DMA configuration and start the DMA transfer
2063 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2064 * the configuration information for CRYP module
2065 * @param inputaddr: address of the Input buffer
2066 * @param Size: Size of the Input buffer, must be a multiple of 16.
2067 * @param outputaddr: address of the Output buffer
2068 * @retval None
2069 */
2070 static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
2071 {
2072 /* Set the CRYP DMA transfer complete callback */
2073 hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
2074 /* Set the DMA error callback */
2075 hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
2076
2077 /* Set the CRYP DMA transfer complete callback */
2078 hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;
2079 /* Set the DMA error callback */
2080 hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;
2081
2082 /* Enable the DMA In DMA Stream */
2083 HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&AES->DINR, Size/4);
2084
2085 /* Enable the DMA Out DMA Stream */
2086 HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&AES->DOUTR, outputaddr, Size/4);
2087
2088 /* Enable In and Out DMA requests */
2089 SET_BIT(AES->CR, (AES_CR_DMAINEN | AES_CR_DMAOUTEN));
2090
2091 /* Enable CRYP */
2092 __HAL_CRYP_ENABLE();
2093 }
2094
2095 /**
2096 * @}
2097 */
2098
2099 #endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE*/
2100
2101 /**
2102 * @}
2103 */
2104
2105 /**
2106 * @}
2107 */
2108
2109 #endif /* HAL_CRYP_MODULE_ENABLED */
2110
2111 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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