tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_i2s.c

   1 /**
   2   ******************************************************************************
   3   * @file    stm32l1xx_hal_i2s.c
   4   * @author  MCD Application Team
   5   * @version V1.0.0
   6   * @date    5-September-2014
   7   * @brief   I2S HAL module driver.
   8   *          This file provides firmware functions to manage the following
   9   *          functionalities of the Integrated Interchip Sound (I2S) peripheral:
  10   *           + Initialization and de-initialization functions
  11   *           + IO operation functions
  12   *           + Peripheral State and Errors functions
  13   @verbatim
  14  ===============================================================================
  15                   ##### How to use this driver #####
  16  ===============================================================================
  17  [..]
  18     The I2S HAL driver can be used as follow:
  19
  20     (#) Declare a I2S_HandleTypeDef handle structure.
  21     (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
  22         (##) Enable the SPIx interface clock.
  23         (##) I2S pins configuration:
  24             (+++) Enable the clock for the I2S GPIOs.
  25             (+++) Configure these I2S pins as alternate function.
  26         (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
  27              and HAL_I2S_Receive_IT() APIs).
  28             (+++) Configure the I2Sx interrupt priority.
  29             (+++) Enable the NVIC I2S IRQ handle.
  30         (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
  31              and HAL_I2S_Receive_DMA() APIs:
  32             (+++) Declare a DMA handle structure for the Tx/Rx Channel.
  33             (+++) Enable the DMAx interface clock.
  34             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
  35             (+++) Configure the DMA Tx/Rx Channel.
  36             (+++) Associate the initilalized DMA handle to the I2S DMA Tx/Rx handle.
  37             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
  38                   DMA Tx/Rx Channel.
  39
  40    (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
  41        using HAL_I2S_Init() function.
  42
  43    -@- The specific I2S interrupts (Transmission complete interrupt,
  44        RXNE interrupt and Error Interrupts) will be managed using the macros
  45        __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
  46    -@- Make sure that either:
  47        (+@) External clock source is configured after setting correctly
  48             the define constant HSE_VALUE in the stm32l1xx_hal_conf.h file.
  49
  50     (#) Three mode of operations are available within this driver :
  51
  52    *** Polling mode IO operation ***
  53    =================================
  54    [..]
  55      (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
  56      (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
  57
  58    *** Interrupt mode IO operation ***
  59    ===================================
  60    [..]
  61      (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
  62      (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
  63          add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
  64      (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
  65          add his own code by customization of function pointer HAL_I2S_TxCpltCallback
  66      (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
  67      (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
  68          add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
  69      (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
  70          add his own code by customization of function pointer HAL_I2S_RxCpltCallback
  71      (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
  72          add his own code by customization of function pointer HAL_I2S_ErrorCallback
  73
  74    *** DMA mode IO operation ***
  75    ==============================
  76    [..]
  77      (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
  78      (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
  79          add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
  80      (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
  81          add his own code by customization of function pointer HAL_I2S_TxCpltCallback
  82      (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
  83      (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
  84          add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
  85      (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
  86          add his own code by customization of function pointer HAL_I2S_RxCpltCallback
  87      (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
  88          add his own code by customization of function pointer HAL_I2S_ErrorCallback
  89      (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
  90      (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
  91      (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
  92
  93    *** I2S HAL driver macros list ***
  94    =============================================
  95    [..]
  96      Below the list of most used macros in USART HAL driver.
  97
  98       (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
  99       (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
 100       (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
 101       (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
 102       (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
 103
 104     [..]
 105       (@) You can refer to the I2S HAL driver header file for more useful macros
 106
 107   @endverbatim
 108   ******************************************************************************
 109   * @attention
 110   *
 111   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
 112   *
 113   * Redistribution and use in source and binary forms, with or without modification,
 114   * are permitted provided that the following conditions are met:
 115   *   1. Redistributions of source code must retain the above copyright notice,
 116   *      this list of conditions and the following disclaimer.
 117   *   2. Redistributions in binary form must reproduce the above copyright notice,
 118   *      this list of conditions and the following disclaimer in the documentation
 119   *      and/or other materials provided with the distribution.
 120   *   3. Neither the name of STMicroelectronics nor the names of its contributors
 121   *      may be used to endorse or promote products derived from this software
 122   *      without specific prior written permission.
 123   *
 124   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 125   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 126   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 127   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 128   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 129   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 130   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 131   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 132   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 133   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 134   *
 135   ******************************************************************************
 136   */
 137
 138 /* Includes ------------------------------------------------------------------*/
 139 #include "stm32l1xx_hal.h"
 140
 141 /** @addtogroup STM32L1xx_HAL_Driver
 142   * @{
 143   */
 144
 145 /** @defgroup I2S I2S
 146   * @brief I2S HAL module driver
 147   * @{
 148   */
 149
 150 #ifdef HAL_I2S_MODULE_ENABLED
 151 #if defined(STM32L100xC) || \
 152     defined(STM32L151xC) || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xE) || \
 153     defined(STM32L152xC) || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L152xE) || \
 154     defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE)
 155
 156 /* Private typedef -----------------------------------------------------------*/
 157 /* Private define ------------------------------------------------------------*/
 158 /* Private macro -------------------------------------------------------------*/
 159 /* Private variables ---------------------------------------------------------*/
 160 /* Private function prototypes -----------------------------------------------*/
 161 static void               I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
 162 static void               I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
 163 static void               I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
 164 static void               I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
 165 static void               I2S_DMAError(DMA_HandleTypeDef *hdma);
 166 static void               I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
 167 static void               I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
 168 static HAL_StatusTypeDef  I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout);
 169
 170 /* Private functions ---------------------------------------------------------*/
 171
 172 /** @defgroup I2S_Exported_Functions I2S Exported Functions
 173   * @{
 174   */
 175
 176 /** @defgroup  I2S_Exported_Functions_Group1 Initialization and de-initialization functions
 177   *  @brief    Initialization and Configuration functions
 178   *
 179 @verbatim
 180  ===============================================================================
 181               ##### Initialization and de-initialization functions #####
 182  ===============================================================================
 183     [..]  This subsection provides a set of functions allowing to initialize and
 184           de-initialiaze the I2Sx peripheral in simplex mode:
 185
 186       (+) User must Implement HAL_I2S_MspInit() function in which he configures
 187           all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
 188
 189       (+) Call the function HAL_I2S_Init() to configure the selected device with
 190           the selected configuration:
 191         (++) Mode
 192         (++) Standard
 193         (++) Data Format
 194         (++) MCLK Output
 195         (++) Audio frequency
 196         (++) Polarity
 197
 198      (+) Call the function HAL_I2S_DeInit() to restore the default configuration
 199          of the selected I2Sx periperal.
 200   @endverbatim
 201   * @{
 202   */
 203
 204 /**
 205   * @brief Initializes the I2S according to the specified parameters
 206   *         in the I2S_InitTypeDef and create the associated handle.
 207   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
 208   *         the configuration information for I2S module
 209   * @retval HAL status
 210   */
 211 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
 212 {
 213   uint32_t i2sdiv = 2, i2sodd = 0, packetlength = 1;
 214   uint32_t tmp = 0, i2sclk = 0;
 215
 216   /* Check the I2S handle allocation */
 217   if(hi2s == HAL_NULL)
 218   {
 219     return HAL_ERROR;
 220   }
 221
 222   /* Check the I2S parameters */
 223   assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
 224   assert_param(IS_I2S_MODE(hi2s->Init.Mode));
 225   assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
 226   assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
 227   assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
 228   assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
 229   assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
 230
 231   if(hi2s->State == HAL_I2S_STATE_RESET)
 232   {
 233     /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
 234     HAL_I2S_MspInit(hi2s);
 235   }
 236
 237   hi2s->State = HAL_I2S_STATE_BUSY;
 238
 239   /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
 240   if(hi2s->Init.AudioFreq == I2S_AUDIOFREQ_DEFAULT)
 241   {
 242     i2sodd = (uint32_t)0;
 243     i2sdiv = (uint32_t)2;
 244   }
 245   /* If the requested audio frequency is not the default, compute the prescaler */
 246   else
 247   {
 248     /* Check the frame length (For the Prescaler computing) *******************/
 249     if(hi2s->Init.DataFormat == I2S_DATAFORMAT_16B)
 250     {
 251       /* Packet length is 16 bits */
 252       packetlength = 1;
 253     }
 254     else
 255     {
 256       /* Packet length is 32 bits */
 257       packetlength = 2;
 258     }
 259
 260     /* Get the source clock value: based on System Clock value */
 261     i2sclk = HAL_RCC_GetSysClockFreq();
 262
 263     /* Compute the Real divider depending on the MCLK output state, with a floating point */
 264     if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
 265     {
 266       /* MCLK output is enabled */
 267       tmp = (uint32_t)(((((i2sclk / 256) * 10) / hi2s->Init.AudioFreq)) + 5);
 268     }
 269     else
 270     {
 271       /* MCLK output is disabled */
 272       tmp = (uint32_t)(((((i2sclk / (32 * packetlength)) *10 ) / hi2s->Init.AudioFreq)) + 5);
 273     }
 274
 275     /* Remove the flatting point */
 276     tmp = tmp / 10;
 277
 278     /* Check the parity of the divider */
 279     i2sodd = (uint32_t)(tmp & (uint32_t)1);
 280
 281     /* Compute the i2sdiv prescaler */
 282     i2sdiv = (uint32_t)((tmp - i2sodd) / 2);
 283
 284     /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
 285     i2sodd = (uint32_t) (i2sodd << 8);
 286   }
 287
 288   /* Test if the divider is 1 or 0 or greater than 0xFF */
 289   if((i2sdiv < 2) || (i2sdiv > 0xFF))
 290   {
 291     /* Set the default values */
 292     i2sdiv = 2;
 293     i2sodd = 0;
 294   }
 295
 296   /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/
 297   /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
 298   /* And configure the I2S with the I2S_InitStruct values                      */
 299   MODIFY_REG( hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN |\
 300                                         SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD |\
 301                                         SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG |\
 302                                         SPI_I2SCFGR_I2SE  | SPI_I2SCFGR_I2SMOD),\
 303                                        (SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode |\
 304                                         hi2s->Init.Standard | hi2s->Init.DataFormat |\
 305                                         hi2s->Init.CPOL));
 306
 307   /* Write to SPIx I2SPR register the computed value */
 308   hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput));
 309
 310   hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
 311   hi2s->State= HAL_I2S_STATE_READY;
 312
 313   return HAL_OK;
 314 }
 315
 316 /**
 317   * @brief DeInitializes the I2S peripheral
 318   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
 319   *         the configuration information for I2S module
 320   * @retval HAL status
 321   */
 322 HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
 323 {
 324   /* Check the I2S handle allocation */
 325   if(hi2s == HAL_NULL)
 326   {
 327     return HAL_ERROR;
 328   }
 329
 330   hi2s->State = HAL_I2S_STATE_BUSY;
 331
 332   /* Disable the I2S Peripheral Clock */
 333   __HAL_I2S_DISABLE(hi2s);
 334
 335   /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
 336   HAL_I2S_MspDeInit(hi2s);
 337
 338   hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
 339   hi2s->State = HAL_I2S_STATE_RESET;
 340
 341   /* Release Lock */
 342   __HAL_UNLOCK(hi2s);
 343
 344   return HAL_OK;
 345 }
 346
 347 /**
 348   * @brief I2S MSP Init
 349   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
 350   *         the configuration information for I2S module
 351   * @retval None
 352   */
 353  __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
 354 {
 355   /* NOTE : This function Should not be modified, when the callback is needed,
 356             the HAL_I2S_MspInit could be implemented in the user file
 357    */
 358 }
 359
 360 /**
 361   * @brief I2S MSP DeInit
 362   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
 363   *         the configuration information for I2S module
 364   * @retval None
 365   */
 366  __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
 367 {
 368   /* NOTE : This function Should not be modified, when the callback is needed,
 369             the HAL_I2S_MspDeInit could be implemented in the user file
 370    */
 371 }
 372
 373 /**
 374   * @}
 375   */
 376
 377 /** @defgroup I2S_Exported_Functions_Group2 IO operation functions
 378   *  @brief Data transfers functions
 379   *
 380 @verbatim
 381  ===============================================================================
 382                       ##### IO operation functions #####
 383  ===============================================================================
 384     [..]
 385     This subsection provides a set of functions allowing to manage the I2S data
 386     transfers.
 387
 388     (#) There are two modes of transfer:
 389        (++) Blocking mode : The communication is performed in the polling mode.
 390             The status of all data processing is returned by the same function
 391             after finishing transfer.
 392        (++) No-Blocking mode : The communication is performed using Interrupts
 393             or DMA. These functions return the status of the transfer startup.
 394             The end of the data processing will be indicated through the
 395             dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
 396             using DMA mode.
 397
 398     (#) Blocking mode functions are :
 399         (++) HAL_I2S_Transmit()
 400         (++) HAL_I2S_Receive()
 401
 402     (#) No-Blocking mode functions with Interrupt are :
 403         (++) HAL_I2S_Transmit_IT()
 404         (++) HAL_I2S_Receive_IT()
 405
 406     (#) No-Blocking mode functions with DMA are :
 407         (++) HAL_I2S_Transmit_DMA()
 408         (++) HAL_I2S_Receive_DMA()
 409
 410     (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
 411         (++) HAL_I2S_TxCpltCallback()
 412         (++) HAL_I2S_RxCpltCallback()
 413         (++) HAL_I2S_ErrorCallback()
 414
 415 @endverbatim
 416   * @{
 417   */
 418
 419 /**
 420   * @brief Transmit an amount of data in blocking mode
 421   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
 422   *         the configuration information for I2S module
 423   * @param pData: a 16-bit pointer to data buffer.
 424   * @param Size: number of data sample to be sent:
 425   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
 426   *       configuration phase, the Size parameter means the number of 16-bit data length
 427   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
 428   *       the Size parameter means the number of 16-bit data length.
 429   * @param  Timeout: Timeout duration
 430   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
 431   *       between Master and Slave(example: audio streaming).
 432   * @retval HAL status
 433   */
 434 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
 435 {
 436   if((pData == HAL_NULL ) || (Size == 0))
 437   {
 438     return  HAL_ERROR;
 439   }
 440
 441   /* Process Locked */
 442   __HAL_LOCK(hi2s);
 443
 444   if(hi2s->State == HAL_I2S_STATE_READY)
 445   {
 446     if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
 447       ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
 448     {
 449       hi2s->TxXferSize = (Size << 1);
 450       hi2s->TxXferCount = (Size << 1);
 451     }
 452     else
 453     {
 454       hi2s->TxXferSize = Size;
 455       hi2s->TxXferCount = Size;
 456     }
 457
 458     /* Set state and reset error code */
 459     hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
 460     hi2s->State = HAL_I2S_STATE_BUSY_TX;
 461     hi2s->pTxBuffPtr = pData;
 462
 463     /* Check if the I2S is already enabled */
 464     if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
 465     {
 466       /* Enable I2S peripheral */
 467       __HAL_I2S_ENABLE(hi2s);
 468     }
 469
 470     while(hi2s->TxXferCount > 0)
 471     {
 472       /* Wait until TXE flag is set */
 473       if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
 474       {
 475         return HAL_TIMEOUT;
 476       }
 477       hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
 478       hi2s->TxXferCount--;
 479     }
 480
 481     /* Wait until TXE flag is set, to confirm the end of the transcation */
 482     if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
 483     {
 484       return HAL_TIMEOUT;
 485     }
 486     /* Wait until Busy flag is reset */
 487     if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK)
 488     {
 489       return HAL_TIMEOUT;
 490     }
 491
 492     hi2s->State = HAL_I2S_STATE_READY;
 493
 494     /* Process Unlocked */
 495     __HAL_UNLOCK(hi2s);
 496
 497     return HAL_OK;
 498   }
 499   else
 500   {
 501     /* Process Unlocked */
 502     __HAL_UNLOCK(hi2s);
 503     return HAL_BUSY;
 504   }
 505 }
 506
 507 /**
 508   * @brief Receive an amount of data in blocking mode
 509   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
 510   *         the configuration information for I2S module
 511   * @param pData: a 16-bit pointer to data buffer.
 512   * @param Size: number of data sample to be sent:
 513   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
 514   *       configuration phase, the Size parameter means the number of 16-bit data length
 515   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
 516   *       the Size parameter means the number of 16-bit data length.
 517   * @param Timeout: Timeout duration
 518   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
 519   *       between Master and Slave(example: audio streaming).
 520   * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
 521   *       in continouse way and as the I2S is not disabled at the end of the I2S transaction.
 522   * @retval HAL status
 523   */
 524 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
 525 {
 526   if((pData == HAL_NULL ) || (Size == 0))
 527   {
 528     return  HAL_ERROR;
 529   }
 530
 531   /* Process Locked */
 532   __HAL_LOCK(hi2s);
 533
 534   if(hi2s->State == HAL_I2S_STATE_READY)
 535   {
 536     if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
 537       ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
 538     {
 539       hi2s->RxXferSize = (Size << 1);
 540       hi2s->RxXferCount = (Size << 1);
 541     }
 542     else
 543     {
 544       hi2s->RxXferSize = Size;
 545       hi2s->RxXferCount = Size;
 546     }
 547
 548     /* Set state and reset error code */
 549     hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
 550     hi2s->State = HAL_I2S_STATE_BUSY_RX;
 551     hi2s->pRxBuffPtr = pData;
 552
 553     /* Check if the I2S is already enabled */
 554     if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
 555     {
 556       /* Enable I2S peripheral */
 557       __HAL_I2S_ENABLE(hi2s);
 558     }
 559
 560     /* Receive data */
 561     while(hi2s->RxXferCount > 0)
 562     {
 563       /* Wait until RXNE flag is set */
 564       if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK)
 565       {
 566         return HAL_TIMEOUT;
 567       }
 568
 569       (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
 570       hi2s->RxXferCount--;
 571     }
 572
 573     hi2s->State = HAL_I2S_STATE_READY;
 574
 575     /* Process Unlocked */
 576     __HAL_UNLOCK(hi2s);
 577
 578     return HAL_OK;
 579   }
 580   else
 581   {
 582     /* Process Unlocked */
 583     __HAL_UNLOCK(hi2s);
 584     return HAL_BUSY;
 585   }
 586 }
 587
 588 /**
 589   * @brief Transmit an amount of data in non-blocking mode with Interrupt
 590   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
 591   *         the configuration information for I2S module
 592   * @param pData: a 16-bit pointer to data buffer.
 593   * @param Size: number of data sample to be sent:
 594   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
 595   *       configuration phase, the Size parameter means the number of 16-bit data length
 596   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
 597   *       the Size parameter means the number of 16-bit data length.
 598   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
 599   *       between Master and Slave(example: audio streaming).
 600   * @retval HAL status
 601   */
 602 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
 603 {
 604   if((pData == HAL_NULL) || (Size == 0))
 605   {
 606     return  HAL_ERROR;
 607   }
 608
 609   /* Process Locked */
 610   __HAL_LOCK(hi2s);
 611
 612   if(hi2s->State == HAL_I2S_STATE_READY)
 613   {
 614     hi2s->pTxBuffPtr = pData;
 615     hi2s->State = HAL_I2S_STATE_BUSY_TX;
 616     hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
 617
 618     if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
 619       ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
 620     {
 621       hi2s->TxXferSize = (Size << 1);
 622       hi2s->TxXferCount = (Size << 1);
 623     }
 624     else
 625     {
 626       hi2s->TxXferSize = Size;
 627       hi2s->TxXferCount = Size;
 628     }
 629
 630     /* Enable TXE and ERR interrupt */
 631     __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
 632
 633     /* Check if the I2S is already enabled */
 634     if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
 635     {
 636       /* Enable I2S peripheral */
 637       __HAL_I2S_ENABLE(hi2s);
 638     }
 639
 640     /* Process Unlocked */
 641     __HAL_UNLOCK(hi2s);
 642
 643     return HAL_OK;
 644   }
 645   else
 646   {
 647     /* Process Unlocked */
 648     __HAL_UNLOCK(hi2s);
 649     return HAL_BUSY;
 650   }
 651 }
 652
 653 /**
 654   * @brief Receive an amount of data in non-blocking mode with Interrupt
 655   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
 656   *         the configuration information for I2S module
 657   * @param pData: a 16-bit pointer to the Receive data buffer.
 658   * @param Size: number of data sample to be sent:
 659   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
 660   *       configuration phase, the Size parameter means the number of 16-bit data length
 661   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
 662   *       the Size parameter means the number of 16-bit data length.
 663   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
 664   *       between Master and Slave(example: audio streaming).
 665   * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation
 666   * between Master and Slave otherwise the I2S interrupt should be optimized.
 667   * @retval HAL status
 668   */
 669 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
 670 {
 671     if((pData == HAL_NULL) || (Size == 0))
 672     {
 673       return  HAL_ERROR;
 674     }
 675
 676   /* Process Locked */
 677   __HAL_LOCK(hi2s);
 678
 679   if(hi2s->State == HAL_I2S_STATE_READY)
 680   {
 681     hi2s->pRxBuffPtr = pData;
 682     hi2s->State = HAL_I2S_STATE_BUSY_RX;
 683     hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
 684
 685     if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
 686       ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
 687     {
 688       hi2s->RxXferSize = (Size << 1);
 689       hi2s->RxXferCount = (Size << 1);
 690     }
 691     else
 692     {
 693       hi2s->RxXferSize = Size;
 694       hi2s->RxXferCount = Size;
 695     }
 696
 697     /* Enable TXE and ERR interrupt */
 698     __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
 699
 700     /* Check if the I2S is already enabled */
 701     if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
 702     {
 703       /* Enable I2S peripheral */
 704       __HAL_I2S_ENABLE(hi2s);
 705     }
 706
 707     /* Process Unlocked */
 708     __HAL_UNLOCK(hi2s);
 709
 710     return HAL_OK;
 711   }
 712   else
 713   {
 714     /* Process Unlocked */
 715     __HAL_UNLOCK(hi2s);
 716     return HAL_BUSY;
 717   }
 718 }
 719
 720 /**
 721   * @brief Transmit an amount of data in non-blocking mode with DMA
 722   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
 723   *         the configuration information for I2S module
 724   * @param pData: a 16-bit pointer to the Transmit data buffer.
 725   * @param Size: number of data sample to be sent:
 726   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
 727   *       configuration phase, the Size parameter means the number of 16-bit data length
 728   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
 729   *       the Size parameter means the number of 16-bit data length.
 730   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
 731   *       between Master and Slave(example: audio streaming).
 732   * @retval HAL status
 733   */
 734 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
 735 {
 736   if((pData == HAL_NULL) || (Size == 0))
 737   {
 738     return  HAL_ERROR;
 739   }
 740
 741   /* Process Locked */
 742   __HAL_LOCK(hi2s);
 743
 744   if(hi2s->State == HAL_I2S_STATE_READY)
 745   {
 746     hi2s->pTxBuffPtr = pData;
 747     hi2s->State = HAL_I2S_STATE_BUSY_TX;
 748     hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
 749
 750     if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
 751       ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
 752     {
 753       hi2s->TxXferSize = (Size << 1);
 754       hi2s->TxXferCount = (Size << 1);
 755     }
 756     else
 757     {
 758       hi2s->TxXferSize = Size;
 759       hi2s->TxXferCount = Size;
 760     }
 761
 762     /* Set the I2S Tx DMA Half transfert complete callback */
 763     hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
 764
 765     /* Set the I2S Tx DMA transfert complete callback */
 766     hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
 767
 768     /* Set the DMA error callback */
 769     hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
 770
 771     /* Enable the Tx DMA Channel */
 772     HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
 773
 774     /* Check if the I2S is already enabled */
 775     if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
 776     {
 777       /* Enable I2S peripheral */
 778       __HAL_I2S_ENABLE(hi2s);
 779     }
 780
 781     /* Check if the I2S Tx request is already enabled */
 782     if((hi2s->Instance->CR2 & SPI_CR2_TXDMAEN) != SPI_CR2_TXDMAEN)
 783     {
 784       /* Enable Tx DMA Request */
 785       SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
 786     }
 787
 788     /* Process Unlocked */
 789     __HAL_UNLOCK(hi2s);
 790
 791     return HAL_OK;
 792   }
 793   else
 794   {
 795     /* Process Unlocked */
 796     __HAL_UNLOCK(hi2s);
 797     return HAL_BUSY;
 798   }
 799 }
 800
 801 /**
 802   * @brief Receive an amount of data in non-blocking mode with DMA
 803   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
 804   *         the configuration information for I2S module
 805   * @param pData: a 16-bit pointer to the Receive data buffer.
 806   * @param Size: number of data sample to be sent:
 807   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
 808   *       configuration phase, the Size parameter means the number of 16-bit data length
 809   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
 810   *       the Size parameter means the number of 16-bit data length.
 811   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
 812   *       between Master and Slave(example: audio streaming).
 813   * @retval HAL status
 814   */
 815 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
 816 {
 817   if((pData == HAL_NULL) || (Size == 0))
 818   {
 819     return  HAL_ERROR;
 820   }
 821
 822   /* Process Locked */
 823   __HAL_LOCK(hi2s);
 824
 825   if(hi2s->State == HAL_I2S_STATE_READY)
 826   {
 827     hi2s->pRxBuffPtr = pData;
 828     hi2s->State = HAL_I2S_STATE_BUSY_RX;
 829     hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
 830
 831     if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
 832       ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
 833     {
 834       hi2s->RxXferSize = (Size << 1);
 835       hi2s->RxXferCount = (Size << 1);
 836     }
 837     else
 838     {
 839       hi2s->RxXferSize = Size;
 840       hi2s->RxXferCount = Size;
 841     }
 842
 843
 844     /* Set the I2S Rx DMA Half transfert complete callback */
 845     hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
 846
 847     /* Set the I2S Rx DMA transfert complete callback */
 848     hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
 849
 850     /* Set the DMA error callback */
 851     hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
 852
 853     /* Check if Master Receiver mode is selected */
 854     if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
 855     {
 856       /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
 857       access to the SPI_SR register. */
 858       __HAL_I2S_CLEAR_OVRFLAG(hi2s);
 859     }
 860
 861     /* Enable the Rx DMA Channel */
 862     HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)hi2s->pRxBuffPtr, hi2s->RxXferSize);
 863
 864     /* Check if the I2S is already enabled */
 865     if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
 866     {
 867       /* Enable I2S peripheral */
 868       __HAL_I2S_ENABLE(hi2s);
 869     }
 870
 871      /* Check if the I2S Rx request is already enabled */
 872     if((hi2s->Instance->CR2 &SPI_CR2_RXDMAEN) != SPI_CR2_RXDMAEN)
 873     {
 874       /* Enable Rx DMA Request */
 875       SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
 876     }
 877
 878     /* Process Unlocked */
 879     __HAL_UNLOCK(hi2s);
 880
 881     return HAL_OK;
 882   }
 883   else
 884   {
 885     /* Process Unlocked */
 886     __HAL_UNLOCK(hi2s);
 887     return HAL_BUSY;
 888   }
 889 }
 890
 891 /**
 892   * @brief Pauses the audio stream playing from the Media.
 893   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
 894   *         the configuration information for I2S module
 895   * @retval HAL status
 896   */
 897 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
 898 {
 899   /* Process Locked */
 900   __HAL_LOCK(hi2s);
 901
 902   if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
 903   {
 904     /* Disable the I2S DMA Tx request */
 905     CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
 906   }
 907   else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
 908   {
 909     /* Disable the I2S DMA Rx request */
 910     CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
 911   }
 912
 913   /* Process Unlocked */
 914   __HAL_UNLOCK(hi2s);
 915
 916   return HAL_OK;
 917 }
 918
 919 /**
 920   * @brief Resumes the audio stream playing from the Media.
 921   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
 922   *         the configuration information for I2S module
 923   * @retval HAL status
 924   */
 925 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
 926 {
 927   /* Process Locked */
 928   __HAL_LOCK(hi2s);
 929
 930   if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
 931   {
 932     /* Enable the I2S DMA Tx request */
 933     SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
 934   }
 935   else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
 936   {
 937     /* Enable the I2S DMA Rx request */
 938     SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
 939   }
 940
 941   /* If the I2S peripheral is still not enabled, enable it */
 942   if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0)
 943   {
 944     /* Enable I2S peripheral */
 945     __HAL_I2S_ENABLE(hi2s);
 946   }
 947
 948   /* Process Unlocked */
 949   __HAL_UNLOCK(hi2s);
 950
 951   return HAL_OK;
 952 }
 953
 954 /**
 955   * @brief Resumes the audio stream playing from the Media.
 956   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
 957   *         the configuration information for I2S module
 958   * @retval HAL status
 959   */
 960 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
 961 {
 962   /* Process Locked */
 963   __HAL_LOCK(hi2s);
 964
 965   /* Disable the I2S Tx/Rx DMA requests */
 966   CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
 967   CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
 968
 969   /* Abort the I2S DMA Channel tx */
 970   if(hi2s->hdmatx != HAL_NULL)
 971   {
 972     /* Disable the I2S DMA channel */
 973     __HAL_DMA_DISABLE(hi2s->hdmatx);
 974     HAL_DMA_Abort(hi2s->hdmatx);
 975   }
 976   /* Abort the I2S DMA Channel rx */
 977   if(hi2s->hdmarx != HAL_NULL)
 978   {
 979     /* Disable the I2S DMA channel */
 980     __HAL_DMA_DISABLE(hi2s->hdmarx);
 981     HAL_DMA_Abort(hi2s->hdmarx);
 982   }
 983
 984   /* Disable I2S peripheral */
 985   __HAL_I2S_DISABLE(hi2s);
 986
 987   hi2s->State = HAL_I2S_STATE_READY;
 988
 989   /* Process Unlocked */
 990   __HAL_UNLOCK(hi2s);
 991
 992   return HAL_OK;
 993 }
 994
 995 /**
 996   * @brief  This function handles I2S interrupt request.
 997   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
 998   *         the configuration information for I2S module
 999   * @retval None
1000   */
1001 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
1002 {
1003   uint32_t i2ssr = hi2s->Instance->SR;
1004
1005   /* I2S in mode Receiver ------------------------------------------------*/
1006   if(((i2ssr & I2S_FLAG_OVR) != I2S_FLAG_OVR) &&
1007      ((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
1008   {
1009     I2S_Receive_IT(hi2s);
1010     return;
1011   }
1012
1013   /* I2S in mode Tramitter -----------------------------------------------*/
1014   if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
1015   {
1016     I2S_Transmit_IT(hi2s);
1017     return;
1018   }
1019
1020   /* I2S interrupt error -------------------------------------------------*/
1021   if(__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)
1022   {
1023     /* I2S Overrun error interrupt occured ---------------------------------*/
1024     if((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR)
1025     {
1026       /* Disable RXNE and ERR interrupt */
1027       __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
1028
1029       /* Set the error code and execute error callback*/
1030       SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
1031     }
1032
1033     /* I2S Underrun error interrupt occured --------------------------------*/
1034     if((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR)
1035     {
1036       /* Disable TXE and ERR interrupt */
1037       __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
1038
1039       /* Set the error code and execute error callback*/
1040       SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
1041     }
1042
1043     /* I2S Frame format error interrupt occured --------------------------*/
1044     if((i2ssr & I2S_FLAG_FRE) == I2S_FLAG_FRE)
1045     {
1046       /* Disable TXE and ERR interrupt */
1047       __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_RXNE | I2S_IT_ERR));
1048
1049       /* Set the error code and execute error callback*/
1050       SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_FRE);
1051     }
1052
1053     /* Set the I2S State ready */
1054     hi2s->State = HAL_I2S_STATE_READY;
1055     /* Call the Error Callback */
1056     HAL_I2S_ErrorCallback(hi2s);
1057   }
1058 }
1059
1060 /**
1061   * @brief Tx Transfer Half completed callbacks
1062   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
1063   *         the configuration information for I2S module
1064   * @retval None
1065   */
1066  __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
1067 {
1068   /* NOTE : This function Should not be modified, when the callback is needed,
1069             the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
1070    */
1071 }
1072
1073 /**
1074   * @brief Tx Transfer completed callbacks
1075   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
1076   *         the configuration information for I2S module
1077   * @retval None
1078   */
1079  __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
1080 {
1081   /* NOTE : This function Should not be modified, when the callback is needed,
1082             the HAL_I2S_TxCpltCallback could be implemented in the user file
1083    */
1084 }
1085
1086 /**
1087   * @brief Rx Transfer half completed callbacks
1088   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
1089   *         the configuration information for I2S module
1090   * @retval None
1091   */
1092 __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
1093 {
1094   /* NOTE : This function Should not be modified, when the callback is needed,
1095             the HAL_I2S_RxHalfCpltCallback could be implemented in the user file
1096    */
1097 }
1098
1099 /**
1100   * @brief Rx Transfer completed callbacks
1101   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
1102   *         the configuration information for I2S module
1103   * @retval None
1104   */
1105 __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
1106 {
1107   /* NOTE : This function Should not be modified, when the callback is needed,
1108             the HAL_I2S_RxCpltCallback could be implemented in the user file
1109    */
1110 }
1111
1112 /**
1113   * @brief I2S error callbacks
1114   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
1115   *         the configuration information for I2S module
1116   * @retval None
1117   */
1118  __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
1119 {
1120   /* NOTE : This function Should not be modified, when the callback is needed,
1121             the HAL_I2S_ErrorCallback could be implemented in the user file
1122    */
1123 }
1124
1125 /**
1126   * @}
1127   */
1128
1129 /** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
1130   *  @brief   Peripheral State functions
1131   *
1132 @verbatim
1133  ===============================================================================
1134                       ##### Peripheral State and Errors functions #####
1135  ===============================================================================
1136     [..]
1137     This subsection permits to get in run-time the status of the peripheral
1138     and the data flow.
1139
1140 @endverbatim
1141   * @{
1142   */
1143
1144 /**
1145   * @brief  Return the I2S state
1146   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
1147   *         the configuration information for I2S module
1148   * @retval HAL state
1149   */
1150 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
1151 {
1152   return hi2s->State;
1153 }
1154
1155 /**
1156   * @brief  Return the I2S error code
1157   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
1158   *         the configuration information for I2S module
1159   * @retval I2S Error Code
1160   */
1161 HAL_I2S_ErrorTypeDef HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
1162 {
1163   return hi2s->ErrorCode;
1164 }
1165 /**
1166   * @}
1167   */
1168
1169 /**
1170   * @}
1171   */
1172
1173
1174 /** @defgroup I2S_Private_Functions I2S Private Functions
1175   * @{
1176   */
1177 /**
1178   * @brief DMA I2S transmit process complete callback
1179   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
1180   *                the configuration information for the specified DMA module.
1181   * @retval None
1182   */
1183 static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
1184 {
1185   I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
1186
1187   if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
1188   {
1189     /* Disable Tx DMA Request */
1190     CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
1191
1192     hi2s->TxXferCount = 0;
1193     hi2s->State = HAL_I2S_STATE_READY;
1194   }
1195   HAL_I2S_TxCpltCallback(hi2s);
1196 }
1197
1198 /**
1199   * @brief DMA I2S transmit process half complete callback
1200   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
1201   *                the configuration information for the specified DMA module.
1202   * @retval None
1203   */
1204 static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
1205 {
1206   I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
1207
1208   HAL_I2S_TxHalfCpltCallback(hi2s);
1209 }
1210
1211 /**
1212   * @brief DMA I2S receive process complete callback
1213   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
1214   *                the configuration information for the specified DMA module.
1215   * @retval None
1216   */
1217 static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
1218 {
1219   I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
1220
1221   if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
1222   {
1223     /* Disable Rx DMA Request */
1224     CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
1225     hi2s->RxXferCount = 0;
1226     hi2s->State = HAL_I2S_STATE_READY;
1227   }
1228   HAL_I2S_RxCpltCallback(hi2s);
1229 }
1230
1231 /**
1232   * @brief DMA I2S receive process half complete callback
1233   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
1234   *                the configuration information for the specified DMA module.
1235   * @retval None
1236   */
1237 static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
1238 {
1239   I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
1240
1241   HAL_I2S_RxHalfCpltCallback(hi2s);
1242 }
1243
1244 /**
1245   * @brief DMA I2S communication error callback
1246   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
1247   *                the configuration information for the specified DMA module.
1248   * @retval None
1249   */
1250 static void I2S_DMAError(DMA_HandleTypeDef *hdma)
1251 {
1252   I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
1253
1254   /* Disable Rx and Tx DMA Request */
1255   CLEAR_BIT(hi2s->Instance->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
1256   hi2s->TxXferCount = 0;
1257   hi2s->RxXferCount = 0;
1258
1259   hi2s->State= HAL_I2S_STATE_READY;
1260
1261   /* Set the error code and execute error callback*/
1262   SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
1263   HAL_I2S_ErrorCallback(hi2s);
1264 }
1265
1266 /**
1267   * @brief Transmit an amount of data in non-blocking mode with Interrupt
1268   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
1269   *         the configuration information for I2S module
1270   * @retval None
1271   */
1272 static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
1273 {
1274   /* Transmit data */
1275   hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
1276   hi2s->TxXferCount--;
1277
1278   if(hi2s->TxXferCount == 0)
1279   {
1280     /* Disable TXE and ERR interrupt */
1281     __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
1282
1283     hi2s->State = HAL_I2S_STATE_READY;
1284     HAL_I2S_TxCpltCallback(hi2s);
1285   }
1286 }
1287
1288 /**
1289   * @brief Receive an amount of data in non-blocking mode with Interrupt
1290   * @param hi2s: I2S handle
1291   * @retval None
1292   */
1293 static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
1294 {
1295   /* Receive data */
1296   (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
1297   hi2s->RxXferCount--;
1298
1299   if(hi2s->RxXferCount == 0)
1300   {
1301     /* Disable RXNE and ERR interrupt */
1302     __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
1303
1304     hi2s->State = HAL_I2S_STATE_READY;
1305     HAL_I2S_RxCpltCallback(hi2s);
1306   }
1307 }
1308
1309
1310 /**
1311   * @brief This function handles I2S Communication Timeout.
1312   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
1313   *         the configuration information for I2S module
1314   * @param Flag: Flag checked
1315   * @param Status: Value of the flag expected
1316   * @param Timeout: Duration of the timeout
1317   * @retval HAL status
1318   */
1319 static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout)
1320 {
1321   uint32_t tickstart = 0;
1322
1323   /* Get tick */
1324   tickstart = HAL_GetTick();
1325
1326   /* Wait until flag is set */
1327   if(Status == RESET)
1328   {
1329     while(__HAL_I2S_GET_FLAG(hi2s, Flag) == RESET)
1330     {
1331       if(Timeout != HAL_MAX_DELAY)
1332       {
1333         if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
1334         {
1335           /* Set the I2S State ready */
1336           hi2s->State= HAL_I2S_STATE_READY;
1337
1338           /* Process Unlocked */
1339           __HAL_UNLOCK(hi2s);
1340
1341           return HAL_TIMEOUT;
1342         }
1343       }
1344     }
1345   }
1346   else
1347   {
1348     while(__HAL_I2S_GET_FLAG(hi2s, Flag) != RESET)
1349     {
1350       if(Timeout != HAL_MAX_DELAY)
1351       {
1352         if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
1353         {
1354           /* Set the I2S State ready */
1355           hi2s->State= HAL_I2S_STATE_READY;
1356
1357           /* Process Unlocked */
1358           __HAL_UNLOCK(hi2s);
1359
1360           return HAL_TIMEOUT;
1361         }
1362       }
1363     }
1364   }
1365   return HAL_OK;
1366 }
1367
1368 /**
1369   * @}
1370   */
1371 #endif /* STM32L100xC ||
1372           STM32L151xC || STM32L151xCA || STM32L151xD || STM32L151xE ||\\
1373           STM32L152xC || STM32L152xCA || STM32L152xD || STM32L152xE ||\\
1374           STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE */
1375 #endif /* HAL_I2S_MODULE_ENABLED */
1376 /**
1377   * @}
1378   */
1379
1380 /**
1381   * @}
1382   */
1383
1384 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/