tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_nor.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32l1xx_hal_nor.h
   4   * @author  MCD Application Team
   5   * @version V1.0.0
   6   * @date    5-September-2014
   7   * @brief   Header file of NOR HAL module.
   8   ******************************************************************************
   9   * @attention
  10   *
  11   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
  12   *
  13   * Redistribution and use in source and binary forms, with or without modification,
  14   * are permitted provided that the following conditions are met:
  15   *   1. Redistributions of source code must retain the above copyright notice,
  16   *      this list of conditions and the following disclaimer.
  17   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18   *      this list of conditions and the following disclaimer in the documentation
  19   *      and/or other materials provided with the distribution.
  20   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21   *      may be used to endorse or promote products derived from this software
  22   *      without specific prior written permission.
  23   *
  24   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34   *
  35   ******************************************************************************
  36   */
  37
  38 /* Define to prevent recursive inclusion -------------------------------------*/
  39 #ifndef __STM32L1xx_HAL_NOR_H
  40 #define __STM32L1xx_HAL_NOR_H
  41
  42 #ifdef __cplusplus
  43  extern "C" {
  44 #endif
  45
  46 /* Includes ------------------------------------------------------------------*/
  47 #include "stm32l1xx_ll_fsmc.h"
  48
  49 /** @addtogroup STM32L1xx_HAL_Driver
  50   * @{
  51   */
  52
  53 /** @addtogroup NOR
  54   * @{
  55   */
  56
  57 #if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
  58
  59 /* Exported typedef ----------------------------------------------------------*/
  60
  61 /** @defgroup NOR_Exported_typedef NOR Exported typedef
  62   * @{
  63   */
  64
  65 /**
  66   * @brief  HAL SRAM State structures definition
  67   */
  68 typedef enum
  69 {
  70   HAL_NOR_STATE_RESET             = 0x00,  /*!< NOR not yet initialized or disabled  */
  71   HAL_NOR_STATE_READY             = 0x01,  /*!< NOR initialized and ready for use    */
  72   HAL_NOR_STATE_BUSY              = 0x02,  /*!< NOR internal processing is ongoing   */
  73   HAL_NOR_STATE_ERROR             = 0x03,  /*!< NOR error state                      */
  74   HAL_NOR_STATE_PROTECTED         = 0x04   /*!< NOR NORSRAM device write protected  */
  75
  76 }HAL_NOR_StateTypeDef;
  77
  78 /**
  79   * @brief  FSMC NOR Status typedef
  80   */
  81 typedef enum
  82 {
  83   NOR_SUCCESS = 0,
  84   NOR_ONGOING,
  85   NOR_ERROR,
  86   NOR_TIMEOUT
  87
  88 }NOR_StatusTypedef;
  89
  90 /**
  91   * @brief  FSMC NOR ID typedef
  92   */
  93 typedef struct
  94 {
  95   uint16_t ManufacturerCode;  /*!< Defines the device's manufacturer code used to identify the memory       */
  96
  97   uint16_t DeviceCode1;
  98
  99   uint16_t DeviceCode2;
 100
 101   uint16_t DeviceCode3;       /*!< Defines the devices' codes used to identify the memory.
 102                                     These codes can be accessed by performing read operations with specific
 103                                     control signals and addresses set.They can also be accessed by issuing
 104                                     an Auto Select command                                                   */
 105
 106 }NOR_IDTypeDef;
 107
 108
 109 /**
 110   * @brief  FSMC NOR CFI typedef
 111   */
 112 typedef struct
 113 {
 114   /*!< Defines the information stored in the memory's Common flash interface
 115        which contains a description of various electrical and timing parameters,
 116        density information and functions supported by the memory                   */
 117
 118   uint16_t CFI1;
 119
 120   uint16_t CFI2;
 121
 122   uint16_t CFI3;
 123
 124   uint16_t CFI4;
 125
 126 }NOR_CFITypeDef;
 127
 128 /**
 129   * @brief  NOR handle Structure definition
 130   */
 131 typedef struct
 132 {
 133   FSMC_NORSRAM_TYPEDEF          *Instance;    /*!< Register base address                        */
 134
 135   FSMC_NORSRAM_EXTENDED_TYPEDEF *Extended;    /*!< Extended mode register base address          */
 136
 137   FSMC_NORSRAM_InitTypeDef      Init;         /*!< NOR device control configuration parameters  */
 138
 139   HAL_LockTypeDef               Lock;         /*!< NOR locking object                           */
 140
 141   __IO HAL_NOR_StateTypeDef     State;        /*!< NOR device access state                      */
 142
 143 }NOR_HandleTypeDef;
 144
 145 /**
 146   * @}
 147   */
 148
 149 /* Exported constants --------------------------------------------------------*/
 150
 151 /** @defgroup NOR_Exported_Constants NOR Exported Constants
 152   * @{
 153   */
 154
 155 /* NOR device IDs addresses */
 156 #define MC_ADDRESS               ((uint16_t)0x0000)
 157 #define DEVICE_CODE1_ADDR        ((uint16_t)0x0001)
 158 #define DEVICE_CODE2_ADDR        ((uint16_t)0x000E)
 159 #define DEVICE_CODE3_ADDR        ((uint16_t)0x000F)
 160
 161 /* NOR CFI IDs addresses */
 162 #define CFI1_ADDRESS             ((uint16_t)0x10)
 163 #define CFI2_ADDRESS             ((uint16_t)0x11)
 164 #define CFI3_ADDRESS             ((uint16_t)0x12)
 165 #define CFI4_ADDRESS             ((uint16_t)0x13)
 166
 167 /* NOR operation wait timeout */
 168 #define NOR_TMEOUT               ((uint16_t)0xFFFF)
 169
 170 /* NOR memory data width */
 171 #define NOR_MEMORY_8B            ((uint8_t)0x0)
 172 #define NOR_MEMORY_16B           ((uint8_t)0x1)
 173
 174 /* NOR memory device read/write start address */
 175 #define NOR_MEMORY_ADRESS1       ((uint32_t)0x60000000)
 176 #define NOR_MEMORY_ADRESS2       ((uint32_t)0x64000000)
 177 #define NOR_MEMORY_ADRESS3       ((uint32_t)0x68000000)
 178 #define NOR_MEMORY_ADRESS4       ((uint32_t)0x6C000000)
 179
 180 /**
 181   * @}
 182   */
 183
 184 /* Exported macro ------------------------------------------------------------*/
 185
 186 /** @defgroup NOR_Exported_macro NOR Exported macro
 187   * @{
 188   */
 189
 190 /** @brief Reset NOR handle state
 191   * @param  __HANDLE__: NOR handle
 192   * @retval None
 193   */
 194 #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
 195
 196
 197 /**
 198   * @brief  NOR memory address shifting.
 199   * @param  __NOR_ADDRESS: NOR base address
 200   * @param  __NOR_MEMORY_WIDTH_: NOR memory width
 201   * @param  __ADDRESS__: NOR memory address
 202   * @retval NOR shifted address value
 203   */
 204 #define __NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__)       \
 205             ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)?              \
 206               ((uint32_t)((__NOR_ADDRESS) + (2 * (__ADDRESS__)))):              \
 207               ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
 208
 209 /**
 210   * @brief  NOR memory write data to specified address.
 211   * @param  __ADDRESS__: NOR memory address
 212   * @param  __DATA__: Data to write
 213   * @retval None
 214   */
 215 #define __NOR_WRITE(__ADDRESS__, __DATA__)  (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__))
 216
 217 /**
 218   * @}
 219   */
 220
 221 /* Exported functions --------------------------------------------------------*/
 222
 223 /** @addtogroup NOR_Exported_Functions
 224  *  @{
 225  */
 226
 227 /** @addtogroup NOR_Exported_Functions_Group1
 228  *  @{
 229  */
 230
 231 /* Initialization/de-initialization functions  **********************************/
 232 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming);
 233 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
 234 void              HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
 235 void              HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
 236 void              HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
 237
 238 /**
 239   * @}
 240   */
 241
 242 /** @addtogroup NOR_Exported_Functions_Group2
 243  *  @{
 244  */
 245
 246 /* I/O operation functions  *****************************************************/
 247 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
 248 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
 249 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
 250 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
 251
 252 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
 253 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
 254
 255 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
 256 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
 257 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
 258
 259 /**
 260   * @}
 261   */
 262
 263 /** @addtogroup NOR_Exported_Functions_Group3
 264  *  @{
 265  */
 266
 267 /* NOR Control functions  *******************************************************/
 268 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
 269 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
 270
 271 /**
 272   * @}
 273   */
 274
 275 /** @addtogroup NOR_Exported_Functions_Group4
 276  *  @{
 277  */
 278
 279 /* NOR State functions **********************************************************/
 280 HAL_NOR_StateTypeDef  HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
 281 NOR_StatusTypedef     HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
 282
 283 /**
 284   * @}
 285   */
 286
 287 /**
 288   * @}
 289   */
 290
 291 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
 292
 293 /**
 294   * @}
 295   */
 296
 297 /**
 298   * @}
 299   */
 300
 301 #ifdef __cplusplus
 302 }
 303 #endif
 304
 305 #endif /* __STM32L1xx_HAL_NOR_H */
 306
 307 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/