tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_spi.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32l1xx_hal_spi.h
   4   * @author  MCD Application Team
   5   * @version V1.0.0
   6   * @date    5-September-2014
   7   * @brief   Header file of SPI HAL module.
   8   ******************************************************************************
   9   * @attention
  10   *
  11   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
  12   *
  13   * Redistribution and use in source and binary forms, with or without modification,
  14   * are permitted provided that the following conditions are met:
  15   *   1. Redistributions of source code must retain the above copyright notice,
  16   *      this list of conditions and the following disclaimer.
  17   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18   *      this list of conditions and the following disclaimer in the documentation
  19   *      and/or other materials provided with the distribution.
  20   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21   *      may be used to endorse or promote products derived from this software
  22   *      without specific prior written permission.
  23   *
  24   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34   *
  35   ******************************************************************************
  36   */
  37
  38 /* Define to prevent recursive inclusion -------------------------------------*/
  39 #ifndef __STM32L1xx_HAL_SPI_H
  40 #define __STM32L1xx_HAL_SPI_H
  41
  42 #ifdef __cplusplus
  43  extern "C" {
  44 #endif
  45
  46 /* Includes ------------------------------------------------------------------*/
  47 #include "stm32l1xx_hal_def.h"
  48
  49 /** @addtogroup STM32L1xx_HAL_Driver
  50   * @{
  51   */
  52
  53 /** @addtogroup SPI
  54   * @{
  55   */
  56
  57 /* Exported types ------------------------------------------------------------*/
  58 /** @defgroup SPI_Exported_Types SPI Exported Types
  59   * @{
  60   */
  61
  62 /**
  63   * @brief  SPI Configuration Structure definition
  64   */
  65 typedef struct
  66 {
  67   uint32_t Mode;               /*!< Specifies the SPI operating mode.
  68                                     This parameter can be a value of @ref SPI_mode */
  69
  70   uint32_t Direction;          /*!< Specifies the SPI Directional mode state.
  71                                     This parameter can be a value of @ref SPI_Direction_mode */
  72
  73   uint32_t DataSize;           /*!< Specifies the SPI data size.
  74                                     This parameter can be a value of @ref SPI_data_size */
  75
  76   uint32_t CLKPolarity;        /*!< Specifies the serial clock steady state.
  77                                     This parameter can be a value of @ref SPI_Clock_Polarity */
  78
  79   uint32_t CLKPhase;           /*!< Specifies the clock active edge for the bit capture.
  80                                     This parameter can be a value of @ref SPI_Clock_Phase */
  81
  82   uint32_t NSS;                /*!< Specifies whether the NSS signal is managed by
  83                                     hardware (NSS pin) or by software using the SSI bit.
  84                                     This parameter can be a value of @ref SPI_Slave_Select_management */
  85
  86   uint32_t BaudRatePrescaler;  /*!< Specifies the Baud Rate prescaler value which will be
  87                                     used to configure the transmit and receive SCK clock.
  88                                     This parameter can be a value of @ref SPI_BaudRate_Prescaler
  89                                     @note The communication clock is derived from the master
  90                                     clock. The slave clock does not need to be set */
  91
  92   uint32_t FirstBit;           /*!< Specifies whether data transfers start from MSB or LSB bit.
  93                                     This parameter can be a value of @ref SPI_MSB_LSB_transmission */
  94
  95   uint32_t TIMode;             /*!< Specifies if the TI mode is enabled or not.
  96                                     This parameter can be a value of @ref SPI_TI_mode */
  97
  98   uint32_t CRCCalculation;     /*!< Specifies if the CRC calculation is enabled or not.
  99                                     This parameter can be a value of @ref SPI_CRC_Calculation */
 100
 101   uint32_t CRCPolynomial;      /*!< Specifies the polynomial used for the CRC calculation.
 102                                     This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */
 103
 104 }SPI_InitTypeDef;
 105
 106 /**
 107   * @brief  HAL SPI State structure definition
 108   */
 109 typedef enum
 110 {
 111   HAL_SPI_STATE_RESET      = 0x00,  /*!< SPI not yet initialized or disabled                */
 112   HAL_SPI_STATE_READY      = 0x01,  /*!< SPI initialized and ready for use                  */
 113   HAL_SPI_STATE_BUSY       = 0x02,  /*!< SPI process is ongoing                             */
 114   HAL_SPI_STATE_BUSY_TX    = 0x12,  /*!< Data Transmission process is ongoing               */
 115   HAL_SPI_STATE_BUSY_RX    = 0x22,  /*!< Data Reception process is ongoing                  */
 116   HAL_SPI_STATE_BUSY_TX_RX = 0x32,  /*!< Data Transmission and Reception process is ongoing */
 117   HAL_SPI_STATE_ERROR      = 0x03   /*!< SPI error state                                    */
 118
 119 }HAL_SPI_StateTypeDef;
 120
 121 /**
 122   * @brief  HAL SPI Error Code structure definition
 123   */
 124 typedef enum
 125 {
 126   HAL_SPI_ERROR_NONE      = 0x00,    /*!< No error             */
 127   HAL_SPI_ERROR_MODF      = 0x01,    /*!< MODF error           */
 128   HAL_SPI_ERROR_CRC       = 0x02,    /*!< CRC error            */
 129   HAL_SPI_ERROR_OVR       = 0x04,    /*!< OVR error            */
 130   HAL_SPI_ERROR_FRE       = 0x08,    /*!< FRE error            */
 131   HAL_SPI_ERROR_DMA       = 0x10,    /*!< DMA transfer error   */
 132   HAL_SPI_ERROR_FLAG      = 0x20     /*!< Flag: RXNE,TXE, BSY  */
 133
 134 }HAL_SPI_ErrorTypeDef;
 135
 136 /**
 137   * @brief  SPI handle Structure definition
 138   */
 139 typedef struct __SPI_HandleTypeDef
 140 {
 141   SPI_TypeDef                *Instance;    /* SPI registers base address */
 142
 143   SPI_InitTypeDef            Init;         /* SPI communication parameters */
 144
 145   uint8_t                    *pTxBuffPtr;  /* Pointer to SPI Tx transfer Buffer */
 146
 147   uint16_t                   TxXferSize;   /* SPI Tx transfer size */
 148
 149   uint16_t                   TxXferCount;  /* SPI Tx Transfer Counter */
 150
 151   uint8_t                    *pRxBuffPtr;  /* Pointer to SPI Rx transfer Buffer */
 152
 153   uint16_t                   RxXferSize;   /* SPI Rx transfer size */
 154
 155   uint16_t                   RxXferCount;  /* SPI Rx Transfer Counter */
 156
 157   DMA_HandleTypeDef          *hdmatx;      /* SPI Tx DMA handle parameters */
 158
 159   DMA_HandleTypeDef          *hdmarx;      /* SPI Rx DMA handle parameters */
 160
 161   void                       (*RxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Rx ISR */
 162
 163   void                       (*TxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Tx ISR */
 164
 165   HAL_LockTypeDef            Lock;         /* SPI locking object */
 166
 167   __IO HAL_SPI_StateTypeDef  State;        /* SPI communication state */
 168
 169   __IO HAL_SPI_ErrorTypeDef  ErrorCode;         /* SPI Error code */
 170
 171 }SPI_HandleTypeDef;
 172 /**
 173   * @}
 174   */
 175
 176
 177 /* Exported constants --------------------------------------------------------*/
 178
 179 /** @defgroup SPI_Exported_Constants SPI Exported Constants
 180   * @{
 181   */
 182
 183 /** @defgroup SPI_mode SPI mode
 184   * @{
 185   */
 186 #define SPI_MODE_SLAVE                  ((uint32_t)0x00000000)
 187 #define SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)
 188
 189 #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
 190                            ((MODE) == SPI_MODE_MASTER))
 191 /**
 192   * @}
 193   */
 194
 195 /** @defgroup SPI_Direction_mode SPI Direction mode
 196   * @{
 197   */
 198 #define SPI_DIRECTION_2LINES             ((uint32_t)0x00000000)
 199 #define SPI_DIRECTION_2LINES_RXONLY      SPI_CR1_RXONLY
 200 #define SPI_DIRECTION_1LINE              SPI_CR1_BIDIMODE
 201
 202 #define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_DIRECTION_2LINES)        || \
 203                                      ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
 204                                      ((MODE) == SPI_DIRECTION_1LINE))
 205
 206 #define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES)  || \
 207                                                 ((MODE) == SPI_DIRECTION_1LINE))
 208
 209 #define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
 210
 211 /**
 212   * @}
 213   */
 214
 215 /** @defgroup SPI_data_size SPI data size
 216   * @{
 217   */
 218 #define SPI_DATASIZE_8BIT               ((uint32_t)0x00000000)
 219 #define SPI_DATASIZE_16BIT              SPI_CR1_DFF
 220
 221 #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
 222                                    ((DATASIZE) == SPI_DATASIZE_8BIT))
 223 /**
 224   * @}
 225   */
 226
 227 /** @defgroup SPI_Clock_Polarity SPI Clock Polarity
 228   * @{
 229   */
 230 #define SPI_POLARITY_LOW                ((uint32_t)0x00000000)
 231 #define SPI_POLARITY_HIGH               SPI_CR1_CPOL
 232
 233 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
 234                            ((CPOL) == SPI_POLARITY_HIGH))
 235 /**
 236   * @}
 237   */
 238
 239 /** @defgroup SPI_Clock_Phase SPI Clock Phase
 240   * @{
 241   */
 242 #define SPI_PHASE_1EDGE                 ((uint32_t)0x00000000)
 243 #define SPI_PHASE_2EDGE                 SPI_CR1_CPHA
 244
 245 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
 246                            ((CPHA) == SPI_PHASE_2EDGE))
 247 /**
 248   * @}
 249   */
 250
 251 /** @defgroup SPI_Slave_Select_management SPI Slave Select management
 252   * @{
 253   */
 254 #define SPI_NSS_SOFT                    SPI_CR1_SSM
 255 #define SPI_NSS_HARD_INPUT              ((uint32_t)0x00000000)
 256 #define SPI_NSS_HARD_OUTPUT             ((uint32_t)(SPI_CR2_SSOE << 16))
 257
 258 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT)       || \
 259                          ((NSS) == SPI_NSS_HARD_INPUT) || \
 260                          ((NSS) == SPI_NSS_HARD_OUTPUT))
 261 /**
 262   * @}
 263   */
 264
 265 /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
 266   * @{
 267   */
 268 #define SPI_BAUDRATEPRESCALER_2         ((uint32_t)0x00000000)
 269 #define SPI_BAUDRATEPRESCALER_4         ((uint32_t)SPI_CR1_BR_0)
 270 #define SPI_BAUDRATEPRESCALER_8         ((uint32_t)SPI_CR1_BR_1)
 271 #define SPI_BAUDRATEPRESCALER_16        ((uint32_t)SPI_CR1_BR_1 | SPI_CR1_BR_0)
 272 #define SPI_BAUDRATEPRESCALER_32        ((uint32_t)SPI_CR1_BR_2)
 273 #define SPI_BAUDRATEPRESCALER_64        ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_0)
 274 #define SPI_BAUDRATEPRESCALER_128       ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_1)
 275 #define SPI_BAUDRATEPRESCALER_256       ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
 276
 277 #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2)   || \
 278                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_4)   || \
 279                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_8)   || \
 280                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_16)  || \
 281                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_32)  || \
 282                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_64)  || \
 283                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
 284                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
 285 /**
 286   * @}
 287   */
 288
 289 /** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB transmission
 290   * @{
 291   */
 292 #define SPI_FIRSTBIT_MSB                ((uint32_t)0x00000000)
 293 #define SPI_FIRSTBIT_LSB                SPI_CR1_LSBFIRST
 294
 295 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
 296                                ((BIT) == SPI_FIRSTBIT_LSB))
 297 /**
 298   * @}
 299   */
 300
 301 /** @defgroup SPI_CRC_Calculation SPI CRC Calculation
 302   * @{
 303   */
 304 #define SPI_CRCCALCULATION_DISABLED     ((uint32_t)0x00000000)
 305 #define SPI_CRCCALCULATION_ENABLED      SPI_CR1_CRCEN
 306
 307 #define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLED) || \
 308                                              ((CALCULATION) == SPI_CRCCALCULATION_ENABLED))
 309
 310 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF))
 311 /**
 312   * @}
 313   */
 314
 315 /** @defgroup SPI_Interrupt_configuration_definition SPI Interrupt configuration definition
 316   * @{
 317   */
 318 #define SPI_IT_TXE                      SPI_CR2_TXEIE
 319 #define SPI_IT_RXNE                     SPI_CR2_RXNEIE
 320 #define SPI_IT_ERR                      SPI_CR2_ERRIE
 321 /**
 322   * @}
 323   */
 324
 325 /** @defgroup SPI_Flag_definition SPI Flag definition
 326   * @{
 327   */
 328 #define SPI_FLAG_RXNE                   SPI_SR_RXNE
 329 #define SPI_FLAG_TXE                    SPI_SR_TXE
 330 #define SPI_FLAG_CRCERR                 SPI_SR_CRCERR
 331 #define SPI_FLAG_MODF                   SPI_SR_MODF
 332 #define SPI_FLAG_OVR                    SPI_SR_OVR
 333 #define SPI_FLAG_BSY                    SPI_SR_BSY
 334 #define SPI_FLAG_FRE                    SPI_SR_FRE
 335
 336 /**
 337   * @}
 338   */
 339
 340 /**
 341   * @}
 342   */
 343
 344
 345 /* Exported macro ------------------------------------------------------------*/
 346 /** @defgroup SPI_Exported_Macros SPI Exported Macros
 347   * @{
 348   */
 349
 350 /** @brief Reset SPI handle state
 351   * @param  __HANDLE__: specifies the SPI handle.
 352   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
 353   * @retval None
 354   */
 355 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
 356
 357 /** @brief  Enable or disable the specified SPI interrupts.
 358   * @param  __HANDLE__: specifies the SPI handle.
 359   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
 360   * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
 361   *         This parameter can be one of the following values:
 362   *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
 363   *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
 364   *            @arg SPI_IT_ERR: Error interrupt enable
 365   * @retval None
 366   */
 367 #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
 368 #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
 369
 370 /** @brief  Check if the specified SPI interrupt source is enabled or disabled.
 371   * @param  __HANDLE__: specifies the SPI handle.
 372   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
 373   * @param  __INTERRUPT__: specifies the SPI interrupt source to check.
 374   *          This parameter can be one of the following values:
 375   *             @arg SPI_IT_TXE: Tx buffer empty interrupt enable
 376   *             @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
 377   *             @arg SPI_IT_ERR: Error interrupt enable
 378   * @retval The new state of __IT__ (TRUE or FALSE).
 379   */
 380 #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
 381
 382 /** @brief  Check whether the specified SPI flag is set or not.
 383   * @param  __HANDLE__: specifies the SPI handle.
 384   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
 385   * @param  __FLAG__: specifies the flag to check.
 386   *         This parameter can be one of the following values:
 387   *            @arg SPI_FLAG_RXNE: Receive buffer not empty flag
 388   *            @arg SPI_FLAG_TXE: Transmit buffer empty flag
 389   *            @arg SPI_FLAG_CRCERR: CRC error flag
 390   *            @arg SPI_FLAG_MODF: Mode fault flag
 391   *            @arg SPI_FLAG_OVR: Overrun flag
 392   *            @arg SPI_FLAG_BSY: Busy flag
 393   *            @arg SPI_FLAG_FRE: Frame format error flag
 394   * @retval The new state of __FLAG__ (TRUE or FALSE).
 395   */
 396 #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
 397
 398 /** @brief  Clear the SPI CRCERR pending flag.
 399   * @param  __HANDLE__: specifies the SPI handle.
 400   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
 401   * @retval None
 402   */
 403 #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = ~(SPI_FLAG_CRCERR))
 404
 405 /** @brief  Clear the SPI MODF pending flag.
 406   * @param  __HANDLE__: specifies the SPI handle.
 407   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
 408   * @retval None
 409   */
 410 #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\
 411                                                 CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE);}while(0)
 412
 413 /** @brief  Clear the SPI OVR pending flag.
 414   * @param  __HANDLE__: specifies the SPI handle.
 415   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
 416   * @retval None
 417   */
 418 #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) do{(__HANDLE__)->Instance->DR;\
 419                                                (__HANDLE__)->Instance->SR;}while(0)
 420
 421 /** @brief  Clear the SPI FRE pending flag.
 422   * @param  __HANDLE__: specifies the SPI handle.
 423   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
 424   * @retval None
 425   */
 426 #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR)
 427
 428 /** @brief  Enables the SPI.
 429   * @param  __HANDLE__: specifies the SPI Handle.
 430   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
 431   * @retval None
 432   */
 433 #define __HAL_SPI_ENABLE(__HANDLE__)  SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
 434
 435 /** @brief  Disables the SPI.
 436   * @param  __HANDLE__: specifies the SPI Handle.
 437   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
 438   * @retval None
 439   */
 440 #define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
 441 /**
 442   * @}
 443   */
 444
 445
 446 /* Private macro ------------------------------------------------------------*/
 447 /** @defgroup SPI_Private_Macros SPI Private Macros
 448   * @{
 449   */
 450
 451 /** @brief  Sets the SPI transmit-only mode.
 452   * @param  __HANDLE__: specifies the SPI Handle.
 453   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
 454   * @retval None
 455   */
 456 #define SPI_1LINE_TX(__HANDLE__)  SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
 457
 458 /** @brief  Sets the SPI receive-only mode.
 459   * @param  __HANDLE__: specifies the SPI Handle.
 460   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
 461   * @retval None
 462   */
 463 #define SPI_1LINE_RX(__HANDLE__)  CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
 464
 465 /** @brief  Resets the CRC calculation of the SPI.
 466   * @param  __HANDLE__: specifies the SPI Handle.
 467   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
 468   * @retval None
 469   */
 470 #define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\
 471                                              SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0)
 472 /**
 473   * @}
 474   */
 475
 476 /* Include SPI HAL Extension module */
 477 #include "stm32l1xx_hal_spi_ex.h"
 478
 479 /* Exported functions --------------------------------------------------------*/
 480 /** @addtogroup SPI_Exported_Functions
 481   * @{
 482   */
 483
 484 /* Initialization/de-initialization functions  **********************************/
 485 /** @addtogroup SPI_Exported_Functions_Group1
 486   * @{
 487   */
 488 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
 489 HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
 490 void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
 491 void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
 492 /**
 493   * @}
 494   */
 495
 496 /* I/O operation functions  *****************************************************/
 497 /** @addtogroup SPI_Exported_Functions_Group2
 498   * @{
 499   */
 500 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
 501 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
 502 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
 503 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
 504 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
 505 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
 506 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
 507 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
 508 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
 509 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
 510 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
 511 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
 512
 513 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
 514 void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
 515 void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
 516 void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
 517 void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
 518 void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
 519 void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
 520 void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
 521 /**
 522   * @}
 523   */
 524
 525
 526 /* Peripheral State and Control functions  **************************************/
 527 /** @addtogroup SPI_Exported_Functions_Group3
 528   * @{
 529   */
 530 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
 531 HAL_SPI_ErrorTypeDef HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
 532
 533 /**
 534   * @}
 535   */
 536
 537 /**
 538   * @}
 539   */
 540
 541
 542 /**
 543   * @}
 544   */
 545
 546 /**
 547   * @}
 548   */
 549
 550 #ifdef __cplusplus
 551 }
 552 #endif
 553
 554 #endif /* __STM32L1xx_HAL_SPI_H */
 555
 556 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/