tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_sram.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32l1xx_hal_sram.h
   4   * @author  MCD Application Team
   5   * @version V1.0.0
   6   * @date    5-September-2014
   7   * @brief   Header file of SRAM HAL module.
   8   ******************************************************************************
   9   * @attention
  10   *
  11   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
  12   *
  13   * Redistribution and use in source and binary forms, with or without modification,
  14   * are permitted provided that the following conditions are met:
  15   *   1. Redistributions of source code must retain the above copyright notice,
  16   *      this list of conditions and the following disclaimer.
  17   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18   *      this list of conditions and the following disclaimer in the documentation
  19   *      and/or other materials provided with the distribution.
  20   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21   *      may be used to endorse or promote products derived from this software
  22   *      without specific prior written permission.
  23   *
  24   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34   *
  35   ******************************************************************************
  36   */
  37
  38 /* Define to prevent recursive inclusion -------------------------------------*/
  39 #ifndef __STM32L1xx_HAL_SRAM_H
  40 #define __STM32L1xx_HAL_SRAM_H
  41
  42 #ifdef __cplusplus
  43  extern "C" {
  44 #endif
  45
  46 /* Includes ------------------------------------------------------------------*/
  47 #include "stm32l1xx_ll_fsmc.h"
  48
  49 /** @addtogroup STM32L1xx_HAL_Driver
  50   * @{
  51   */
  52
  53 /** @addtogroup SRAM
  54   * @{
  55   */
  56
  57 #if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
  58
  59 /* Exported typedef ----------------------------------------------------------*/
  60
  61 /** @defgroup SRAM_Exported_typedef SRAM Exported typedef
  62   * @{
  63   */
  64
  65 /**
  66   * @brief  HAL SRAM State structures definition
  67   */
  68 typedef enum
  69 {
  70   HAL_SRAM_STATE_RESET     = 0x00,  /*!< SRAM not yet initialized or disabled           */
  71   HAL_SRAM_STATE_READY     = 0x01,  /*!< SRAM initialized and ready for use             */
  72   HAL_SRAM_STATE_BUSY      = 0x02,  /*!< SRAM internal process is ongoing               */
  73   HAL_SRAM_STATE_ERROR     = 0x03,  /*!< SRAM error state                               */
  74   HAL_SRAM_STATE_PROTECTED = 0x04   /*!< SRAM peripheral NORSRAM device write protected */
  75
  76 }HAL_SRAM_StateTypeDef;
  77
  78 /**
  79   * @brief  SRAM handle Structure definition
  80   */
  81 typedef struct
  82 {
  83   FSMC_NORSRAM_TYPEDEF           *Instance;  /*!< Register base address                        */
  84
  85   FSMC_NORSRAM_EXTENDED_TYPEDEF  *Extended;  /*!< Extended mode register base address          */
  86
  87   FSMC_NORSRAM_InitTypeDef       Init;       /*!< SRAM device control configuration parameters */
  88
  89   HAL_LockTypeDef               Lock;       /*!< SRAM locking object                          */
  90
  91   __IO HAL_SRAM_StateTypeDef    State;      /*!< SRAM device access state                     */
  92
  93   DMA_HandleTypeDef             *hdma;      /*!< Pointer DMA handler                          */
  94
  95 }SRAM_HandleTypeDef;
  96
  97 /**
  98   * @}
  99   */
 100
 101 /* Exported constants --------------------------------------------------------*/
 102 /* Exported macro ------------------------------------------------------------*/
 103
 104 /** @defgroup SRAM_Exported_macro SRAM Exported macro
 105   * @{
 106   */
 107
 108 /** @brief Reset SRAM handle state
 109   * @param  __HANDLE__: SRAM handle
 110   * @retval None
 111   */
 112 #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
 113
 114 /**
 115   * @}
 116   */
 117
 118 /* Exported functions --------------------------------------------------------*/
 119
 120 /** @addtogroup SRAM_Exported_Functions
 121  *  @{
 122  */
 123
 124 /** @addtogroup SRAM_Exported_Functions_Group1
 125  *  @{
 126  */
 127
 128 /* Initialization/de-initialization functions  **********************************/
 129 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming);
 130 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
 131 void              HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
 132 void              HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
 133
 134 void              HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
 135 void              HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
 136
 137 /**
 138   * @}
 139   */
 140
 141 /** @addtogroup SRAM_Exported_Functions_Group2
 142  *  @{
 143  */
 144
 145 /* I/O operation functions  *****************************************************/
 146 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
 147 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
 148 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
 149 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
 150 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
 151 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
 152 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
 153 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
 154
 155 /**
 156   * @}
 157   */
 158
 159 /** @addtogroup SRAM_Exported_Functions_Group3
 160  *  @{
 161  */
 162
 163 /* SRAM Control functions  ******************************************************/
 164 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
 165 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
 166
 167 /**
 168   * @}
 169   */
 170
 171 /** @addtogroup SRAM_Exported_Functions_Group4
 172  *  @{
 173  */
 174
 175 /* SRAM State functions *********************************************************/
 176 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
 177
 178 /**
 179   * @}
 180   */
 181
 182 /**
 183   * @}
 184   */
 185
 186 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
 187
 188 /**
 189   * @}
 190   */
 191
 192 /**
 193   * @}
 194   */
 195
 196 #ifdef __cplusplus
 197 }
 198 #endif
 199
 200 #endif /* __STM32L1xx_HAL_SRAM_H */
 201
 202 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/