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[tmk_keyboard.git] / tool / mbed / mbed-sdk / libraries / mbed / targets / cmsis / TARGET_STM / TARGET_STM32L1 / stm32l1xx_hal_tim.h
1 /**
2 ******************************************************************************
3 * @file stm32l1xx_hal_tim.h
4 * @author MCD Application Team
5 * @version V1.0.0
6 * @date 5-September-2014
7 * @brief Header file of TIM HAL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32L1xx_HAL_TIM_H
40 #define __STM32L1xx_HAL_TIM_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32l1xx_hal_def.h"
48
49 /** @addtogroup STM32L1xx_HAL_Driver
50 * @{
51 */
52
53 /** @addtogroup TIM
54 * @{
55 */
56
57 /* Exported types ------------------------------------------------------------*/
58 /** @defgroup TIM_Exported_Types TIM Exported Types
59 * @{
60 */
61 /**
62 * @brief TIM Time base Configuration Structure definition
63 */
64 typedef struct
65 {
66 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
67 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
68
69 uint32_t CounterMode; /*!< Specifies the counter mode.
70 This parameter can be a value of @ref TIM_Counter_Mode */
71
72 uint32_t Period; /*!< Specifies the period value to be loaded into the active
73 Auto-Reload Register at the next update event.
74 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
75
76 uint32_t ClockDivision; /*!< Specifies the clock division.
77 This parameter can be a value of @ref TIM_ClockDivision */
78
79 } TIM_Base_InitTypeDef;
80
81 /**
82 * @brief TIM Output Compare Configuration Structure definition
83 */
84 typedef struct
85 {
86 uint32_t OCMode; /*!< Specifies the TIM mode.
87 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
88
89 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
90 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
91
92 uint32_t OCPolarity; /*!< Specifies the output polarity.
93 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
94
95 uint32_t OCFastMode; /*!< Specifies the Fast mode state.
96 This parameter can be a value of @ref TIM_Output_Fast_State
97 @note This parameter is valid only in PWM1 and PWM2 mode. */
98
99 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
100 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
101 @note This parameter is valid only for TIM1 and TIM8. */
102 } TIM_OC_InitTypeDef;
103
104 /**
105 * @brief TIM One Pulse Mode Configuration Structure definition
106 */
107 typedef struct
108 {
109 uint32_t OCMode; /*!< Specifies the TIM mode.
110 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
111
112 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
113 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
114
115 uint32_t OCPolarity; /*!< Specifies the output polarity.
116 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
117
118 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
119 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
120 @note This parameter is valid only for TIM1 and TIM8. */
121
122 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
123 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
124
125 uint32_t ICSelection; /*!< Specifies the input.
126 This parameter can be a value of @ref TIM_Input_Capture_Selection */
127
128 uint32_t ICFilter; /*!< Specifies the input capture filter.
129 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
130 } TIM_OnePulse_InitTypeDef;
131
132
133 /**
134 * @brief TIM Input Capture Configuration Structure definition
135 */
136 typedef struct
137 {
138 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
139 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
140
141 uint32_t ICSelection; /*!< Specifies the input.
142 This parameter can be a value of @ref TIM_Input_Capture_Selection */
143
144 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
145 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
146
147 uint32_t ICFilter; /*!< Specifies the input capture filter.
148 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
149 } TIM_IC_InitTypeDef;
150
151 /**
152 * @brief TIM Encoder Configuration Structure definition
153 */
154 typedef struct
155 {
156 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
157 This parameter can be a value of @ref TIM_Encoder_Mode */
158
159 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
160 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
161
162 uint32_t IC1Selection; /*!< Specifies the input.
163 This parameter can be a value of @ref TIM_Input_Capture_Selection */
164
165 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
166 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
167
168 uint32_t IC1Filter; /*!< Specifies the input capture filter.
169 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
170
171 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
172 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
173
174 uint32_t IC2Selection; /*!< Specifies the input.
175 This parameter can be a value of @ref TIM_Input_Capture_Selection */
176
177 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
178 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
179
180 uint32_t IC2Filter; /*!< Specifies the input capture filter.
181 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
182 } TIM_Encoder_InitTypeDef;
183
184
185 /**
186 * @brief Clock Configuration Handle Structure definition
187 */
188 typedef struct
189 {
190 uint32_t ClockSource; /*!< TIM clock sources
191 This parameter can be a value of @ref TIM_Clock_Source */
192 uint32_t ClockPolarity; /*!< TIM clock polarity
193 This parameter can be a value of @ref TIM_Clock_Polarity */
194 uint32_t ClockPrescaler; /*!< TIM clock prescaler
195 This parameter can be a value of @ref TIM_Clock_Prescaler */
196 uint32_t ClockFilter; /*!< TIM clock filter
197 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
198 }TIM_ClockConfigTypeDef;
199
200 /**
201 * @brief Clear Input Configuration Handle Structure definition
202 */
203 typedef struct
204 {
205 uint32_t ClearInputState; /*!< TIM clear Input state
206 This parameter can be ENABLE or DISABLE */
207 uint32_t ClearInputSource; /*!< TIM clear Input sources
208 This parameter can be a value of @ref TIM_ClearInput_Source */
209 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
210 This parameter can be a value of @ref TIM_ClearInput_Polarity */
211 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
212 This parameter can be a value of @ref TIM_ClearInput_Prescaler */
213 uint32_t ClearInputFilter; /*!< TIM Clear Input filter
214 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
215 }TIM_ClearInputConfigTypeDef;
216
217 /**
218 * @brief TIM Slave configuration Structure definition
219 */
220 typedef struct {
221 uint32_t SlaveMode; /*!< Slave mode selection
222 This parameter can be a value of @ref TIM_Slave_Mode */
223 uint32_t InputTrigger; /*!< Input Trigger source
224 This parameter can be a value of @ref TIM_Trigger_Selection */
225 uint32_t TriggerPolarity; /*!< Input Trigger polarity
226 This parameter can be a value of @ref TIM_Trigger_Polarity */
227 uint32_t TriggerPrescaler; /*!< Input trigger prescaler
228 This parameter can be a value of @ref TIM_Trigger_Prescaler */
229 uint32_t TriggerFilter; /*!< Input trigger filter
230 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
231
232 }TIM_SlaveConfigTypeDef;
233
234 /**
235 * @brief HAL State structures definition
236 */
237 typedef enum
238 {
239 HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */
240 HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
241 HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
242 HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */
243 HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
244 }HAL_TIM_StateTypeDef;
245
246 /**
247 * @brief HAL Active channel structures definition
248 */
249 typedef enum
250 {
251 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */
252 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */
253 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */
254 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */
255 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */
256 }HAL_TIM_ActiveChannel;
257
258 /**
259 * @brief TIM Time Base Handle Structure definition
260 */
261 typedef struct
262 {
263 TIM_TypeDef *Instance; /*!< Register base address */
264 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
265 HAL_TIM_ActiveChannel Channel; /*!< Active channel */
266 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
267 This array is accessed by a @ref DMA_Handle_index */
268 HAL_LockTypeDef Lock; /*!< Locking object */
269 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
270 }TIM_HandleTypeDef;
271
272 /**
273 * @}
274 */
275
276 /* Exported constants --------------------------------------------------------*/
277 /** @defgroup TIM_Exported_Constants TIM Exported Constants
278 * @{
279 */
280
281 /** @defgroup TIM_Input_Channel_Polarity TIM_Input_Channel_Polarity
282 * @{
283 */
284 #define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /*!< Polarity for TIx source */
285 #define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */
286 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
287 /**
288 * @}
289 */
290
291 /** @defgroup TIM_ETR_Polarity TIM_ETR_Polarity
292 * @{
293 */
294 #define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */
295 #define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */
296 /**
297 * @}
298 */
299
300 /** @defgroup TIM_ETR_Prescaler TIM_ETR_Prescaler
301 * @{
302 */
303 #define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /*!< No prescaler is used */
304 #define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */
305 #define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */
306 #define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */
307 /**
308 * @}
309 */
310
311 /** @defgroup TIM_Counter_Mode TIM_Counter_Mode
312 * @{
313 */
314 #define TIM_COUNTERMODE_UP ((uint32_t)0x0000)
315 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
316 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
317 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
318 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
319
320 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \
321 ((MODE) == TIM_COUNTERMODE_DOWN) || \
322 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \
323 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \
324 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
325 /**
326 * @}
327 */
328
329 /** @defgroup TIM_ClockDivision TIM_ClockDivision
330 * @{
331 */
332 #define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
333 #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
334 #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
335
336 #define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \
337 ((DIV) == TIM_CLOCKDIVISION_DIV2) || \
338 ((DIV) == TIM_CLOCKDIVISION_DIV4))
339 /**
340 * @}
341 */
342
343 /** @defgroup TIM_Output_Compare_and_PWM_modes TIM_Output_Compare_and_PWM_modes
344 * @{
345 */
346 #define TIM_OCMODE_TIMING ((uint32_t)0x0000)
347 #define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
348 #define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
349 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
350 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
351 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
352 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
353 #define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
354
355 #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
356 ((MODE) == TIM_OCMODE_PWM2))
357
358 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
359 ((MODE) == TIM_OCMODE_ACTIVE) || \
360 ((MODE) == TIM_OCMODE_INACTIVE) || \
361 ((MODE) == TIM_OCMODE_TOGGLE) || \
362 ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
363 ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
364 /**
365 * @}
366 */
367
368 /** @defgroup TIM_Output_Compare_State TIM_Output_Compare_State
369 * @{
370 */
371 #define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
372 #define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
373
374 #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \
375 ((STATE) == TIM_OUTPUTSTATE_ENABLE))
376 /**
377 * @}
378 */
379
380 /** @defgroup TIM_Output_Fast_State TIM_Output_Fast_State
381 * @{
382 */
383 #define TIM_OCFAST_DISABLE ((uint32_t)0x0000)
384 #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
385
386 #define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \
387 ((STATE) == TIM_OCFAST_ENABLE))
388 /**
389 * @}
390 */
391
392 /** @defgroup TIM_Output_Compare_Polarity TIM_Output_Compare_Polarity
393 * @{
394 */
395 #define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
396 #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
397
398 #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \
399 ((POLARITY) == TIM_OCPOLARITY_LOW))
400 /**
401 * @}
402 */
403
404 /** @defgroup TIM_Output_Compare_Idle_State TIM_Output_Compare_Idle_State
405 * @{
406 */
407 #define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
408 #define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)
409 #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \
410 ((STATE) == TIM_OCIDLESTATE_RESET))
411 /**
412 * @}
413 */
414
415 /** @defgroup TIM_Channel TIM_Channel
416 * @{
417 */
418 #define TIM_CHANNEL_1 ((uint32_t)0x0000)
419 #define TIM_CHANNEL_2 ((uint32_t)0x0004)
420 #define TIM_CHANNEL_3 ((uint32_t)0x0008)
421 #define TIM_CHANNEL_4 ((uint32_t)0x000C)
422 #define TIM_CHANNEL_ALL ((uint32_t)0x0018)
423
424 #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
425 ((CHANNEL) == TIM_CHANNEL_2) || \
426 ((CHANNEL) == TIM_CHANNEL_3) || \
427 ((CHANNEL) == TIM_CHANNEL_4) || \
428 ((CHANNEL) == TIM_CHANNEL_ALL))
429
430 #define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
431 ((CHANNEL) == TIM_CHANNEL_2))
432
433 #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
434 ((CHANNEL) == TIM_CHANNEL_2))
435 /**
436 * @}
437 */
438
439 /** @defgroup TIM_Input_Capture_Polarity TIM_Input_Capture_Polarity
440 * @{
441 */
442 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
443 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
444 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
445
446 #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \
447 ((POLARITY) == TIM_ICPOLARITY_FALLING) || \
448 ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
449 /**
450 * @}
451 */
452
453 /** @defgroup TIM_Input_Capture_Selection TIM_Input_Capture_Selection
454 * @{
455 */
456 #define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
457 connected to IC1, IC2, IC3 or IC4, respectively */
458 #define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
459 connected to IC2, IC1, IC4 or IC3, respectively */
460 #define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
461
462 #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \
463 ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
464 ((SELECTION) == TIM_ICSELECTION_TRC))
465 /**
466 * @}
467 */
468
469 /** @defgroup TIM_Input_Capture_Prescaler TIM_Input_Capture_Prescaler
470 * @{
471 */
472 #define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */
473 #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */
474 #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */
475 #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */
476
477 #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
478 ((PRESCALER) == TIM_ICPSC_DIV2) || \
479 ((PRESCALER) == TIM_ICPSC_DIV4) || \
480 ((PRESCALER) == TIM_ICPSC_DIV8))
481 /**
482 * @}
483 */
484
485 /** @defgroup TIM_One_Pulse_Mode TIM_One_Pulse_Mode
486 * @{
487 */
488 #define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
489 #define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
490
491 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \
492 ((MODE) == TIM_OPMODE_REPETITIVE))
493 /**
494 * @}
495 */
496
497 /** @defgroup TIM_Encoder_Mode TIM_Encoder_Mode
498 * @{
499 */
500 #define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
501 #define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
502 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
503
504 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \
505 ((MODE) == TIM_ENCODERMODE_TI2) || \
506 ((MODE) == TIM_ENCODERMODE_TI12))
507 /**
508 * @}
509 */
510
511 /** @defgroup TIM_Interrupt_definition TIM_Interrupt_definition
512 * @{
513 */
514 #define TIM_IT_UPDATE (TIM_DIER_UIE)
515 #define TIM_IT_CC1 (TIM_DIER_CC1IE)
516 #define TIM_IT_CC2 (TIM_DIER_CC2IE)
517 #define TIM_IT_CC3 (TIM_DIER_CC3IE)
518 #define TIM_IT_CC4 (TIM_DIER_CC4IE)
519 #define TIM_IT_TRIGGER (TIM_DIER_TIE)
520
521 /**
522 * @}
523 */
524
525 /** @defgroup TIM_DMA_sources TIM_DMA_sources
526 * @{
527 */
528 #define TIM_DMA_UPDATE (TIM_DIER_UDE)
529 #define TIM_DMA_CC1 (TIM_DIER_CC1DE)
530 #define TIM_DMA_CC2 (TIM_DIER_CC2DE)
531 #define TIM_DMA_CC3 (TIM_DIER_CC3DE)
532 #define TIM_DMA_CC4 (TIM_DIER_CC4DE)
533 #define TIM_DMA_TRIGGER (TIM_DIER_TDE)
534
535 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000))
536 /**
537 * @}
538 */
539
540 /** @defgroup TIM_Event_Source TIM_Event_Source
541 * @{
542 */
543 #define TIM_EventSource_Update TIM_EGR_UG
544 #define TIM_EventSource_CC1 TIM_EGR_CC1G
545 #define TIM_EventSource_CC2 TIM_EGR_CC2G
546 #define TIM_EventSource_CC3 TIM_EGR_CC3G
547 #define TIM_EventSource_CC4 TIM_EGR_CC4G
548 #define TIM_EventSource_Trigger TIM_EGR_TG
549
550 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000))
551 /**
552 * @}
553 */
554
555 /** @defgroup TIM_Flag_definition TIM_Flag_definition
556 * @{
557 */
558 #define TIM_FLAG_UPDATE (TIM_SR_UIF)
559 #define TIM_FLAG_CC1 (TIM_SR_CC1IF)
560 #define TIM_FLAG_CC2 (TIM_SR_CC2IF)
561 #define TIM_FLAG_CC3 (TIM_SR_CC3IF)
562 #define TIM_FLAG_CC4 (TIM_SR_CC4IF)
563 #define TIM_FLAG_TRIGGER (TIM_SR_TIF)
564 #define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
565 #define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
566 #define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
567 #define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
568
569 /**
570 * @}
571 */
572
573 /** @defgroup TIM_Clock_Source TIM_Clock_Source
574 * @{
575 */
576 #define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
577 #define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
578 #define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
579 #define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
580 #define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
581 #define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
582 #define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
583 #define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
584 #define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
585 #define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
586
587 #define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
588 ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
589 ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \
590 ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \
591 ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \
592 ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \
593 ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \
594 ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \
595 ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \
596 ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
597 /**
598 * @}
599 */
600
601 /** @defgroup TIM_Clock_Polarity TIM_Clock_Polarity
602 * @{
603 */
604 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
605 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
606 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
607 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
608 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
609
610 #define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \
611 ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \
612 ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \
613 ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \
614 ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
615 /**
616 * @}
617 */
618
619 /** @defgroup TIM_Clock_Prescaler TIM_Clock_Prescaler
620 * @{
621 */
622 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
623 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
624 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
625 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
626
627 #define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \
628 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \
629 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
630 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
631 /**
632 * @}
633 */
634
635 /** @defgroup TIM_Clock_Filter TIM_Clock_Filter
636 * @{
637 */
638 #define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
639 /**
640 * @}
641 */
642
643 /** @defgroup TIM_ClearInput_Source TIM_ClearInput_Source
644 * @{
645 */
646 #define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
647 #define TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002)
648 #define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
649
650 #define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_ETR) || \
651 ((SOURCE) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \
652 ((SOURCE) == TIM_CLEARINPUTSOURCE_NONE))
653 /**
654 * @}
655 */
656
657 /** @defgroup TIM_ClearInput_Polarity TIM_ClearInput_Polarity
658 * @{
659 */
660 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
661 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
662
663
664 #define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
665 ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
666 /**
667 * @}
668 */
669
670 /** @defgroup TIM_ClearInput_Prescaler TIM_ClearInput_Prescaler
671 * @{
672 */
673 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
674 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
675 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
676 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
677
678 #define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \
679 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \
680 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
681 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
682 /**
683 * @}
684 */
685
686 /** @defgroup TIM_ClearInput_Filter TIM_ClearInput_Filter
687 * @{
688 */
689 #define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
690 /**
691 * @}
692 */
693
694 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM_OSSR_Off_State_Selection_for_Run_mode_state
695 * @{
696 */
697 #define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
698 #define TIM_OSSR_DISABLE ((uint32_t)0x0000)
699
700 #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
701 ((STATE) == TIM_OSSR_DISABLE))
702 /**
703 * @}
704 */
705
706 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM_OSSI_Off_State_Selection_for_Idle_mode_state
707 * @{
708 */
709 #define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
710 #define TIM_OSSI_DISABLE ((uint32_t)0x0000)
711
712 #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \
713 ((STATE) == TIM_OSSI_DISABLE))
714 /**
715 * @}
716 */
717
718 /** @defgroup TIM_Lock_level TIM_Lock_level
719 * @{
720 */
721 #define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)
722 #define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
723 #define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
724 #define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
725
726 #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \
727 ((LEVEL) == TIM_LOCKLEVEL_1) || \
728 ((LEVEL) == TIM_LOCKLEVEL_2) || \
729 ((LEVEL) == TIM_LOCKLEVEL_3))
730 /**
731 * @}
732 */
733
734 /** @defgroup TIM_AOE_Bit_Set_Reset TIM_AOE_Bit_Set_Reset
735 * @{
736 */
737 #define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
738 #define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)
739
740 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
741 ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
742 /**
743 * @}
744 */
745
746 /** @defgroup TIM_Master_Mode_Selection TIM_Master_Mode_Selection
747 * @{
748 */
749 #define TIM_TRGO_RESET ((uint32_t)0x0000)
750 #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
751 #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
752 #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
753 #define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
754 #define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
755 #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
756 #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
757
758 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \
759 ((SOURCE) == TIM_TRGO_ENABLE) || \
760 ((SOURCE) == TIM_TRGO_UPDATE) || \
761 ((SOURCE) == TIM_TRGO_OC1) || \
762 ((SOURCE) == TIM_TRGO_OC1REF) || \
763 ((SOURCE) == TIM_TRGO_OC2REF) || \
764 ((SOURCE) == TIM_TRGO_OC3REF) || \
765 ((SOURCE) == TIM_TRGO_OC4REF))
766 /**
767 * @}
768 */
769
770 /** @defgroup TIM_Slave_Mode TIM_Slave_Mode
771 * @{
772 */
773 #define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
774 #define TIM_SLAVEMODE_RESET ((uint32_t)0x0004)
775 #define TIM_SLAVEMODE_GATED ((uint32_t)0x0005)
776 #define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006)
777 #define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007)
778
779 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
780 ((MODE) == TIM_SLAVEMODE_GATED) || \
781 ((MODE) == TIM_SLAVEMODE_RESET) || \
782 ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
783 ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
784 /**
785 * @}
786 */
787
788 /** @defgroup TIM_Master_Slave_Mode TIM_Master_Slave_Mode
789 * @{
790 */
791 #define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
792 #define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
793
794 #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
795 ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
796 /**
797 * @}
798 */
799
800 /** @defgroup TIM_Trigger_Selection TIM_Trigger_Selection
801 * @{
802 */
803 #define TIM_TS_ITR0 ((uint32_t)0x0000)
804 #define TIM_TS_ITR1 ((uint32_t)0x0010)
805 #define TIM_TS_ITR2 ((uint32_t)0x0020)
806 #define TIM_TS_ITR3 ((uint32_t)0x0030)
807 #define TIM_TS_TI1F_ED ((uint32_t)0x0040)
808 #define TIM_TS_TI1FP1 ((uint32_t)0x0050)
809 #define TIM_TS_TI2FP2 ((uint32_t)0x0060)
810 #define TIM_TS_ETRF ((uint32_t)0x0070)
811 #define TIM_TS_NONE ((uint32_t)0xFFFF)
812
813 #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
814 ((SELECTION) == TIM_TS_ITR1) || \
815 ((SELECTION) == TIM_TS_ITR2) || \
816 ((SELECTION) == TIM_TS_ITR3) || \
817 ((SELECTION) == TIM_TS_TI1F_ED) || \
818 ((SELECTION) == TIM_TS_TI1FP1) || \
819 ((SELECTION) == TIM_TS_TI2FP2) || \
820 ((SELECTION) == TIM_TS_ETRF))
821
822 #define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
823 ((SELECTION) == TIM_TS_ITR1) || \
824 ((SELECTION) == TIM_TS_ITR2) || \
825 ((SELECTION) == TIM_TS_ITR3))
826
827 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
828 ((SELECTION) == TIM_TS_ITR1) || \
829 ((SELECTION) == TIM_TS_ITR2) || \
830 ((SELECTION) == TIM_TS_ITR3) || \
831 ((SELECTION) == TIM_TS_NONE))
832 /**
833 * @}
834 */
835
836 /** @defgroup TIM_Trigger_Polarity TIM_Trigger_Polarity
837 * @{
838 */
839 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
840 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
841 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
842 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
843 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
844
845 #define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \
846 ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
847 ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \
848 ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \
849 ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
850 /**
851 * @}
852 */
853
854 /** @defgroup TIM_Trigger_Prescaler TIM_Trigger_Prescaler
855 * @{
856 */
857 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
858 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
859 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
860 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
861
862 #define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \
863 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \
864 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
865 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
866 /**
867 * @}
868 */
869
870 /** @defgroup TIM_Trigger_Filter TIM_Trigger_Filter
871 * @{
872 */
873 #define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF)
874 /**
875 * @}
876 */
877
878 /** @defgroup TIM_TI1_Selection TIM_TI1_Selection
879 * @{
880 */
881 #define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
882 #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
883
884 #define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \
885 ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
886 /**
887 * @}
888 */
889
890 /** @defgroup TIM_DMA_Base_address TIM_DMA_Base_address
891 * @{
892 */
893 #define TIM_DMABase_CR1 (0x00000000)
894 #define TIM_DMABase_CR2 (0x00000001)
895 #define TIM_DMABase_SMCR (0x00000002)
896 #define TIM_DMABase_DIER (0x00000003)
897 #define TIM_DMABase_SR (0x00000004)
898 #define TIM_DMABase_EGR (0x00000005)
899 #define TIM_DMABase_CCMR1 (0x00000006)
900 #define TIM_DMABase_CCMR2 (0x00000007)
901 #define TIM_DMABase_CCER (0x00000008)
902 #define TIM_DMABase_CNT (0x00000009)
903 #define TIM_DMABase_PSC (0x0000000A)
904 #define TIM_DMABase_ARR (0x0000000B)
905 #define TIM_DMABase_CCR1 (0x0000000D)
906 #define TIM_DMABase_CCR2 (0x0000000E)
907 #define TIM_DMABase_CCR3 (0x0000000F)
908 #define TIM_DMABase_CCR4 (0x00000010)
909 #define TIM_DMABase_DCR (0x00000012)
910 #define TIM_DMABase_OR (0x00000013)
911
912 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
913 ((BASE) == TIM_DMABase_CR2) || \
914 ((BASE) == TIM_DMABase_SMCR) || \
915 ((BASE) == TIM_DMABase_DIER) || \
916 ((BASE) == TIM_DMABase_SR) || \
917 ((BASE) == TIM_DMABase_EGR) || \
918 ((BASE) == TIM_DMABase_CCMR1) || \
919 ((BASE) == TIM_DMABase_CCMR2) || \
920 ((BASE) == TIM_DMABase_CCER) || \
921 ((BASE) == TIM_DMABase_CNT) || \
922 ((BASE) == TIM_DMABase_PSC) || \
923 ((BASE) == TIM_DMABase_ARR) || \
924 ((BASE) == TIM_DMABase_CCR1) || \
925 ((BASE) == TIM_DMABase_CCR2) || \
926 ((BASE) == TIM_DMABase_CCR3) || \
927 ((BASE) == TIM_DMABase_CCR4) || \
928 ((BASE) == TIM_DMABase_DCR) || \
929 ((BASE) == TIM_DMABase_OR))
930 /**
931 * @}
932 */
933
934 /** @defgroup TIM_DMA_Burst_Length TIM_DMA_Burst_Length
935 * @{
936 */
937 #define TIM_DMABurstLength_1Transfer (0x00000000)
938 #define TIM_DMABurstLength_2Transfers (0x00000100)
939 #define TIM_DMABurstLength_3Transfers (0x00000200)
940 #define TIM_DMABurstLength_4Transfers (0x00000300)
941 #define TIM_DMABurstLength_5Transfers (0x00000400)
942 #define TIM_DMABurstLength_6Transfers (0x00000500)
943 #define TIM_DMABurstLength_7Transfers (0x00000600)
944 #define TIM_DMABurstLength_8Transfers (0x00000700)
945 #define TIM_DMABurstLength_9Transfers (0x00000800)
946 #define TIM_DMABurstLength_10Transfers (0x00000900)
947 #define TIM_DMABurstLength_11Transfers (0x00000A00)
948 #define TIM_DMABurstLength_12Transfers (0x00000B00)
949 #define TIM_DMABurstLength_13Transfers (0x00000C00)
950 #define TIM_DMABurstLength_14Transfers (0x00000D00)
951 #define TIM_DMABurstLength_15Transfers (0x00000E00)
952 #define TIM_DMABurstLength_16Transfers (0x00000F00)
953 #define TIM_DMABurstLength_17Transfers (0x00001000)
954 #define TIM_DMABurstLength_18Transfers (0x00001100)
955
956 #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \
957 ((LENGTH) == TIM_DMABurstLength_2Transfers) || \
958 ((LENGTH) == TIM_DMABurstLength_3Transfers) || \
959 ((LENGTH) == TIM_DMABurstLength_4Transfers) || \
960 ((LENGTH) == TIM_DMABurstLength_5Transfers) || \
961 ((LENGTH) == TIM_DMABurstLength_6Transfers) || \
962 ((LENGTH) == TIM_DMABurstLength_7Transfers) || \
963 ((LENGTH) == TIM_DMABurstLength_8Transfers) || \
964 ((LENGTH) == TIM_DMABurstLength_9Transfers) || \
965 ((LENGTH) == TIM_DMABurstLength_10Transfers) || \
966 ((LENGTH) == TIM_DMABurstLength_11Transfers) || \
967 ((LENGTH) == TIM_DMABurstLength_12Transfers) || \
968 ((LENGTH) == TIM_DMABurstLength_13Transfers) || \
969 ((LENGTH) == TIM_DMABurstLength_14Transfers) || \
970 ((LENGTH) == TIM_DMABurstLength_15Transfers) || \
971 ((LENGTH) == TIM_DMABurstLength_16Transfers) || \
972 ((LENGTH) == TIM_DMABurstLength_17Transfers) || \
973 ((LENGTH) == TIM_DMABurstLength_18Transfers))
974 /**
975 * @}
976 */
977
978 /** @defgroup TIM_Input_Capture_Filer_Value TIM_Input_Capture_Filer_Value
979 * @{
980 */
981 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
982 /**
983 * @}
984 */
985
986 /** @defgroup DMA_Handle_index DMA_Handle_index
987 * @{
988 */
989 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */
990 #define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
991 #define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
992 #define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
993 #define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
994 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /*!< Index of the DMA handle used for Trigger DMA requests */
995 /**
996 * @}
997 */
998
999 /** @defgroup Channel_CC_State Channel_CC_State
1000 * @{
1001 */
1002 #define TIM_CCx_ENABLE ((uint32_t)0x0001)
1003 #define TIM_CCx_DISABLE ((uint32_t)0x0000)
1004 /**
1005 * @}
1006 */
1007
1008 /**
1009 * @}
1010 */
1011
1012 /* Private Constants -----------------------------------------------------------*/
1013 /** @defgroup TIM_Private_Constants TIM_Private_Constants
1014 * @{
1015 */
1016
1017 /* The counter of a timer instance is disabled only if all the CCx
1018 channels have been disabled */
1019 #define CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
1020 /**
1021 * @}
1022 */
1023
1024
1025
1026 /* Exported macros -----------------------------------------------------------*/
1027 /** @defgroup TIM_Exported_Macros TIM Exported Macros
1028 * @{
1029 */
1030
1031 /** @brief Reset TIM handle state
1032 * @param __HANDLE__: TIM handle.
1033 * @retval None
1034 */
1035 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
1036
1037 /**
1038 * @brief Enable the TIM peripheral.
1039 * @param __HANDLE__: TIM handle
1040 * @retval None
1041 */
1042 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
1043
1044 /**
1045 * @brief Disable the TIM peripheral.
1046 * @param __HANDLE__: TIM handle
1047 * @retval None
1048 */
1049 #define __HAL_TIM_DISABLE(__HANDLE__) \
1050 do { \
1051 if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \
1052 { \
1053 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
1054 } \
1055 } while(0)
1056
1057 /**
1058 * @brief Enable the specified TIM interrupt.
1059 * @param __HANDLE__: TIM handle
1060 * @param __INTERRUPT__: specifies the TIM interrupt sources to be enabled or disabled.
1061 * @retval None
1062 */
1063 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
1064
1065 /**
1066 * @brief Enable the specified DMA Channel.
1067 * @param __HANDLE__: TIM handle
1068 * @param __DMA__: specifies the DMA Channel to be enabled or disabled.
1069 * @retval None
1070 */
1071 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
1072
1073 /**
1074 * @brief Disable the specified TIM interrupt.
1075 * @param __HANDLE__: TIM handle
1076 * @param __INTERRUPT__: specifies the TIM interrupt sources to be enabled or disabled.
1077 * @retval None
1078 */
1079 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
1080
1081 /**
1082 * @brief Disable the specified DMA Channel.
1083 * @param __HANDLE__: TIM handle
1084 * @param __DMA__: specifies the DMA Channel to be enabled or disabled.
1085 * @retval None
1086 */
1087 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
1088
1089 /**
1090 * @brief Get the TIM Channel pending flags.
1091 * @param __HANDLE__: TIM handle
1092 * @param __FLAG__: Get the specified flag.
1093 * @retval The state of FLAG (SET or RESET).
1094 */
1095 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
1096
1097 /**
1098 * @brief Clear the TIM Channel pending flags.
1099 * @param __HANDLE__: TIM handle
1100 * @param __FLAG__: specifies the flag to clear.
1101 * @retval None
1102 */
1103 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
1104
1105 /**
1106 * @brief Checks whether the specified TIM interrupt has occurred or not.
1107 * @param __HANDLE__: TIM handle
1108 * @param __INTERRUPT__: specifies the TIM interrupt source to check.
1109 * @retval The state of TIM_IT (SET or RESET).
1110 */
1111 #define __HAL_TIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
1112
1113 /** @brief Clear the TIM interrupt pending bits
1114 * @param __HANDLE__: TIM handle
1115 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
1116 * @retval None
1117 */
1118 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
1119
1120 /** @brief TIM counter direction
1121 * @param __HANDLE__: TIM handle
1122 */
1123 #define __HAL_TIM_DIRECTION_STATUS(__HANDLE__) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR))
1124
1125 /** @brief Set TIM prescaler
1126 * @param __HANDLE__: TIM handle
1127 * @param __PRESC__: specifies the prescaler value.
1128 * @retval None
1129 */
1130 #define __HAL_TIM_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
1131
1132 /** @brief Set TIM IC prescaler
1133 * @param __HANDLE__: TIM handle
1134 * @param __CHANNEL__: specifies TIM Channel
1135 * @param __ICPSC__: specifies the prescaler value.
1136 * @retval None
1137 */
1138 #define __HAL_TIM_SetICPrescalerValue(__HANDLE__, __CHANNEL__, __ICPSC__) \
1139 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
1140 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\
1141 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
1142 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8)))
1143
1144 /** @brief Reset TIM IC prescaler
1145 * @param __HANDLE__: TIM handle
1146 * @param __CHANNEL__: specifies TIM Channel
1147 * @retval None
1148 */
1149 #define __HAL_TIM_ResetICPrescalerValue(__HANDLE__, __CHANNEL__) \
1150 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
1151 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
1152 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
1153 ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
1154
1155 /**
1156 * @brief Sets the TIM Capture Compare Register value on runtime without
1157 * calling another time ConfigChannel function.
1158 * @param __HANDLE__: TIM handle.
1159 * @param __CHANNEL__ : TIM Channels to be configured.
1160 * This parameter can be one of the following values:
1161 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1162 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1163 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1164 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1165 * @param __COMPARE__: specifies the Capture Compare register new value.
1166 * @retval None
1167 */
1168 #define __HAL_TIM_SetCompare(__HANDLE__, __CHANNEL__, __COMPARE__) \
1169 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
1170
1171 /**
1172 * @brief Gets the TIM Capture Compare Register value on runtime
1173 * @param __HANDLE__: TIM handle.
1174 * @param __CHANNEL__ : TIM Channel associated with the capture compare register
1175 * This parameter can be one of the following values:
1176 * @arg TIM_CHANNEL_1: get capture/compare 1 register value
1177 * @arg TIM_CHANNEL_2: get capture/compare 2 register value
1178 * @arg TIM_CHANNEL_3: get capture/compare 3 register value
1179 * @arg TIM_CHANNEL_4: get capture/compare 4 register value
1180 * @retval None
1181 */
1182 #define __HAL_TIM_GetCompare(__HANDLE__, __CHANNEL__) \
1183 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
1184
1185 /**
1186 * @brief Sets the TIM Counter Register value on runtime.
1187 * @param __HANDLE__: TIM handle.
1188 * @param __COUNTER__: specifies the Counter register new value.
1189 * @retval None
1190 */
1191 #define __HAL_TIM_SetCounter(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
1192
1193 /**
1194 * @brief Gets the TIM Counter Register value on runtime.
1195 * @param __HANDLE__: TIM handle.
1196 * @retval None
1197 */
1198 #define __HAL_TIM_GetCounter(__HANDLE__) \
1199 ((__HANDLE__)->Instance->CNT)
1200
1201 /**
1202 * @brief Sets the TIM Autoreload Register value on runtime without calling
1203 * another time any Init function.
1204 * @param __HANDLE__: TIM handle.
1205 * @param __AUTORELOAD__: specifies the Counter register new value.
1206 * @retval None
1207 */
1208 #define __HAL_TIM_SetAutoreload(__HANDLE__, __AUTORELOAD__) \
1209 do{ \
1210 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
1211 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
1212 } while(0)
1213
1214 /**
1215 * @brief Gets the TIM Autoreload Register value on runtime
1216 * @param __HANDLE__: TIM handle.
1217 * @retval None
1218 */
1219 #define __HAL_TIM_GetAutoreload(__HANDLE__) \
1220 ((__HANDLE__)->Instance->ARR)
1221
1222 /**
1223 * @brief Sets the TIM Clock Division value on runtime without calling
1224 * another time any Init function.
1225 * @param __HANDLE__: TIM handle.
1226 * @param __CKD__: specifies the clock division value.
1227 * This parameter can be one of the following value:
1228 * @arg TIM_CLOCKDIVISION_DIV1
1229 * @arg TIM_CLOCKDIVISION_DIV2
1230 * @arg TIM_CLOCKDIVISION_DIV4
1231 * @retval None
1232 */
1233 #define __HAL_TIM_SetClockDivision(__HANDLE__, __CKD__) \
1234 do{ \
1235 (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
1236 (__HANDLE__)->Instance->CR1 |= (__CKD__); \
1237 (__HANDLE__)->Init.ClockDivision = (__CKD__); \
1238 } while(0)
1239
1240 /**
1241 * @brief Gets the TIM Clock Division value on runtime
1242 * @param __HANDLE__: TIM handle.
1243 * @retval None
1244 */
1245 #define __HAL_TIM_GetClockDivision(__HANDLE__) \
1246 ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
1247
1248 /**
1249 * @brief Sets the TIM Input Capture prescaler on runtime without calling
1250 * another time HAL_TIM_IC_ConfigChannel() function.
1251 * @param __HANDLE__: TIM handle.
1252 * @param __CHANNEL__ : TIM Channels to be configured.
1253 * This parameter can be one of the following values:
1254 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1255 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1256 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1257 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1258 * @param __ICPSC__: specifies the Input Capture4 prescaler new value.
1259 * This parameter can be one of the following values:
1260 * @arg TIM_ICPSC_DIV1: no prescaler
1261 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
1262 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
1263 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
1264 * @retval None
1265 */
1266 #define __HAL_TIM_SetICPrescaler(__HANDLE__, __CHANNEL__, __ICPSC__) \
1267 do{ \
1268 __HAL_TIM_ResetICPrescalerValue((__HANDLE__), (__CHANNEL__)); \
1269 __HAL_TIM_SetICPrescalerValue((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
1270 } while(0)
1271
1272 /**
1273 * @brief Gets the TIM Input Capture prescaler on runtime
1274 * @param __HANDLE__: TIM handle.
1275 * @param __CHANNEL__ : TIM Channels to be configured.
1276 * This parameter can be one of the following values:
1277 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
1278 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
1279 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
1280 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
1281 * @retval None
1282 */
1283 #define __HAL_TIM_GetICPrescaler(__HANDLE__, __CHANNEL__) \
1284 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
1285 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
1286 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
1287 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
1288
1289 /**
1290 * @}
1291 */
1292
1293 /* Include TIM HAL Extension module */
1294 #include "stm32l1xx_hal_tim_ex.h"
1295
1296 /* Exported functions --------------------------------------------------------*/
1297 /** @addtogroup TIM_Exported_Functions
1298 * @{
1299 */
1300
1301 /** @addtogroup TIM_Exported_Functions_Group1
1302 * @{
1303 */
1304 /* Time Base functions ********************************************************/
1305 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
1306 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
1307 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
1308 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
1309 /* Blocking mode: Polling */
1310 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
1311 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
1312 /* Non-Blocking mode: Interrupt */
1313 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
1314 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
1315 /* Non-Blocking mode: DMA */
1316 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
1317 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
1318
1319 /**
1320 * @}
1321 */
1322
1323 /** @addtogroup TIM_Exported_Functions_Group2
1324 * @{
1325 */
1326 /* Timer Output Compare functions **********************************************/
1327 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
1328 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
1329 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
1330 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
1331 /* Blocking mode: Polling */
1332 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1333 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1334 /* Non-Blocking mode: Interrupt */
1335 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1336 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1337 /* Non-Blocking mode: DMA */
1338 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1339 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1340
1341 /**
1342 * @}
1343 */
1344
1345 /** @addtogroup TIM_Exported_Functions_Group3
1346 * @{
1347 */
1348 /* Timer PWM functions *********************************************************/
1349 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
1350 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
1351 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
1352 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
1353 /* Blocking mode: Polling */
1354 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1355 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1356 /* Non-Blocking mode: Interrupt */
1357 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1358 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1359 /* Non-Blocking mode: DMA */
1360 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1361 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1362 /**
1363 * @}
1364 */
1365
1366 /** @addtogroup TIM_Exported_Functions_Group4
1367 * @{
1368 */
1369 /* Timer Input Capture functions ***********************************************/
1370 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
1371 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
1372 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
1373 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
1374 /* Blocking mode: Polling */
1375 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1376 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1377 /* Non-Blocking mode: Interrupt */
1378 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1379 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1380 /* Non-Blocking mode: DMA */
1381 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1382 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1383 /**
1384 * @}
1385 */
1386
1387 /** @addtogroup TIM_Exported_Functions_Group5
1388 * @{
1389 */
1390 /* Timer One Pulse functions ***************************************************/
1391 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
1392 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
1393 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
1394 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
1395 /* Blocking mode: Polling */
1396 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1397 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1398 /* Non-Blocking mode: Interrupt */
1399 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1400 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1401 /**
1402 * @}
1403 */
1404
1405 /** @addtogroup TIM_Exported_Functions_Group6
1406 * @{
1407 */
1408 /* Timer Encoder functions *****************************************************/
1409 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig);
1410 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
1411 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
1412 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
1413 /* Blocking mode: Polling */
1414 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1415 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1416 /* Non-Blocking mode: Interrupt */
1417 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1418 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1419 /* Non-Blocking mode: DMA */
1420 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
1421 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1422
1423 /**
1424 * @}
1425 */
1426
1427 /** @addtogroup TIM_Exported_Functions_Group7
1428 * @{
1429 */
1430 /* Interrupt Handler functions **********************************************/
1431 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
1432 /**
1433 * @}
1434 */
1435
1436 /** @addtogroup TIM_Exported_Functions_Group8
1437 * @{
1438 */
1439 /* Control functions *********************************************************/
1440 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
1441 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
1442 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
1443 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel);
1444 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
1445 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
1446 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
1447 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
1448 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
1449 uint32_t *BurstBuffer, uint32_t BurstLength);
1450 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
1451 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
1452 uint32_t *BurstBuffer, uint32_t BurstLength);
1453 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
1454 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
1455 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
1456
1457 /**
1458 * @}
1459 */
1460
1461 /** @addtogroup TIM_Exported_Functions_Group9
1462 * @{
1463 */
1464 /* Callback in non blocking modes (Interrupt and DMA) *************************/
1465 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
1466 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
1467 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
1468 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
1469 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
1470 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
1471 /**
1472 * @}
1473 */
1474
1475 /** @addtogroup TIM_Exported_Functions_Group10
1476 * @{
1477 */
1478 /* Peripheral State functions **************************************************/
1479 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
1480 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
1481 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
1482 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
1483 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
1484 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
1485
1486 /**
1487 * @}
1488 */
1489
1490 /**
1491 * @}
1492 */
1493
1494 /**
1495 * @}
1496 */
1497
1498 /**
1499 * @}
1500 */
1501
1502 #ifdef __cplusplus
1503 }
1504 #endif
1505
1506 #endif /* __STM32L1xx_HAL_TIM_H */
1507
1508 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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