tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_ll_fsmc.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32l1xx_ll_fsmc.h
   4   * @author  MCD Application Team
   5   * @version V1.0.0
   6   * @date    5-September-2014
   7   * @brief   Header file of FSMC HAL module.
   8   ******************************************************************************
   9   * @attention
  10   *
  11   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
  12   *
  13   * Redistribution and use in source and binary forms, with or without modification,
  14   * are permitted provided that the following conditions are met:
  15   *   1. Redistributions of source code must retain the above copyright notice,
  16   *      this list of conditions and the following disclaimer.
  17   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18   *      this list of conditions and the following disclaimer in the documentation
  19   *      and/or other materials provided with the distribution.
  20   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21   *      may be used to endorse or promote products derived from this software
  22   *      without specific prior written permission.
  23   *
  24   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34   *
  35   ******************************************************************************
  36   */
  37
  38 /* Define to prevent recursive inclusion -------------------------------------*/
  39 #ifndef __STM32L1xx_LL_FSMC_H
  40 #define __STM32L1xx_LL_FSMC_H
  41
  42 #ifdef __cplusplus
  43  extern "C" {
  44 #endif
  45
  46 #if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
  47
  48 /* Includes ------------------------------------------------------------------*/
  49 #include "stm32l1xx_hal_def.h"
  50
  51 /** @addtogroup STM32L1xx_HAL_Driver
  52   * @{
  53   */
  54
  55 /** @addtogroup FSMC_LL
  56   * @{
  57   */
  58
  59 /* Exported typedef ----------------------------------------------------------*/
  60
  61 /** @defgroup FSMC_NORSRAM_Exported_typedef FSMC NOR/SRAM Exported typedef
  62   * @{
  63   */
  64
  65 #define FSMC_NORSRAM_TYPEDEF            FSMC_Bank1_TypeDef
  66 #define FSMC_NORSRAM_EXTENDED_TYPEDEF   FSMC_Bank1E_TypeDef
  67
  68 #define FSMC_NORSRAM_DEVICE             FSMC_Bank1
  69 #define FSMC_NORSRAM_EXTENDED_DEVICE    FSMC_Bank1E
  70
  71 /**
  72   * @brief  FSMC_NORSRAM Configuration Structure definition
  73   */
  74 typedef struct
  75 {
  76   uint32_t NSBank;                       /*!< Specifies the NORSRAM memory device that will be used.
  77                                               This parameter can be a value of @ref FSMC_NORSRAM_Bank                     */
  78
  79   uint32_t DataAddressMux;               /*!< Specifies whether the address and data values are
  80                                               multiplexed on the data bus or not.
  81                                               This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing    */
  82
  83   uint32_t MemoryType;                   /*!< Specifies the type of external memory attached to
  84                                               the corresponding memory device.
  85                                               This parameter can be a value of @ref FSMC_Memory_Type                      */
  86
  87   uint32_t MemoryDataWidth;              /*!< Specifies the external memory device width.
  88                                               This parameter can be a value of @ref FSMC_NORSRAM_Data_Width               */
  89
  90   uint32_t BurstAccessMode;              /*!< Enables or disables the burst access mode for Flash memory,
  91                                               valid only with synchronous burst Flash memories.
  92                                               This parameter can be a value of @ref FSMC_Burst_Access_Mode                */
  93
  94   uint32_t WaitSignalPolarity;           /*!< Specifies the wait signal polarity, valid only when accessing
  95                                               the Flash memory in burst mode.
  96                                               This parameter can be a value of @ref FSMC_Wait_Signal_Polarity             */
  97
  98   uint32_t WrapMode;                     /*!< Enables or disables the Wrapped burst access mode for Flash
  99                                               memory, valid only when accessing Flash memories in burst mode.
 100                                               This parameter can be a value of @ref FSMC_Wrap_Mode                        */
 101
 102   uint32_t WaitSignalActive;             /*!< Specifies if the wait signal is asserted by the memory one
 103                                               clock cycle before the wait state or during the wait state,
 104                                               valid only when accessing memories in burst mode.
 105                                               This parameter can be a value of @ref FSMC_Wait_Timing                      */
 106
 107   uint32_t WriteOperation;               /*!< Enables or disables the write operation in the selected device by the FSMC.
 108                                               This parameter can be a value of @ref FSMC_Write_Operation                  */
 109
 110   uint32_t WaitSignal;                   /*!< Enables or disables the wait state insertion via wait
 111                                               signal, valid for Flash memory access in burst mode.
 112                                               This parameter can be a value of @ref FSMC_Wait_Signal                      */
 113
 114   uint32_t ExtendedMode;                 /*!< Enables or disables the extended mode.
 115                                               This parameter can be a value of @ref FSMC_Extended_Mode                    */
 116
 117   uint32_t AsynchronousWait;             /*!< Enables or disables wait signal during asynchronous transfers,
 118                                               valid only with asynchronous Flash memories.
 119                                               This parameter can be a value of @ref FSMC_AsynchronousWait                 */
 120
 121   uint32_t WriteBurst;                   /*!< Enables or disables the write burst operation.
 122                                               This parameter can be a value of @ref FSMC_Write_Burst                      */
 123
 124 }FSMC_NORSRAM_InitTypeDef;
 125
 126
 127 /**
 128   * @brief  FSMC_NORSRAM Timing parameters structure definition
 129   */
 130 typedef struct
 131 {
 132   uint32_t AddressSetupTime;             /*!< Defines the number of HCLK cycles to configure
 133                                               the duration of the address setup time.
 134                                               This parameter can be a value between Min_Data = 0 and Max_Data = 15.
 135                                               @note This parameter is not used with synchronous NOR Flash memories.      */
 136
 137   uint32_t AddressHoldTime;              /*!< Defines the number of HCLK cycles to configure
 138                                               the duration of the address hold time.
 139                                               This parameter can be a value between Min_Data = 1 and Max_Data = 15.
 140                                               @note This parameter is not used with synchronous NOR Flash memories.      */
 141
 142   uint32_t DataSetupTime;                /*!< Defines the number of HCLK cycles to configure
 143                                               the duration of the data setup time.
 144                                               This parameter can be a value between Min_Data = 1 and Max_Data = 255.
 145                                               @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
 146                                               NOR Flash memories.                                                        */
 147
 148   uint32_t BusTurnAroundDuration;        /*!< Defines the number of HCLK cycles to configure
 149                                               the duration of the bus turnaround.
 150                                               This parameter can be a value between Min_Data = 0 and Max_Data = 15.
 151                                               @note This parameter is only used for multiplexed NOR Flash memories.      */
 152
 153   uint32_t CLKDivision;                  /*!< Defines the period of CLK clock output signal, expressed in number of
 154                                               HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
 155                                               @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
 156                                               accesses.                                                                  */
 157
 158   uint32_t DataLatency;                  /*!< Defines the number of memory clock cycles to issue
 159                                               to the memory before getting the first data.
 160                                               The parameter value depends on the memory type as shown below:
 161                                               - It must be set to 0 in case of a CRAM
 162                                               - It is don't care in asynchronous NOR, SRAM or ROM accesses
 163                                               - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
 164                                                 with synchronous burst mode enable                                       */
 165
 166   uint32_t AccessMode;                   /*!< Specifies the asynchronous access mode.
 167                                               This parameter can be a value of @ref FSMC_Access_Mode                      */
 168
 169 }FSMC_NORSRAM_TimingTypeDef;
 170
 171 /**
 172   * @}
 173   */
 174
 175 /* Exported constants --------------------------------------------------------*/
 176
 177 /** @defgroup FSMC_NORSRAM_Exported_constants FSMC NOR/SRAM Exported constants
 178   * @{
 179   */
 180
 181 /** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank
 182   * @{
 183   */
 184 #define FSMC_BANK1_NORSRAM1                       ((uint32_t)0x00000000)
 185 #define FSMC_BANK1_NORSRAM2                       ((uint32_t)0x00000002)
 186 #define FSMC_BANK1_NORSRAM3                       ((uint32_t)0x00000004)
 187 #define FSMC_BANK1_NORSRAM4                       ((uint32_t)0x00000006)
 188
 189 /* To keep compatibility with previous families */
 190 #define FSMC_NORSRAM_BANK1                        FSMC_BANK1_NORSRAM1
 191 #define FSMC_NORSRAM_BANK2                        FSMC_BANK1_NORSRAM2
 192 #define FSMC_NORSRAM_BANK3                        FSMC_BANK1_NORSRAM3
 193 #define FSMC_NORSRAM_BANK4                        FSMC_BANK1_NORSRAM4
 194
 195 #define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_BANK1_NORSRAM1) || \
 196                                         ((__BANK__) == FSMC_BANK1_NORSRAM2) || \
 197                                         ((__BANK__) == FSMC_BANK1_NORSRAM3) || \
 198                                         ((__BANK__) == FSMC_BANK1_NORSRAM4))
 199 /**
 200   * @}
 201   */
 202
 203 /** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing
 204   * @{
 205   */
 206
 207 #define FSMC_DATA_ADDRESS_MUX_DISABLE            ((uint32_t)0x00000000)
 208 #define FSMC_DATA_ADDRESS_MUX_ENABLE             ((uint32_t)FSMC_BCRx_MUXEN)
 209
 210 #define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
 211                               ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
 212 /**
 213   * @}
 214   */
 215
 216 /** @defgroup FSMC_Memory_Type FSMC Memory Type
 217   * @{
 218   */
 219
 220 #define FSMC_MEMORY_TYPE_SRAM                    ((uint32_t)0x00000000)
 221 #define FSMC_MEMORY_TYPE_PSRAM                   ((uint32_t)FSMC_BCRx_MTYP_0)
 222 #define FSMC_MEMORY_TYPE_NOR                     ((uint32_t)FSMC_BCRx_MTYP_1)
 223
 224
 225 #define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \
 226                                     ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \
 227                                     ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
 228 /**
 229   * @}
 230   */
 231
 232 /** @defgroup FSMC_NORSRAM_Data_Width FSMC NOR/SRAM Data Width
 233   * @{
 234   */
 235
 236 #define FSMC_NORSRAM_MEM_BUS_WIDTH_8             ((uint32_t)0x00000000)
 237 #define FSMC_NORSRAM_MEM_BUS_WIDTH_16            ((uint32_t)FSMC_BCRx_MWID_0)
 238 #define FSMC_NORSRAM_MEM_BUS_WIDTH_32            ((uint32_t)FSMC_BCRx_MWID_1)
 239
 240 #define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8)  || \
 241                                                  ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
 242                                                  ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
 243 /**
 244   * @}
 245   */
 246
 247 /** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access
 248   * @{
 249   */
 250
 251 #define FSMC_NORSRAM_FLASH_ACCESS_ENABLE         ((uint32_t)FSMC_BCRx_FACCEN)
 252 #define FSMC_NORSRAM_FLASH_ACCESS_DISABLE        ((uint32_t)0x00000000)
 253 /**
 254   * @}
 255   */
 256
 257 /** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode
 258   * @{
 259   */
 260
 261 #define FSMC_BURST_ACCESS_MODE_DISABLE           ((uint32_t)0x00000000)
 262 #define FSMC_BURST_ACCESS_MODE_ENABLE            ((uint32_t)FSMC_BCRx_BURSTEN)
 263
 264 #define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
 265                                       ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
 266 /**
 267   * @}
 268   */
 269
 270
 271 /** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity
 272   * @{
 273   */
 274
 275 #define FSMC_WAIT_SIGNAL_POLARITY_LOW            ((uint32_t)0x00000000)
 276 #define FSMC_WAIT_SIGNAL_POLARITY_HIGH           ((uint32_t)FSMC_BCRx_WAITPOL)
 277
 278 #define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
 279                                              ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
 280 /**
 281   * @}
 282   */
 283
 284 /** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode
 285   * @{
 286   */
 287
 288 #define FSMC_WRAP_MODE_DISABLE                   ((uint32_t)0x00000000)
 289 #define FSMC_WRAP_MODE_ENABLE                    ((uint32_t)FSMC_BCRx_WRAPMOD)
 290
 291 #define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \
 292                                      ((__MODE__) == FSMC_WRAP_MODE_ENABLE))
 293 /**
 294   * @}
 295   */
 296
 297 /** @defgroup FSMC_Wait_Timing FSMC Wait Timing
 298   * @{
 299   */
 300
 301 #define FSMC_WAIT_TIMING_BEFORE_WS               ((uint32_t)0x00000000)
 302 #define FSMC_WAIT_TIMING_DURING_WS               ((uint32_t)FSMC_BCRx_WAITCFG)
 303
 304 #define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \
 305                                                 ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
 306 /**
 307   * @}
 308   */
 309
 310 /** @defgroup FSMC_Write_Operation FSMC Write Operation
 311   * @{
 312   */
 313
 314 #define FSMC_WRITE_OPERATION_DISABLE             ((uint32_t)0x00000000)
 315 #define FSMC_WRITE_OPERATION_ENABLE              ((uint32_t)FSMC_BCRx_WREN)
 316
 317 #define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \
 318                                                 ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
 319 /**
 320   * @}
 321   */
 322
 323 /** @defgroup FSMC_Wait_Signal FSMC Wait Signal
 324   * @{
 325   */
 326
 327 #define FSMC_WAIT_SIGNAL_DISABLE                 ((uint32_t)0x00000000)
 328 #define FSMC_WAIT_SIGNAL_ENABLE                  ((uint32_t)FSMC_BCRx_WAITEN)
 329
 330 #define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \
 331                                           ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
 332
 333 /**
 334   * @}
 335   */
 336
 337 /** @defgroup FSMC_Extended_Mode FSMC Extended Mode
 338   * @{
 339   */
 340
 341 #define FSMC_EXTENDED_MODE_DISABLE               ((uint32_t)0x00000000)
 342 #define FSMC_EXTENDED_MODE_ENABLE                ((uint32_t)FSMC_BCRx_EXTMOD)
 343
 344 #define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \
 345                                          ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
 346 /**
 347   * @}
 348   */
 349
 350 /** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait
 351   * @{
 352   */
 353
 354 #define FSMC_ASYNCHRONOUS_WAIT_DISABLE           ((uint32_t)0x00000000)
 355 #define FSMC_ASYNCHRONOUS_WAIT_ENABLE            ((uint32_t)FSMC_BCRx_ASYNCWAIT)
 356
 357 #define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
 358                                      ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
 359
 360 /**
 361   * @}
 362   */
 363
 364 /** @defgroup FSMC_Write_Burst FSMC Write Burst
 365   * @{
 366   */
 367
 368 #define FSMC_WRITE_BURST_DISABLE                 ((uint32_t)0x00000000)
 369 #define FSMC_WRITE_BURST_ENABLE                  ((uint32_t)FSMC_BCRx_CBURSTRW)
 370
 371 #define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \
 372                                         ((__BURST__) == FSMC_WRITE_BURST_ENABLE))
 373 /**
 374   * @}
 375   */
 376
 377 /** @defgroup FSMC_Address_Setup_Time FSMC Address Setup Time
 378   * @{
 379   */
 380
 381 #define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)
 382 /**
 383   * @}
 384   */
 385
 386 /** @defgroup FSMC_Address_Hold_Time FSMC Address Hold Time
 387   * @{
 388   */
 389
 390 #define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))
 391 /**
 392   * @}
 393   */
 394
 395 /** @defgroup FSMC_Data_Setup_Time FSMC Data Setup Time
 396   * @{
 397   */
 398
 399 #define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))
 400 /**
 401   * @}
 402   */
 403
 404 /** @defgroup FSMC_Bus_Turn_around_Duration FSMC Bus Turn around Duration
 405   * @{
 406   */
 407
 408 #define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
 409 /**
 410   * @}
 411   */
 412
 413 /** @defgroup FSMC_CLK_Division FSMC CLK Division
 414   * @{
 415   */
 416
 417 #define FSMC_CLK_DIV2                        ((uint32_t)0x00000002)
 418 #define FSMC_CLK_DIV3                        ((uint32_t)0x00000003)
 419 #define FSMC_CLK_DIV4                        ((uint32_t)0x00000004)
 420 #define FSMC_CLK_DIV5                        ((uint32_t)0x00000005)
 421 #define FSMC_CLK_DIV6                        ((uint32_t)0x00000006)
 422 #define FSMC_CLK_DIV7                        ((uint32_t)0x00000007)
 423 #define FSMC_CLK_DIV8                        ((uint32_t)0x00000008)
 424 #define FSMC_CLK_DIV9                        ((uint32_t)0x00000009)
 425 #define FSMC_CLK_DIV10                       ((uint32_t)0x0000000A)
 426 #define FSMC_CLK_DIV11                       ((uint32_t)0x0000000B)
 427 #define FSMC_CLK_DIV12                       ((uint32_t)0x0000000C)
 428 #define FSMC_CLK_DIV13                       ((uint32_t)0x0000000D)
 429 #define FSMC_CLK_DIV14                       ((uint32_t)0x0000000E)
 430 #define FSMC_CLK_DIV15                       ((uint32_t)0x0000000F)
 431 #define FSMC_CLK_DIV16                       ((uint32_t)0x00000010)
 432 #define IS_FSMC_CLK_DIV(__DIV__) (((__DIV__) > 1) && ((__DIV__) <= 16))
 433 /**
 434   * @}
 435   */
 436
 437 /** @defgroup FSMC_Data_Latency FSMC Data Latency
 438   * @{
 439   */
 440
 441 #define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
 442 /**
 443   * @}
 444   */
 445
 446 /** @defgroup FSMC_Access_Mode FSMC Access Mode
 447   * @{
 448   */
 449
 450 #define FSMC_ACCESS_MODE_A                        ((uint32_t)0x00000000)
 451 #define FSMC_ACCESS_MODE_B                        ((uint32_t)FSMC_BTRx_ACCMOD_0)
 452 #define FSMC_ACCESS_MODE_C                        ((uint32_t)FSMC_BTRx_ACCMOD_1)
 453 #define FSMC_ACCESS_MODE_D                        ((uint32_t)(FSMC_BTRx_ACCMOD_0 | FSMC_BTRx_ACCMOD_1))
 454
 455 #define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \
 456                                        ((__MODE__) == FSMC_ACCESS_MODE_B) || \
 457                                        ((__MODE__) == FSMC_ACCESS_MODE_C) || \
 458                                        ((__MODE__) == FSMC_ACCESS_MODE_D))
 459 /**
 460   * @}
 461   */
 462
 463 /** @defgroup FSMC_NORSRAM_Device_Instance FSMC NOR/SRAM Device Instance
 464   * @{
 465   */
 466
 467 #define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
 468
 469 /**
 470   * @}
 471   */
 472
 473 /** @defgroup FSMC_NORSRAM_EXTENDED_Device_Instance FSMC NOR/SRAM EXTENDED Device Instance
 474   * @{
 475   */
 476
 477 #define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
 478
 479 /**
 480   * @}
 481   */
 482
 483 /**
 484   * @}
 485   */
 486
 487 /* Exported macro ------------------------------------------------------------*/
 488
 489 /** @defgroup FSMC_NOR_Macros FSMC NOR/SRAM Exported Macros
 490  *  @brief macros to handle NOR device enable/disable and read/write operations
 491  *  @{
 492  */
 493
 494 /**
 495   * @brief  Enable the NORSRAM device access.
 496   * @param  __INSTANCE__: FSMC_NORSRAM Instance
 497   * @param  __BANK__: FSMC_NORSRAM Bank
 498   * @retval none
 499   */
 500 #define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__)  ((__INSTANCE__)->BTCR[(__BANK__)] |= FSMC_BCRx_MBKEN)
 501
 502 /**
 503   * @brief  Disable the NORSRAM device access.
 504   * @param  __INSTANCE__: FSMC_NORSRAM Instance
 505   * @param  __BANK__: FSMC_NORSRAM Bank
 506   * @retval none
 507   */
 508 #define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCRx_MBKEN)
 509
 510 /**
 511   * @}
 512   */
 513
 514 /* Exported functions --------------------------------------------------------*/
 515
 516 /** @addtogroup FSMC_Exported_Functions
 517  *  @{
 518  */
 519
 520 /** @addtogroup HAL_FSMC_NORSRAM_Group1
 521  *  @{
 522  */
 523
 524 /* FSMC_NORSRAM Controller functions ******************************************/
 525 /* Initialization/de-initialization functions */
 526 HAL_StatusTypeDef  FSMC_NORSRAM_Init(FSMC_NORSRAM_TYPEDEF *Device, FSMC_NORSRAM_InitTypeDef *Init);
 527 HAL_StatusTypeDef  FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TYPEDEF *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
 528 HAL_StatusTypeDef  FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TYPEDEF *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
 529 HAL_StatusTypeDef  FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TYPEDEF *Device, FSMC_NORSRAM_EXTENDED_TYPEDEF *ExDevice, uint32_t Bank);
 530
 531 /**
 532   * @}
 533   */
 534
 535 /** @addtogroup HAL_FSMC_NORSRAM_Group2
 536  *  @{
 537  */
 538
 539 /* FSMC_NORSRAM Control functions */
 540 HAL_StatusTypeDef  FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TYPEDEF *Device, uint32_t Bank);
 541 HAL_StatusTypeDef  FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TYPEDEF *Device, uint32_t Bank);
 542
 543 /**
 544   * @}
 545   */
 546
 547 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
 548
 549 /**
 550   * @}
 551   */
 552
 553 /**
 554   * @}
 555   */
 556
 557 /**
 558   * @}
 559   */
 560
 561 #ifdef __cplusplus
 562 }
 563 #endif
 564
 565 #endif /* __STM32L1xx_LL_FSMC_H */
 566
 567 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/