tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_ll_sdmmc.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32l1xx_ll_sdmmc.h
   4   * @author  MCD Application Team
   5   * @version V1.0.0
   6   * @date    5-September-2014
   7   * @brief   Header file of low layer SDMMC HAL module.
   8   ******************************************************************************
   9   * @attention
  10   *
  11   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
  12   *
  13   * Redistribution and use in source and binary forms, with or without modification,
  14   * are permitted provided that the following conditions are met:
  15   *   1. Redistributions of source code must retain the above copyright notice,
  16   *      this list of conditions and the following disclaimer.
  17   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18   *      this list of conditions and the following disclaimer in the documentation
  19   *      and/or other materials provided with the distribution.
  20   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21   *      may be used to endorse or promote products derived from this software
  22   *      without specific prior written permission.
  23   *
  24   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34   *
  35   ******************************************************************************
  36   */
  37
  38 /* Define to prevent recursive inclusion -------------------------------------*/
  39 #ifndef __STM32L1xx_LL_SD_H
  40 #define __STM32L1xx_LL_SD_H
  41
  42 #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
  43
  44 #ifdef __cplusplus
  45  extern "C" {
  46 #endif
  47
  48 /* Includes ------------------------------------------------------------------*/
  49 #include "stm32l1xx_hal_def.h"
  50
  51 /** @addtogroup STM32L1xx_HAL_Driver
  52   * @{
  53   */
  54
  55 /** @addtogroup SDMMC_LL
  56   * @{
  57   */
  58
  59 /* Exported types ------------------------------------------------------------*/
  60 /** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
  61   * @{
  62   */
  63
  64 /**
  65   * @brief  SDMMC Configuration Structure definition
  66   */
  67 typedef struct
  68 {
  69   uint32_t ClockEdge;            /*!< Specifies the clock transition on which the bit capture is made.
  70                                       This parameter can be a value of @ref SDMMC_LL_Clock_Edge                 */
  71
  72   uint32_t ClockBypass;          /*!< Specifies whether the SDIO Clock divider bypass is
  73                                       enabled or disabled.
  74                                       This parameter can be a value of @ref SDMMC_LL_Clock_Bypass               */
  75
  76   uint32_t ClockPowerSave;       /*!< Specifies whether SDIO Clock output is enabled or
  77                                       disabled when the bus is idle.
  78                                       This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save           */
  79
  80   uint32_t BusWide;              /*!< Specifies the SDIO bus width.
  81                                       This parameter can be a value of @ref SDMMC_LL_Bus_Wide                   */
  82
  83   uint32_t HardwareFlowControl;  /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
  84                                       This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control      */
  85
  86   uint32_t ClockDiv;             /*!< Specifies the clock frequency of the SDIO controller.
  87                                       This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
  88
  89 }SDIO_InitTypeDef;
  90
  91
  92 /**
  93   * @brief  SDIO Command Control structure
  94   */
  95 typedef struct
  96 {
  97   uint32_t Argument;            /*!< Specifies the SDIO command argument which is sent
  98                                      to a card as part of a command message. If a command
  99                                      contains an argument, it must be loaded into this register
 100                                      before writing the command to the command register.              */
 101
 102   uint32_t CmdIndex;            /*!< Specifies the SDIO command index. It must be Min_Data = 0 and
 103                                      Max_Data = 64                                                    */
 104
 105   uint32_t Response;            /*!< Specifies the SDIO response type.
 106                                      This parameter can be a value of @ref SDMMC_LL_Response_Type         */
 107
 108   uint32_t WaitForInterrupt;    /*!< Specifies whether SDIO wait for interrupt request is
 109                                      enabled or disabled.
 110                                      This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State  */
 111
 112   uint32_t CPSM;                /*!< Specifies whether SDIO Command path state machine (CPSM)
 113                                      is enabled or disabled.
 114                                      This parameter can be a value of @ref SDMMC_LL_CPSM_State            */
 115 }SDIO_CmdInitTypeDef;
 116
 117
 118 /**
 119   * @brief  SDIO Data Control structure
 120   */
 121 typedef struct
 122 {
 123   uint32_t DataTimeOut;         /*!< Specifies the data timeout period in card bus clock periods.  */
 124
 125   uint32_t DataLength;          /*!< Specifies the number of data bytes to be transferred.         */
 126
 127   uint32_t DataBlockSize;       /*!< Specifies the data block size for block transfer.
 128                                      This parameter can be a value of @ref SDMMC_LL_Data_Block_Size    */
 129
 130   uint32_t TransferDir;         /*!< Specifies the data transfer direction, whether the transfer
 131                                      is a read or write.
 132                                      This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */
 133
 134   uint32_t TransferMode;        /*!< Specifies whether data transfer is in stream or block mode.
 135                                      This parameter can be a value of @ref SDMMC_LL_Transfer_Type      */
 136
 137   uint32_t DPSM;                /*!< Specifies whether SDIO Data path state machine (DPSM)
 138                                      is enabled or disabled.
 139                                      This parameter can be a value of @ref SDMMC_LL_DPSM_State         */
 140 }SDIO_DataInitTypeDef;
 141
 142 /**
 143   * @}
 144   */
 145
 146 /* Exported constants --------------------------------------------------------*/
 147 /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
 148   * @{
 149   */
 150
 151 /** @defgroup SDMMC_LL_Clock_Edge Clock Edge
 152   * @{
 153   */
 154 #define SDIO_CLOCK_EDGE_RISING               ((uint32_t)0x00000000)
 155 #define SDIO_CLOCK_EDGE_FALLING              SDIO_CLKCR_NEGEDGE
 156
 157 #define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \
 158                                   ((EDGE) == SDIO_CLOCK_EDGE_FALLING))
 159 /**
 160   * @}
 161   */
 162
 163 /** @defgroup SDMMC_LL_Clock_Bypass Clock Bypass
 164   * @{
 165   */
 166 #define SDIO_CLOCK_BYPASS_DISABLE             ((uint32_t)0x00000000)
 167 #define SDIO_CLOCK_BYPASS_ENABLE              SDIO_CLKCR_BYPASS
 168
 169 #define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \
 170                                       ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE))
 171 /**
 172   * @}
 173   */
 174
 175 /** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving
 176   * @{
 177   */
 178 #define SDIO_CLOCK_POWER_SAVE_DISABLE         ((uint32_t)0x00000000)
 179 #define SDIO_CLOCK_POWER_SAVE_ENABLE          SDIO_CLKCR_PWRSAV
 180
 181 #define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \
 182                                         ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))
 183 /**
 184   * @}
 185   */
 186
 187 /** @defgroup SDMMC_LL_Bus_Wide Bus Width
 188   * @{
 189   */
 190 #define SDIO_BUS_WIDE_1B                      ((uint32_t)0x00000000)
 191 #define SDIO_BUS_WIDE_4B                      SDIO_CLKCR_WIDBUS_0
 192 #define SDIO_BUS_WIDE_8B                      SDIO_CLKCR_WIDBUS_1
 193
 194 #define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \
 195                                 ((WIDE) == SDIO_BUS_WIDE_4B) || \
 196                                 ((WIDE) == SDIO_BUS_WIDE_8B))
 197 /**
 198   * @}
 199   */
 200
 201 /** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control
 202   * @{
 203   */
 204 #define SDIO_HARDWARE_FLOW_CONTROL_DISABLE    ((uint32_t)0x00000000)
 205 #define SDIO_HARDWARE_FLOW_CONTROL_ENABLE     SDIO_CLKCR_HWFC_EN
 206
 207 #define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \
 208                                                 ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))
 209 /**
 210   * @}
 211   */
 212
 213 /** @defgroup SDMMC_LL_Clock_Division Clock Division
 214   * @{
 215   */
 216 #define IS_SDIO_CLKDIV(DIV)   ((DIV) <= 0xFF)
 217 /**
 218   * @}
 219   */
 220
 221 /** @defgroup SDMMC_LL_Command_Index Command Index
 222   * @{
 223   */
 224 #define IS_SDIO_CMD_INDEX(INDEX)            ((INDEX) < 0x40)
 225 /**
 226   * @}
 227   */
 228
 229 /** @defgroup SDMMC_LL_Response_Type Response Type
 230   * @{
 231   */
 232 #define SDIO_RESPONSE_NO                    ((uint32_t)0x00000000)
 233 #define SDIO_RESPONSE_SHORT                 SDIO_CMD_WAITRESP_0
 234 #define SDIO_RESPONSE_LONG                  SDIO_CMD_WAITRESP
 235
 236 #define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO)    || \
 237                                     ((RESPONSE) == SDIO_RESPONSE_SHORT) || \
 238                                     ((RESPONSE) == SDIO_RESPONSE_LONG))
 239 /**
 240   * @}
 241   */
 242
 243 /** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt
 244   * @{
 245   */
 246 #define SDIO_WAIT_NO                        ((uint32_t)0x00000000)
 247 #define SDIO_WAIT_IT                        SDIO_CMD_WAITINT
 248 #define SDIO_WAIT_PEND                      SDIO_CMD_WAITPEND
 249
 250 #define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \
 251                             ((WAIT) == SDIO_WAIT_IT) || \
 252                             ((WAIT) == SDIO_WAIT_PEND))
 253 /**
 254   * @}
 255   */
 256
 257 /** @defgroup SDMMC_LL_CPSM_State CPSM State
 258   * @{
 259   */
 260 #define SDIO_CPSM_DISABLE                   ((uint32_t)0x00000000)
 261 #define SDIO_CPSM_ENABLE                    SDIO_CMD_CPSMEN
 262
 263 #define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \
 264                             ((CPSM) == SDIO_CPSM_ENABLE))
 265 /**
 266   * @}
 267   */
 268
 269 /** @defgroup SDMMC_LL_Response_Registers Response Register
 270   * @{
 271   */
 272 #define SDIO_RESP1                          ((uint32_t)0x00000000)
 273 #define SDIO_RESP2                          ((uint32_t)0x00000004)
 274 #define SDIO_RESP3                          ((uint32_t)0x00000008)
 275 #define SDIO_RESP4                          ((uint32_t)0x0000000C)
 276
 277 #define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \
 278                             ((RESP) == SDIO_RESP2) || \
 279                             ((RESP) == SDIO_RESP3) || \
 280                             ((RESP) == SDIO_RESP4))
 281 /**
 282   * @}
 283   */
 284
 285 /** @defgroup SDMMC_LL_Data_Length Data Lenght
 286   * @{
 287   */
 288 #define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
 289 /**
 290   * @}
 291   */
 292
 293 /** @defgroup SDMMC_LL_Data_Block_Size  Data Block Size
 294   * @{
 295   */
 296 #define SDIO_DATABLOCK_SIZE_1B               ((uint32_t)0x00000000)
 297 #define SDIO_DATABLOCK_SIZE_2B               SDIO_DCTRL_DBLOCKSIZE_0
 298 #define SDIO_DATABLOCK_SIZE_4B               SDIO_DCTRL_DBLOCKSIZE_1
 299 #define SDIO_DATABLOCK_SIZE_8B               ((uint32_t)0x00000030)
 300 #define SDIO_DATABLOCK_SIZE_16B              SDIO_DCTRL_DBLOCKSIZE_2
 301 #define SDIO_DATABLOCK_SIZE_32B              ((uint32_t)0x00000050)
 302 #define SDIO_DATABLOCK_SIZE_64B              ((uint32_t)0x00000060)
 303 #define SDIO_DATABLOCK_SIZE_128B             ((uint32_t)0x00000070)
 304 #define SDIO_DATABLOCK_SIZE_256B             SDIO_DCTRL_DBLOCKSIZE_3
 305 #define SDIO_DATABLOCK_SIZE_512B             ((uint32_t)0x00000090)
 306 #define SDIO_DATABLOCK_SIZE_1024B            ((uint32_t)0x000000A0)
 307 #define SDIO_DATABLOCK_SIZE_2048B            ((uint32_t)0x000000B0)
 308 #define SDIO_DATABLOCK_SIZE_4096B            ((uint32_t)0x000000C0)
 309 #define SDIO_DATABLOCK_SIZE_8192B            ((uint32_t)0x000000D0)
 310 #define SDIO_DATABLOCK_SIZE_16384B           ((uint32_t)0x000000E0)
 311
 312 #define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B)    || \
 313                                   ((SIZE) == SDIO_DATABLOCK_SIZE_2B)    || \
 314                                   ((SIZE) == SDIO_DATABLOCK_SIZE_4B)    || \
 315                                   ((SIZE) == SDIO_DATABLOCK_SIZE_8B)    || \
 316                                   ((SIZE) == SDIO_DATABLOCK_SIZE_16B)   || \
 317                                   ((SIZE) == SDIO_DATABLOCK_SIZE_32B)   || \
 318                                   ((SIZE) == SDIO_DATABLOCK_SIZE_64B)   || \
 319                                   ((SIZE) == SDIO_DATABLOCK_SIZE_128B)  || \
 320                                   ((SIZE) == SDIO_DATABLOCK_SIZE_256B)  || \
 321                                   ((SIZE) == SDIO_DATABLOCK_SIZE_512B)  || \
 322                                   ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \
 323                                   ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \
 324                                   ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \
 325                                   ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \
 326                                   ((SIZE) == SDIO_DATABLOCK_SIZE_16384B))
 327 /**
 328   * @}
 329   */
 330
 331 /** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction
 332   * @{
 333   */
 334 #define SDIO_TRANSFER_DIR_TO_CARD            ((uint32_t)0x00000000)
 335 #define SDIO_TRANSFER_DIR_TO_SDIO            SDIO_DCTRL_DTDIR
 336
 337 #define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \
 338                                    ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))
 339 /**
 340   * @}
 341   */
 342
 343 /** @defgroup SDMMC_LL_Transfer_Type Transfer Type
 344   * @{
 345   */
 346 #define SDIO_TRANSFER_MODE_BLOCK             ((uint32_t)0x00000000)
 347 #define SDIO_TRANSFER_MODE_STREAM            SDIO_DCTRL_DTMODE
 348
 349 #define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \
 350                                      ((MODE) == SDIO_TRANSFER_MODE_STREAM))
 351 /**
 352   * @}
 353   */
 354
 355 /** @defgroup SDMMC_LL_DPSM_State DPSM State
 356   * @{
 357   */
 358 #define SDIO_DPSM_DISABLE                    ((uint32_t)0x00000000)
 359 #define SDIO_DPSM_ENABLE                     SDIO_DCTRL_DTEN
 360
 361 #define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\
 362                             ((DPSM) == SDIO_DPSM_ENABLE))
 363 /**
 364   * @}
 365   */
 366
 367 /** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode
 368   * @{
 369   */
 370 #define SDIO_READ_WAIT_MODE_CLK               ((uint32_t)0x00000000)
 371 #define SDIO_READ_WAIT_MODE_DATA2             ((uint32_t)0x00000001)
 372
 373 #define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \
 374                                      ((MODE) == SDIO_READ_WAIT_MODE_DATA2))
 375 /**
 376   * @}
 377   */
 378
 379 /** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources
 380   * @{
 381   */
 382 #define SDIO_IT_CCRCFAIL                    SDIO_STA_CCRCFAIL
 383 #define SDIO_IT_DCRCFAIL                    SDIO_STA_DCRCFAIL
 384 #define SDIO_IT_CTIMEOUT                    SDIO_STA_CTIMEOUT
 385 #define SDIO_IT_DTIMEOUT                    SDIO_STA_DTIMEOUT
 386 #define SDIO_IT_TXUNDERR                    SDIO_STA_TXUNDERR
 387 #define SDIO_IT_RXOVERR                     SDIO_STA_RXOVERR
 388 #define SDIO_IT_CMDREND                     SDIO_STA_CMDREND
 389 #define SDIO_IT_CMDSENT                     SDIO_STA_CMDSENT
 390 #define SDIO_IT_DATAEND                     SDIO_STA_DATAEND
 391 #define SDIO_IT_STBITERR                    SDIO_STA_STBITERR
 392 #define SDIO_IT_DBCKEND                     SDIO_STA_DBCKEND
 393 #define SDIO_IT_CMDACT                      SDIO_STA_CMDACT
 394 #define SDIO_IT_TXACT                       SDIO_STA_TXACT
 395 #define SDIO_IT_RXACT                       SDIO_STA_RXACT
 396 #define SDIO_IT_TXFIFOHE                    SDIO_STA_TXFIFOHE
 397 #define SDIO_IT_RXFIFOHF                    SDIO_STA_RXFIFOHF
 398 #define SDIO_IT_TXFIFOF                     SDIO_STA_TXFIFOF
 399 #define SDIO_IT_RXFIFOF                     SDIO_STA_RXFIFOF
 400 #define SDIO_IT_TXFIFOE                     SDIO_STA_TXFIFOE
 401 #define SDIO_IT_RXFIFOE                     SDIO_STA_RXFIFOE
 402 #define SDIO_IT_TXDAVL                      SDIO_STA_TXDAVL
 403 #define SDIO_IT_RXDAVL                      SDIO_STA_RXDAVL
 404 #define SDIO_IT_SDIOIT                      SDIO_STA_SDIOIT
 405 #define SDIO_IT_CEATAEND                    SDIO_STA_CEATAEND
 406
 407 /**
 408   * @}
 409   */
 410
 411 /** @defgroup SDMMC_LL_Flags Flags
 412   * @{
 413   */
 414 #define SDIO_FLAG_CCRCFAIL                  SDIO_STA_CCRCFAIL
 415 #define SDIO_FLAG_DCRCFAIL                  SDIO_STA_DCRCFAIL
 416 #define SDIO_FLAG_CTIMEOUT                  SDIO_STA_CTIMEOUT
 417 #define SDIO_FLAG_DTIMEOUT                  SDIO_STA_DTIMEOUT
 418 #define SDIO_FLAG_TXUNDERR                  SDIO_STA_TXUNDERR
 419 #define SDIO_FLAG_RXOVERR                   SDIO_STA_RXOVERR
 420 #define SDIO_FLAG_CMDREND                   SDIO_STA_CMDREND
 421 #define SDIO_FLAG_CMDSENT                   SDIO_STA_CMDSENT
 422 #define SDIO_FLAG_DATAEND                   SDIO_STA_DATAEND
 423 #define SDIO_FLAG_STBITERR                  SDIO_STA_STBITERR
 424 #define SDIO_FLAG_DBCKEND                   SDIO_STA_DBCKEND
 425 #define SDIO_FLAG_CMDACT                    SDIO_STA_CMDACT
 426 #define SDIO_FLAG_TXACT                     SDIO_STA_TXACT
 427 #define SDIO_FLAG_RXACT                     SDIO_STA_RXACT
 428 #define SDIO_FLAG_TXFIFOHE                  SDIO_STA_TXFIFOHE
 429 #define SDIO_FLAG_RXFIFOHF                  SDIO_STA_RXFIFOHF
 430 #define SDIO_FLAG_TXFIFOF                   SDIO_STA_TXFIFOF
 431 #define SDIO_FLAG_RXFIFOF                   SDIO_STA_RXFIFOF
 432 #define SDIO_FLAG_TXFIFOE                   SDIO_STA_TXFIFOE
 433 #define SDIO_FLAG_RXFIFOE                   SDIO_STA_RXFIFOE
 434 #define SDIO_FLAG_TXDAVL                    SDIO_STA_TXDAVL
 435 #define SDIO_FLAG_RXDAVL                    SDIO_STA_RXDAVL
 436 #define SDIO_FLAG_SDIOIT                    SDIO_STA_SDIOIT
 437 #define SDIO_FLAG_CEATAEND                  SDIO_STA_CEATAEND
 438
 439 /**
 440   * @}
 441   */
 442
 443 /**
 444   * @}
 445   */
 446
 447 /* Exported macro ------------------------------------------------------------*/
 448 /** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros
 449   * @{
 450   */
 451
 452 /** @defgroup SDMMC_LL_Register Bits And Addresses Definitions
 453   * @brief SDMMC_LL registers bit address in the alias region
 454   * @{
 455   */
 456
 457 /* ------------ SDIO registers bit address in the alias region -------------- */
 458 #define SDIO_OFFSET               (SDIO_BASE - PERIPH_BASE)
 459
 460 /* --- CLKCR Register ---*/
 461 /* Alias word address of CLKEN bit */
 462 #define CLKCR_OFFSET              (SDIO_OFFSET + 0x04)
 463 #define CLKEN_BITNUMBER           0x08
 464 #define CLKCR_CLKEN_BB            (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BITNUMBER * 4))
 465
 466 /* --- CMD Register ---*/
 467 /* Alias word address of SDIOSUSPEND bit */
 468 #define CMD_OFFSET                (SDIO_OFFSET + 0x0C)
 469 #define SDIOSUSPEND_BITNUMBER     0x0B
 470 #define CMD_SDIOSUSPEND_BB        (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BITNUMBER * 4))
 471
 472 /* Alias word address of ENCMDCOMPL bit */
 473 #define ENCMDCOMPL_BITNUMBER      0x0C
 474 #define CMD_ENCMDCOMPL_BB         (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BITNUMBER * 4))
 475
 476 /* Alias word address of NIEN bit */
 477 #define NIEN_BITNUMBER            0x0D
 478 #define CMD_NIEN_BB               (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BITNUMBER * 4))
 479
 480 /* Alias word address of ATACMD bit */
 481 #define ATACMD_BITNUMBER          0x0E
 482 #define CMD_ATACMD_BB             (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BITNUMBER * 4))
 483
 484 /* --- DCTRL Register ---*/
 485 /* Alias word address of DMAEN bit */
 486 #define DCTRL_OFFSET              (SDIO_OFFSET + 0x2C)
 487 #define DMAEN_BITNUMBER           0x03
 488 #define DCTRL_DMAEN_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BITNUMBER * 4))
 489
 490 /* Alias word address of RWSTART bit */
 491 #define RWSTART_BITNUMBER         0x08
 492 #define DCTRL_RWSTART_BB          (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BITNUMBER * 4))
 493
 494 /* Alias word address of RWSTOP bit */
 495 #define RWSTOP_BITNUMBER          0x09
 496 #define DCTRL_RWSTOP_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BITNUMBER * 4))
 497
 498 /* Alias word address of RWMOD bit */
 499 #define RWMOD_BITNUMBER           0x0A
 500 #define DCTRL_RWMOD_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BITNUMBER * 4))
 501
 502 /* Alias word address of SDIOEN bit */
 503 #define SDIOEN_BITNUMBER          0x0B
 504 #define DCTRL_SDIOEN_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BITNUMBER * 4))
 505
 506 /* ---------------------- SDIO registers bit mask --------------------------- */
 507 /* --- CLKCR Register ---*/
 508 /* CLKCR register clear mask */
 509 #define CLKCR_CLEAR_MASK         ((uint32_t)(SDIO_CLKCR_CLKDIV  | SDIO_CLKCR_PWRSAV |\
 510                                              SDIO_CLKCR_BYPASS  | SDIO_CLKCR_WIDBUS |\
 511                                              SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN))
 512
 513 /* --- DCTRL Register ---*/
 514 /* SDIO DCTRL Clear Mask */
 515 #define DCTRL_CLEAR_MASK         ((uint32_t)(SDIO_DCTRL_DTEN    | SDIO_DCTRL_DTDIR |\
 516                                              SDIO_DCTRL_DTMODE  | SDIO_DCTRL_DBLOCKSIZE))
 517
 518 /* --- CMD Register ---*/
 519 /* CMD Register clear mask */
 520 #define CMD_CLEAR_MASK           ((uint32_t)(SDIO_CMD_CMDINDEX | SDIO_CMD_WAITRESP |\
 521                                              SDIO_CMD_WAITINT  | SDIO_CMD_WAITPEND |\
 522                                              SDIO_CMD_CPSMEN   | SDIO_CMD_SDIOSUSPEND))
 523
 524 /* SDIO RESP Registers Address */
 525 #define SDIO_RESP_ADDR           ((uint32_t)(SDIO_BASE + 0x14))
 526
 527 /* SDIO Intialization Frequency (400KHz max) */
 528 #define SDIO_INIT_CLK_DIV ((uint8_t)0x76)
 529
 530 /* SDIO Data Transfer Frequency */
 531 #define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x4)
 532
 533 /**
 534   * @}
 535   */
 536
 537 /** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration
 538   * @brief macros to handle interrupts and specific clock configurations
 539   * @{
 540   */
 541
 542 /**
 543   * @brief  Enable the SDIO device.
 544   * @retval None
 545   */
 546 #define __SDIO_ENABLE()   (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE)
 547
 548 /**
 549   * @brief  Disable the SDIO device.
 550   * @retval None
 551   */
 552 #define __SDIO_DISABLE()   (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE)
 553
 554 /**
 555   * @brief  Enable the SDIO DMA transfer.
 556   * @retval None
 557   */
 558 #define __SDIO_DMA_ENABLE()   (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE)
 559
 560 /**
 561   * @brief  Disable the SDIO DMA transfer.
 562   * @retval None
 563   */
 564 #define __SDIO_DMA_DISABLE()   (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE)
 565
 566 /**
 567   * @brief  Enable the SDIO device interrupt.
 568   * @param  __INSTANCE__ : Pointer to SDIO register base
 569   * @param  __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled.
 570   *         This parameter can be one or a combination of the following values:
 571   *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
 572   *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
 573   *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
 574   *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
 575   *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
 576   *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
 577   *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
 578   *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
 579   *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
 580   *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
 581   *                                   bus mode interrupt
 582   *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
 583   *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
 584   *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
 585   *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
 586   *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
 587   *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
 588   *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
 589   *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
 590   *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
 591   *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
 592   *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
 593   *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
 594   *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
 595   *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
 596   * @retval None
 597   */
 598 #define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->MASK |= (__INTERRUPT__))
 599
 600 /**
 601   * @brief  Disable the SDIO device interrupt.
 602   * @param  __INSTANCE__ : Pointer to SDIO register base
 603   * @param  __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled.
 604   *          This parameter can be one or a combination of the following values:
 605   *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
 606   *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
 607   *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
 608   *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
 609   *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
 610   *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
 611   *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
 612   *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
 613   *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
 614   *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
 615   *                                   bus mode interrupt
 616   *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
 617   *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
 618   *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
 619   *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
 620   *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
 621   *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
 622   *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
 623   *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
 624   *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
 625   *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
 626   *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
 627   *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
 628   *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
 629   *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
 630   * @retval None
 631   */
 632 #define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
 633
 634 /**
 635   * @brief  Checks whether the specified SDIO flag is set or not.
 636   * @param  __INSTANCE__ : Pointer to SDIO register base
 637   * @param  __FLAG__: specifies the flag to check.
 638   *          This parameter can be one of the following values:
 639   *            @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
 640   *            @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
 641   *            @arg SDIO_FLAG_CTIMEOUT: Command response timeout
 642   *            @arg SDIO_FLAG_DTIMEOUT: Data timeout
 643   *            @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
 644   *            @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
 645   *            @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
 646   *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
 647   *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
 648   *            @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
 649   *            @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
 650   *            @arg SDIO_FLAG_CMDACT:   Command transfer in progress
 651   *            @arg SDIO_FLAG_TXACT:    Data transmit in progress
 652   *            @arg SDIO_FLAG_RXACT:    Data receive in progress
 653   *            @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
 654   *            @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
 655   *            @arg SDIO_FLAG_TXFIFOF:  Transmit FIFO full
 656   *            @arg SDIO_FLAG_RXFIFOF:  Receive FIFO full
 657   *            @arg SDIO_FLAG_TXFIFOE:  Transmit FIFO empty
 658   *            @arg SDIO_FLAG_RXFIFOE:  Receive FIFO empty
 659   *            @arg SDIO_FLAG_TXDAVL:   Data available in transmit FIFO
 660   *            @arg SDIO_FLAG_RXDAVL:   Data available in receive FIFO
 661   *            @arg SDIO_FLAG_SDIOIT:   SD I/O interrupt received
 662   *            @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
 663   * @retval The new state of SDIO_FLAG (SET or RESET).
 664   */
 665 #define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__)   (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
 666
 667
 668 /**
 669   * @brief  Clears the SDIO pending flags.
 670   * @param  __INSTANCE__ : Pointer to SDIO register base
 671   * @param  __FLAG__: specifies the flag to clear.
 672   *          This parameter can be one or a combination of the following values:
 673   *            @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
 674   *            @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
 675   *            @arg SDIO_FLAG_CTIMEOUT: Command response timeout
 676   *            @arg SDIO_FLAG_DTIMEOUT: Data timeout
 677   *            @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
 678   *            @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
 679   *            @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
 680   *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
 681   *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
 682   *            @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
 683   *            @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
 684   *            @arg SDIO_FLAG_SDIOIT:   SD I/O interrupt received
 685   *            @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
 686   * @retval None
 687   */
 688 #define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__)   ((__INSTANCE__)->ICR = (__FLAG__))
 689
 690 /**
 691   * @brief  Checks whether the specified SDIO interrupt has occurred or not.
 692   * @param  __INSTANCE__ : Pointer to SDIO register base
 693   * @param  __INTERRUPT__: specifies the SDIO interrupt source to check.
 694   *          This parameter can be one of the following values:
 695   *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
 696   *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
 697   *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
 698   *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
 699   *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
 700   *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
 701   *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
 702   *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
 703   *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
 704   *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
 705   *                                   bus mode interrupt
 706   *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
 707   *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
 708   *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
 709   *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
 710   *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
 711   *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
 712   *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
 713   *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
 714   *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
 715   *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
 716   *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
 717   *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
 718   *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
 719   *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
 720   * @retval The new state of SDIO_IT (SET or RESET).
 721   */
 722 #define __SDIO_GET_IT  (__INSTANCE__, __INTERRUPT__)   (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
 723
 724 /**
 725   * @brief  Clears the SDIO's interrupt pending bits.
 726   * @param  __INSTANCE__ : Pointer to SDIO register base
 727   * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
 728   *          This parameter can be one or a combination of the following values:
 729   *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
 730   *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
 731   *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
 732   *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
 733   *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
 734   *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
 735   *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
 736   *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
 737   *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIO_DCOUNT, is zero) interrupt
 738   *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
 739   *                                   bus mode interrupt
 740   *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
 741   *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
 742   * @retval None
 743   */
 744 #define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__)   ((__INSTANCE__)->ICR = (__INTERRUPT__))
 745
 746 /**
 747   * @brief  Enable Start the SD I/O Read Wait operation.
 748   * @retval None
 749   */
 750 #define __SDIO_START_READWAIT_ENABLE()   (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE)
 751
 752 /**
 753   * @brief  Disable Start the SD I/O Read Wait operations.
 754   * @retval None
 755   */
 756 #define __SDIO_START_READWAIT_DISABLE()   (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE)
 757
 758 /**
 759   * @brief  Enable Start the SD I/O Read Wait operation.
 760   * @retval None
 761   */
 762 #define __SDIO_STOP_READWAIT_ENABLE()   (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE)
 763
 764 /**
 765   * @brief  Disable Stop the SD I/O Read Wait operations.
 766   * @retval None
 767   */
 768 #define __SDIO_STOP_READWAIT_DISABLE()   (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE)
 769
 770 /**
 771   * @brief  Enable the SD I/O Mode Operation.
 772   * @retval None
 773   */
 774 #define __SDIO_OPERATION_ENABLE()   (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE)
 775
 776 /**
 777   * @brief  Disable the SD I/O Mode Operation.
 778   * @retval None
 779   */
 780 #define __SDIO_OPERATION_DISABLE()   (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE)
 781
 782 /**
 783   * @brief  Enable the SD I/O Suspend command sending.
 784   * @retval None
 785   */
 786 #define __SDIO_SUSPEND_CMD_ENABLE()   (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE)
 787
 788 /**
 789   * @brief  Disable the SD I/O Suspend command sending.
 790   * @retval None
 791   */
 792 #define __SDIO_SUSPEND_CMD_DISABLE()   (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE)
 793
 794 /**
 795   * @brief  Enable the command completion signal.
 796   * @retval None
 797   */
 798 #define __SDIO_CEATA_CMD_COMPLETION_ENABLE()   (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE)
 799
 800 /**
 801   * @brief  Disable the command completion signal.
 802   * @retval None
 803   */
 804 #define __SDIO_CEATA_CMD_COMPLETION_DISABLE()   (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = DISABLE)
 805
 806 /**
 807   * @brief  Enable the CE-ATA interrupt.
 808   * @retval None
 809   */
 810 #define __SDIO_CEATA_ENABLE_IT()   (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)0)
 811
 812 /**
 813   * @brief  Disable the CE-ATA interrupt.
 814   * @retval None
 815   */
 816 #define __SDIO_CEATA_DISABLE_IT()   (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)1)
 817
 818 /**
 819   * @brief  Enable send CE-ATA command (CMD61).
 820   * @retval None
 821   */
 822 #define __SDIO_CEATA_SENDCMD_ENABLE()   (*(__IO uint32_t *) CMD_ATACMD_BB = ENABLE)
 823
 824 /**
 825   * @brief  Disable send CE-ATA command (CMD61).
 826   * @retval None
 827   */
 828 #define __SDIO_CEATA_SENDCMD_DISABLE()   (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE)
 829
 830 /**
 831   * @}
 832   */
 833
 834 /**
 835   * @}
 836   */
 837
 838 /* Exported functions --------------------------------------------------------*/
 839 /** @addtogroup SDMMC_LL_Exported_Functions
 840   * @{
 841   */
 842
 843 /* Initialization/de-initialization functions  **********************************/
 844 /** @addtogroup HAL_SDMMC_LL_Group1
 845   * @{
 846   */
 847 HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init);
 848 /**
 849   * @}
 850   */
 851
 852 /* I/O operation functions  *****************************************************/
 853 /** @addtogroup HAL_SDMMC_LL_Group2
 854   * @{
 855   */
 856 /* Blocking mode: Polling */
 857 uint32_t          SDIO_ReadFIFO(SDIO_TypeDef *SDIOx);
 858 HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData);
 859 /**
 860   * @}
 861   */
 862
 863 /* Peripheral Control functions  ************************************************/
 864 /** @addtogroup HAL_SDMMC_LL_Group3
 865   * @{
 866   */
 867 HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx);
 868 HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx);
 869 uint32_t          SDIO_GetPowerState(SDIO_TypeDef *SDIOx);
 870
 871 /* Command path state machine (CPSM) management functions */
 872 HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
 873 uint8_t           SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx);
 874 uint32_t          SDIO_GetResponse(uint32_t SDIO_RESP);
 875
 876 /* Data path state machine (DPSM) management functions */
 877 HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* SDIO_DataInitStruct);
 878 uint32_t          SDIO_GetDataCounter(SDIO_TypeDef *SDIOx);
 879 uint32_t          SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx);
 880
 881 /* SDIO IO Cards mode management functions */
 882 HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
 883 /**
 884   * @}
 885   */
 886
 887 /**
 888   * @}
 889   */
 890
 891 /**
 892   * @}
 893   */
 894
 895 /**
 896   * @}
 897   */
 898
 899 #ifdef __cplusplus
 900 }
 901 #endif
 902
 903 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
 904
 905 #endif /* __STM32L1xx_LL_SD_H */
 906
 907 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/