tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/clk_freqs.h

   1 /* mbed Microcontroller Library
   2  * Copyright (c) 2006-2015 ARM Limited
   3  *
   4  * Licensed under the Apache License, Version 2.0 (the "License");
   5  * you may not use this file except in compliance with the License.
   6  * You may obtain a copy of the License at
   7  *
   8  *     http://www.apache.org/licenses/LICENSE-2.0
   9  *
  10  * Unless required by applicable law or agreed to in writing, software
  11  * distributed under the License is distributed on an "AS IS" BASIS,
  12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  13  * See the License for the specific language governing permissions and
  14  * limitations under the License.
  15  */
  16 #ifndef CLK_FREQS_H
  17 #define CLK_FREQS_H
  18
  19 #ifdef __cplusplus
  20 extern "C" {
  21 #endif
  22
  23 /*!
  24  * \brief Get the peripheral bus clock frequency
  25  * \return Bus frequency
  26  */
  27 static inline uint32_t bus_frequency(void) {
  28     return SystemCoreClock / (((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV2_MASK) >> SIM_CLKDIV1_OUTDIV2_SHIFT) + 1);
  29 }
  30
  31 /*!
  32  * \brief Get external oscillator (crystal) frequency
  33  * \return External osc frequency
  34  */
  35 static uint32_t extosc_frequency(void) {
  36     uint32_t MCGClock = SystemCoreClock * (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT));
  37
  38     if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(2))     //MCG clock = external reference clock
  39         return MCGClock;
  40
  41     if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0)) {   //PLL/FLL is selected
  42         uint32_t divider, multiplier;
  43         if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {         //FLL is selected
  44             if ((MCG->S & MCG_S_IREFST_MASK) == 0x0u) {     //FLL uses external reference
  45                 divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
  46                 if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u)
  47                     divider <<= 5u;
  48                 /* Select correct multiplier to calculate the MCG output clock  */
  49                 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
  50                     case 0x0u:
  51                       multiplier = 640u;
  52                       break;
  53                     case 0x20u:
  54                       multiplier = 1280u;
  55                       break;
  56                     case 0x40u:
  57                       multiplier = 1920u;
  58                       break;
  59                     case 0x60u:
  60                       multiplier = 2560u;
  61                       break;
  62                     case 0x80u:
  63                       multiplier = 732u;
  64                       break;
  65                     case 0xA0u:
  66                       multiplier = 1464u;
  67                       break;
  68                     case 0xC0u:
  69                       multiplier = 2197u;
  70                       break;
  71                     case 0xE0u:
  72                     default:
  73                       multiplier = 2929u;
  74                       break;
  75                 }
  76
  77                 return MCGClock * divider / multiplier;
  78             }
  79         } else {             //PLL is selected
  80             divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
  81             multiplier = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
  82             return MCGClock * divider / multiplier;
  83         }
  84     }
  85
  86     //In all other cases either there is no crystal or we cannot determine it
  87     //For example when the FLL is running on the internal reference, and there is also an
  88     //external crystal. However these are unlikely situations
  89     return 0;
  90 }
  91
  92 //Get MCG PLL/2 or FLL frequency, depending on which one is active, sets PLLFLLSEL bit
  93 static uint32_t mcgpllfll_frequency(void) {
  94     if ((MCG->C1 & MCG_C1_CLKS_MASK) != MCG_C1_CLKS(0))   //PLL/FLL is not selected
  95         return 0;
  96
  97     uint32_t MCGClock = SystemCoreClock * (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT));
  98     if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {         //FLL is selected
  99         SIM->SOPT2 &= ~SIM_SOPT2_PLLFLLSEL_MASK;        //MCG peripheral clock is FLL output
 100         return MCGClock;
 101     } else {                                            //PLL is selected
 102         SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK;         //MCG peripheral clock is PLL output
 103         return MCGClock;
 104     }
 105
 106     //It is possible the SystemCoreClock isn't running on the PLL, and the PLL is still active
 107     //for the peripherals, this is however an unlikely setup
 108 }
 109
 110
 111 #ifdef __cplusplus
 112 }
 113 #endif
 114
 115 #endif