]>
git.gir.st - tmk_keyboard.git/blob - tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_adc.h
2 ** ###################################################################
3 ** Compilers: Keil ARM C/C++ Compiler
4 ** Freescale C/C++ for Embedded ARM
6 ** IAR ANSI C/C++ Compiler for ARM
8 ** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
9 ** Version: rev. 2.5, 2014-05-06
13 ** Extension to the CMSIS register access layer header.
15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
16 ** All rights reserved.
18 ** Redistribution and use in source and binary forms, with or without modification,
19 ** are permitted provided that the following conditions are met:
21 ** o Redistributions of source code must retain the above copyright notice, this list
22 ** of conditions and the following disclaimer.
24 ** o Redistributions in binary form must reproduce the above copyright notice, this
25 ** list of conditions and the following disclaimer in the documentation and/or
26 ** other materials provided with the distribution.
28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
29 ** contributors may be used to endorse or promote products derived from this
30 ** software without specific prior written permission.
32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 ** http: www.freescale.com
44 ** mail: support@freescale.com
47 ** - rev. 1.0 (2013-07-23)
49 ** - rev. 1.1 (2013-09-17)
50 ** RM rev. 0.4 update.
51 ** - rev. 2.0 (2013-10-29)
52 ** Register accessor macros added to the memory map.
53 ** Symbols for Processor Expert memory map compatibility added to the memory map.
54 ** Startup file for gcc has been updated according to CMSIS 3.2.
55 ** System initialization updated.
56 ** - rev. 2.1 (2013-10-30)
57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
58 ** - rev. 2.2 (2013-12-20)
59 ** Update according to reference manual rev. 0.6,
60 ** - rev. 2.3 (2014-01-13)
61 ** Update according to reference manual rev. 0.61,
62 ** - rev. 2.4 (2014-02-10)
63 ** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
64 ** - rev. 2.5 (2014-05-06)
65 ** Update according to reference manual rev. 1.0,
66 ** Update of system and startup files.
67 ** Module access macro module_BASES replaced by module_BASE_PTRS.
69 ** ###################################################################
73 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
75 * This file was generated automatically and any changes may be lost.
77 #ifndef __HW_ADC_REGISTERS_H__
78 #define __HW_ADC_REGISTERS_H__
80 #include "MK22F51212.h"
81 #include "fsl_bitaccess.h"
86 * Analog-to-Digital Converter
88 * Registers defined in this header file:
89 * - HW_ADC_SC1n - ADC Status and Control Registers 1
90 * - HW_ADC_CFG1 - ADC Configuration Register 1
91 * - HW_ADC_CFG2 - ADC Configuration Register 2
92 * - HW_ADC_Rn - ADC Data Result Register
93 * - HW_ADC_CV1 - Compare Value Registers
94 * - HW_ADC_CV2 - Compare Value Registers
95 * - HW_ADC_SC2 - Status and Control Register 2
96 * - HW_ADC_SC3 - Status and Control Register 3
97 * - HW_ADC_OFS - ADC Offset Correction Register
98 * - HW_ADC_PG - ADC Plus-Side Gain Register
99 * - HW_ADC_MG - ADC Minus-Side Gain Register
100 * - HW_ADC_CLPD - ADC Plus-Side General Calibration Value Register
101 * - HW_ADC_CLPS - ADC Plus-Side General Calibration Value Register
102 * - HW_ADC_CLP4 - ADC Plus-Side General Calibration Value Register
103 * - HW_ADC_CLP3 - ADC Plus-Side General Calibration Value Register
104 * - HW_ADC_CLP2 - ADC Plus-Side General Calibration Value Register
105 * - HW_ADC_CLP1 - ADC Plus-Side General Calibration Value Register
106 * - HW_ADC_CLP0 - ADC Plus-Side General Calibration Value Register
107 * - HW_ADC_CLMD - ADC Minus-Side General Calibration Value Register
108 * - HW_ADC_CLMS - ADC Minus-Side General Calibration Value Register
109 * - HW_ADC_CLM4 - ADC Minus-Side General Calibration Value Register
110 * - HW_ADC_CLM3 - ADC Minus-Side General Calibration Value Register
111 * - HW_ADC_CLM2 - ADC Minus-Side General Calibration Value Register
112 * - HW_ADC_CLM1 - ADC Minus-Side General Calibration Value Register
113 * - HW_ADC_CLM0 - ADC Minus-Side General Calibration Value Register
115 * - hw_adc_t - Struct containing all module registers.
118 #define HW_ADC_INSTANCE_COUNT (2U) /*!< Number of instances of the ADC module. */
119 #define HW_ADC0 (0U) /*!< Instance number for ADC0. */
120 #define HW_ADC1 (1U) /*!< Instance number for ADC1. */
122 /*******************************************************************************
123 * HW_ADC_SC1n - ADC Status and Control Registers 1
124 ******************************************************************************/
127 * @brief HW_ADC_SC1n - ADC Status and Control Registers 1 (RW)
129 * Reset value: 0x0000001FU
131 * SC1A is used for both software and hardware trigger modes of operation. To
132 * allow sequential conversions of the ADC to be triggered by internal peripherals,
133 * the ADC can have more than one status and control register: one for each
134 * conversion. The SC1B-SC1n registers indicate potentially multiple SC1 registers
135 * for use only in hardware trigger mode. See the chip configuration information
136 * about the number of SC1n registers specific to this device. The SC1n registers
137 * have identical fields, and are used in a "ping-pong" approach to control ADC
138 * operation. At any one point in time, only one of the SC1n registers is actively
139 * controlling ADC conversions. Updating SC1A while SC1n is actively controlling
140 * a conversion is allowed, and vice-versa for any of the SC1n registers specific
141 * to this MCU. Writing SC1A while SC1A is actively controlling a conversion
142 * aborts the current conversion. In Software Trigger mode, when SC2[ADTRG]=0,
143 * writes to SC1A subsequently initiate a new conversion, if SC1[ADCH] contains a
144 * value other than all 1s. Writing any of the SC1n registers while that specific
145 * SC1n register is actively controlling a conversion aborts the current conversion.
146 * None of the SC1B-SC1n registers are used for software trigger operation and
147 * therefore writes to the SC1B-SC1n registers do not initiate a new conversion.
149 typedef union _hw_adc_sc1n
152 struct _hw_adc_sc1n_bitfields
154 uint32_t ADCH
: 5; /*!< [4:0] Input channel select */
155 uint32_t DIFF
: 1; /*!< [5] Differential Mode Enable */
156 uint32_t AIEN
: 1; /*!< [6] Interrupt Enable */
157 uint32_t COCO
: 1; /*!< [7] Conversion Complete Flag */
158 uint32_t RESERVED0
: 24; /*!< [31:8] */
163 * @name Constants and macros for entire ADC_SC1n register
166 #define HW_ADC_SC1n_COUNT (2U)
168 #define HW_ADC_SC1n_ADDR(x, n) ((x) + 0x0U + (0x4U * (n)))
170 #define HW_ADC_SC1n(x, n) (*(__IO hw_adc_sc1n_t *) HW_ADC_SC1n_ADDR(x, n))
171 #define HW_ADC_SC1n_RD(x, n) (HW_ADC_SC1n(x, n).U)
172 #define HW_ADC_SC1n_WR(x, n, v) (HW_ADC_SC1n(x, n).U = (v))
173 #define HW_ADC_SC1n_SET(x, n, v) (HW_ADC_SC1n_WR(x, n, HW_ADC_SC1n_RD(x, n) | (v)))
174 #define HW_ADC_SC1n_CLR(x, n, v) (HW_ADC_SC1n_WR(x, n, HW_ADC_SC1n_RD(x, n) & ~(v)))
175 #define HW_ADC_SC1n_TOG(x, n, v) (HW_ADC_SC1n_WR(x, n, HW_ADC_SC1n_RD(x, n) ^ (v)))
179 * Constants & macros for individual ADC_SC1n bitfields
183 * @name Register ADC_SC1n, field ADCH[4:0] (RW)
185 * Selects one of the input channels. The input channel decode depends on the
186 * value of DIFF. DAD0-DAD3 are associated with the input pin pairs DADPx and
187 * DADMx. Some of the input channel options in the bitfield-setting descriptions might
188 * not be available for your device. For the actual ADC channel assignments for
189 * your device, see the Chip Configuration details. The successive approximation
190 * converter subsystem is turned off when the channel select bits are all set,
191 * that is, ADCH = 11111. This feature allows explicit disabling of the ADC and
192 * isolation of the input channel from all sources. Terminating continuous
193 * conversions this way prevents an additional single conversion from being performed. It
194 * is not necessary to set ADCH to all 1s to place the ADC in a low-power state
195 * when continuous conversions are not enabled because the module automatically
196 * enters a low-power state when a conversion completes.
199 * - 00000 - When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is
201 * - 00001 - When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is
203 * - 00010 - When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is
205 * - 00011 - When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is
207 * - 00100 - When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved.
208 * - 00101 - When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved.
209 * - 00110 - When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved.
210 * - 00111 - When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved.
211 * - 01000 - When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved.
212 * - 01001 - When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved.
213 * - 01010 - When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved.
214 * - 01011 - When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved.
215 * - 01100 - When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved.
216 * - 01101 - When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved.
217 * - 01110 - When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved.
218 * - 01111 - When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved.
219 * - 10000 - When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved.
220 * - 10001 - When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved.
221 * - 10010 - When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved.
222 * - 10011 - When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved.
223 * - 10100 - When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved.
224 * - 10101 - When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved.
225 * - 10110 - When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved.
226 * - 10111 - When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved.
227 * - 11000 - Reserved.
228 * - 11001 - Reserved.
229 * - 11010 - When DIFF=0, Temp Sensor (single-ended) is selected as input; when
230 * DIFF=1, Temp Sensor (differential) is selected as input.
231 * - 11011 - When DIFF=0, Bandgap (single-ended) is selected as input; when
232 * DIFF=1, Bandgap (differential) is selected as input.
233 * - 11100 - Reserved.
234 * - 11101 - When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH
235 * (differential) is selected as input. Voltage reference selected is determined
237 * - 11110 - When DIFF=0,VREFSL is selected as input; when DIFF=1, it is
238 * reserved. Voltage reference selected is determined by SC2[REFSEL].
239 * - 11111 - Module is disabled.
242 #define BP_ADC_SC1n_ADCH (0U) /*!< Bit position for ADC_SC1n_ADCH. */
243 #define BM_ADC_SC1n_ADCH (0x0000001FU) /*!< Bit mask for ADC_SC1n_ADCH. */
244 #define BS_ADC_SC1n_ADCH (5U) /*!< Bit field size in bits for ADC_SC1n_ADCH. */
246 /*! @brief Read current value of the ADC_SC1n_ADCH field. */
247 #define BR_ADC_SC1n_ADCH(x, n) (HW_ADC_SC1n(x, n).B.ADCH)
249 /*! @brief Format value for bitfield ADC_SC1n_ADCH. */
250 #define BF_ADC_SC1n_ADCH(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC1n_ADCH) & BM_ADC_SC1n_ADCH)
252 /*! @brief Set the ADCH field to a new value. */
253 #define BW_ADC_SC1n_ADCH(x, n, v) (HW_ADC_SC1n_WR(x, n, (HW_ADC_SC1n_RD(x, n) & ~BM_ADC_SC1n_ADCH) | BF_ADC_SC1n_ADCH(v)))
257 * @name Register ADC_SC1n, field DIFF[5] (RW)
259 * Configures the ADC to operate in differential mode. When enabled, this mode
260 * automatically selects from the differential channels, and changes the
261 * conversion algorithm and the number of cycles to complete a conversion.
264 * - 0 - Single-ended conversions and input channels are selected.
265 * - 1 - Differential conversions and input channels are selected.
268 #define BP_ADC_SC1n_DIFF (5U) /*!< Bit position for ADC_SC1n_DIFF. */
269 #define BM_ADC_SC1n_DIFF (0x00000020U) /*!< Bit mask for ADC_SC1n_DIFF. */
270 #define BS_ADC_SC1n_DIFF (1U) /*!< Bit field size in bits for ADC_SC1n_DIFF. */
272 /*! @brief Read current value of the ADC_SC1n_DIFF field. */
273 #define BR_ADC_SC1n_DIFF(x, n) (BITBAND_ACCESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_DIFF))
275 /*! @brief Format value for bitfield ADC_SC1n_DIFF. */
276 #define BF_ADC_SC1n_DIFF(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC1n_DIFF) & BM_ADC_SC1n_DIFF)
278 /*! @brief Set the DIFF field to a new value. */
279 #define BW_ADC_SC1n_DIFF(x, n, v) (BITBAND_ACCESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_DIFF) = (v))
283 * @name Register ADC_SC1n, field AIEN[6] (RW)
285 * Enables conversion complete interrupts. When COCO becomes set while the
286 * respective AIEN is high, an interrupt is asserted.
289 * - 0 - Conversion complete interrupt is disabled.
290 * - 1 - Conversion complete interrupt is enabled.
293 #define BP_ADC_SC1n_AIEN (6U) /*!< Bit position for ADC_SC1n_AIEN. */
294 #define BM_ADC_SC1n_AIEN (0x00000040U) /*!< Bit mask for ADC_SC1n_AIEN. */
295 #define BS_ADC_SC1n_AIEN (1U) /*!< Bit field size in bits for ADC_SC1n_AIEN. */
297 /*! @brief Read current value of the ADC_SC1n_AIEN field. */
298 #define BR_ADC_SC1n_AIEN(x, n) (BITBAND_ACCESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_AIEN))
300 /*! @brief Format value for bitfield ADC_SC1n_AIEN. */
301 #define BF_ADC_SC1n_AIEN(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC1n_AIEN) & BM_ADC_SC1n_AIEN)
303 /*! @brief Set the AIEN field to a new value. */
304 #define BW_ADC_SC1n_AIEN(x, n, v) (BITBAND_ACCESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_AIEN) = (v))
308 * @name Register ADC_SC1n, field COCO[7] (RO)
310 * This is a read-only field that is set each time a conversion is completed
311 * when the compare function is disabled, or SC2[ACFE]=0 and the hardware average
312 * function is disabled, or SC3[AVGE]=0. When the compare function is enabled, or
313 * SC2[ACFE]=1, COCO is set upon completion of a conversion only if the compare
314 * result is true. When the hardware average function is enabled, or SC3[AVGE]=1,
315 * COCO is set upon completion of the selected number of conversions (determined
316 * by AVGS). COCO in SC1A is also set at the completion of a calibration sequence.
317 * COCO is cleared when the respective SC1n register is written or when the
318 * respective Rn register is read.
321 * - 0 - Conversion is not completed.
322 * - 1 - Conversion is completed.
325 #define BP_ADC_SC1n_COCO (7U) /*!< Bit position for ADC_SC1n_COCO. */
326 #define BM_ADC_SC1n_COCO (0x00000080U) /*!< Bit mask for ADC_SC1n_COCO. */
327 #define BS_ADC_SC1n_COCO (1U) /*!< Bit field size in bits for ADC_SC1n_COCO. */
329 /*! @brief Read current value of the ADC_SC1n_COCO field. */
330 #define BR_ADC_SC1n_COCO(x, n) (BITBAND_ACCESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_COCO))
333 /*******************************************************************************
334 * HW_ADC_CFG1 - ADC Configuration Register 1
335 ******************************************************************************/
338 * @brief HW_ADC_CFG1 - ADC Configuration Register 1 (RW)
340 * Reset value: 0x00000000U
342 * The configuration Register 1 (CFG1) selects the mode of operation, clock
343 * source, clock divide, and configuration for low power or long sample time.
345 typedef union _hw_adc_cfg1
348 struct _hw_adc_cfg1_bitfields
350 uint32_t ADICLK
: 2; /*!< [1:0] Input Clock Select */
351 uint32_t MODE
: 2; /*!< [3:2] Conversion mode selection */
352 uint32_t ADLSMP
: 1; /*!< [4] Sample Time Configuration */
353 uint32_t ADIV
: 2; /*!< [6:5] Clock Divide Select */
354 uint32_t ADLPC
: 1; /*!< [7] Low-Power Configuration */
355 uint32_t RESERVED0
: 24; /*!< [31:8] */
360 * @name Constants and macros for entire ADC_CFG1 register
363 #define HW_ADC_CFG1_ADDR(x) ((x) + 0x8U)
365 #define HW_ADC_CFG1(x) (*(__IO hw_adc_cfg1_t *) HW_ADC_CFG1_ADDR(x))
366 #define HW_ADC_CFG1_RD(x) (HW_ADC_CFG1(x).U)
367 #define HW_ADC_CFG1_WR(x, v) (HW_ADC_CFG1(x).U = (v))
368 #define HW_ADC_CFG1_SET(x, v) (HW_ADC_CFG1_WR(x, HW_ADC_CFG1_RD(x) | (v)))
369 #define HW_ADC_CFG1_CLR(x, v) (HW_ADC_CFG1_WR(x, HW_ADC_CFG1_RD(x) & ~(v)))
370 #define HW_ADC_CFG1_TOG(x, v) (HW_ADC_CFG1_WR(x, HW_ADC_CFG1_RD(x) ^ (v)))
374 * Constants & macros for individual ADC_CFG1 bitfields
378 * @name Register ADC_CFG1, field ADICLK[1:0] (RW)
380 * Selects the input clock source to generate the internal clock, ADCK. Note
381 * that when the ADACK clock source is selected, it is not required to be active
382 * prior to conversion start. When it is selected and it is not active prior to a
383 * conversion start, when CFG2[ADACKEN]=0, the asynchronous clock is activated at
384 * the start of a conversion and deactivated when conversions are terminated. In
385 * this case, there is an associated clock startup delay each time the clock
386 * source is re-activated.
390 * - 01 - Alternate clock 2 (ALTCLK2)
391 * - 10 - Alternate clock (ALTCLK)
392 * - 11 - Asynchronous clock (ADACK)
395 #define BP_ADC_CFG1_ADICLK (0U) /*!< Bit position for ADC_CFG1_ADICLK. */
396 #define BM_ADC_CFG1_ADICLK (0x00000003U) /*!< Bit mask for ADC_CFG1_ADICLK. */
397 #define BS_ADC_CFG1_ADICLK (2U) /*!< Bit field size in bits for ADC_CFG1_ADICLK. */
399 /*! @brief Read current value of the ADC_CFG1_ADICLK field. */
400 #define BR_ADC_CFG1_ADICLK(x) (HW_ADC_CFG1(x).B.ADICLK)
402 /*! @brief Format value for bitfield ADC_CFG1_ADICLK. */
403 #define BF_ADC_CFG1_ADICLK(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CFG1_ADICLK) & BM_ADC_CFG1_ADICLK)
405 /*! @brief Set the ADICLK field to a new value. */
406 #define BW_ADC_CFG1_ADICLK(x, v) (HW_ADC_CFG1_WR(x, (HW_ADC_CFG1_RD(x) & ~BM_ADC_CFG1_ADICLK) | BF_ADC_CFG1_ADICLK(v)))
410 * @name Register ADC_CFG1, field MODE[3:2] (RW)
412 * Selects the ADC resolution mode.
415 * - 00 - When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is
416 * differential 9-bit conversion with 2's complement output.
417 * - 01 - When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is
418 * differential 13-bit conversion with 2's complement output.
419 * - 10 - When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is
420 * differential 11-bit conversion with 2's complement output
421 * - 11 - When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it is
422 * differential 16-bit conversion with 2's complement output
425 #define BP_ADC_CFG1_MODE (2U) /*!< Bit position for ADC_CFG1_MODE. */
426 #define BM_ADC_CFG1_MODE (0x0000000CU) /*!< Bit mask for ADC_CFG1_MODE. */
427 #define BS_ADC_CFG1_MODE (2U) /*!< Bit field size in bits for ADC_CFG1_MODE. */
429 /*! @brief Read current value of the ADC_CFG1_MODE field. */
430 #define BR_ADC_CFG1_MODE(x) (HW_ADC_CFG1(x).B.MODE)
432 /*! @brief Format value for bitfield ADC_CFG1_MODE. */
433 #define BF_ADC_CFG1_MODE(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CFG1_MODE) & BM_ADC_CFG1_MODE)
435 /*! @brief Set the MODE field to a new value. */
436 #define BW_ADC_CFG1_MODE(x, v) (HW_ADC_CFG1_WR(x, (HW_ADC_CFG1_RD(x) & ~BM_ADC_CFG1_MODE) | BF_ADC_CFG1_MODE(v)))
440 * @name Register ADC_CFG1, field ADLSMP[4] (RW)
442 * Selects between different sample times based on the conversion mode selected.
443 * This field adjusts the sample period to allow higher impedance inputs to be
444 * accurately sampled or to maximize conversion speed for lower impedance inputs.
445 * Longer sample times can also be used to lower overall power consumption if
446 * continuous conversions are enabled and high conversion rates are not required.
447 * When ADLSMP=1, the long sample time select bits, (ADLSTS[1:0]), can select the
448 * extent of the long sample time.
451 * - 0 - Short sample time.
452 * - 1 - Long sample time.
455 #define BP_ADC_CFG1_ADLSMP (4U) /*!< Bit position for ADC_CFG1_ADLSMP. */
456 #define BM_ADC_CFG1_ADLSMP (0x00000010U) /*!< Bit mask for ADC_CFG1_ADLSMP. */
457 #define BS_ADC_CFG1_ADLSMP (1U) /*!< Bit field size in bits for ADC_CFG1_ADLSMP. */
459 /*! @brief Read current value of the ADC_CFG1_ADLSMP field. */
460 #define BR_ADC_CFG1_ADLSMP(x) (BITBAND_ACCESS32(HW_ADC_CFG1_ADDR(x), BP_ADC_CFG1_ADLSMP))
462 /*! @brief Format value for bitfield ADC_CFG1_ADLSMP. */
463 #define BF_ADC_CFG1_ADLSMP(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CFG1_ADLSMP) & BM_ADC_CFG1_ADLSMP)
465 /*! @brief Set the ADLSMP field to a new value. */
466 #define BW_ADC_CFG1_ADLSMP(x, v) (BITBAND_ACCESS32(HW_ADC_CFG1_ADDR(x), BP_ADC_CFG1_ADLSMP) = (v))
470 * @name Register ADC_CFG1, field ADIV[6:5] (RW)
472 * Selects the divide ratio used by the ADC to generate the internal clock ADCK.
475 * - 00 - The divide ratio is 1 and the clock rate is input clock.
476 * - 01 - The divide ratio is 2 and the clock rate is (input clock)/2.
477 * - 10 - The divide ratio is 4 and the clock rate is (input clock)/4.
478 * - 11 - The divide ratio is 8 and the clock rate is (input clock)/8.
481 #define BP_ADC_CFG1_ADIV (5U) /*!< Bit position for ADC_CFG1_ADIV. */
482 #define BM_ADC_CFG1_ADIV (0x00000060U) /*!< Bit mask for ADC_CFG1_ADIV. */
483 #define BS_ADC_CFG1_ADIV (2U) /*!< Bit field size in bits for ADC_CFG1_ADIV. */
485 /*! @brief Read current value of the ADC_CFG1_ADIV field. */
486 #define BR_ADC_CFG1_ADIV(x) (HW_ADC_CFG1(x).B.ADIV)
488 /*! @brief Format value for bitfield ADC_CFG1_ADIV. */
489 #define BF_ADC_CFG1_ADIV(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CFG1_ADIV) & BM_ADC_CFG1_ADIV)
491 /*! @brief Set the ADIV field to a new value. */
492 #define BW_ADC_CFG1_ADIV(x, v) (HW_ADC_CFG1_WR(x, (HW_ADC_CFG1_RD(x) & ~BM_ADC_CFG1_ADIV) | BF_ADC_CFG1_ADIV(v)))
496 * @name Register ADC_CFG1, field ADLPC[7] (RW)
498 * Controls the power configuration of the successive approximation converter.
499 * This optimizes power consumption when higher sample rates are not required.
502 * - 0 - Normal power configuration.
503 * - 1 - Low-power configuration. The power is reduced at the expense of maximum
507 #define BP_ADC_CFG1_ADLPC (7U) /*!< Bit position for ADC_CFG1_ADLPC. */
508 #define BM_ADC_CFG1_ADLPC (0x00000080U) /*!< Bit mask for ADC_CFG1_ADLPC. */
509 #define BS_ADC_CFG1_ADLPC (1U) /*!< Bit field size in bits for ADC_CFG1_ADLPC. */
511 /*! @brief Read current value of the ADC_CFG1_ADLPC field. */
512 #define BR_ADC_CFG1_ADLPC(x) (BITBAND_ACCESS32(HW_ADC_CFG1_ADDR(x), BP_ADC_CFG1_ADLPC))
514 /*! @brief Format value for bitfield ADC_CFG1_ADLPC. */
515 #define BF_ADC_CFG1_ADLPC(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CFG1_ADLPC) & BM_ADC_CFG1_ADLPC)
517 /*! @brief Set the ADLPC field to a new value. */
518 #define BW_ADC_CFG1_ADLPC(x, v) (BITBAND_ACCESS32(HW_ADC_CFG1_ADDR(x), BP_ADC_CFG1_ADLPC) = (v))
521 /*******************************************************************************
522 * HW_ADC_CFG2 - ADC Configuration Register 2
523 ******************************************************************************/
526 * @brief HW_ADC_CFG2 - ADC Configuration Register 2 (RW)
528 * Reset value: 0x00000000U
530 * Configuration Register 2 (CFG2) selects the special high-speed configuration
531 * for very high speed conversions and selects the long sample time duration
532 * during long sample mode.
534 typedef union _hw_adc_cfg2
537 struct _hw_adc_cfg2_bitfields
539 uint32_t ADLSTS
: 2; /*!< [1:0] Long Sample Time Select */
540 uint32_t ADHSC
: 1; /*!< [2] High-Speed Configuration */
541 uint32_t ADACKEN
: 1; /*!< [3] Asynchronous Clock Output Enable */
542 uint32_t MUXSEL
: 1; /*!< [4] ADC Mux Select */
543 uint32_t RESERVED0
: 27; /*!< [31:5] */
548 * @name Constants and macros for entire ADC_CFG2 register
551 #define HW_ADC_CFG2_ADDR(x) ((x) + 0xCU)
553 #define HW_ADC_CFG2(x) (*(__IO hw_adc_cfg2_t *) HW_ADC_CFG2_ADDR(x))
554 #define HW_ADC_CFG2_RD(x) (HW_ADC_CFG2(x).U)
555 #define HW_ADC_CFG2_WR(x, v) (HW_ADC_CFG2(x).U = (v))
556 #define HW_ADC_CFG2_SET(x, v) (HW_ADC_CFG2_WR(x, HW_ADC_CFG2_RD(x) | (v)))
557 #define HW_ADC_CFG2_CLR(x, v) (HW_ADC_CFG2_WR(x, HW_ADC_CFG2_RD(x) & ~(v)))
558 #define HW_ADC_CFG2_TOG(x, v) (HW_ADC_CFG2_WR(x, HW_ADC_CFG2_RD(x) ^ (v)))
562 * Constants & macros for individual ADC_CFG2 bitfields
566 * @name Register ADC_CFG2, field ADLSTS[1:0] (RW)
568 * Selects between the extended sample times when long sample time is selected,
569 * that is, when CFG1[ADLSMP]=1. This allows higher impedance inputs to be
570 * accurately sampled or to maximize conversion speed for lower impedance inputs.
571 * Longer sample times can also be used to lower overall power consumption when
572 * continuous conversions are enabled if high conversion rates are not required.
575 * - 00 - Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles
577 * - 01 - 12 extra ADCK cycles; 16 ADCK cycles total sample time.
578 * - 10 - 6 extra ADCK cycles; 10 ADCK cycles total sample time.
579 * - 11 - 2 extra ADCK cycles; 6 ADCK cycles total sample time.
582 #define BP_ADC_CFG2_ADLSTS (0U) /*!< Bit position for ADC_CFG2_ADLSTS. */
583 #define BM_ADC_CFG2_ADLSTS (0x00000003U) /*!< Bit mask for ADC_CFG2_ADLSTS. */
584 #define BS_ADC_CFG2_ADLSTS (2U) /*!< Bit field size in bits for ADC_CFG2_ADLSTS. */
586 /*! @brief Read current value of the ADC_CFG2_ADLSTS field. */
587 #define BR_ADC_CFG2_ADLSTS(x) (HW_ADC_CFG2(x).B.ADLSTS)
589 /*! @brief Format value for bitfield ADC_CFG2_ADLSTS. */
590 #define BF_ADC_CFG2_ADLSTS(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CFG2_ADLSTS) & BM_ADC_CFG2_ADLSTS)
592 /*! @brief Set the ADLSTS field to a new value. */
593 #define BW_ADC_CFG2_ADLSTS(x, v) (HW_ADC_CFG2_WR(x, (HW_ADC_CFG2_RD(x) & ~BM_ADC_CFG2_ADLSTS) | BF_ADC_CFG2_ADLSTS(v)))
597 * @name Register ADC_CFG2, field ADHSC[2] (RW)
599 * Configures the ADC for very high-speed operation. The conversion sequence is
600 * altered with 2 ADCK cycles added to the conversion time to allow higher speed
604 * - 0 - Normal conversion sequence selected.
605 * - 1 - High-speed conversion sequence selected with 2 additional ADCK cycles
606 * to total conversion time.
609 #define BP_ADC_CFG2_ADHSC (2U) /*!< Bit position for ADC_CFG2_ADHSC. */
610 #define BM_ADC_CFG2_ADHSC (0x00000004U) /*!< Bit mask for ADC_CFG2_ADHSC. */
611 #define BS_ADC_CFG2_ADHSC (1U) /*!< Bit field size in bits for ADC_CFG2_ADHSC. */
613 /*! @brief Read current value of the ADC_CFG2_ADHSC field. */
614 #define BR_ADC_CFG2_ADHSC(x) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_ADHSC))
616 /*! @brief Format value for bitfield ADC_CFG2_ADHSC. */
617 #define BF_ADC_CFG2_ADHSC(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CFG2_ADHSC) & BM_ADC_CFG2_ADHSC)
619 /*! @brief Set the ADHSC field to a new value. */
620 #define BW_ADC_CFG2_ADHSC(x, v) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_ADHSC) = (v))
624 * @name Register ADC_CFG2, field ADACKEN[3] (RW)
626 * Enables the asynchronous clock source and the clock source output regardless
627 * of the conversion and status of CFG1[ADICLK]. Based on MCU configuration, the
628 * asynchronous clock may be used by other modules. See chip configuration
629 * information. Setting this field allows the clock to be used even while the ADC is
630 * idle or operating from a different clock source. Also, latency of initiating a
631 * single or first-continuous conversion with the asynchronous clock selected is
632 * reduced because the ADACK clock is already operational.
635 * - 0 - Asynchronous clock output disabled; Asynchronous clock is enabled only
636 * if selected by ADICLK and a conversion is active.
637 * - 1 - Asynchronous clock and clock output is enabled regardless of the state
641 #define BP_ADC_CFG2_ADACKEN (3U) /*!< Bit position for ADC_CFG2_ADACKEN. */
642 #define BM_ADC_CFG2_ADACKEN (0x00000008U) /*!< Bit mask for ADC_CFG2_ADACKEN. */
643 #define BS_ADC_CFG2_ADACKEN (1U) /*!< Bit field size in bits for ADC_CFG2_ADACKEN. */
645 /*! @brief Read current value of the ADC_CFG2_ADACKEN field. */
646 #define BR_ADC_CFG2_ADACKEN(x) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_ADACKEN))
648 /*! @brief Format value for bitfield ADC_CFG2_ADACKEN. */
649 #define BF_ADC_CFG2_ADACKEN(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CFG2_ADACKEN) & BM_ADC_CFG2_ADACKEN)
651 /*! @brief Set the ADACKEN field to a new value. */
652 #define BW_ADC_CFG2_ADACKEN(x, v) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_ADACKEN) = (v))
656 * @name Register ADC_CFG2, field MUXSEL[4] (RW)
658 * Changes the ADC mux setting to select between alternate sets of ADC channels.
661 * - 0 - ADxxa channels are selected.
662 * - 1 - ADxxb channels are selected.
665 #define BP_ADC_CFG2_MUXSEL (4U) /*!< Bit position for ADC_CFG2_MUXSEL. */
666 #define BM_ADC_CFG2_MUXSEL (0x00000010U) /*!< Bit mask for ADC_CFG2_MUXSEL. */
667 #define BS_ADC_CFG2_MUXSEL (1U) /*!< Bit field size in bits for ADC_CFG2_MUXSEL. */
669 /*! @brief Read current value of the ADC_CFG2_MUXSEL field. */
670 #define BR_ADC_CFG2_MUXSEL(x) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_MUXSEL))
672 /*! @brief Format value for bitfield ADC_CFG2_MUXSEL. */
673 #define BF_ADC_CFG2_MUXSEL(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CFG2_MUXSEL) & BM_ADC_CFG2_MUXSEL)
675 /*! @brief Set the MUXSEL field to a new value. */
676 #define BW_ADC_CFG2_MUXSEL(x, v) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_MUXSEL) = (v))
679 /*******************************************************************************
680 * HW_ADC_Rn - ADC Data Result Register
681 ******************************************************************************/
684 * @brief HW_ADC_Rn - ADC Data Result Register (RO)
686 * Reset value: 0x00000000U
688 * The data result registers (Rn) contain the result of an ADC conversion of the
689 * channel selected by the corresponding status and channel control register
690 * (SC1A:SC1n). For every status and channel control register, there is a
691 * corresponding data result register. Unused bits in R n are cleared in unsigned
692 * right-aligned modes and carry the sign bit (MSB) in sign-extended 2's complement modes.
693 * For example, when configured for 10-bit single-ended mode, D[15:10] are
694 * cleared. When configured for 11-bit differential mode, D[15:10] carry the sign bit,
695 * that is, bit 10 extended through bit 15. The following table describes the
696 * behavior of the data result registers in the different modes of operation. Data
697 * result register description Conversion mode D15 D14 D13 D12 D11 D10 D9 D8 D7
698 * D6 D5 D4 D3 D2 D1 D0 Format 16-bit differential S D D D D D D D D D D D D D D D
699 * Signed 2's complement 16-bit single-ended D D D D D D D D D D D D D D D D
700 * Unsigned right justified 13-bit differential S S S S D D D D D D D D D D D D
701 * Sign-extended 2's complement 12-bit single-ended 0 0 0 0 D D D D D D D D D D D D
702 * Unsigned right-justified 11-bit differential S S S S S S D D D D D D D D D D
703 * Sign-extended 2's complement 10-bit single-ended 0 0 0 0 0 0 D D D D D D D D D D
704 * Unsigned right-justified 9-bit differential S S S S S S S S D D D D D D D D
705 * Sign-extended 2's complement 8-bit single-ended 0 0 0 0 0 0 0 0 D D D D D D D D
706 * Unsigned right-justified S: Sign bit or sign bit extension; D: Data, which is
707 * 2's complement data if indicated
709 typedef union _hw_adc_rn
712 struct _hw_adc_rn_bitfields
714 uint32_t D
: 16; /*!< [15:0] Data result */
715 uint32_t RESERVED0
: 16; /*!< [31:16] */
720 * @name Constants and macros for entire ADC_Rn register
723 #define HW_ADC_Rn_COUNT (2U)
725 #define HW_ADC_Rn_ADDR(x, n) ((x) + 0x10U + (0x4U * (n)))
727 #define HW_ADC_Rn(x, n) (*(__I hw_adc_rn_t *) HW_ADC_Rn_ADDR(x, n))
728 #define HW_ADC_Rn_RD(x, n) (HW_ADC_Rn(x, n).U)
732 * Constants & macros for individual ADC_Rn bitfields
736 * @name Register ADC_Rn, field D[15:0] (RO)
739 #define BP_ADC_Rn_D (0U) /*!< Bit position for ADC_Rn_D. */
740 #define BM_ADC_Rn_D (0x0000FFFFU) /*!< Bit mask for ADC_Rn_D. */
741 #define BS_ADC_Rn_D (16U) /*!< Bit field size in bits for ADC_Rn_D. */
743 /*! @brief Read current value of the ADC_Rn_D field. */
744 #define BR_ADC_Rn_D(x, n) (HW_ADC_Rn(x, n).B.D)
747 /*******************************************************************************
748 * HW_ADC_CV1 - Compare Value Registers
749 ******************************************************************************/
752 * @brief HW_ADC_CV1 - Compare Value Registers (RW)
754 * Reset value: 0x00000000U
756 * The Compare Value Registers (CV1 and CV2) contain a compare value used to
757 * compare the conversion result when the compare function is enabled, that is,
758 * SC2[ACFE]=1. This register is formatted in the same way as the Rn registers in
759 * different modes of operation for both bit position definition and value format
760 * using unsigned or sign-extended 2's complement. Therefore, the compare function
761 * uses only the CVn fields that are related to the ADC mode of operation. The
762 * compare value 2 register (CV2) is used only when the compare range function is
763 * enabled, that is, SC2[ACREN]=1.
765 typedef union _hw_adc_cv1
768 struct _hw_adc_cv1_bitfields
770 uint32_t CV
: 16; /*!< [15:0] Compare Value. */
771 uint32_t RESERVED0
: 16; /*!< [31:16] */
776 * @name Constants and macros for entire ADC_CV1 register
779 #define HW_ADC_CV1_ADDR(x) ((x) + 0x18U)
781 #define HW_ADC_CV1(x) (*(__IO hw_adc_cv1_t *) HW_ADC_CV1_ADDR(x))
782 #define HW_ADC_CV1_RD(x) (HW_ADC_CV1(x).U)
783 #define HW_ADC_CV1_WR(x, v) (HW_ADC_CV1(x).U = (v))
784 #define HW_ADC_CV1_SET(x, v) (HW_ADC_CV1_WR(x, HW_ADC_CV1_RD(x) | (v)))
785 #define HW_ADC_CV1_CLR(x, v) (HW_ADC_CV1_WR(x, HW_ADC_CV1_RD(x) & ~(v)))
786 #define HW_ADC_CV1_TOG(x, v) (HW_ADC_CV1_WR(x, HW_ADC_CV1_RD(x) ^ (v)))
790 * Constants & macros for individual ADC_CV1 bitfields
794 * @name Register ADC_CV1, field CV[15:0] (RW)
797 #define BP_ADC_CV1_CV (0U) /*!< Bit position for ADC_CV1_CV. */
798 #define BM_ADC_CV1_CV (0x0000FFFFU) /*!< Bit mask for ADC_CV1_CV. */
799 #define BS_ADC_CV1_CV (16U) /*!< Bit field size in bits for ADC_CV1_CV. */
801 /*! @brief Read current value of the ADC_CV1_CV field. */
802 #define BR_ADC_CV1_CV(x) (HW_ADC_CV1(x).B.CV)
804 /*! @brief Format value for bitfield ADC_CV1_CV. */
805 #define BF_ADC_CV1_CV(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CV1_CV) & BM_ADC_CV1_CV)
807 /*! @brief Set the CV field to a new value. */
808 #define BW_ADC_CV1_CV(x, v) (HW_ADC_CV1_WR(x, (HW_ADC_CV1_RD(x) & ~BM_ADC_CV1_CV) | BF_ADC_CV1_CV(v)))
811 /*******************************************************************************
812 * HW_ADC_CV2 - Compare Value Registers
813 ******************************************************************************/
816 * @brief HW_ADC_CV2 - Compare Value Registers (RW)
818 * Reset value: 0x00000000U
820 * The Compare Value Registers (CV1 and CV2) contain a compare value used to
821 * compare the conversion result when the compare function is enabled, that is,
822 * SC2[ACFE]=1. This register is formatted in the same way as the Rn registers in
823 * different modes of operation for both bit position definition and value format
824 * using unsigned or sign-extended 2's complement. Therefore, the compare function
825 * uses only the CVn fields that are related to the ADC mode of operation. The
826 * compare value 2 register (CV2) is used only when the compare range function is
827 * enabled, that is, SC2[ACREN]=1.
829 typedef union _hw_adc_cv2
832 struct _hw_adc_cv2_bitfields
834 uint32_t CV
: 16; /*!< [15:0] Compare Value. */
835 uint32_t RESERVED0
: 16; /*!< [31:16] */
840 * @name Constants and macros for entire ADC_CV2 register
843 #define HW_ADC_CV2_ADDR(x) ((x) + 0x1CU)
845 #define HW_ADC_CV2(x) (*(__IO hw_adc_cv2_t *) HW_ADC_CV2_ADDR(x))
846 #define HW_ADC_CV2_RD(x) (HW_ADC_CV2(x).U)
847 #define HW_ADC_CV2_WR(x, v) (HW_ADC_CV2(x).U = (v))
848 #define HW_ADC_CV2_SET(x, v) (HW_ADC_CV2_WR(x, HW_ADC_CV2_RD(x) | (v)))
849 #define HW_ADC_CV2_CLR(x, v) (HW_ADC_CV2_WR(x, HW_ADC_CV2_RD(x) & ~(v)))
850 #define HW_ADC_CV2_TOG(x, v) (HW_ADC_CV2_WR(x, HW_ADC_CV2_RD(x) ^ (v)))
854 * Constants & macros for individual ADC_CV2 bitfields
858 * @name Register ADC_CV2, field CV[15:0] (RW)
861 #define BP_ADC_CV2_CV (0U) /*!< Bit position for ADC_CV2_CV. */
862 #define BM_ADC_CV2_CV (0x0000FFFFU) /*!< Bit mask for ADC_CV2_CV. */
863 #define BS_ADC_CV2_CV (16U) /*!< Bit field size in bits for ADC_CV2_CV. */
865 /*! @brief Read current value of the ADC_CV2_CV field. */
866 #define BR_ADC_CV2_CV(x) (HW_ADC_CV2(x).B.CV)
868 /*! @brief Format value for bitfield ADC_CV2_CV. */
869 #define BF_ADC_CV2_CV(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CV2_CV) & BM_ADC_CV2_CV)
871 /*! @brief Set the CV field to a new value. */
872 #define BW_ADC_CV2_CV(x, v) (HW_ADC_CV2_WR(x, (HW_ADC_CV2_RD(x) & ~BM_ADC_CV2_CV) | BF_ADC_CV2_CV(v)))
875 /*******************************************************************************
876 * HW_ADC_SC2 - Status and Control Register 2
877 ******************************************************************************/
880 * @brief HW_ADC_SC2 - Status and Control Register 2 (RW)
882 * Reset value: 0x00000000U
884 * The status and control register 2 (SC2) contains the conversion active,
885 * hardware/software trigger select, compare function, and voltage reference select of
888 typedef union _hw_adc_sc2
891 struct _hw_adc_sc2_bitfields
893 uint32_t REFSEL
: 2; /*!< [1:0] Voltage Reference Selection */
894 uint32_t DMAEN
: 1; /*!< [2] DMA Enable */
895 uint32_t ACREN
: 1; /*!< [3] Compare Function Range Enable */
896 uint32_t ACFGT
: 1; /*!< [4] Compare Function Greater Than Enable */
897 uint32_t ACFE
: 1; /*!< [5] Compare Function Enable */
898 uint32_t ADTRG
: 1; /*!< [6] Conversion Trigger Select */
899 uint32_t ADACT
: 1; /*!< [7] Conversion Active */
900 uint32_t RESERVED0
: 24; /*!< [31:8] */
905 * @name Constants and macros for entire ADC_SC2 register
908 #define HW_ADC_SC2_ADDR(x) ((x) + 0x20U)
910 #define HW_ADC_SC2(x) (*(__IO hw_adc_sc2_t *) HW_ADC_SC2_ADDR(x))
911 #define HW_ADC_SC2_RD(x) (HW_ADC_SC2(x).U)
912 #define HW_ADC_SC2_WR(x, v) (HW_ADC_SC2(x).U = (v))
913 #define HW_ADC_SC2_SET(x, v) (HW_ADC_SC2_WR(x, HW_ADC_SC2_RD(x) | (v)))
914 #define HW_ADC_SC2_CLR(x, v) (HW_ADC_SC2_WR(x, HW_ADC_SC2_RD(x) & ~(v)))
915 #define HW_ADC_SC2_TOG(x, v) (HW_ADC_SC2_WR(x, HW_ADC_SC2_RD(x) ^ (v)))
919 * Constants & macros for individual ADC_SC2 bitfields
923 * @name Register ADC_SC2, field REFSEL[1:0] (RW)
925 * Selects the voltage reference source used for conversions.
928 * - 00 - Default voltage reference pin pair, that is, external pins VREFH and
930 * - 01 - Alternate reference pair, that is, VALTH and VALTL . This pair may be
931 * additional external pins or internal sources depending on the MCU
932 * configuration. See the chip configuration information for details specific to this
938 #define BP_ADC_SC2_REFSEL (0U) /*!< Bit position for ADC_SC2_REFSEL. */
939 #define BM_ADC_SC2_REFSEL (0x00000003U) /*!< Bit mask for ADC_SC2_REFSEL. */
940 #define BS_ADC_SC2_REFSEL (2U) /*!< Bit field size in bits for ADC_SC2_REFSEL. */
942 /*! @brief Read current value of the ADC_SC2_REFSEL field. */
943 #define BR_ADC_SC2_REFSEL(x) (HW_ADC_SC2(x).B.REFSEL)
945 /*! @brief Format value for bitfield ADC_SC2_REFSEL. */
946 #define BF_ADC_SC2_REFSEL(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC2_REFSEL) & BM_ADC_SC2_REFSEL)
948 /*! @brief Set the REFSEL field to a new value. */
949 #define BW_ADC_SC2_REFSEL(x, v) (HW_ADC_SC2_WR(x, (HW_ADC_SC2_RD(x) & ~BM_ADC_SC2_REFSEL) | BF_ADC_SC2_REFSEL(v)))
953 * @name Register ADC_SC2, field DMAEN[2] (RW)
956 * - 0 - DMA is disabled.
957 * - 1 - DMA is enabled and will assert the ADC DMA request during an ADC
958 * conversion complete event noted when any of the SC1n[COCO] flags is asserted.
961 #define BP_ADC_SC2_DMAEN (2U) /*!< Bit position for ADC_SC2_DMAEN. */
962 #define BM_ADC_SC2_DMAEN (0x00000004U) /*!< Bit mask for ADC_SC2_DMAEN. */
963 #define BS_ADC_SC2_DMAEN (1U) /*!< Bit field size in bits for ADC_SC2_DMAEN. */
965 /*! @brief Read current value of the ADC_SC2_DMAEN field. */
966 #define BR_ADC_SC2_DMAEN(x) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_DMAEN))
968 /*! @brief Format value for bitfield ADC_SC2_DMAEN. */
969 #define BF_ADC_SC2_DMAEN(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC2_DMAEN) & BM_ADC_SC2_DMAEN)
971 /*! @brief Set the DMAEN field to a new value. */
972 #define BW_ADC_SC2_DMAEN(x, v) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_DMAEN) = (v))
976 * @name Register ADC_SC2, field ACREN[3] (RW)
978 * Configures the compare function to check if the conversion result of the
979 * input being monitored is either between or outside the range formed by CV1 and CV2
980 * determined by the value of ACFGT. ACFE must be set for ACFGT to have any
984 * - 0 - Range function disabled. Only CV1 is compared.
985 * - 1 - Range function enabled. Both CV1 and CV2 are compared.
988 #define BP_ADC_SC2_ACREN (3U) /*!< Bit position for ADC_SC2_ACREN. */
989 #define BM_ADC_SC2_ACREN (0x00000008U) /*!< Bit mask for ADC_SC2_ACREN. */
990 #define BS_ADC_SC2_ACREN (1U) /*!< Bit field size in bits for ADC_SC2_ACREN. */
992 /*! @brief Read current value of the ADC_SC2_ACREN field. */
993 #define BR_ADC_SC2_ACREN(x) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACREN))
995 /*! @brief Format value for bitfield ADC_SC2_ACREN. */
996 #define BF_ADC_SC2_ACREN(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC2_ACREN) & BM_ADC_SC2_ACREN)
998 /*! @brief Set the ACREN field to a new value. */
999 #define BW_ADC_SC2_ACREN(x, v) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACREN) = (v))
1003 * @name Register ADC_SC2, field ACFGT[4] (RW)
1005 * Configures the compare function to check the conversion result relative to
1006 * the CV1 and CV2 based upon the value of ACREN. ACFE must be set for ACFGT to
1010 * - 0 - Configures less than threshold, outside range not inclusive and inside
1011 * range not inclusive; functionality based on the values placed in CV1 and
1013 * - 1 - Configures greater than or equal to threshold, outside and inside
1014 * ranges inclusive; functionality based on the values placed in CV1 and CV2.
1017 #define BP_ADC_SC2_ACFGT (4U) /*!< Bit position for ADC_SC2_ACFGT. */
1018 #define BM_ADC_SC2_ACFGT (0x00000010U) /*!< Bit mask for ADC_SC2_ACFGT. */
1019 #define BS_ADC_SC2_ACFGT (1U) /*!< Bit field size in bits for ADC_SC2_ACFGT. */
1021 /*! @brief Read current value of the ADC_SC2_ACFGT field. */
1022 #define BR_ADC_SC2_ACFGT(x) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACFGT))
1024 /*! @brief Format value for bitfield ADC_SC2_ACFGT. */
1025 #define BF_ADC_SC2_ACFGT(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC2_ACFGT) & BM_ADC_SC2_ACFGT)
1027 /*! @brief Set the ACFGT field to a new value. */
1028 #define BW_ADC_SC2_ACFGT(x, v) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACFGT) = (v))
1032 * @name Register ADC_SC2, field ACFE[5] (RW)
1034 * Enables the compare function.
1037 * - 0 - Compare function disabled.
1038 * - 1 - Compare function enabled.
1041 #define BP_ADC_SC2_ACFE (5U) /*!< Bit position for ADC_SC2_ACFE. */
1042 #define BM_ADC_SC2_ACFE (0x00000020U) /*!< Bit mask for ADC_SC2_ACFE. */
1043 #define BS_ADC_SC2_ACFE (1U) /*!< Bit field size in bits for ADC_SC2_ACFE. */
1045 /*! @brief Read current value of the ADC_SC2_ACFE field. */
1046 #define BR_ADC_SC2_ACFE(x) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACFE))
1048 /*! @brief Format value for bitfield ADC_SC2_ACFE. */
1049 #define BF_ADC_SC2_ACFE(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC2_ACFE) & BM_ADC_SC2_ACFE)
1051 /*! @brief Set the ACFE field to a new value. */
1052 #define BW_ADC_SC2_ACFE(x, v) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACFE) = (v))
1056 * @name Register ADC_SC2, field ADTRG[6] (RW)
1058 * Selects the type of trigger used for initiating a conversion. Two types of
1059 * trigger are selectable: Software trigger: When software trigger is selected, a
1060 * conversion is initiated following a write to SC1A. Hardware trigger: When
1061 * hardware trigger is selected, a conversion is initiated following the assertion of
1062 * the ADHWT input after a pulse of the ADHWTSn input.
1065 * - 0 - Software trigger selected.
1066 * - 1 - Hardware trigger selected.
1069 #define BP_ADC_SC2_ADTRG (6U) /*!< Bit position for ADC_SC2_ADTRG. */
1070 #define BM_ADC_SC2_ADTRG (0x00000040U) /*!< Bit mask for ADC_SC2_ADTRG. */
1071 #define BS_ADC_SC2_ADTRG (1U) /*!< Bit field size in bits for ADC_SC2_ADTRG. */
1073 /*! @brief Read current value of the ADC_SC2_ADTRG field. */
1074 #define BR_ADC_SC2_ADTRG(x) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ADTRG))
1076 /*! @brief Format value for bitfield ADC_SC2_ADTRG. */
1077 #define BF_ADC_SC2_ADTRG(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC2_ADTRG) & BM_ADC_SC2_ADTRG)
1079 /*! @brief Set the ADTRG field to a new value. */
1080 #define BW_ADC_SC2_ADTRG(x, v) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ADTRG) = (v))
1084 * @name Register ADC_SC2, field ADACT[7] (RO)
1086 * Indicates that a conversion or hardware averaging is in progress. ADACT is
1087 * set when a conversion is initiated and cleared when a conversion is completed or
1091 * - 0 - Conversion not in progress.
1092 * - 1 - Conversion in progress.
1095 #define BP_ADC_SC2_ADACT (7U) /*!< Bit position for ADC_SC2_ADACT. */
1096 #define BM_ADC_SC2_ADACT (0x00000080U) /*!< Bit mask for ADC_SC2_ADACT. */
1097 #define BS_ADC_SC2_ADACT (1U) /*!< Bit field size in bits for ADC_SC2_ADACT. */
1099 /*! @brief Read current value of the ADC_SC2_ADACT field. */
1100 #define BR_ADC_SC2_ADACT(x) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ADACT))
1103 /*******************************************************************************
1104 * HW_ADC_SC3 - Status and Control Register 3
1105 ******************************************************************************/
1108 * @brief HW_ADC_SC3 - Status and Control Register 3 (RW)
1110 * Reset value: 0x00000000U
1112 * The Status and Control Register 3 (SC3) controls the calibration, continuous
1113 * convert, and hardware averaging functions of the ADC module.
1115 typedef union _hw_adc_sc3
1118 struct _hw_adc_sc3_bitfields
1120 uint32_t AVGS
: 2; /*!< [1:0] Hardware Average Select */
1121 uint32_t AVGE
: 1; /*!< [2] Hardware Average Enable */
1122 uint32_t ADCO
: 1; /*!< [3] Continuous Conversion Enable */
1123 uint32_t RESERVED0
: 2; /*!< [5:4] */
1124 uint32_t CALF
: 1; /*!< [6] Calibration Failed Flag */
1125 uint32_t CAL
: 1; /*!< [7] Calibration */
1126 uint32_t RESERVED1
: 24; /*!< [31:8] */
1131 * @name Constants and macros for entire ADC_SC3 register
1134 #define HW_ADC_SC3_ADDR(x) ((x) + 0x24U)
1136 #define HW_ADC_SC3(x) (*(__IO hw_adc_sc3_t *) HW_ADC_SC3_ADDR(x))
1137 #define HW_ADC_SC3_RD(x) (HW_ADC_SC3(x).U)
1138 #define HW_ADC_SC3_WR(x, v) (HW_ADC_SC3(x).U = (v))
1139 #define HW_ADC_SC3_SET(x, v) (HW_ADC_SC3_WR(x, HW_ADC_SC3_RD(x) | (v)))
1140 #define HW_ADC_SC3_CLR(x, v) (HW_ADC_SC3_WR(x, HW_ADC_SC3_RD(x) & ~(v)))
1141 #define HW_ADC_SC3_TOG(x, v) (HW_ADC_SC3_WR(x, HW_ADC_SC3_RD(x) ^ (v)))
1145 * Constants & macros for individual ADC_SC3 bitfields
1149 * @name Register ADC_SC3, field AVGS[1:0] (RW)
1151 * Determines how many ADC conversions will be averaged to create the ADC
1155 * - 00 - 4 samples averaged.
1156 * - 01 - 8 samples averaged.
1157 * - 10 - 16 samples averaged.
1158 * - 11 - 32 samples averaged.
1161 #define BP_ADC_SC3_AVGS (0U) /*!< Bit position for ADC_SC3_AVGS. */
1162 #define BM_ADC_SC3_AVGS (0x00000003U) /*!< Bit mask for ADC_SC3_AVGS. */
1163 #define BS_ADC_SC3_AVGS (2U) /*!< Bit field size in bits for ADC_SC3_AVGS. */
1165 /*! @brief Read current value of the ADC_SC3_AVGS field. */
1166 #define BR_ADC_SC3_AVGS(x) (HW_ADC_SC3(x).B.AVGS)
1168 /*! @brief Format value for bitfield ADC_SC3_AVGS. */
1169 #define BF_ADC_SC3_AVGS(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC3_AVGS) & BM_ADC_SC3_AVGS)
1171 /*! @brief Set the AVGS field to a new value. */
1172 #define BW_ADC_SC3_AVGS(x, v) (HW_ADC_SC3_WR(x, (HW_ADC_SC3_RD(x) & ~BM_ADC_SC3_AVGS) | BF_ADC_SC3_AVGS(v)))
1176 * @name Register ADC_SC3, field AVGE[2] (RW)
1178 * Enables the hardware average function of the ADC.
1181 * - 0 - Hardware average function disabled.
1182 * - 1 - Hardware average function enabled.
1185 #define BP_ADC_SC3_AVGE (2U) /*!< Bit position for ADC_SC3_AVGE. */
1186 #define BM_ADC_SC3_AVGE (0x00000004U) /*!< Bit mask for ADC_SC3_AVGE. */
1187 #define BS_ADC_SC3_AVGE (1U) /*!< Bit field size in bits for ADC_SC3_AVGE. */
1189 /*! @brief Read current value of the ADC_SC3_AVGE field. */
1190 #define BR_ADC_SC3_AVGE(x) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_AVGE))
1192 /*! @brief Format value for bitfield ADC_SC3_AVGE. */
1193 #define BF_ADC_SC3_AVGE(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC3_AVGE) & BM_ADC_SC3_AVGE)
1195 /*! @brief Set the AVGE field to a new value. */
1196 #define BW_ADC_SC3_AVGE(x, v) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_AVGE) = (v))
1200 * @name Register ADC_SC3, field ADCO[3] (RW)
1202 * Enables continuous conversions.
1205 * - 0 - One conversion or one set of conversions if the hardware average
1206 * function is enabled, that is, AVGE=1, after initiating a conversion.
1207 * - 1 - Continuous conversions or sets of conversions if the hardware average
1208 * function is enabled, that is, AVGE=1, after initiating a conversion.
1211 #define BP_ADC_SC3_ADCO (3U) /*!< Bit position for ADC_SC3_ADCO. */
1212 #define BM_ADC_SC3_ADCO (0x00000008U) /*!< Bit mask for ADC_SC3_ADCO. */
1213 #define BS_ADC_SC3_ADCO (1U) /*!< Bit field size in bits for ADC_SC3_ADCO. */
1215 /*! @brief Read current value of the ADC_SC3_ADCO field. */
1216 #define BR_ADC_SC3_ADCO(x) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_ADCO))
1218 /*! @brief Format value for bitfield ADC_SC3_ADCO. */
1219 #define BF_ADC_SC3_ADCO(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC3_ADCO) & BM_ADC_SC3_ADCO)
1221 /*! @brief Set the ADCO field to a new value. */
1222 #define BW_ADC_SC3_ADCO(x, v) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_ADCO) = (v))
1226 * @name Register ADC_SC3, field CALF[6] (RO)
1228 * Displays the result of the calibration sequence. The calibration sequence
1229 * will fail if SC2[ADTRG] = 1, any ADC register is written, or any stop mode is
1230 * entered before the calibration sequence completes. Writing 1 to CALF clears it.
1233 * - 0 - Calibration completed normally.
1234 * - 1 - Calibration failed. ADC accuracy specifications are not guaranteed.
1237 #define BP_ADC_SC3_CALF (6U) /*!< Bit position for ADC_SC3_CALF. */
1238 #define BM_ADC_SC3_CALF (0x00000040U) /*!< Bit mask for ADC_SC3_CALF. */
1239 #define BS_ADC_SC3_CALF (1U) /*!< Bit field size in bits for ADC_SC3_CALF. */
1241 /*! @brief Read current value of the ADC_SC3_CALF field. */
1242 #define BR_ADC_SC3_CALF(x) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_CALF))
1246 * @name Register ADC_SC3, field CAL[7] (RW)
1248 * Begins the calibration sequence when set. This field stays set while the
1249 * calibration is in progress and is cleared when the calibration sequence is
1250 * completed. CALF must be checked to determine the result of the calibration sequence.
1251 * Once started, the calibration routine cannot be interrupted by writes to the
1252 * ADC registers or the results will be invalid and CALF will set. Setting CAL
1253 * will abort any current conversion.
1256 #define BP_ADC_SC3_CAL (7U) /*!< Bit position for ADC_SC3_CAL. */
1257 #define BM_ADC_SC3_CAL (0x00000080U) /*!< Bit mask for ADC_SC3_CAL. */
1258 #define BS_ADC_SC3_CAL (1U) /*!< Bit field size in bits for ADC_SC3_CAL. */
1260 /*! @brief Read current value of the ADC_SC3_CAL field. */
1261 #define BR_ADC_SC3_CAL(x) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_CAL))
1263 /*! @brief Format value for bitfield ADC_SC3_CAL. */
1264 #define BF_ADC_SC3_CAL(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC3_CAL) & BM_ADC_SC3_CAL)
1266 /*! @brief Set the CAL field to a new value. */
1267 #define BW_ADC_SC3_CAL(x, v) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_CAL) = (v))
1270 /*******************************************************************************
1271 * HW_ADC_OFS - ADC Offset Correction Register
1272 ******************************************************************************/
1275 * @brief HW_ADC_OFS - ADC Offset Correction Register (RW)
1277 * Reset value: 0x00000004U
1279 * The ADC Offset Correction Register (OFS) contains the user-selected or
1280 * calibration-generated offset error correction value. This register is a 2's
1281 * complement, left-justified, 16-bit value . The value in OFS is subtracted from the
1282 * conversion and the result is transferred into the result registers, Rn. If the
1283 * result is greater than the maximum or less than the minimum result value, it is
1284 * forced to the appropriate limit for the current mode of operation.
1286 typedef union _hw_adc_ofs
1289 struct _hw_adc_ofs_bitfields
1291 uint32_t OFS
: 16; /*!< [15:0] Offset Error Correction Value */
1292 uint32_t RESERVED0
: 16; /*!< [31:16] */
1297 * @name Constants and macros for entire ADC_OFS register
1300 #define HW_ADC_OFS_ADDR(x) ((x) + 0x28U)
1302 #define HW_ADC_OFS(x) (*(__IO hw_adc_ofs_t *) HW_ADC_OFS_ADDR(x))
1303 #define HW_ADC_OFS_RD(x) (HW_ADC_OFS(x).U)
1304 #define HW_ADC_OFS_WR(x, v) (HW_ADC_OFS(x).U = (v))
1305 #define HW_ADC_OFS_SET(x, v) (HW_ADC_OFS_WR(x, HW_ADC_OFS_RD(x) | (v)))
1306 #define HW_ADC_OFS_CLR(x, v) (HW_ADC_OFS_WR(x, HW_ADC_OFS_RD(x) & ~(v)))
1307 #define HW_ADC_OFS_TOG(x, v) (HW_ADC_OFS_WR(x, HW_ADC_OFS_RD(x) ^ (v)))
1311 * Constants & macros for individual ADC_OFS bitfields
1315 * @name Register ADC_OFS, field OFS[15:0] (RW)
1318 #define BP_ADC_OFS_OFS (0U) /*!< Bit position for ADC_OFS_OFS. */
1319 #define BM_ADC_OFS_OFS (0x0000FFFFU) /*!< Bit mask for ADC_OFS_OFS. */
1320 #define BS_ADC_OFS_OFS (16U) /*!< Bit field size in bits for ADC_OFS_OFS. */
1322 /*! @brief Read current value of the ADC_OFS_OFS field. */
1323 #define BR_ADC_OFS_OFS(x) (HW_ADC_OFS(x).B.OFS)
1325 /*! @brief Format value for bitfield ADC_OFS_OFS. */
1326 #define BF_ADC_OFS_OFS(v) ((uint32_t)((uint32_t)(v) << BP_ADC_OFS_OFS) & BM_ADC_OFS_OFS)
1328 /*! @brief Set the OFS field to a new value. */
1329 #define BW_ADC_OFS_OFS(x, v) (HW_ADC_OFS_WR(x, (HW_ADC_OFS_RD(x) & ~BM_ADC_OFS_OFS) | BF_ADC_OFS_OFS(v)))
1332 /*******************************************************************************
1333 * HW_ADC_PG - ADC Plus-Side Gain Register
1334 ******************************************************************************/
1337 * @brief HW_ADC_PG - ADC Plus-Side Gain Register (RW)
1339 * Reset value: 0x00008200U
1341 * The Plus-Side Gain Register (PG) contains the gain error correction for the
1342 * plus-side input in differential mode or the overall conversion in single-ended
1343 * mode. PG, a 16-bit real number in binary format, is the gain adjustment
1344 * factor, with the radix point fixed between ADPG15 and ADPG14. This register must be
1345 * written by the user with the value described in the calibration procedure.
1346 * Otherwise, the gain error specifications may not be met.
1348 typedef union _hw_adc_pg
1351 struct _hw_adc_pg_bitfields
1353 uint32_t PG
: 16; /*!< [15:0] Plus-Side Gain */
1354 uint32_t RESERVED0
: 16; /*!< [31:16] */
1359 * @name Constants and macros for entire ADC_PG register
1362 #define HW_ADC_PG_ADDR(x) ((x) + 0x2CU)
1364 #define HW_ADC_PG(x) (*(__IO hw_adc_pg_t *) HW_ADC_PG_ADDR(x))
1365 #define HW_ADC_PG_RD(x) (HW_ADC_PG(x).U)
1366 #define HW_ADC_PG_WR(x, v) (HW_ADC_PG(x).U = (v))
1367 #define HW_ADC_PG_SET(x, v) (HW_ADC_PG_WR(x, HW_ADC_PG_RD(x) | (v)))
1368 #define HW_ADC_PG_CLR(x, v) (HW_ADC_PG_WR(x, HW_ADC_PG_RD(x) & ~(v)))
1369 #define HW_ADC_PG_TOG(x, v) (HW_ADC_PG_WR(x, HW_ADC_PG_RD(x) ^ (v)))
1373 * Constants & macros for individual ADC_PG bitfields
1377 * @name Register ADC_PG, field PG[15:0] (RW)
1380 #define BP_ADC_PG_PG (0U) /*!< Bit position for ADC_PG_PG. */
1381 #define BM_ADC_PG_PG (0x0000FFFFU) /*!< Bit mask for ADC_PG_PG. */
1382 #define BS_ADC_PG_PG (16U) /*!< Bit field size in bits for ADC_PG_PG. */
1384 /*! @brief Read current value of the ADC_PG_PG field. */
1385 #define BR_ADC_PG_PG(x) (HW_ADC_PG(x).B.PG)
1387 /*! @brief Format value for bitfield ADC_PG_PG. */
1388 #define BF_ADC_PG_PG(v) ((uint32_t)((uint32_t)(v) << BP_ADC_PG_PG) & BM_ADC_PG_PG)
1390 /*! @brief Set the PG field to a new value. */
1391 #define BW_ADC_PG_PG(x, v) (HW_ADC_PG_WR(x, (HW_ADC_PG_RD(x) & ~BM_ADC_PG_PG) | BF_ADC_PG_PG(v)))
1394 /*******************************************************************************
1395 * HW_ADC_MG - ADC Minus-Side Gain Register
1396 ******************************************************************************/
1399 * @brief HW_ADC_MG - ADC Minus-Side Gain Register (RW)
1401 * Reset value: 0x00008200U
1403 * The Minus-Side Gain Register (MG) contains the gain error correction for the
1404 * minus-side input in differential mode. This register is ignored in
1405 * single-ended mode. MG, a 16-bit real number in binary format, is the gain adjustment
1406 * factor, with the radix point fixed between ADMG15 and ADMG14. This register must
1407 * be written by the user with the value described in the calibration procedure.
1408 * Otherwise, the gain error specifications may not be met.
1410 typedef union _hw_adc_mg
1413 struct _hw_adc_mg_bitfields
1415 uint32_t MG
: 16; /*!< [15:0] Minus-Side Gain */
1416 uint32_t RESERVED0
: 16; /*!< [31:16] */
1421 * @name Constants and macros for entire ADC_MG register
1424 #define HW_ADC_MG_ADDR(x) ((x) + 0x30U)
1426 #define HW_ADC_MG(x) (*(__IO hw_adc_mg_t *) HW_ADC_MG_ADDR(x))
1427 #define HW_ADC_MG_RD(x) (HW_ADC_MG(x).U)
1428 #define HW_ADC_MG_WR(x, v) (HW_ADC_MG(x).U = (v))
1429 #define HW_ADC_MG_SET(x, v) (HW_ADC_MG_WR(x, HW_ADC_MG_RD(x) | (v)))
1430 #define HW_ADC_MG_CLR(x, v) (HW_ADC_MG_WR(x, HW_ADC_MG_RD(x) & ~(v)))
1431 #define HW_ADC_MG_TOG(x, v) (HW_ADC_MG_WR(x, HW_ADC_MG_RD(x) ^ (v)))
1435 * Constants & macros for individual ADC_MG bitfields
1439 * @name Register ADC_MG, field MG[15:0] (RW)
1442 #define BP_ADC_MG_MG (0U) /*!< Bit position for ADC_MG_MG. */
1443 #define BM_ADC_MG_MG (0x0000FFFFU) /*!< Bit mask for ADC_MG_MG. */
1444 #define BS_ADC_MG_MG (16U) /*!< Bit field size in bits for ADC_MG_MG. */
1446 /*! @brief Read current value of the ADC_MG_MG field. */
1447 #define BR_ADC_MG_MG(x) (HW_ADC_MG(x).B.MG)
1449 /*! @brief Format value for bitfield ADC_MG_MG. */
1450 #define BF_ADC_MG_MG(v) ((uint32_t)((uint32_t)(v) << BP_ADC_MG_MG) & BM_ADC_MG_MG)
1452 /*! @brief Set the MG field to a new value. */
1453 #define BW_ADC_MG_MG(x, v) (HW_ADC_MG_WR(x, (HW_ADC_MG_RD(x) & ~BM_ADC_MG_MG) | BF_ADC_MG_MG(v)))
1456 /*******************************************************************************
1457 * HW_ADC_CLPD - ADC Plus-Side General Calibration Value Register
1458 ******************************************************************************/
1461 * @brief HW_ADC_CLPD - ADC Plus-Side General Calibration Value Register (RW)
1463 * Reset value: 0x0000000AU
1465 * The Plus-Side General Calibration Value Registers (CLPx) contain calibration
1466 * information that is generated by the calibration function. These registers
1467 * contain seven calibration values of varying widths: CLP0[5:0], CLP1[6:0],
1468 * CLP2[7:0], CLP3[8:0], CLP4[9:0], CLPS[5:0], and CLPD[5:0]. CLPx are automatically set
1469 * when the self-calibration sequence is done, that is, CAL is cleared. If these
1470 * registers are written by the user after calibration, the linearity error
1471 * specifications may not be met.
1473 typedef union _hw_adc_clpd
1476 struct _hw_adc_clpd_bitfields
1478 uint32_t CLPD
: 6; /*!< [5:0] */
1479 uint32_t RESERVED0
: 26; /*!< [31:6] */
1484 * @name Constants and macros for entire ADC_CLPD register
1487 #define HW_ADC_CLPD_ADDR(x) ((x) + 0x34U)
1489 #define HW_ADC_CLPD(x) (*(__IO hw_adc_clpd_t *) HW_ADC_CLPD_ADDR(x))
1490 #define HW_ADC_CLPD_RD(x) (HW_ADC_CLPD(x).U)
1491 #define HW_ADC_CLPD_WR(x, v) (HW_ADC_CLPD(x).U = (v))
1492 #define HW_ADC_CLPD_SET(x, v) (HW_ADC_CLPD_WR(x, HW_ADC_CLPD_RD(x) | (v)))
1493 #define HW_ADC_CLPD_CLR(x, v) (HW_ADC_CLPD_WR(x, HW_ADC_CLPD_RD(x) & ~(v)))
1494 #define HW_ADC_CLPD_TOG(x, v) (HW_ADC_CLPD_WR(x, HW_ADC_CLPD_RD(x) ^ (v)))
1498 * Constants & macros for individual ADC_CLPD bitfields
1502 * @name Register ADC_CLPD, field CLPD[5:0] (RW)
1507 #define BP_ADC_CLPD_CLPD (0U) /*!< Bit position for ADC_CLPD_CLPD. */
1508 #define BM_ADC_CLPD_CLPD (0x0000003FU) /*!< Bit mask for ADC_CLPD_CLPD. */
1509 #define BS_ADC_CLPD_CLPD (6U) /*!< Bit field size in bits for ADC_CLPD_CLPD. */
1511 /*! @brief Read current value of the ADC_CLPD_CLPD field. */
1512 #define BR_ADC_CLPD_CLPD(x) (HW_ADC_CLPD(x).B.CLPD)
1514 /*! @brief Format value for bitfield ADC_CLPD_CLPD. */
1515 #define BF_ADC_CLPD_CLPD(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLPD_CLPD) & BM_ADC_CLPD_CLPD)
1517 /*! @brief Set the CLPD field to a new value. */
1518 #define BW_ADC_CLPD_CLPD(x, v) (HW_ADC_CLPD_WR(x, (HW_ADC_CLPD_RD(x) & ~BM_ADC_CLPD_CLPD) | BF_ADC_CLPD_CLPD(v)))
1521 /*******************************************************************************
1522 * HW_ADC_CLPS - ADC Plus-Side General Calibration Value Register
1523 ******************************************************************************/
1526 * @brief HW_ADC_CLPS - ADC Plus-Side General Calibration Value Register (RW)
1528 * Reset value: 0x00000020U
1530 * For more information, see CLPD register description.
1532 typedef union _hw_adc_clps
1535 struct _hw_adc_clps_bitfields
1537 uint32_t CLPS
: 6; /*!< [5:0] */
1538 uint32_t RESERVED0
: 26; /*!< [31:6] */
1543 * @name Constants and macros for entire ADC_CLPS register
1546 #define HW_ADC_CLPS_ADDR(x) ((x) + 0x38U)
1548 #define HW_ADC_CLPS(x) (*(__IO hw_adc_clps_t *) HW_ADC_CLPS_ADDR(x))
1549 #define HW_ADC_CLPS_RD(x) (HW_ADC_CLPS(x).U)
1550 #define HW_ADC_CLPS_WR(x, v) (HW_ADC_CLPS(x).U = (v))
1551 #define HW_ADC_CLPS_SET(x, v) (HW_ADC_CLPS_WR(x, HW_ADC_CLPS_RD(x) | (v)))
1552 #define HW_ADC_CLPS_CLR(x, v) (HW_ADC_CLPS_WR(x, HW_ADC_CLPS_RD(x) & ~(v)))
1553 #define HW_ADC_CLPS_TOG(x, v) (HW_ADC_CLPS_WR(x, HW_ADC_CLPS_RD(x) ^ (v)))
1557 * Constants & macros for individual ADC_CLPS bitfields
1561 * @name Register ADC_CLPS, field CLPS[5:0] (RW)
1566 #define BP_ADC_CLPS_CLPS (0U) /*!< Bit position for ADC_CLPS_CLPS. */
1567 #define BM_ADC_CLPS_CLPS (0x0000003FU) /*!< Bit mask for ADC_CLPS_CLPS. */
1568 #define BS_ADC_CLPS_CLPS (6U) /*!< Bit field size in bits for ADC_CLPS_CLPS. */
1570 /*! @brief Read current value of the ADC_CLPS_CLPS field. */
1571 #define BR_ADC_CLPS_CLPS(x) (HW_ADC_CLPS(x).B.CLPS)
1573 /*! @brief Format value for bitfield ADC_CLPS_CLPS. */
1574 #define BF_ADC_CLPS_CLPS(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLPS_CLPS) & BM_ADC_CLPS_CLPS)
1576 /*! @brief Set the CLPS field to a new value. */
1577 #define BW_ADC_CLPS_CLPS(x, v) (HW_ADC_CLPS_WR(x, (HW_ADC_CLPS_RD(x) & ~BM_ADC_CLPS_CLPS) | BF_ADC_CLPS_CLPS(v)))
1580 /*******************************************************************************
1581 * HW_ADC_CLP4 - ADC Plus-Side General Calibration Value Register
1582 ******************************************************************************/
1585 * @brief HW_ADC_CLP4 - ADC Plus-Side General Calibration Value Register (RW)
1587 * Reset value: 0x00000200U
1589 * For more information, see CLPD register description.
1591 typedef union _hw_adc_clp4
1594 struct _hw_adc_clp4_bitfields
1596 uint32_t CLP4
: 10; /*!< [9:0] */
1597 uint32_t RESERVED0
: 22; /*!< [31:10] */
1602 * @name Constants and macros for entire ADC_CLP4 register
1605 #define HW_ADC_CLP4_ADDR(x) ((x) + 0x3CU)
1607 #define HW_ADC_CLP4(x) (*(__IO hw_adc_clp4_t *) HW_ADC_CLP4_ADDR(x))
1608 #define HW_ADC_CLP4_RD(x) (HW_ADC_CLP4(x).U)
1609 #define HW_ADC_CLP4_WR(x, v) (HW_ADC_CLP4(x).U = (v))
1610 #define HW_ADC_CLP4_SET(x, v) (HW_ADC_CLP4_WR(x, HW_ADC_CLP4_RD(x) | (v)))
1611 #define HW_ADC_CLP4_CLR(x, v) (HW_ADC_CLP4_WR(x, HW_ADC_CLP4_RD(x) & ~(v)))
1612 #define HW_ADC_CLP4_TOG(x, v) (HW_ADC_CLP4_WR(x, HW_ADC_CLP4_RD(x) ^ (v)))
1616 * Constants & macros for individual ADC_CLP4 bitfields
1620 * @name Register ADC_CLP4, field CLP4[9:0] (RW)
1625 #define BP_ADC_CLP4_CLP4 (0U) /*!< Bit position for ADC_CLP4_CLP4. */
1626 #define BM_ADC_CLP4_CLP4 (0x000003FFU) /*!< Bit mask for ADC_CLP4_CLP4. */
1627 #define BS_ADC_CLP4_CLP4 (10U) /*!< Bit field size in bits for ADC_CLP4_CLP4. */
1629 /*! @brief Read current value of the ADC_CLP4_CLP4 field. */
1630 #define BR_ADC_CLP4_CLP4(x) (HW_ADC_CLP4(x).B.CLP4)
1632 /*! @brief Format value for bitfield ADC_CLP4_CLP4. */
1633 #define BF_ADC_CLP4_CLP4(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLP4_CLP4) & BM_ADC_CLP4_CLP4)
1635 /*! @brief Set the CLP4 field to a new value. */
1636 #define BW_ADC_CLP4_CLP4(x, v) (HW_ADC_CLP4_WR(x, (HW_ADC_CLP4_RD(x) & ~BM_ADC_CLP4_CLP4) | BF_ADC_CLP4_CLP4(v)))
1639 /*******************************************************************************
1640 * HW_ADC_CLP3 - ADC Plus-Side General Calibration Value Register
1641 ******************************************************************************/
1644 * @brief HW_ADC_CLP3 - ADC Plus-Side General Calibration Value Register (RW)
1646 * Reset value: 0x00000100U
1648 * For more information, see CLPD register description.
1650 typedef union _hw_adc_clp3
1653 struct _hw_adc_clp3_bitfields
1655 uint32_t CLP3
: 9; /*!< [8:0] */
1656 uint32_t RESERVED0
: 23; /*!< [31:9] */
1661 * @name Constants and macros for entire ADC_CLP3 register
1664 #define HW_ADC_CLP3_ADDR(x) ((x) + 0x40U)
1666 #define HW_ADC_CLP3(x) (*(__IO hw_adc_clp3_t *) HW_ADC_CLP3_ADDR(x))
1667 #define HW_ADC_CLP3_RD(x) (HW_ADC_CLP3(x).U)
1668 #define HW_ADC_CLP3_WR(x, v) (HW_ADC_CLP3(x).U = (v))
1669 #define HW_ADC_CLP3_SET(x, v) (HW_ADC_CLP3_WR(x, HW_ADC_CLP3_RD(x) | (v)))
1670 #define HW_ADC_CLP3_CLR(x, v) (HW_ADC_CLP3_WR(x, HW_ADC_CLP3_RD(x) & ~(v)))
1671 #define HW_ADC_CLP3_TOG(x, v) (HW_ADC_CLP3_WR(x, HW_ADC_CLP3_RD(x) ^ (v)))
1675 * Constants & macros for individual ADC_CLP3 bitfields
1679 * @name Register ADC_CLP3, field CLP3[8:0] (RW)
1684 #define BP_ADC_CLP3_CLP3 (0U) /*!< Bit position for ADC_CLP3_CLP3. */
1685 #define BM_ADC_CLP3_CLP3 (0x000001FFU) /*!< Bit mask for ADC_CLP3_CLP3. */
1686 #define BS_ADC_CLP3_CLP3 (9U) /*!< Bit field size in bits for ADC_CLP3_CLP3. */
1688 /*! @brief Read current value of the ADC_CLP3_CLP3 field. */
1689 #define BR_ADC_CLP3_CLP3(x) (HW_ADC_CLP3(x).B.CLP3)
1691 /*! @brief Format value for bitfield ADC_CLP3_CLP3. */
1692 #define BF_ADC_CLP3_CLP3(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLP3_CLP3) & BM_ADC_CLP3_CLP3)
1694 /*! @brief Set the CLP3 field to a new value. */
1695 #define BW_ADC_CLP3_CLP3(x, v) (HW_ADC_CLP3_WR(x, (HW_ADC_CLP3_RD(x) & ~BM_ADC_CLP3_CLP3) | BF_ADC_CLP3_CLP3(v)))
1698 /*******************************************************************************
1699 * HW_ADC_CLP2 - ADC Plus-Side General Calibration Value Register
1700 ******************************************************************************/
1703 * @brief HW_ADC_CLP2 - ADC Plus-Side General Calibration Value Register (RW)
1705 * Reset value: 0x00000080U
1707 * For more information, see CLPD register description.
1709 typedef union _hw_adc_clp2
1712 struct _hw_adc_clp2_bitfields
1714 uint32_t CLP2
: 8; /*!< [7:0] */
1715 uint32_t RESERVED0
: 24; /*!< [31:8] */
1720 * @name Constants and macros for entire ADC_CLP2 register
1723 #define HW_ADC_CLP2_ADDR(x) ((x) + 0x44U)
1725 #define HW_ADC_CLP2(x) (*(__IO hw_adc_clp2_t *) HW_ADC_CLP2_ADDR(x))
1726 #define HW_ADC_CLP2_RD(x) (HW_ADC_CLP2(x).U)
1727 #define HW_ADC_CLP2_WR(x, v) (HW_ADC_CLP2(x).U = (v))
1728 #define HW_ADC_CLP2_SET(x, v) (HW_ADC_CLP2_WR(x, HW_ADC_CLP2_RD(x) | (v)))
1729 #define HW_ADC_CLP2_CLR(x, v) (HW_ADC_CLP2_WR(x, HW_ADC_CLP2_RD(x) & ~(v)))
1730 #define HW_ADC_CLP2_TOG(x, v) (HW_ADC_CLP2_WR(x, HW_ADC_CLP2_RD(x) ^ (v)))
1734 * Constants & macros for individual ADC_CLP2 bitfields
1738 * @name Register ADC_CLP2, field CLP2[7:0] (RW)
1743 #define BP_ADC_CLP2_CLP2 (0U) /*!< Bit position for ADC_CLP2_CLP2. */
1744 #define BM_ADC_CLP2_CLP2 (0x000000FFU) /*!< Bit mask for ADC_CLP2_CLP2. */
1745 #define BS_ADC_CLP2_CLP2 (8U) /*!< Bit field size in bits for ADC_CLP2_CLP2. */
1747 /*! @brief Read current value of the ADC_CLP2_CLP2 field. */
1748 #define BR_ADC_CLP2_CLP2(x) (HW_ADC_CLP2(x).B.CLP2)
1750 /*! @brief Format value for bitfield ADC_CLP2_CLP2. */
1751 #define BF_ADC_CLP2_CLP2(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLP2_CLP2) & BM_ADC_CLP2_CLP2)
1753 /*! @brief Set the CLP2 field to a new value. */
1754 #define BW_ADC_CLP2_CLP2(x, v) (HW_ADC_CLP2_WR(x, (HW_ADC_CLP2_RD(x) & ~BM_ADC_CLP2_CLP2) | BF_ADC_CLP2_CLP2(v)))
1757 /*******************************************************************************
1758 * HW_ADC_CLP1 - ADC Plus-Side General Calibration Value Register
1759 ******************************************************************************/
1762 * @brief HW_ADC_CLP1 - ADC Plus-Side General Calibration Value Register (RW)
1764 * Reset value: 0x00000040U
1766 * For more information, see CLPD register description.
1768 typedef union _hw_adc_clp1
1771 struct _hw_adc_clp1_bitfields
1773 uint32_t CLP1
: 7; /*!< [6:0] */
1774 uint32_t RESERVED0
: 25; /*!< [31:7] */
1779 * @name Constants and macros for entire ADC_CLP1 register
1782 #define HW_ADC_CLP1_ADDR(x) ((x) + 0x48U)
1784 #define HW_ADC_CLP1(x) (*(__IO hw_adc_clp1_t *) HW_ADC_CLP1_ADDR(x))
1785 #define HW_ADC_CLP1_RD(x) (HW_ADC_CLP1(x).U)
1786 #define HW_ADC_CLP1_WR(x, v) (HW_ADC_CLP1(x).U = (v))
1787 #define HW_ADC_CLP1_SET(x, v) (HW_ADC_CLP1_WR(x, HW_ADC_CLP1_RD(x) | (v)))
1788 #define HW_ADC_CLP1_CLR(x, v) (HW_ADC_CLP1_WR(x, HW_ADC_CLP1_RD(x) & ~(v)))
1789 #define HW_ADC_CLP1_TOG(x, v) (HW_ADC_CLP1_WR(x, HW_ADC_CLP1_RD(x) ^ (v)))
1793 * Constants & macros for individual ADC_CLP1 bitfields
1797 * @name Register ADC_CLP1, field CLP1[6:0] (RW)
1802 #define BP_ADC_CLP1_CLP1 (0U) /*!< Bit position for ADC_CLP1_CLP1. */
1803 #define BM_ADC_CLP1_CLP1 (0x0000007FU) /*!< Bit mask for ADC_CLP1_CLP1. */
1804 #define BS_ADC_CLP1_CLP1 (7U) /*!< Bit field size in bits for ADC_CLP1_CLP1. */
1806 /*! @brief Read current value of the ADC_CLP1_CLP1 field. */
1807 #define BR_ADC_CLP1_CLP1(x) (HW_ADC_CLP1(x).B.CLP1)
1809 /*! @brief Format value for bitfield ADC_CLP1_CLP1. */
1810 #define BF_ADC_CLP1_CLP1(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLP1_CLP1) & BM_ADC_CLP1_CLP1)
1812 /*! @brief Set the CLP1 field to a new value. */
1813 #define BW_ADC_CLP1_CLP1(x, v) (HW_ADC_CLP1_WR(x, (HW_ADC_CLP1_RD(x) & ~BM_ADC_CLP1_CLP1) | BF_ADC_CLP1_CLP1(v)))
1816 /*******************************************************************************
1817 * HW_ADC_CLP0 - ADC Plus-Side General Calibration Value Register
1818 ******************************************************************************/
1821 * @brief HW_ADC_CLP0 - ADC Plus-Side General Calibration Value Register (RW)
1823 * Reset value: 0x00000020U
1825 * For more information, see CLPD register description.
1827 typedef union _hw_adc_clp0
1830 struct _hw_adc_clp0_bitfields
1832 uint32_t CLP0
: 6; /*!< [5:0] */
1833 uint32_t RESERVED0
: 26; /*!< [31:6] */
1838 * @name Constants and macros for entire ADC_CLP0 register
1841 #define HW_ADC_CLP0_ADDR(x) ((x) + 0x4CU)
1843 #define HW_ADC_CLP0(x) (*(__IO hw_adc_clp0_t *) HW_ADC_CLP0_ADDR(x))
1844 #define HW_ADC_CLP0_RD(x) (HW_ADC_CLP0(x).U)
1845 #define HW_ADC_CLP0_WR(x, v) (HW_ADC_CLP0(x).U = (v))
1846 #define HW_ADC_CLP0_SET(x, v) (HW_ADC_CLP0_WR(x, HW_ADC_CLP0_RD(x) | (v)))
1847 #define HW_ADC_CLP0_CLR(x, v) (HW_ADC_CLP0_WR(x, HW_ADC_CLP0_RD(x) & ~(v)))
1848 #define HW_ADC_CLP0_TOG(x, v) (HW_ADC_CLP0_WR(x, HW_ADC_CLP0_RD(x) ^ (v)))
1852 * Constants & macros for individual ADC_CLP0 bitfields
1856 * @name Register ADC_CLP0, field CLP0[5:0] (RW)
1861 #define BP_ADC_CLP0_CLP0 (0U) /*!< Bit position for ADC_CLP0_CLP0. */
1862 #define BM_ADC_CLP0_CLP0 (0x0000003FU) /*!< Bit mask for ADC_CLP0_CLP0. */
1863 #define BS_ADC_CLP0_CLP0 (6U) /*!< Bit field size in bits for ADC_CLP0_CLP0. */
1865 /*! @brief Read current value of the ADC_CLP0_CLP0 field. */
1866 #define BR_ADC_CLP0_CLP0(x) (HW_ADC_CLP0(x).B.CLP0)
1868 /*! @brief Format value for bitfield ADC_CLP0_CLP0. */
1869 #define BF_ADC_CLP0_CLP0(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLP0_CLP0) & BM_ADC_CLP0_CLP0)
1871 /*! @brief Set the CLP0 field to a new value. */
1872 #define BW_ADC_CLP0_CLP0(x, v) (HW_ADC_CLP0_WR(x, (HW_ADC_CLP0_RD(x) & ~BM_ADC_CLP0_CLP0) | BF_ADC_CLP0_CLP0(v)))
1875 /*******************************************************************************
1876 * HW_ADC_CLMD - ADC Minus-Side General Calibration Value Register
1877 ******************************************************************************/
1880 * @brief HW_ADC_CLMD - ADC Minus-Side General Calibration Value Register (RW)
1882 * Reset value: 0x0000000AU
1884 * The Minus-Side General Calibration Value (CLMx) registers contain calibration
1885 * information that is generated by the calibration function. These registers
1886 * contain seven calibration values of varying widths: CLM0[5:0], CLM1[6:0],
1887 * CLM2[7:0], CLM3[8:0], CLM4[9:0], CLMS[5:0], and CLMD[5:0]. CLMx are automatically
1888 * set when the self-calibration sequence is done, that is, CAL is cleared. If
1889 * these registers are written by the user after calibration, the linearity error
1890 * specifications may not be met.
1892 typedef union _hw_adc_clmd
1895 struct _hw_adc_clmd_bitfields
1897 uint32_t CLMD
: 6; /*!< [5:0] */
1898 uint32_t RESERVED0
: 26; /*!< [31:6] */
1903 * @name Constants and macros for entire ADC_CLMD register
1906 #define HW_ADC_CLMD_ADDR(x) ((x) + 0x54U)
1908 #define HW_ADC_CLMD(x) (*(__IO hw_adc_clmd_t *) HW_ADC_CLMD_ADDR(x))
1909 #define HW_ADC_CLMD_RD(x) (HW_ADC_CLMD(x).U)
1910 #define HW_ADC_CLMD_WR(x, v) (HW_ADC_CLMD(x).U = (v))
1911 #define HW_ADC_CLMD_SET(x, v) (HW_ADC_CLMD_WR(x, HW_ADC_CLMD_RD(x) | (v)))
1912 #define HW_ADC_CLMD_CLR(x, v) (HW_ADC_CLMD_WR(x, HW_ADC_CLMD_RD(x) & ~(v)))
1913 #define HW_ADC_CLMD_TOG(x, v) (HW_ADC_CLMD_WR(x, HW_ADC_CLMD_RD(x) ^ (v)))
1917 * Constants & macros for individual ADC_CLMD bitfields
1921 * @name Register ADC_CLMD, field CLMD[5:0] (RW)
1926 #define BP_ADC_CLMD_CLMD (0U) /*!< Bit position for ADC_CLMD_CLMD. */
1927 #define BM_ADC_CLMD_CLMD (0x0000003FU) /*!< Bit mask for ADC_CLMD_CLMD. */
1928 #define BS_ADC_CLMD_CLMD (6U) /*!< Bit field size in bits for ADC_CLMD_CLMD. */
1930 /*! @brief Read current value of the ADC_CLMD_CLMD field. */
1931 #define BR_ADC_CLMD_CLMD(x) (HW_ADC_CLMD(x).B.CLMD)
1933 /*! @brief Format value for bitfield ADC_CLMD_CLMD. */
1934 #define BF_ADC_CLMD_CLMD(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLMD_CLMD) & BM_ADC_CLMD_CLMD)
1936 /*! @brief Set the CLMD field to a new value. */
1937 #define BW_ADC_CLMD_CLMD(x, v) (HW_ADC_CLMD_WR(x, (HW_ADC_CLMD_RD(x) & ~BM_ADC_CLMD_CLMD) | BF_ADC_CLMD_CLMD(v)))
1940 /*******************************************************************************
1941 * HW_ADC_CLMS - ADC Minus-Side General Calibration Value Register
1942 ******************************************************************************/
1945 * @brief HW_ADC_CLMS - ADC Minus-Side General Calibration Value Register (RW)
1947 * Reset value: 0x00000020U
1949 * For more information, see CLMD register description.
1951 typedef union _hw_adc_clms
1954 struct _hw_adc_clms_bitfields
1956 uint32_t CLMS
: 6; /*!< [5:0] */
1957 uint32_t RESERVED0
: 26; /*!< [31:6] */
1962 * @name Constants and macros for entire ADC_CLMS register
1965 #define HW_ADC_CLMS_ADDR(x) ((x) + 0x58U)
1967 #define HW_ADC_CLMS(x) (*(__IO hw_adc_clms_t *) HW_ADC_CLMS_ADDR(x))
1968 #define HW_ADC_CLMS_RD(x) (HW_ADC_CLMS(x).U)
1969 #define HW_ADC_CLMS_WR(x, v) (HW_ADC_CLMS(x).U = (v))
1970 #define HW_ADC_CLMS_SET(x, v) (HW_ADC_CLMS_WR(x, HW_ADC_CLMS_RD(x) | (v)))
1971 #define HW_ADC_CLMS_CLR(x, v) (HW_ADC_CLMS_WR(x, HW_ADC_CLMS_RD(x) & ~(v)))
1972 #define HW_ADC_CLMS_TOG(x, v) (HW_ADC_CLMS_WR(x, HW_ADC_CLMS_RD(x) ^ (v)))
1976 * Constants & macros for individual ADC_CLMS bitfields
1980 * @name Register ADC_CLMS, field CLMS[5:0] (RW)
1985 #define BP_ADC_CLMS_CLMS (0U) /*!< Bit position for ADC_CLMS_CLMS. */
1986 #define BM_ADC_CLMS_CLMS (0x0000003FU) /*!< Bit mask for ADC_CLMS_CLMS. */
1987 #define BS_ADC_CLMS_CLMS (6U) /*!< Bit field size in bits for ADC_CLMS_CLMS. */
1989 /*! @brief Read current value of the ADC_CLMS_CLMS field. */
1990 #define BR_ADC_CLMS_CLMS(x) (HW_ADC_CLMS(x).B.CLMS)
1992 /*! @brief Format value for bitfield ADC_CLMS_CLMS. */
1993 #define BF_ADC_CLMS_CLMS(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLMS_CLMS) & BM_ADC_CLMS_CLMS)
1995 /*! @brief Set the CLMS field to a new value. */
1996 #define BW_ADC_CLMS_CLMS(x, v) (HW_ADC_CLMS_WR(x, (HW_ADC_CLMS_RD(x) & ~BM_ADC_CLMS_CLMS) | BF_ADC_CLMS_CLMS(v)))
1999 /*******************************************************************************
2000 * HW_ADC_CLM4 - ADC Minus-Side General Calibration Value Register
2001 ******************************************************************************/
2004 * @brief HW_ADC_CLM4 - ADC Minus-Side General Calibration Value Register (RW)
2006 * Reset value: 0x00000200U
2008 * For more information, see CLMD register description.
2010 typedef union _hw_adc_clm4
2013 struct _hw_adc_clm4_bitfields
2015 uint32_t CLM4
: 10; /*!< [9:0] */
2016 uint32_t RESERVED0
: 22; /*!< [31:10] */
2021 * @name Constants and macros for entire ADC_CLM4 register
2024 #define HW_ADC_CLM4_ADDR(x) ((x) + 0x5CU)
2026 #define HW_ADC_CLM4(x) (*(__IO hw_adc_clm4_t *) HW_ADC_CLM4_ADDR(x))
2027 #define HW_ADC_CLM4_RD(x) (HW_ADC_CLM4(x).U)
2028 #define HW_ADC_CLM4_WR(x, v) (HW_ADC_CLM4(x).U = (v))
2029 #define HW_ADC_CLM4_SET(x, v) (HW_ADC_CLM4_WR(x, HW_ADC_CLM4_RD(x) | (v)))
2030 #define HW_ADC_CLM4_CLR(x, v) (HW_ADC_CLM4_WR(x, HW_ADC_CLM4_RD(x) & ~(v)))
2031 #define HW_ADC_CLM4_TOG(x, v) (HW_ADC_CLM4_WR(x, HW_ADC_CLM4_RD(x) ^ (v)))
2035 * Constants & macros for individual ADC_CLM4 bitfields
2039 * @name Register ADC_CLM4, field CLM4[9:0] (RW)
2044 #define BP_ADC_CLM4_CLM4 (0U) /*!< Bit position for ADC_CLM4_CLM4. */
2045 #define BM_ADC_CLM4_CLM4 (0x000003FFU) /*!< Bit mask for ADC_CLM4_CLM4. */
2046 #define BS_ADC_CLM4_CLM4 (10U) /*!< Bit field size in bits for ADC_CLM4_CLM4. */
2048 /*! @brief Read current value of the ADC_CLM4_CLM4 field. */
2049 #define BR_ADC_CLM4_CLM4(x) (HW_ADC_CLM4(x).B.CLM4)
2051 /*! @brief Format value for bitfield ADC_CLM4_CLM4. */
2052 #define BF_ADC_CLM4_CLM4(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLM4_CLM4) & BM_ADC_CLM4_CLM4)
2054 /*! @brief Set the CLM4 field to a new value. */
2055 #define BW_ADC_CLM4_CLM4(x, v) (HW_ADC_CLM4_WR(x, (HW_ADC_CLM4_RD(x) & ~BM_ADC_CLM4_CLM4) | BF_ADC_CLM4_CLM4(v)))
2058 /*******************************************************************************
2059 * HW_ADC_CLM3 - ADC Minus-Side General Calibration Value Register
2060 ******************************************************************************/
2063 * @brief HW_ADC_CLM3 - ADC Minus-Side General Calibration Value Register (RW)
2065 * Reset value: 0x00000100U
2067 * For more information, see CLMD register description.
2069 typedef union _hw_adc_clm3
2072 struct _hw_adc_clm3_bitfields
2074 uint32_t CLM3
: 9; /*!< [8:0] */
2075 uint32_t RESERVED0
: 23; /*!< [31:9] */
2080 * @name Constants and macros for entire ADC_CLM3 register
2083 #define HW_ADC_CLM3_ADDR(x) ((x) + 0x60U)
2085 #define HW_ADC_CLM3(x) (*(__IO hw_adc_clm3_t *) HW_ADC_CLM3_ADDR(x))
2086 #define HW_ADC_CLM3_RD(x) (HW_ADC_CLM3(x).U)
2087 #define HW_ADC_CLM3_WR(x, v) (HW_ADC_CLM3(x).U = (v))
2088 #define HW_ADC_CLM3_SET(x, v) (HW_ADC_CLM3_WR(x, HW_ADC_CLM3_RD(x) | (v)))
2089 #define HW_ADC_CLM3_CLR(x, v) (HW_ADC_CLM3_WR(x, HW_ADC_CLM3_RD(x) & ~(v)))
2090 #define HW_ADC_CLM3_TOG(x, v) (HW_ADC_CLM3_WR(x, HW_ADC_CLM3_RD(x) ^ (v)))
2094 * Constants & macros for individual ADC_CLM3 bitfields
2098 * @name Register ADC_CLM3, field CLM3[8:0] (RW)
2103 #define BP_ADC_CLM3_CLM3 (0U) /*!< Bit position for ADC_CLM3_CLM3. */
2104 #define BM_ADC_CLM3_CLM3 (0x000001FFU) /*!< Bit mask for ADC_CLM3_CLM3. */
2105 #define BS_ADC_CLM3_CLM3 (9U) /*!< Bit field size in bits for ADC_CLM3_CLM3. */
2107 /*! @brief Read current value of the ADC_CLM3_CLM3 field. */
2108 #define BR_ADC_CLM3_CLM3(x) (HW_ADC_CLM3(x).B.CLM3)
2110 /*! @brief Format value for bitfield ADC_CLM3_CLM3. */
2111 #define BF_ADC_CLM3_CLM3(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLM3_CLM3) & BM_ADC_CLM3_CLM3)
2113 /*! @brief Set the CLM3 field to a new value. */
2114 #define BW_ADC_CLM3_CLM3(x, v) (HW_ADC_CLM3_WR(x, (HW_ADC_CLM3_RD(x) & ~BM_ADC_CLM3_CLM3) | BF_ADC_CLM3_CLM3(v)))
2117 /*******************************************************************************
2118 * HW_ADC_CLM2 - ADC Minus-Side General Calibration Value Register
2119 ******************************************************************************/
2122 * @brief HW_ADC_CLM2 - ADC Minus-Side General Calibration Value Register (RW)
2124 * Reset value: 0x00000080U
2126 * For more information, see CLMD register description.
2128 typedef union _hw_adc_clm2
2131 struct _hw_adc_clm2_bitfields
2133 uint32_t CLM2
: 8; /*!< [7:0] */
2134 uint32_t RESERVED0
: 24; /*!< [31:8] */
2139 * @name Constants and macros for entire ADC_CLM2 register
2142 #define HW_ADC_CLM2_ADDR(x) ((x) + 0x64U)
2144 #define HW_ADC_CLM2(x) (*(__IO hw_adc_clm2_t *) HW_ADC_CLM2_ADDR(x))
2145 #define HW_ADC_CLM2_RD(x) (HW_ADC_CLM2(x).U)
2146 #define HW_ADC_CLM2_WR(x, v) (HW_ADC_CLM2(x).U = (v))
2147 #define HW_ADC_CLM2_SET(x, v) (HW_ADC_CLM2_WR(x, HW_ADC_CLM2_RD(x) | (v)))
2148 #define HW_ADC_CLM2_CLR(x, v) (HW_ADC_CLM2_WR(x, HW_ADC_CLM2_RD(x) & ~(v)))
2149 #define HW_ADC_CLM2_TOG(x, v) (HW_ADC_CLM2_WR(x, HW_ADC_CLM2_RD(x) ^ (v)))
2153 * Constants & macros for individual ADC_CLM2 bitfields
2157 * @name Register ADC_CLM2, field CLM2[7:0] (RW)
2162 #define BP_ADC_CLM2_CLM2 (0U) /*!< Bit position for ADC_CLM2_CLM2. */
2163 #define BM_ADC_CLM2_CLM2 (0x000000FFU) /*!< Bit mask for ADC_CLM2_CLM2. */
2164 #define BS_ADC_CLM2_CLM2 (8U) /*!< Bit field size in bits for ADC_CLM2_CLM2. */
2166 /*! @brief Read current value of the ADC_CLM2_CLM2 field. */
2167 #define BR_ADC_CLM2_CLM2(x) (HW_ADC_CLM2(x).B.CLM2)
2169 /*! @brief Format value for bitfield ADC_CLM2_CLM2. */
2170 #define BF_ADC_CLM2_CLM2(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLM2_CLM2) & BM_ADC_CLM2_CLM2)
2172 /*! @brief Set the CLM2 field to a new value. */
2173 #define BW_ADC_CLM2_CLM2(x, v) (HW_ADC_CLM2_WR(x, (HW_ADC_CLM2_RD(x) & ~BM_ADC_CLM2_CLM2) | BF_ADC_CLM2_CLM2(v)))
2176 /*******************************************************************************
2177 * HW_ADC_CLM1 - ADC Minus-Side General Calibration Value Register
2178 ******************************************************************************/
2181 * @brief HW_ADC_CLM1 - ADC Minus-Side General Calibration Value Register (RW)
2183 * Reset value: 0x00000040U
2185 * For more information, see CLMD register description.
2187 typedef union _hw_adc_clm1
2190 struct _hw_adc_clm1_bitfields
2192 uint32_t CLM1
: 7; /*!< [6:0] */
2193 uint32_t RESERVED0
: 25; /*!< [31:7] */
2198 * @name Constants and macros for entire ADC_CLM1 register
2201 #define HW_ADC_CLM1_ADDR(x) ((x) + 0x68U)
2203 #define HW_ADC_CLM1(x) (*(__IO hw_adc_clm1_t *) HW_ADC_CLM1_ADDR(x))
2204 #define HW_ADC_CLM1_RD(x) (HW_ADC_CLM1(x).U)
2205 #define HW_ADC_CLM1_WR(x, v) (HW_ADC_CLM1(x).U = (v))
2206 #define HW_ADC_CLM1_SET(x, v) (HW_ADC_CLM1_WR(x, HW_ADC_CLM1_RD(x) | (v)))
2207 #define HW_ADC_CLM1_CLR(x, v) (HW_ADC_CLM1_WR(x, HW_ADC_CLM1_RD(x) & ~(v)))
2208 #define HW_ADC_CLM1_TOG(x, v) (HW_ADC_CLM1_WR(x, HW_ADC_CLM1_RD(x) ^ (v)))
2212 * Constants & macros for individual ADC_CLM1 bitfields
2216 * @name Register ADC_CLM1, field CLM1[6:0] (RW)
2221 #define BP_ADC_CLM1_CLM1 (0U) /*!< Bit position for ADC_CLM1_CLM1. */
2222 #define BM_ADC_CLM1_CLM1 (0x0000007FU) /*!< Bit mask for ADC_CLM1_CLM1. */
2223 #define BS_ADC_CLM1_CLM1 (7U) /*!< Bit field size in bits for ADC_CLM1_CLM1. */
2225 /*! @brief Read current value of the ADC_CLM1_CLM1 field. */
2226 #define BR_ADC_CLM1_CLM1(x) (HW_ADC_CLM1(x).B.CLM1)
2228 /*! @brief Format value for bitfield ADC_CLM1_CLM1. */
2229 #define BF_ADC_CLM1_CLM1(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLM1_CLM1) & BM_ADC_CLM1_CLM1)
2231 /*! @brief Set the CLM1 field to a new value. */
2232 #define BW_ADC_CLM1_CLM1(x, v) (HW_ADC_CLM1_WR(x, (HW_ADC_CLM1_RD(x) & ~BM_ADC_CLM1_CLM1) | BF_ADC_CLM1_CLM1(v)))
2235 /*******************************************************************************
2236 * HW_ADC_CLM0 - ADC Minus-Side General Calibration Value Register
2237 ******************************************************************************/
2240 * @brief HW_ADC_CLM0 - ADC Minus-Side General Calibration Value Register (RW)
2242 * Reset value: 0x00000020U
2244 * For more information, see CLMD register description.
2246 typedef union _hw_adc_clm0
2249 struct _hw_adc_clm0_bitfields
2251 uint32_t CLM0
: 6; /*!< [5:0] */
2252 uint32_t RESERVED0
: 26; /*!< [31:6] */
2257 * @name Constants and macros for entire ADC_CLM0 register
2260 #define HW_ADC_CLM0_ADDR(x) ((x) + 0x6CU)
2262 #define HW_ADC_CLM0(x) (*(__IO hw_adc_clm0_t *) HW_ADC_CLM0_ADDR(x))
2263 #define HW_ADC_CLM0_RD(x) (HW_ADC_CLM0(x).U)
2264 #define HW_ADC_CLM0_WR(x, v) (HW_ADC_CLM0(x).U = (v))
2265 #define HW_ADC_CLM0_SET(x, v) (HW_ADC_CLM0_WR(x, HW_ADC_CLM0_RD(x) | (v)))
2266 #define HW_ADC_CLM0_CLR(x, v) (HW_ADC_CLM0_WR(x, HW_ADC_CLM0_RD(x) & ~(v)))
2267 #define HW_ADC_CLM0_TOG(x, v) (HW_ADC_CLM0_WR(x, HW_ADC_CLM0_RD(x) ^ (v)))
2271 * Constants & macros for individual ADC_CLM0 bitfields
2275 * @name Register ADC_CLM0, field CLM0[5:0] (RW)
2280 #define BP_ADC_CLM0_CLM0 (0U) /*!< Bit position for ADC_CLM0_CLM0. */
2281 #define BM_ADC_CLM0_CLM0 (0x0000003FU) /*!< Bit mask for ADC_CLM0_CLM0. */
2282 #define BS_ADC_CLM0_CLM0 (6U) /*!< Bit field size in bits for ADC_CLM0_CLM0. */
2284 /*! @brief Read current value of the ADC_CLM0_CLM0 field. */
2285 #define BR_ADC_CLM0_CLM0(x) (HW_ADC_CLM0(x).B.CLM0)
2287 /*! @brief Format value for bitfield ADC_CLM0_CLM0. */
2288 #define BF_ADC_CLM0_CLM0(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLM0_CLM0) & BM_ADC_CLM0_CLM0)
2290 /*! @brief Set the CLM0 field to a new value. */
2291 #define BW_ADC_CLM0_CLM0(x, v) (HW_ADC_CLM0_WR(x, (HW_ADC_CLM0_RD(x) & ~BM_ADC_CLM0_CLM0) | BF_ADC_CLM0_CLM0(v)))
2294 /*******************************************************************************
2295 * hw_adc_t - module struct
2296 ******************************************************************************/
2298 * @brief All ADC module registers.
2301 typedef struct _hw_adc
2303 __IO hw_adc_sc1n_t SC1n
[2]; /*!< [0x0] ADC Status and Control Registers 1 */
2304 __IO hw_adc_cfg1_t CFG1
; /*!< [0x8] ADC Configuration Register 1 */
2305 __IO hw_adc_cfg2_t CFG2
; /*!< [0xC] ADC Configuration Register 2 */
2306 __I hw_adc_rn_t Rn
[2]; /*!< [0x10] ADC Data Result Register */
2307 __IO hw_adc_cv1_t CV1
; /*!< [0x18] Compare Value Registers */
2308 __IO hw_adc_cv2_t CV2
; /*!< [0x1C] Compare Value Registers */
2309 __IO hw_adc_sc2_t SC2
; /*!< [0x20] Status and Control Register 2 */
2310 __IO hw_adc_sc3_t SC3
; /*!< [0x24] Status and Control Register 3 */
2311 __IO hw_adc_ofs_t OFS
; /*!< [0x28] ADC Offset Correction Register */
2312 __IO hw_adc_pg_t PG
; /*!< [0x2C] ADC Plus-Side Gain Register */
2313 __IO hw_adc_mg_t MG
; /*!< [0x30] ADC Minus-Side Gain Register */
2314 __IO hw_adc_clpd_t CLPD
; /*!< [0x34] ADC Plus-Side General Calibration Value Register */
2315 __IO hw_adc_clps_t CLPS
; /*!< [0x38] ADC Plus-Side General Calibration Value Register */
2316 __IO hw_adc_clp4_t CLP4
; /*!< [0x3C] ADC Plus-Side General Calibration Value Register */
2317 __IO hw_adc_clp3_t CLP3
; /*!< [0x40] ADC Plus-Side General Calibration Value Register */
2318 __IO hw_adc_clp2_t CLP2
; /*!< [0x44] ADC Plus-Side General Calibration Value Register */
2319 __IO hw_adc_clp1_t CLP1
; /*!< [0x48] ADC Plus-Side General Calibration Value Register */
2320 __IO hw_adc_clp0_t CLP0
; /*!< [0x4C] ADC Plus-Side General Calibration Value Register */
2321 uint8_t _reserved0
[4];
2322 __IO hw_adc_clmd_t CLMD
; /*!< [0x54] ADC Minus-Side General Calibration Value Register */
2323 __IO hw_adc_clms_t CLMS
; /*!< [0x58] ADC Minus-Side General Calibration Value Register */
2324 __IO hw_adc_clm4_t CLM4
; /*!< [0x5C] ADC Minus-Side General Calibration Value Register */
2325 __IO hw_adc_clm3_t CLM3
; /*!< [0x60] ADC Minus-Side General Calibration Value Register */
2326 __IO hw_adc_clm2_t CLM2
; /*!< [0x64] ADC Minus-Side General Calibration Value Register */
2327 __IO hw_adc_clm1_t CLM1
; /*!< [0x68] ADC Minus-Side General Calibration Value Register */
2328 __IO hw_adc_clm0_t CLM0
; /*!< [0x6C] ADC Minus-Side General Calibration Value Register */
2332 /*! @brief Macro to access all ADC registers. */
2333 /*! @param x ADC module instance base address. */
2334 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
2335 * use the '&' operator, like <code>&HW_ADC(ADC0_BASE)</code>. */
2336 #define HW_ADC(x) (*(hw_adc_t *)(x))
2338 #endif /* __HW_ADC_REGISTERS_H__ */