tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_cmp.h

   1 /*
   2 ** ###################################################################
   3 **     Compilers:           Keil ARM C/C++ Compiler
   4 **                          Freescale C/C++ for Embedded ARM
   5 **                          GNU C Compiler
   6 **                          IAR ANSI C/C++ Compiler for ARM
   7 **
   8 **     Reference manual:    K22P121M120SF7RM, Rev. 1, March 24, 2014
   9 **     Version:             rev. 2.5, 2014-05-06
  10 **     Build:               b140604
  11 **
  12 **     Abstract:
  13 **         Extension to the CMSIS register access layer header.
  14 **
  15 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
  16 **     All rights reserved.
  17 **
  18 **     Redistribution and use in source and binary forms, with or without modification,
  19 **     are permitted provided that the following conditions are met:
  20 **
  21 **     o Redistributions of source code must retain the above copyright notice, this list
  22 **       of conditions and the following disclaimer.
  23 **
  24 **     o Redistributions in binary form must reproduce the above copyright notice, this
  25 **       list of conditions and the following disclaimer in the documentation and/or
  26 **       other materials provided with the distribution.
  27 **
  28 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  29 **       contributors may be used to endorse or promote products derived from this
  30 **       software without specific prior written permission.
  31 **
  32 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  33 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  34 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  35 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  36 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  37 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  38 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  39 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  41 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42 **
  43 **     http:                 www.freescale.com
  44 **     mail:                 support@freescale.com
  45 **
  46 **     Revisions:
  47 **     - rev. 1.0 (2013-07-23)
  48 **         Initial version.
  49 **     - rev. 1.1 (2013-09-17)
  50 **         RM rev. 0.4 update.
  51 **     - rev. 2.0 (2013-10-29)
  52 **         Register accessor macros added to the memory map.
  53 **         Symbols for Processor Expert memory map compatibility added to the memory map.
  54 **         Startup file for gcc has been updated according to CMSIS 3.2.
  55 **         System initialization updated.
  56 **     - rev. 2.1 (2013-10-30)
  57 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
  58 **     - rev. 2.2 (2013-12-20)
  59 **         Update according to reference manual rev. 0.6,
  60 **     - rev. 2.3 (2014-01-13)
  61 **         Update according to reference manual rev. 0.61,
  62 **     - rev. 2.4 (2014-02-10)
  63 **         The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
  64 **     - rev. 2.5 (2014-05-06)
  65 **         Update according to reference manual rev. 1.0,
  66 **         Update of system and startup files.
  67 **         Module access macro module_BASES replaced by module_BASE_PTRS.
  68 **
  69 ** ###################################################################
  70 */
  71
  72 /*
  73  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
  74  *
  75  * This file was generated automatically and any changes may be lost.
  76  */
  77 #ifndef __HW_CMP_REGISTERS_H__
  78 #define __HW_CMP_REGISTERS_H__
  79
  80 #include "MK22F51212.h"
  81 #include "fsl_bitaccess.h"
  82
  83 /*
  84  * MK22F51212 CMP
  85  *
  86  * High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)
  87  *
  88  * Registers defined in this header file:
  89  * - HW_CMP_CR0 - CMP Control Register 0
  90  * - HW_CMP_CR1 - CMP Control Register 1
  91  * - HW_CMP_FPR - CMP Filter Period Register
  92  * - HW_CMP_SCR - CMP Status and Control Register
  93  * - HW_CMP_DACCR - DAC Control Register
  94  * - HW_CMP_MUXCR - MUX Control Register
  95  *
  96  * - hw_cmp_t - Struct containing all module registers.
  97  */
  98
  99 #define HW_CMP_INSTANCE_COUNT (2U) /*!< Number of instances of the CMP module. */
 100 #define HW_CMP0 (0U) /*!< Instance number for CMP0. */
 101 #define HW_CMP1 (1U) /*!< Instance number for CMP1. */
 102
 103 /*******************************************************************************
 104  * HW_CMP_CR0 - CMP Control Register 0
 105  ******************************************************************************/
 106
 107 /*!
 108  * @brief HW_CMP_CR0 - CMP Control Register 0 (RW)
 109  *
 110  * Reset value: 0x00U
 111  */
 112 typedef union _hw_cmp_cr0
 113 {
 114     uint8_t U;
 115     struct _hw_cmp_cr0_bitfields
 116     {
 117         uint8_t HYSTCTR : 2;           /*!< [1:0] Comparator hard block hysteresis
 118                                         * control */
 119         uint8_t RESERVED0 : 2;         /*!< [3:2]  */
 120         uint8_t FILTER_CNT : 3;        /*!< [6:4] Filter Sample Count */
 121         uint8_t RESERVED1 : 1;         /*!< [7]  */
 122     } B;
 123 } hw_cmp_cr0_t;
 124
 125 /*!
 126  * @name Constants and macros for entire CMP_CR0 register
 127  */
 128 /*@{*/
 129 #define HW_CMP_CR0_ADDR(x)       ((x) + 0x0U)
 130
 131 #define HW_CMP_CR0(x)            (*(__IO hw_cmp_cr0_t *) HW_CMP_CR0_ADDR(x))
 132 #define HW_CMP_CR0_RD(x)         (HW_CMP_CR0(x).U)
 133 #define HW_CMP_CR0_WR(x, v)      (HW_CMP_CR0(x).U = (v))
 134 #define HW_CMP_CR0_SET(x, v)     (HW_CMP_CR0_WR(x, HW_CMP_CR0_RD(x) |  (v)))
 135 #define HW_CMP_CR0_CLR(x, v)     (HW_CMP_CR0_WR(x, HW_CMP_CR0_RD(x) & ~(v)))
 136 #define HW_CMP_CR0_TOG(x, v)     (HW_CMP_CR0_WR(x, HW_CMP_CR0_RD(x) ^  (v)))
 137 /*@}*/
 138
 139 /*
 140  * Constants & macros for individual CMP_CR0 bitfields
 141  */
 142
 143 /*!
 144  * @name Register CMP_CR0, field HYSTCTR[1:0] (RW)
 145  *
 146  * Defines the programmable hysteresis level. The hysteresis values associated
 147  * with each level are device-specific. See the Data Sheet of the device for the
 148  * exact values.
 149  *
 150  * Values:
 151  * - 00 - Level 0
 152  * - 01 - Level 1
 153  * - 10 - Level 2
 154  * - 11 - Level 3
 155  */
 156 /*@{*/
 157 #define BP_CMP_CR0_HYSTCTR   (0U)          /*!< Bit position for CMP_CR0_HYSTCTR. */
 158 #define BM_CMP_CR0_HYSTCTR   (0x03U)       /*!< Bit mask for CMP_CR0_HYSTCTR. */
 159 #define BS_CMP_CR0_HYSTCTR   (2U)          /*!< Bit field size in bits for CMP_CR0_HYSTCTR. */
 160
 161 /*! @brief Read current value of the CMP_CR0_HYSTCTR field. */
 162 #define BR_CMP_CR0_HYSTCTR(x) (HW_CMP_CR0(x).B.HYSTCTR)
 163
 164 /*! @brief Format value for bitfield CMP_CR0_HYSTCTR. */
 165 #define BF_CMP_CR0_HYSTCTR(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR0_HYSTCTR) & BM_CMP_CR0_HYSTCTR)
 166
 167 /*! @brief Set the HYSTCTR field to a new value. */
 168 #define BW_CMP_CR0_HYSTCTR(x, v) (HW_CMP_CR0_WR(x, (HW_CMP_CR0_RD(x) & ~BM_CMP_CR0_HYSTCTR) | BF_CMP_CR0_HYSTCTR(v)))
 169 /*@}*/
 170
 171 /*!
 172  * @name Register CMP_CR0, field FILTER_CNT[6:4] (RW)
 173  *
 174  * Represents the number of consecutive samples that must agree prior to the
 175  * comparator ouput filter accepting a new output state. For information regarding
 176  * filter programming and latency, see the Functional descriptionThe CMP module
 177  * can be used to compare two analog input voltages applied to INP and INM. .
 178  *
 179  * Values:
 180  * - 000 - Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a
 181  *     legal state, and is not recommended. If SE = 0, COUT = COUTA.
 182  * - 001 - One sample must agree. The comparator output is simply sampled.
 183  * - 010 - 2 consecutive samples must agree.
 184  * - 011 - 3 consecutive samples must agree.
 185  * - 100 - 4 consecutive samples must agree.
 186  * - 101 - 5 consecutive samples must agree.
 187  * - 110 - 6 consecutive samples must agree.
 188  * - 111 - 7 consecutive samples must agree.
 189  */
 190 /*@{*/
 191 #define BP_CMP_CR0_FILTER_CNT (4U)         /*!< Bit position for CMP_CR0_FILTER_CNT. */
 192 #define BM_CMP_CR0_FILTER_CNT (0x70U)      /*!< Bit mask for CMP_CR0_FILTER_CNT. */
 193 #define BS_CMP_CR0_FILTER_CNT (3U)         /*!< Bit field size in bits for CMP_CR0_FILTER_CNT. */
 194
 195 /*! @brief Read current value of the CMP_CR0_FILTER_CNT field. */
 196 #define BR_CMP_CR0_FILTER_CNT(x) (HW_CMP_CR0(x).B.FILTER_CNT)
 197
 198 /*! @brief Format value for bitfield CMP_CR0_FILTER_CNT. */
 199 #define BF_CMP_CR0_FILTER_CNT(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR0_FILTER_CNT) & BM_CMP_CR0_FILTER_CNT)
 200
 201 /*! @brief Set the FILTER_CNT field to a new value. */
 202 #define BW_CMP_CR0_FILTER_CNT(x, v) (HW_CMP_CR0_WR(x, (HW_CMP_CR0_RD(x) & ~BM_CMP_CR0_FILTER_CNT) | BF_CMP_CR0_FILTER_CNT(v)))
 203 /*@}*/
 204
 205 /*******************************************************************************
 206  * HW_CMP_CR1 - CMP Control Register 1
 207  ******************************************************************************/
 208
 209 /*!
 210  * @brief HW_CMP_CR1 - CMP Control Register 1 (RW)
 211  *
 212  * Reset value: 0x00U
 213  */
 214 typedef union _hw_cmp_cr1
 215 {
 216     uint8_t U;
 217     struct _hw_cmp_cr1_bitfields
 218     {
 219         uint8_t EN : 1;                /*!< [0] Comparator Module Enable */
 220         uint8_t OPE : 1;               /*!< [1] Comparator Output Pin Enable */
 221         uint8_t COS : 1;               /*!< [2] Comparator Output Select */
 222         uint8_t INV : 1;               /*!< [3] Comparator INVERT */
 223         uint8_t PMODE : 1;             /*!< [4] Power Mode Select */
 224         uint8_t TRIGM : 1;             /*!< [5] Trigger Mode Enable */
 225         uint8_t WE : 1;                /*!< [6] Windowing Enable */
 226         uint8_t SE : 1;                /*!< [7] Sample Enable */
 227     } B;
 228 } hw_cmp_cr1_t;
 229
 230 /*!
 231  * @name Constants and macros for entire CMP_CR1 register
 232  */
 233 /*@{*/
 234 #define HW_CMP_CR1_ADDR(x)       ((x) + 0x1U)
 235
 236 #define HW_CMP_CR1(x)            (*(__IO hw_cmp_cr1_t *) HW_CMP_CR1_ADDR(x))
 237 #define HW_CMP_CR1_RD(x)         (HW_CMP_CR1(x).U)
 238 #define HW_CMP_CR1_WR(x, v)      (HW_CMP_CR1(x).U = (v))
 239 #define HW_CMP_CR1_SET(x, v)     (HW_CMP_CR1_WR(x, HW_CMP_CR1_RD(x) |  (v)))
 240 #define HW_CMP_CR1_CLR(x, v)     (HW_CMP_CR1_WR(x, HW_CMP_CR1_RD(x) & ~(v)))
 241 #define HW_CMP_CR1_TOG(x, v)     (HW_CMP_CR1_WR(x, HW_CMP_CR1_RD(x) ^  (v)))
 242 /*@}*/
 243
 244 /*
 245  * Constants & macros for individual CMP_CR1 bitfields
 246  */
 247
 248 /*!
 249  * @name Register CMP_CR1, field EN[0] (RW)
 250  *
 251  * Enables the Analog Comparator module. When the module is not enabled, it
 252  * remains in the off state, and consumes no power. When the user selects the same
 253  * input from analog mux to the positive and negative port, the comparator is
 254  * disabled automatically.
 255  *
 256  * Values:
 257  * - 0 - Analog Comparator is disabled.
 258  * - 1 - Analog Comparator is enabled.
 259  */
 260 /*@{*/
 261 #define BP_CMP_CR1_EN        (0U)          /*!< Bit position for CMP_CR1_EN. */
 262 #define BM_CMP_CR1_EN        (0x01U)       /*!< Bit mask for CMP_CR1_EN. */
 263 #define BS_CMP_CR1_EN        (1U)          /*!< Bit field size in bits for CMP_CR1_EN. */
 264
 265 /*! @brief Read current value of the CMP_CR1_EN field. */
 266 #define BR_CMP_CR1_EN(x)     (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_EN))
 267
 268 /*! @brief Format value for bitfield CMP_CR1_EN. */
 269 #define BF_CMP_CR1_EN(v)     ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_EN) & BM_CMP_CR1_EN)
 270
 271 /*! @brief Set the EN field to a new value. */
 272 #define BW_CMP_CR1_EN(x, v)  (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_EN) = (v))
 273 /*@}*/
 274
 275 /*!
 276  * @name Register CMP_CR1, field OPE[1] (RW)
 277  *
 278  * Values:
 279  * - 0 - CMPO is not available on the associated CMPO output pin. If the
 280  *     comparator does not own the pin, this field has no effect.
 281  * - 1 - CMPO is available on the associated CMPO output pin. The comparator
 282  *     output (CMPO) is driven out on the associated CMPO output pin if the
 283  *     comparator owns the pin. If the comparator does not own the field, this bit has no
 284  *     effect.
 285  */
 286 /*@{*/
 287 #define BP_CMP_CR1_OPE       (1U)          /*!< Bit position for CMP_CR1_OPE. */
 288 #define BM_CMP_CR1_OPE       (0x02U)       /*!< Bit mask for CMP_CR1_OPE. */
 289 #define BS_CMP_CR1_OPE       (1U)          /*!< Bit field size in bits for CMP_CR1_OPE. */
 290
 291 /*! @brief Read current value of the CMP_CR1_OPE field. */
 292 #define BR_CMP_CR1_OPE(x)    (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_OPE))
 293
 294 /*! @brief Format value for bitfield CMP_CR1_OPE. */
 295 #define BF_CMP_CR1_OPE(v)    ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_OPE) & BM_CMP_CR1_OPE)
 296
 297 /*! @brief Set the OPE field to a new value. */
 298 #define BW_CMP_CR1_OPE(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_OPE) = (v))
 299 /*@}*/
 300
 301 /*!
 302  * @name Register CMP_CR1, field COS[2] (RW)
 303  *
 304  * Values:
 305  * - 0 - Set the filtered comparator output (CMPO) to equal COUT.
 306  * - 1 - Set the unfiltered comparator output (CMPO) to equal COUTA.
 307  */
 308 /*@{*/
 309 #define BP_CMP_CR1_COS       (2U)          /*!< Bit position for CMP_CR1_COS. */
 310 #define BM_CMP_CR1_COS       (0x04U)       /*!< Bit mask for CMP_CR1_COS. */
 311 #define BS_CMP_CR1_COS       (1U)          /*!< Bit field size in bits for CMP_CR1_COS. */
 312
 313 /*! @brief Read current value of the CMP_CR1_COS field. */
 314 #define BR_CMP_CR1_COS(x)    (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_COS))
 315
 316 /*! @brief Format value for bitfield CMP_CR1_COS. */
 317 #define BF_CMP_CR1_COS(v)    ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_COS) & BM_CMP_CR1_COS)
 318
 319 /*! @brief Set the COS field to a new value. */
 320 #define BW_CMP_CR1_COS(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_COS) = (v))
 321 /*@}*/
 322
 323 /*!
 324  * @name Register CMP_CR1, field INV[3] (RW)
 325  *
 326  * Allows selection of the polarity of the analog comparator function. It is
 327  * also driven to the COUT output, on both the device pin and as SCR[COUT], when
 328  * OPE=0.
 329  *
 330  * Values:
 331  * - 0 - Does not invert the comparator output.
 332  * - 1 - Inverts the comparator output.
 333  */
 334 /*@{*/
 335 #define BP_CMP_CR1_INV       (3U)          /*!< Bit position for CMP_CR1_INV. */
 336 #define BM_CMP_CR1_INV       (0x08U)       /*!< Bit mask for CMP_CR1_INV. */
 337 #define BS_CMP_CR1_INV       (1U)          /*!< Bit field size in bits for CMP_CR1_INV. */
 338
 339 /*! @brief Read current value of the CMP_CR1_INV field. */
 340 #define BR_CMP_CR1_INV(x)    (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_INV))
 341
 342 /*! @brief Format value for bitfield CMP_CR1_INV. */
 343 #define BF_CMP_CR1_INV(v)    ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_INV) & BM_CMP_CR1_INV)
 344
 345 /*! @brief Set the INV field to a new value. */
 346 #define BW_CMP_CR1_INV(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_INV) = (v))
 347 /*@}*/
 348
 349 /*!
 350  * @name Register CMP_CR1, field PMODE[4] (RW)
 351  *
 352  * See the electrical specifications table in the device Data Sheet for details.
 353  *
 354  * Values:
 355  * - 0 - Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower
 356  *     output propagation delay and lower current consumption.
 357  * - 1 - High-Speed (HS) Comparison mode selected. In this mode, CMP has faster
 358  *     output propagation delay and higher current consumption.
 359  */
 360 /*@{*/
 361 #define BP_CMP_CR1_PMODE     (4U)          /*!< Bit position for CMP_CR1_PMODE. */
 362 #define BM_CMP_CR1_PMODE     (0x10U)       /*!< Bit mask for CMP_CR1_PMODE. */
 363 #define BS_CMP_CR1_PMODE     (1U)          /*!< Bit field size in bits for CMP_CR1_PMODE. */
 364
 365 /*! @brief Read current value of the CMP_CR1_PMODE field. */
 366 #define BR_CMP_CR1_PMODE(x)  (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_PMODE))
 367
 368 /*! @brief Format value for bitfield CMP_CR1_PMODE. */
 369 #define BF_CMP_CR1_PMODE(v)  ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_PMODE) & BM_CMP_CR1_PMODE)
 370
 371 /*! @brief Set the PMODE field to a new value. */
 372 #define BW_CMP_CR1_PMODE(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_PMODE) = (v))
 373 /*@}*/
 374
 375 /*!
 376  * @name Register CMP_CR1, field TRIGM[5] (RW)
 377  *
 378  * CMP and DAC are configured to CMP Trigger mode when CMP_CR1[TRIGM] is set to
 379  * 1. In addition, the CMP should be enabled. If the DAC is to be used as a
 380  * reference to the CMP, it should also be enabled. CMP Trigger mode depends on an
 381  * external timer resource to periodically enable the CMP and 6-bit DAC in order to
 382  * generate a triggered compare. Upon setting TRIGM, the CMP and DAC are placed
 383  * in a standby state until an external timer resource trigger is received. See
 384  * the chip configuration for details about the external timer resource.
 385  *
 386  * Values:
 387  * - 0 - Trigger mode is disabled.
 388  * - 1 - Trigger mode is enabled.
 389  */
 390 /*@{*/
 391 #define BP_CMP_CR1_TRIGM     (5U)          /*!< Bit position for CMP_CR1_TRIGM. */
 392 #define BM_CMP_CR1_TRIGM     (0x20U)       /*!< Bit mask for CMP_CR1_TRIGM. */
 393 #define BS_CMP_CR1_TRIGM     (1U)          /*!< Bit field size in bits for CMP_CR1_TRIGM. */
 394
 395 /*! @brief Read current value of the CMP_CR1_TRIGM field. */
 396 #define BR_CMP_CR1_TRIGM(x)  (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_TRIGM))
 397
 398 /*! @brief Format value for bitfield CMP_CR1_TRIGM. */
 399 #define BF_CMP_CR1_TRIGM(v)  ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_TRIGM) & BM_CMP_CR1_TRIGM)
 400
 401 /*! @brief Set the TRIGM field to a new value. */
 402 #define BW_CMP_CR1_TRIGM(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_TRIGM) = (v))
 403 /*@}*/
 404
 405 /*!
 406  * @name Register CMP_CR1, field WE[6] (RW)
 407  *
 408  * At any given time, either SE or WE can be set. If a write to this register
 409  * attempts to set both, then SE is set and WE is cleared. However, avoid writing
 410  * 1s to both field locations because this "11" case is reserved and may change in
 411  * future implementations.
 412  *
 413  * Values:
 414  * - 0 - Windowing mode is not selected.
 415  * - 1 - Windowing mode is selected.
 416  */
 417 /*@{*/
 418 #define BP_CMP_CR1_WE        (6U)          /*!< Bit position for CMP_CR1_WE. */
 419 #define BM_CMP_CR1_WE        (0x40U)       /*!< Bit mask for CMP_CR1_WE. */
 420 #define BS_CMP_CR1_WE        (1U)          /*!< Bit field size in bits for CMP_CR1_WE. */
 421
 422 /*! @brief Read current value of the CMP_CR1_WE field. */
 423 #define BR_CMP_CR1_WE(x)     (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_WE))
 424
 425 /*! @brief Format value for bitfield CMP_CR1_WE. */
 426 #define BF_CMP_CR1_WE(v)     ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_WE) & BM_CMP_CR1_WE)
 427
 428 /*! @brief Set the WE field to a new value. */
 429 #define BW_CMP_CR1_WE(x, v)  (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_WE) = (v))
 430 /*@}*/
 431
 432 /*!
 433  * @name Register CMP_CR1, field SE[7] (RW)
 434  *
 435  * At any given time, either SE or WE can be set. If a write to this register
 436  * attempts to set both, then SE is set and WE is cleared. However, avoid writing
 437  * 1s to both field locations because this "11" case is reserved and may change in
 438  * future implementations.
 439  *
 440  * Values:
 441  * - 0 - Sampling mode is not selected.
 442  * - 1 - Sampling mode is selected.
 443  */
 444 /*@{*/
 445 #define BP_CMP_CR1_SE        (7U)          /*!< Bit position for CMP_CR1_SE. */
 446 #define BM_CMP_CR1_SE        (0x80U)       /*!< Bit mask for CMP_CR1_SE. */
 447 #define BS_CMP_CR1_SE        (1U)          /*!< Bit field size in bits for CMP_CR1_SE. */
 448
 449 /*! @brief Read current value of the CMP_CR1_SE field. */
 450 #define BR_CMP_CR1_SE(x)     (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_SE))
 451
 452 /*! @brief Format value for bitfield CMP_CR1_SE. */
 453 #define BF_CMP_CR1_SE(v)     ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_SE) & BM_CMP_CR1_SE)
 454
 455 /*! @brief Set the SE field to a new value. */
 456 #define BW_CMP_CR1_SE(x, v)  (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_SE) = (v))
 457 /*@}*/
 458
 459 /*******************************************************************************
 460  * HW_CMP_FPR - CMP Filter Period Register
 461  ******************************************************************************/
 462
 463 /*!
 464  * @brief HW_CMP_FPR - CMP Filter Period Register (RW)
 465  *
 466  * Reset value: 0x00U
 467  */
 468 typedef union _hw_cmp_fpr
 469 {
 470     uint8_t U;
 471     struct _hw_cmp_fpr_bitfields
 472     {
 473         uint8_t FILT_PER : 8;          /*!< [7:0] Filter Sample Period */
 474     } B;
 475 } hw_cmp_fpr_t;
 476
 477 /*!
 478  * @name Constants and macros for entire CMP_FPR register
 479  */
 480 /*@{*/
 481 #define HW_CMP_FPR_ADDR(x)       ((x) + 0x2U)
 482
 483 #define HW_CMP_FPR(x)            (*(__IO hw_cmp_fpr_t *) HW_CMP_FPR_ADDR(x))
 484 #define HW_CMP_FPR_RD(x)         (HW_CMP_FPR(x).U)
 485 #define HW_CMP_FPR_WR(x, v)      (HW_CMP_FPR(x).U = (v))
 486 #define HW_CMP_FPR_SET(x, v)     (HW_CMP_FPR_WR(x, HW_CMP_FPR_RD(x) |  (v)))
 487 #define HW_CMP_FPR_CLR(x, v)     (HW_CMP_FPR_WR(x, HW_CMP_FPR_RD(x) & ~(v)))
 488 #define HW_CMP_FPR_TOG(x, v)     (HW_CMP_FPR_WR(x, HW_CMP_FPR_RD(x) ^  (v)))
 489 /*@}*/
 490
 491 /*
 492  * Constants & macros for individual CMP_FPR bitfields
 493  */
 494
 495 /*!
 496  * @name Register CMP_FPR, field FILT_PER[7:0] (RW)
 497  *
 498  * Specifies the sampling period, in bus clock cycles, of the comparator output
 499  * filter, when CR1[SE]=0. Setting FILT_PER to 0x0 disables the filter. Filter
 500  * programming and latency details appear in the Functional descriptionThe CMP
 501  * module can be used to compare two analog input voltages applied to INP and INM. .
 502  * This field has no effect when CR1[SE]=1. In that case, the external SAMPLE
 503  * signal is used to determine the sampling period.
 504  */
 505 /*@{*/
 506 #define BP_CMP_FPR_FILT_PER  (0U)          /*!< Bit position for CMP_FPR_FILT_PER. */
 507 #define BM_CMP_FPR_FILT_PER  (0xFFU)       /*!< Bit mask for CMP_FPR_FILT_PER. */
 508 #define BS_CMP_FPR_FILT_PER  (8U)          /*!< Bit field size in bits for CMP_FPR_FILT_PER. */
 509
 510 /*! @brief Read current value of the CMP_FPR_FILT_PER field. */
 511 #define BR_CMP_FPR_FILT_PER(x) (HW_CMP_FPR(x).U)
 512
 513 /*! @brief Format value for bitfield CMP_FPR_FILT_PER. */
 514 #define BF_CMP_FPR_FILT_PER(v) ((uint8_t)((uint8_t)(v) << BP_CMP_FPR_FILT_PER) & BM_CMP_FPR_FILT_PER)
 515
 516 /*! @brief Set the FILT_PER field to a new value. */
 517 #define BW_CMP_FPR_FILT_PER(x, v) (HW_CMP_FPR_WR(x, v))
 518 /*@}*/
 519
 520 /*******************************************************************************
 521  * HW_CMP_SCR - CMP Status and Control Register
 522  ******************************************************************************/
 523
 524 /*!
 525  * @brief HW_CMP_SCR - CMP Status and Control Register (RW)
 526  *
 527  * Reset value: 0x00U
 528  */
 529 typedef union _hw_cmp_scr
 530 {
 531     uint8_t U;
 532     struct _hw_cmp_scr_bitfields
 533     {
 534         uint8_t COUT : 1;              /*!< [0] Analog Comparator Output */
 535         uint8_t CFF : 1;               /*!< [1] Analog Comparator Flag Falling */
 536         uint8_t CFR : 1;               /*!< [2] Analog Comparator Flag Rising */
 537         uint8_t IEF : 1;               /*!< [3] Comparator Interrupt Enable Falling */
 538         uint8_t IER : 1;               /*!< [4] Comparator Interrupt Enable Rising */
 539         uint8_t RESERVED0 : 1;         /*!< [5]  */
 540         uint8_t DMAEN : 1;             /*!< [6] DMA Enable Control */
 541         uint8_t RESERVED1 : 1;         /*!< [7]  */
 542     } B;
 543 } hw_cmp_scr_t;
 544
 545 /*!
 546  * @name Constants and macros for entire CMP_SCR register
 547  */
 548 /*@{*/
 549 #define HW_CMP_SCR_ADDR(x)       ((x) + 0x3U)
 550
 551 #define HW_CMP_SCR(x)            (*(__IO hw_cmp_scr_t *) HW_CMP_SCR_ADDR(x))
 552 #define HW_CMP_SCR_RD(x)         (HW_CMP_SCR(x).U)
 553 #define HW_CMP_SCR_WR(x, v)      (HW_CMP_SCR(x).U = (v))
 554 #define HW_CMP_SCR_SET(x, v)     (HW_CMP_SCR_WR(x, HW_CMP_SCR_RD(x) |  (v)))
 555 #define HW_CMP_SCR_CLR(x, v)     (HW_CMP_SCR_WR(x, HW_CMP_SCR_RD(x) & ~(v)))
 556 #define HW_CMP_SCR_TOG(x, v)     (HW_CMP_SCR_WR(x, HW_CMP_SCR_RD(x) ^  (v)))
 557 /*@}*/
 558
 559 /*
 560  * Constants & macros for individual CMP_SCR bitfields
 561  */
 562
 563 /*!
 564  * @name Register CMP_SCR, field COUT[0] (RO)
 565  *
 566  * Returns the current value of the Analog Comparator output, when read. The
 567  * field is reset to 0 and will read as CR1[INV] when the Analog Comparator module
 568  * is disabled, that is, when CR1[EN] = 0. Writes to this field are ignored.
 569  */
 570 /*@{*/
 571 #define BP_CMP_SCR_COUT      (0U)          /*!< Bit position for CMP_SCR_COUT. */
 572 #define BM_CMP_SCR_COUT      (0x01U)       /*!< Bit mask for CMP_SCR_COUT. */
 573 #define BS_CMP_SCR_COUT      (1U)          /*!< Bit field size in bits for CMP_SCR_COUT. */
 574
 575 /*! @brief Read current value of the CMP_SCR_COUT field. */
 576 #define BR_CMP_SCR_COUT(x)   (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_COUT))
 577 /*@}*/
 578
 579 /*!
 580  * @name Register CMP_SCR, field CFF[1] (W1C)
 581  *
 582  * Detects a falling-edge on COUT, when set, during normal operation. CFF is
 583  * cleared by writing 1 to it. During Stop modes, CFF is level sensitive .
 584  *
 585  * Values:
 586  * - 0 - Falling-edge on COUT has not been detected.
 587  * - 1 - Falling-edge on COUT has occurred.
 588  */
 589 /*@{*/
 590 #define BP_CMP_SCR_CFF       (1U)          /*!< Bit position for CMP_SCR_CFF. */
 591 #define BM_CMP_SCR_CFF       (0x02U)       /*!< Bit mask for CMP_SCR_CFF. */
 592 #define BS_CMP_SCR_CFF       (1U)          /*!< Bit field size in bits for CMP_SCR_CFF. */
 593
 594 /*! @brief Read current value of the CMP_SCR_CFF field. */
 595 #define BR_CMP_SCR_CFF(x)    (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFF))
 596
 597 /*! @brief Format value for bitfield CMP_SCR_CFF. */
 598 #define BF_CMP_SCR_CFF(v)    ((uint8_t)((uint8_t)(v) << BP_CMP_SCR_CFF) & BM_CMP_SCR_CFF)
 599
 600 /*! @brief Set the CFF field to a new value. */
 601 #define BW_CMP_SCR_CFF(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFF) = (v))
 602 /*@}*/
 603
 604 /*!
 605  * @name Register CMP_SCR, field CFR[2] (W1C)
 606  *
 607  * Detects a rising-edge on COUT, when set, during normal operation. CFR is
 608  * cleared by writing 1 to it. During Stop modes, CFR is level sensitive .
 609  *
 610  * Values:
 611  * - 0 - Rising-edge on COUT has not been detected.
 612  * - 1 - Rising-edge on COUT has occurred.
 613  */
 614 /*@{*/
 615 #define BP_CMP_SCR_CFR       (2U)          /*!< Bit position for CMP_SCR_CFR. */
 616 #define BM_CMP_SCR_CFR       (0x04U)       /*!< Bit mask for CMP_SCR_CFR. */
 617 #define BS_CMP_SCR_CFR       (1U)          /*!< Bit field size in bits for CMP_SCR_CFR. */
 618
 619 /*! @brief Read current value of the CMP_SCR_CFR field. */
 620 #define BR_CMP_SCR_CFR(x)    (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFR))
 621
 622 /*! @brief Format value for bitfield CMP_SCR_CFR. */
 623 #define BF_CMP_SCR_CFR(v)    ((uint8_t)((uint8_t)(v) << BP_CMP_SCR_CFR) & BM_CMP_SCR_CFR)
 624
 625 /*! @brief Set the CFR field to a new value. */
 626 #define BW_CMP_SCR_CFR(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFR) = (v))
 627 /*@}*/
 628
 629 /*!
 630  * @name Register CMP_SCR, field IEF[3] (RW)
 631  *
 632  * Enables the CFF interrupt from the CMP. When this field is set, an interrupt
 633  * will be asserted when CFF is set.
 634  *
 635  * Values:
 636  * - 0 - Interrupt is disabled.
 637  * - 1 - Interrupt is enabled.
 638  */
 639 /*@{*/
 640 #define BP_CMP_SCR_IEF       (3U)          /*!< Bit position for CMP_SCR_IEF. */
 641 #define BM_CMP_SCR_IEF       (0x08U)       /*!< Bit mask for CMP_SCR_IEF. */
 642 #define BS_CMP_SCR_IEF       (1U)          /*!< Bit field size in bits for CMP_SCR_IEF. */
 643
 644 /*! @brief Read current value of the CMP_SCR_IEF field. */
 645 #define BR_CMP_SCR_IEF(x)    (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IEF))
 646
 647 /*! @brief Format value for bitfield CMP_SCR_IEF. */
 648 #define BF_CMP_SCR_IEF(v)    ((uint8_t)((uint8_t)(v) << BP_CMP_SCR_IEF) & BM_CMP_SCR_IEF)
 649
 650 /*! @brief Set the IEF field to a new value. */
 651 #define BW_CMP_SCR_IEF(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IEF) = (v))
 652 /*@}*/
 653
 654 /*!
 655  * @name Register CMP_SCR, field IER[4] (RW)
 656  *
 657  * Enables the CFR interrupt from the CMP. When this field is set, an interrupt
 658  * will be asserted when CFR is set.
 659  *
 660  * Values:
 661  * - 0 - Interrupt is disabled.
 662  * - 1 - Interrupt is enabled.
 663  */
 664 /*@{*/
 665 #define BP_CMP_SCR_IER       (4U)          /*!< Bit position for CMP_SCR_IER. */
 666 #define BM_CMP_SCR_IER       (0x10U)       /*!< Bit mask for CMP_SCR_IER. */
 667 #define BS_CMP_SCR_IER       (1U)          /*!< Bit field size in bits for CMP_SCR_IER. */
 668
 669 /*! @brief Read current value of the CMP_SCR_IER field. */
 670 #define BR_CMP_SCR_IER(x)    (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IER))
 671
 672 /*! @brief Format value for bitfield CMP_SCR_IER. */
 673 #define BF_CMP_SCR_IER(v)    ((uint8_t)((uint8_t)(v) << BP_CMP_SCR_IER) & BM_CMP_SCR_IER)
 674
 675 /*! @brief Set the IER field to a new value. */
 676 #define BW_CMP_SCR_IER(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IER) = (v))
 677 /*@}*/
 678
 679 /*!
 680  * @name Register CMP_SCR, field DMAEN[6] (RW)
 681  *
 682  * Enables the DMA transfer triggered from the CMP module. When this field is
 683  * set, a DMA request is asserted when CFR or CFF is set.
 684  *
 685  * Values:
 686  * - 0 - DMA is disabled.
 687  * - 1 - DMA is enabled.
 688  */
 689 /*@{*/
 690 #define BP_CMP_SCR_DMAEN     (6U)          /*!< Bit position for CMP_SCR_DMAEN. */
 691 #define BM_CMP_SCR_DMAEN     (0x40U)       /*!< Bit mask for CMP_SCR_DMAEN. */
 692 #define BS_CMP_SCR_DMAEN     (1U)          /*!< Bit field size in bits for CMP_SCR_DMAEN. */
 693
 694 /*! @brief Read current value of the CMP_SCR_DMAEN field. */
 695 #define BR_CMP_SCR_DMAEN(x)  (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_DMAEN))
 696
 697 /*! @brief Format value for bitfield CMP_SCR_DMAEN. */
 698 #define BF_CMP_SCR_DMAEN(v)  ((uint8_t)((uint8_t)(v) << BP_CMP_SCR_DMAEN) & BM_CMP_SCR_DMAEN)
 699
 700 /*! @brief Set the DMAEN field to a new value. */
 701 #define BW_CMP_SCR_DMAEN(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_DMAEN) = (v))
 702 /*@}*/
 703
 704 /*******************************************************************************
 705  * HW_CMP_DACCR - DAC Control Register
 706  ******************************************************************************/
 707
 708 /*!
 709  * @brief HW_CMP_DACCR - DAC Control Register (RW)
 710  *
 711  * Reset value: 0x00U
 712  */
 713 typedef union _hw_cmp_daccr
 714 {
 715     uint8_t U;
 716     struct _hw_cmp_daccr_bitfields
 717     {
 718         uint8_t VOSEL : 6;             /*!< [5:0] DAC Output Voltage Select */
 719         uint8_t VRSEL : 1;             /*!< [6] Supply Voltage Reference Source Select */
 720         uint8_t DACEN : 1;             /*!< [7] DAC Enable */
 721     } B;
 722 } hw_cmp_daccr_t;
 723
 724 /*!
 725  * @name Constants and macros for entire CMP_DACCR register
 726  */
 727 /*@{*/
 728 #define HW_CMP_DACCR_ADDR(x)     ((x) + 0x4U)
 729
 730 #define HW_CMP_DACCR(x)          (*(__IO hw_cmp_daccr_t *) HW_CMP_DACCR_ADDR(x))
 731 #define HW_CMP_DACCR_RD(x)       (HW_CMP_DACCR(x).U)
 732 #define HW_CMP_DACCR_WR(x, v)    (HW_CMP_DACCR(x).U = (v))
 733 #define HW_CMP_DACCR_SET(x, v)   (HW_CMP_DACCR_WR(x, HW_CMP_DACCR_RD(x) |  (v)))
 734 #define HW_CMP_DACCR_CLR(x, v)   (HW_CMP_DACCR_WR(x, HW_CMP_DACCR_RD(x) & ~(v)))
 735 #define HW_CMP_DACCR_TOG(x, v)   (HW_CMP_DACCR_WR(x, HW_CMP_DACCR_RD(x) ^  (v)))
 736 /*@}*/
 737
 738 /*
 739  * Constants & macros for individual CMP_DACCR bitfields
 740  */
 741
 742 /*!
 743  * @name Register CMP_DACCR, field VOSEL[5:0] (RW)
 744  *
 745  * Selects an output voltage from one of 64 distinct levels. DACO = (V in /64) *
 746  * (VOSEL[5:0] + 1) , so the DACO range is from V in /64 to V in .
 747  */
 748 /*@{*/
 749 #define BP_CMP_DACCR_VOSEL   (0U)          /*!< Bit position for CMP_DACCR_VOSEL. */
 750 #define BM_CMP_DACCR_VOSEL   (0x3FU)       /*!< Bit mask for CMP_DACCR_VOSEL. */
 751 #define BS_CMP_DACCR_VOSEL   (6U)          /*!< Bit field size in bits for CMP_DACCR_VOSEL. */
 752
 753 /*! @brief Read current value of the CMP_DACCR_VOSEL field. */
 754 #define BR_CMP_DACCR_VOSEL(x) (HW_CMP_DACCR(x).B.VOSEL)
 755
 756 /*! @brief Format value for bitfield CMP_DACCR_VOSEL. */
 757 #define BF_CMP_DACCR_VOSEL(v) ((uint8_t)((uint8_t)(v) << BP_CMP_DACCR_VOSEL) & BM_CMP_DACCR_VOSEL)
 758
 759 /*! @brief Set the VOSEL field to a new value. */
 760 #define BW_CMP_DACCR_VOSEL(x, v) (HW_CMP_DACCR_WR(x, (HW_CMP_DACCR_RD(x) & ~BM_CMP_DACCR_VOSEL) | BF_CMP_DACCR_VOSEL(v)))
 761 /*@}*/
 762
 763 /*!
 764  * @name Register CMP_DACCR, field VRSEL[6] (RW)
 765  *
 766  * Values:
 767  * - 0 - V is selected as resistor ladder network supply reference V. in1 in
 768  * - 1 - V is selected as resistor ladder network supply reference V. in2 in
 769  */
 770 /*@{*/
 771 #define BP_CMP_DACCR_VRSEL   (6U)          /*!< Bit position for CMP_DACCR_VRSEL. */
 772 #define BM_CMP_DACCR_VRSEL   (0x40U)       /*!< Bit mask for CMP_DACCR_VRSEL. */
 773 #define BS_CMP_DACCR_VRSEL   (1U)          /*!< Bit field size in bits for CMP_DACCR_VRSEL. */
 774
 775 /*! @brief Read current value of the CMP_DACCR_VRSEL field. */
 776 #define BR_CMP_DACCR_VRSEL(x) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_VRSEL))
 777
 778 /*! @brief Format value for bitfield CMP_DACCR_VRSEL. */
 779 #define BF_CMP_DACCR_VRSEL(v) ((uint8_t)((uint8_t)(v) << BP_CMP_DACCR_VRSEL) & BM_CMP_DACCR_VRSEL)
 780
 781 /*! @brief Set the VRSEL field to a new value. */
 782 #define BW_CMP_DACCR_VRSEL(x, v) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_VRSEL) = (v))
 783 /*@}*/
 784
 785 /*!
 786  * @name Register CMP_DACCR, field DACEN[7] (RW)
 787  *
 788  * Enables the DAC. When the DAC is disabled, it is powered down to conserve
 789  * power.
 790  *
 791  * Values:
 792  * - 0 - DAC is disabled.
 793  * - 1 - DAC is enabled.
 794  */
 795 /*@{*/
 796 #define BP_CMP_DACCR_DACEN   (7U)          /*!< Bit position for CMP_DACCR_DACEN. */
 797 #define BM_CMP_DACCR_DACEN   (0x80U)       /*!< Bit mask for CMP_DACCR_DACEN. */
 798 #define BS_CMP_DACCR_DACEN   (1U)          /*!< Bit field size in bits for CMP_DACCR_DACEN. */
 799
 800 /*! @brief Read current value of the CMP_DACCR_DACEN field. */
 801 #define BR_CMP_DACCR_DACEN(x) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_DACEN))
 802
 803 /*! @brief Format value for bitfield CMP_DACCR_DACEN. */
 804 #define BF_CMP_DACCR_DACEN(v) ((uint8_t)((uint8_t)(v) << BP_CMP_DACCR_DACEN) & BM_CMP_DACCR_DACEN)
 805
 806 /*! @brief Set the DACEN field to a new value. */
 807 #define BW_CMP_DACCR_DACEN(x, v) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_DACEN) = (v))
 808 /*@}*/
 809
 810 /*******************************************************************************
 811  * HW_CMP_MUXCR - MUX Control Register
 812  ******************************************************************************/
 813
 814 /*!
 815  * @brief HW_CMP_MUXCR - MUX Control Register (RW)
 816  *
 817  * Reset value: 0x00U
 818  */
 819 typedef union _hw_cmp_muxcr
 820 {
 821     uint8_t U;
 822     struct _hw_cmp_muxcr_bitfields
 823     {
 824         uint8_t MSEL : 3;              /*!< [2:0] Minus Input Mux Control */
 825         uint8_t PSEL : 3;              /*!< [5:3] Plus Input Mux Control */
 826         uint8_t RESERVED0 : 2;         /*!< [7:6] Bit can be programmed to zero only
 827                                         * . */
 828     } B;
 829 } hw_cmp_muxcr_t;
 830
 831 /*!
 832  * @name Constants and macros for entire CMP_MUXCR register
 833  */
 834 /*@{*/
 835 #define HW_CMP_MUXCR_ADDR(x)     ((x) + 0x5U)
 836
 837 #define HW_CMP_MUXCR(x)          (*(__IO hw_cmp_muxcr_t *) HW_CMP_MUXCR_ADDR(x))
 838 #define HW_CMP_MUXCR_RD(x)       (HW_CMP_MUXCR(x).U)
 839 #define HW_CMP_MUXCR_WR(x, v)    (HW_CMP_MUXCR(x).U = (v))
 840 #define HW_CMP_MUXCR_SET(x, v)   (HW_CMP_MUXCR_WR(x, HW_CMP_MUXCR_RD(x) |  (v)))
 841 #define HW_CMP_MUXCR_CLR(x, v)   (HW_CMP_MUXCR_WR(x, HW_CMP_MUXCR_RD(x) & ~(v)))
 842 #define HW_CMP_MUXCR_TOG(x, v)   (HW_CMP_MUXCR_WR(x, HW_CMP_MUXCR_RD(x) ^  (v)))
 843 /*@}*/
 844
 845 /*
 846  * Constants & macros for individual CMP_MUXCR bitfields
 847  */
 848
 849 /*!
 850  * @name Register CMP_MUXCR, field MSEL[2:0] (RW)
 851  *
 852  * Determines which input is selected for the minus input of the comparator. For
 853  * INx inputs, see CMP, DAC, and ANMUX block diagrams. When an inappropriate
 854  * operation selects the same input for both muxes, the comparator automatically
 855  * shuts down to prevent itself from becoming a noise generator.
 856  *
 857  * Values:
 858  * - 000 - IN0
 859  * - 001 - IN1
 860  * - 010 - IN2
 861  * - 011 - IN3
 862  * - 100 - IN4
 863  * - 101 - IN5
 864  * - 110 - IN6
 865  * - 111 - IN7
 866  */
 867 /*@{*/
 868 #define BP_CMP_MUXCR_MSEL    (0U)          /*!< Bit position for CMP_MUXCR_MSEL. */
 869 #define BM_CMP_MUXCR_MSEL    (0x07U)       /*!< Bit mask for CMP_MUXCR_MSEL. */
 870 #define BS_CMP_MUXCR_MSEL    (3U)          /*!< Bit field size in bits for CMP_MUXCR_MSEL. */
 871
 872 /*! @brief Read current value of the CMP_MUXCR_MSEL field. */
 873 #define BR_CMP_MUXCR_MSEL(x) (HW_CMP_MUXCR(x).B.MSEL)
 874
 875 /*! @brief Format value for bitfield CMP_MUXCR_MSEL. */
 876 #define BF_CMP_MUXCR_MSEL(v) ((uint8_t)((uint8_t)(v) << BP_CMP_MUXCR_MSEL) & BM_CMP_MUXCR_MSEL)
 877
 878 /*! @brief Set the MSEL field to a new value. */
 879 #define BW_CMP_MUXCR_MSEL(x, v) (HW_CMP_MUXCR_WR(x, (HW_CMP_MUXCR_RD(x) & ~BM_CMP_MUXCR_MSEL) | BF_CMP_MUXCR_MSEL(v)))
 880 /*@}*/
 881
 882 /*!
 883  * @name Register CMP_MUXCR, field PSEL[5:3] (RW)
 884  *
 885  * Determines which input is selected for the plus input of the comparator. For
 886  * INx inputs, see CMP, DAC, and ANMUX block diagrams. When an inappropriate
 887  * operation selects the same input for both muxes, the comparator automatically
 888  * shuts down to prevent itself from becoming a noise generator.
 889  *
 890  * Values:
 891  * - 000 - IN0
 892  * - 001 - IN1
 893  * - 010 - IN2
 894  * - 011 - IN3
 895  * - 100 - IN4
 896  * - 101 - IN5
 897  * - 110 - IN6
 898  * - 111 - IN7
 899  */
 900 /*@{*/
 901 #define BP_CMP_MUXCR_PSEL    (3U)          /*!< Bit position for CMP_MUXCR_PSEL. */
 902 #define BM_CMP_MUXCR_PSEL    (0x38U)       /*!< Bit mask for CMP_MUXCR_PSEL. */
 903 #define BS_CMP_MUXCR_PSEL    (3U)          /*!< Bit field size in bits for CMP_MUXCR_PSEL. */
 904
 905 /*! @brief Read current value of the CMP_MUXCR_PSEL field. */
 906 #define BR_CMP_MUXCR_PSEL(x) (HW_CMP_MUXCR(x).B.PSEL)
 907
 908 /*! @brief Format value for bitfield CMP_MUXCR_PSEL. */
 909 #define BF_CMP_MUXCR_PSEL(v) ((uint8_t)((uint8_t)(v) << BP_CMP_MUXCR_PSEL) & BM_CMP_MUXCR_PSEL)
 910
 911 /*! @brief Set the PSEL field to a new value. */
 912 #define BW_CMP_MUXCR_PSEL(x, v) (HW_CMP_MUXCR_WR(x, (HW_CMP_MUXCR_RD(x) & ~BM_CMP_MUXCR_PSEL) | BF_CMP_MUXCR_PSEL(v)))
 913 /*@}*/
 914
 915 /*******************************************************************************
 916  * hw_cmp_t - module struct
 917  ******************************************************************************/
 918 /*!
 919  * @brief All CMP module registers.
 920  */
 921 #pragma pack(1)
 922 typedef struct _hw_cmp
 923 {
 924     __IO hw_cmp_cr0_t CR0;                 /*!< [0x0] CMP Control Register 0 */
 925     __IO hw_cmp_cr1_t CR1;                 /*!< [0x1] CMP Control Register 1 */
 926     __IO hw_cmp_fpr_t FPR;                 /*!< [0x2] CMP Filter Period Register */
 927     __IO hw_cmp_scr_t SCR;                 /*!< [0x3] CMP Status and Control Register */
 928     __IO hw_cmp_daccr_t DACCR;             /*!< [0x4] DAC Control Register */
 929     __IO hw_cmp_muxcr_t MUXCR;             /*!< [0x5] MUX Control Register */
 930 } hw_cmp_t;
 931 #pragma pack()
 932
 933 /*! @brief Macro to access all CMP registers. */
 934 /*! @param x CMP module instance base address. */
 935 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
 936  *     use the '&' operator, like <code>&HW_CMP(CMP0_BASE)</code>. */
 937 #define HW_CMP(x)      (*(hw_cmp_t *)(x))
 938
 939 #endif /* __HW_CMP_REGISTERS_H__ */
 940 /* EOF */