tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_dac.h

   1 /*
   2 ** ###################################################################
   3 **     Compilers:           Keil ARM C/C++ Compiler
   4 **                          Freescale C/C++ for Embedded ARM
   5 **                          GNU C Compiler
   6 **                          IAR ANSI C/C++ Compiler for ARM
   7 **
   8 **     Reference manual:    K22P121M120SF7RM, Rev. 1, March 24, 2014
   9 **     Version:             rev. 2.5, 2014-05-06
  10 **     Build:               b140604
  11 **
  12 **     Abstract:
  13 **         Extension to the CMSIS register access layer header.
  14 **
  15 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
  16 **     All rights reserved.
  17 **
  18 **     Redistribution and use in source and binary forms, with or without modification,
  19 **     are permitted provided that the following conditions are met:
  20 **
  21 **     o Redistributions of source code must retain the above copyright notice, this list
  22 **       of conditions and the following disclaimer.
  23 **
  24 **     o Redistributions in binary form must reproduce the above copyright notice, this
  25 **       list of conditions and the following disclaimer in the documentation and/or
  26 **       other materials provided with the distribution.
  27 **
  28 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  29 **       contributors may be used to endorse or promote products derived from this
  30 **       software without specific prior written permission.
  31 **
  32 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  33 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  34 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  35 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  36 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  37 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  38 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  39 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  41 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42 **
  43 **     http:                 www.freescale.com
  44 **     mail:                 support@freescale.com
  45 **
  46 **     Revisions:
  47 **     - rev. 1.0 (2013-07-23)
  48 **         Initial version.
  49 **     - rev. 1.1 (2013-09-17)
  50 **         RM rev. 0.4 update.
  51 **     - rev. 2.0 (2013-10-29)
  52 **         Register accessor macros added to the memory map.
  53 **         Symbols for Processor Expert memory map compatibility added to the memory map.
  54 **         Startup file for gcc has been updated according to CMSIS 3.2.
  55 **         System initialization updated.
  56 **     - rev. 2.1 (2013-10-30)
  57 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
  58 **     - rev. 2.2 (2013-12-20)
  59 **         Update according to reference manual rev. 0.6,
  60 **     - rev. 2.3 (2014-01-13)
  61 **         Update according to reference manual rev. 0.61,
  62 **     - rev. 2.4 (2014-02-10)
  63 **         The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
  64 **     - rev. 2.5 (2014-05-06)
  65 **         Update according to reference manual rev. 1.0,
  66 **         Update of system and startup files.
  67 **         Module access macro module_BASES replaced by module_BASE_PTRS.
  68 **
  69 ** ###################################################################
  70 */
  71
  72 /*
  73  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
  74  *
  75  * This file was generated automatically and any changes may be lost.
  76  */
  77 #ifndef __HW_DAC_REGISTERS_H__
  78 #define __HW_DAC_REGISTERS_H__
  79
  80 #include "MK22F51212.h"
  81 #include "fsl_bitaccess.h"
  82
  83 /*
  84  * MK22F51212 DAC
  85  *
  86  * 12-Bit Digital-to-Analog Converter
  87  *
  88  * Registers defined in this header file:
  89  * - HW_DAC_DATnL - DAC Data Low Register
  90  * - HW_DAC_DATnH - DAC Data High Register
  91  * - HW_DAC_SR - DAC Status Register
  92  * - HW_DAC_C0 - DAC Control Register
  93  * - HW_DAC_C1 - DAC Control Register 1
  94  * - HW_DAC_C2 - DAC Control Register 2
  95  *
  96  * - hw_dac_t - Struct containing all module registers.
  97  */
  98
  99 #define HW_DAC_INSTANCE_COUNT (2U) /*!< Number of instances of the DAC module. */
 100 #define HW_DAC0 (0U) /*!< Instance number for DAC0. */
 101 #define HW_DAC1 (1U) /*!< Instance number for DAC1. */
 102
 103 /*******************************************************************************
 104  * HW_DAC_DATnL - DAC Data Low Register
 105  ******************************************************************************/
 106
 107 /*!
 108  * @brief HW_DAC_DATnL - DAC Data Low Register (RW)
 109  *
 110  * Reset value: 0x00U
 111  */
 112 typedef union _hw_dac_datnl
 113 {
 114     uint8_t U;
 115     struct _hw_dac_datnl_bitfields
 116     {
 117         uint8_t DATA0 : 8;             /*!< [7:0]  */
 118     } B;
 119 } hw_dac_datnl_t;
 120
 121 /*!
 122  * @name Constants and macros for entire DAC_DATnL register
 123  */
 124 /*@{*/
 125 #define HW_DAC_DATnL_COUNT (16U)
 126
 127 #define HW_DAC_DATnL_ADDR(x, n)  ((x) + 0x0U + (0x2U * (n)))
 128
 129 #define HW_DAC_DATnL(x, n)       (*(__IO hw_dac_datnl_t *) HW_DAC_DATnL_ADDR(x, n))
 130 #define HW_DAC_DATnL_RD(x, n)    (HW_DAC_DATnL(x, n).U)
 131 #define HW_DAC_DATnL_WR(x, n, v) (HW_DAC_DATnL(x, n).U = (v))
 132 #define HW_DAC_DATnL_SET(x, n, v) (HW_DAC_DATnL_WR(x, n, HW_DAC_DATnL_RD(x, n) |  (v)))
 133 #define HW_DAC_DATnL_CLR(x, n, v) (HW_DAC_DATnL_WR(x, n, HW_DAC_DATnL_RD(x, n) & ~(v)))
 134 #define HW_DAC_DATnL_TOG(x, n, v) (HW_DAC_DATnL_WR(x, n, HW_DAC_DATnL_RD(x, n) ^  (v)))
 135 /*@}*/
 136
 137 /*
 138  * Constants & macros for individual DAC_DATnL bitfields
 139  */
 140
 141 /*!
 142  * @name Register DAC_DATnL, field DATA0[7:0] (RW)
 143  *
 144  * When the DAC buffer is not enabled, DATA[11:0] controls the output voltage
 145  * based on the following formula: V out = V in * (1 + DACDAT0[11:0])/4096 When the
 146  * DAC buffer is enabled, DATA is mapped to the 16-word buffer.
 147  */
 148 /*@{*/
 149 #define BP_DAC_DATnL_DATA0   (0U)          /*!< Bit position for DAC_DATnL_DATA0. */
 150 #define BM_DAC_DATnL_DATA0   (0xFFU)       /*!< Bit mask for DAC_DATnL_DATA0. */
 151 #define BS_DAC_DATnL_DATA0   (8U)          /*!< Bit field size in bits for DAC_DATnL_DATA0. */
 152
 153 /*! @brief Read current value of the DAC_DATnL_DATA0 field. */
 154 #define BR_DAC_DATnL_DATA0(x, n) (HW_DAC_DATnL(x, n).U)
 155
 156 /*! @brief Format value for bitfield DAC_DATnL_DATA0. */
 157 #define BF_DAC_DATnL_DATA0(v) ((uint8_t)((uint8_t)(v) << BP_DAC_DATnL_DATA0) & BM_DAC_DATnL_DATA0)
 158
 159 /*! @brief Set the DATA0 field to a new value. */
 160 #define BW_DAC_DATnL_DATA0(x, n, v) (HW_DAC_DATnL_WR(x, n, v))
 161 /*@}*/
 162 /*******************************************************************************
 163  * HW_DAC_DATnH - DAC Data High Register
 164  ******************************************************************************/
 165
 166 /*!
 167  * @brief HW_DAC_DATnH - DAC Data High Register (RW)
 168  *
 169  * Reset value: 0x00U
 170  */
 171 typedef union _hw_dac_datnh
 172 {
 173     uint8_t U;
 174     struct _hw_dac_datnh_bitfields
 175     {
 176         uint8_t DATA1 : 4;             /*!< [3:0]  */
 177         uint8_t RESERVED0 : 4;         /*!< [7:4]  */
 178     } B;
 179 } hw_dac_datnh_t;
 180
 181 /*!
 182  * @name Constants and macros for entire DAC_DATnH register
 183  */
 184 /*@{*/
 185 #define HW_DAC_DATnH_COUNT (16U)
 186
 187 #define HW_DAC_DATnH_ADDR(x, n)  ((x) + 0x1U + (0x2U * (n)))
 188
 189 #define HW_DAC_DATnH(x, n)       (*(__IO hw_dac_datnh_t *) HW_DAC_DATnH_ADDR(x, n))
 190 #define HW_DAC_DATnH_RD(x, n)    (HW_DAC_DATnH(x, n).U)
 191 #define HW_DAC_DATnH_WR(x, n, v) (HW_DAC_DATnH(x, n).U = (v))
 192 #define HW_DAC_DATnH_SET(x, n, v) (HW_DAC_DATnH_WR(x, n, HW_DAC_DATnH_RD(x, n) |  (v)))
 193 #define HW_DAC_DATnH_CLR(x, n, v) (HW_DAC_DATnH_WR(x, n, HW_DAC_DATnH_RD(x, n) & ~(v)))
 194 #define HW_DAC_DATnH_TOG(x, n, v) (HW_DAC_DATnH_WR(x, n, HW_DAC_DATnH_RD(x, n) ^  (v)))
 195 /*@}*/
 196
 197 /*
 198  * Constants & macros for individual DAC_DATnH bitfields
 199  */
 200
 201 /*!
 202  * @name Register DAC_DATnH, field DATA1[3:0] (RW)
 203  *
 204  * When the DAC Buffer is not enabled, DATA[11:0] controls the output voltage
 205  * based on the following formula. V out = V in * (1 + DACDAT0[11:0])/4096 When the
 206  * DAC buffer is enabled, DATA[11:0] is mapped to the 16-word buffer.
 207  */
 208 /*@{*/
 209 #define BP_DAC_DATnH_DATA1   (0U)          /*!< Bit position for DAC_DATnH_DATA1. */
 210 #define BM_DAC_DATnH_DATA1   (0x0FU)       /*!< Bit mask for DAC_DATnH_DATA1. */
 211 #define BS_DAC_DATnH_DATA1   (4U)          /*!< Bit field size in bits for DAC_DATnH_DATA1. */
 212
 213 /*! @brief Read current value of the DAC_DATnH_DATA1 field. */
 214 #define BR_DAC_DATnH_DATA1(x, n) (HW_DAC_DATnH(x, n).B.DATA1)
 215
 216 /*! @brief Format value for bitfield DAC_DATnH_DATA1. */
 217 #define BF_DAC_DATnH_DATA1(v) ((uint8_t)((uint8_t)(v) << BP_DAC_DATnH_DATA1) & BM_DAC_DATnH_DATA1)
 218
 219 /*! @brief Set the DATA1 field to a new value. */
 220 #define BW_DAC_DATnH_DATA1(x, n, v) (HW_DAC_DATnH_WR(x, n, (HW_DAC_DATnH_RD(x, n) & ~BM_DAC_DATnH_DATA1) | BF_DAC_DATnH_DATA1(v)))
 221 /*@}*/
 222
 223 /*******************************************************************************
 224  * HW_DAC_SR - DAC Status Register
 225  ******************************************************************************/
 226
 227 /*!
 228  * @brief HW_DAC_SR - DAC Status Register (RW)
 229  *
 230  * Reset value: 0x02U
 231  *
 232  * If DMA is enabled, the flags can be cleared automatically by DMA when the DMA
 233  * request is done. Writing 0 to a field clears it whereas writing 1 has no
 234  * effect. After reset, DACBFRPTF is set and can be cleared by software, if needed.
 235  * The flags are set only when the data buffer status is changed.
 236  */
 237 typedef union _hw_dac_sr
 238 {
 239     uint8_t U;
 240     struct _hw_dac_sr_bitfields
 241     {
 242         uint8_t DACBFRPBF : 1;         /*!< [0] DAC Buffer Read Pointer Bottom
 243                                         * Position Flag */
 244         uint8_t DACBFRPTF : 1;         /*!< [1] DAC Buffer Read Pointer Top Position
 245                                         * Flag */
 246         uint8_t DACBFWMF : 1;          /*!< [2] DAC Buffer Watermark Flag */
 247         uint8_t RESERVED0 : 5;         /*!< [7:3]  */
 248     } B;
 249 } hw_dac_sr_t;
 250
 251 /*!
 252  * @name Constants and macros for entire DAC_SR register
 253  */
 254 /*@{*/
 255 #define HW_DAC_SR_ADDR(x)        ((x) + 0x20U)
 256
 257 #define HW_DAC_SR(x)             (*(__IO hw_dac_sr_t *) HW_DAC_SR_ADDR(x))
 258 #define HW_DAC_SR_RD(x)          (HW_DAC_SR(x).U)
 259 #define HW_DAC_SR_WR(x, v)       (HW_DAC_SR(x).U = (v))
 260 #define HW_DAC_SR_SET(x, v)      (HW_DAC_SR_WR(x, HW_DAC_SR_RD(x) |  (v)))
 261 #define HW_DAC_SR_CLR(x, v)      (HW_DAC_SR_WR(x, HW_DAC_SR_RD(x) & ~(v)))
 262 #define HW_DAC_SR_TOG(x, v)      (HW_DAC_SR_WR(x, HW_DAC_SR_RD(x) ^  (v)))
 263 /*@}*/
 264
 265 /*
 266  * Constants & macros for individual DAC_SR bitfields
 267  */
 268
 269 /*!
 270  * @name Register DAC_SR, field DACBFRPBF[0] (RW)
 271  *
 272  * In FIFO mode, it is FIFO FULL status bit. It means FIFO read pointer equals
 273  * Write Pointer because of Write Pointer increase. If this bit is set, any write
 274  * to FIFO from either DMA or CPU is ignored by DAC. It is cleared if there is
 275  * any DAC trigger making the DAC read pointer increase. Write to this bit is
 276  * ignored in FIFO mode.
 277  *
 278  * Values:
 279  * - 0 - The DAC buffer read pointer is not equal to C2[DACBFUP].
 280  * - 1 - The DAC buffer read pointer is equal to C2[DACBFUP].
 281  */
 282 /*@{*/
 283 #define BP_DAC_SR_DACBFRPBF  (0U)          /*!< Bit position for DAC_SR_DACBFRPBF. */
 284 #define BM_DAC_SR_DACBFRPBF  (0x01U)       /*!< Bit mask for DAC_SR_DACBFRPBF. */
 285 #define BS_DAC_SR_DACBFRPBF  (1U)          /*!< Bit field size in bits for DAC_SR_DACBFRPBF. */
 286
 287 /*! @brief Read current value of the DAC_SR_DACBFRPBF field. */
 288 #define BR_DAC_SR_DACBFRPBF(x) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPBF))
 289
 290 /*! @brief Format value for bitfield DAC_SR_DACBFRPBF. */
 291 #define BF_DAC_SR_DACBFRPBF(v) ((uint8_t)((uint8_t)(v) << BP_DAC_SR_DACBFRPBF) & BM_DAC_SR_DACBFRPBF)
 292
 293 /*! @brief Set the DACBFRPBF field to a new value. */
 294 #define BW_DAC_SR_DACBFRPBF(x, v) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPBF) = (v))
 295 /*@}*/
 296
 297 /*!
 298  * @name Register DAC_SR, field DACBFRPTF[1] (RW)
 299  *
 300  * In FIFO mode, it is FIFO nearly empty flag. It is set when only one data
 301  * remains in FIFO. Any DAC trigger does not increase the Read Pointer if this bit is
 302  * set to avoid any possible glitch or abrupt change at DAC output. It is
 303  * cleared automatically if FIFO is not empty.
 304  *
 305  * Values:
 306  * - 0 - The DAC buffer read pointer is not zero.
 307  * - 1 - The DAC buffer read pointer is zero.
 308  */
 309 /*@{*/
 310 #define BP_DAC_SR_DACBFRPTF  (1U)          /*!< Bit position for DAC_SR_DACBFRPTF. */
 311 #define BM_DAC_SR_DACBFRPTF  (0x02U)       /*!< Bit mask for DAC_SR_DACBFRPTF. */
 312 #define BS_DAC_SR_DACBFRPTF  (1U)          /*!< Bit field size in bits for DAC_SR_DACBFRPTF. */
 313
 314 /*! @brief Read current value of the DAC_SR_DACBFRPTF field. */
 315 #define BR_DAC_SR_DACBFRPTF(x) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPTF))
 316
 317 /*! @brief Format value for bitfield DAC_SR_DACBFRPTF. */
 318 #define BF_DAC_SR_DACBFRPTF(v) ((uint8_t)((uint8_t)(v) << BP_DAC_SR_DACBFRPTF) & BM_DAC_SR_DACBFRPTF)
 319
 320 /*! @brief Set the DACBFRPTF field to a new value. */
 321 #define BW_DAC_SR_DACBFRPTF(x, v) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPTF) = (v))
 322 /*@}*/
 323
 324 /*!
 325  * @name Register DAC_SR, field DACBFWMF[2] (RW)
 326  *
 327  * This bit is set if the remaining FIFO data is less than the watermark
 328  * setting. It is cleared automatically by writing data into FIFO by DMA or CPU. Write
 329  * to this bit is ignored in FIFO mode.
 330  *
 331  * Values:
 332  * - 0 - The DAC buffer read pointer has not reached the watermark level.
 333  * - 1 - The DAC buffer read pointer has reached the watermark level.
 334  */
 335 /*@{*/
 336 #define BP_DAC_SR_DACBFWMF   (2U)          /*!< Bit position for DAC_SR_DACBFWMF. */
 337 #define BM_DAC_SR_DACBFWMF   (0x04U)       /*!< Bit mask for DAC_SR_DACBFWMF. */
 338 #define BS_DAC_SR_DACBFWMF   (1U)          /*!< Bit field size in bits for DAC_SR_DACBFWMF. */
 339
 340 /*! @brief Read current value of the DAC_SR_DACBFWMF field. */
 341 #define BR_DAC_SR_DACBFWMF(x) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFWMF))
 342
 343 /*! @brief Format value for bitfield DAC_SR_DACBFWMF. */
 344 #define BF_DAC_SR_DACBFWMF(v) ((uint8_t)((uint8_t)(v) << BP_DAC_SR_DACBFWMF) & BM_DAC_SR_DACBFWMF)
 345
 346 /*! @brief Set the DACBFWMF field to a new value. */
 347 #define BW_DAC_SR_DACBFWMF(x, v) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFWMF) = (v))
 348 /*@}*/
 349
 350 /*******************************************************************************
 351  * HW_DAC_C0 - DAC Control Register
 352  ******************************************************************************/
 353
 354 /*!
 355  * @brief HW_DAC_C0 - DAC Control Register (RW)
 356  *
 357  * Reset value: 0x00U
 358  */
 359 typedef union _hw_dac_c0
 360 {
 361     uint8_t U;
 362     struct _hw_dac_c0_bitfields
 363     {
 364         uint8_t DACBBIEN : 1;          /*!< [0] DAC Buffer Read Pointer Bottom Flag
 365                                         * Interrupt Enable */
 366         uint8_t DACBTIEN : 1;          /*!< [1] DAC Buffer Read Pointer Top Flag
 367                                         * Interrupt Enable */
 368         uint8_t DACBWIEN : 1;          /*!< [2] DAC Buffer Watermark Interrupt Enable
 369                                         * */
 370         uint8_t LPEN : 1;              /*!< [3] DAC Low Power Control */
 371         uint8_t DACSWTRG : 1;          /*!< [4] DAC Software Trigger */
 372         uint8_t DACTRGSEL : 1;         /*!< [5] DAC Trigger Select */
 373         uint8_t DACRFS : 1;            /*!< [6] DAC Reference Select */
 374         uint8_t DACEN : 1;             /*!< [7] DAC Enable */
 375     } B;
 376 } hw_dac_c0_t;
 377
 378 /*!
 379  * @name Constants and macros for entire DAC_C0 register
 380  */
 381 /*@{*/
 382 #define HW_DAC_C0_ADDR(x)        ((x) + 0x21U)
 383
 384 #define HW_DAC_C0(x)             (*(__IO hw_dac_c0_t *) HW_DAC_C0_ADDR(x))
 385 #define HW_DAC_C0_RD(x)          (HW_DAC_C0(x).U)
 386 #define HW_DAC_C0_WR(x, v)       (HW_DAC_C0(x).U = (v))
 387 #define HW_DAC_C0_SET(x, v)      (HW_DAC_C0_WR(x, HW_DAC_C0_RD(x) |  (v)))
 388 #define HW_DAC_C0_CLR(x, v)      (HW_DAC_C0_WR(x, HW_DAC_C0_RD(x) & ~(v)))
 389 #define HW_DAC_C0_TOG(x, v)      (HW_DAC_C0_WR(x, HW_DAC_C0_RD(x) ^  (v)))
 390 /*@}*/
 391
 392 /*
 393  * Constants & macros for individual DAC_C0 bitfields
 394  */
 395
 396 /*!
 397  * @name Register DAC_C0, field DACBBIEN[0] (RW)
 398  *
 399  * Values:
 400  * - 0 - The DAC buffer read pointer bottom flag interrupt is disabled.
 401  * - 1 - The DAC buffer read pointer bottom flag interrupt is enabled.
 402  */
 403 /*@{*/
 404 #define BP_DAC_C0_DACBBIEN   (0U)          /*!< Bit position for DAC_C0_DACBBIEN. */
 405 #define BM_DAC_C0_DACBBIEN   (0x01U)       /*!< Bit mask for DAC_C0_DACBBIEN. */
 406 #define BS_DAC_C0_DACBBIEN   (1U)          /*!< Bit field size in bits for DAC_C0_DACBBIEN. */
 407
 408 /*! @brief Read current value of the DAC_C0_DACBBIEN field. */
 409 #define BR_DAC_C0_DACBBIEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBBIEN))
 410
 411 /*! @brief Format value for bitfield DAC_C0_DACBBIEN. */
 412 #define BF_DAC_C0_DACBBIEN(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACBBIEN) & BM_DAC_C0_DACBBIEN)
 413
 414 /*! @brief Set the DACBBIEN field to a new value. */
 415 #define BW_DAC_C0_DACBBIEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBBIEN) = (v))
 416 /*@}*/
 417
 418 /*!
 419  * @name Register DAC_C0, field DACBTIEN[1] (RW)
 420  *
 421  * Values:
 422  * - 0 - The DAC buffer read pointer top flag interrupt is disabled.
 423  * - 1 - The DAC buffer read pointer top flag interrupt is enabled.
 424  */
 425 /*@{*/
 426 #define BP_DAC_C0_DACBTIEN   (1U)          /*!< Bit position for DAC_C0_DACBTIEN. */
 427 #define BM_DAC_C0_DACBTIEN   (0x02U)       /*!< Bit mask for DAC_C0_DACBTIEN. */
 428 #define BS_DAC_C0_DACBTIEN   (1U)          /*!< Bit field size in bits for DAC_C0_DACBTIEN. */
 429
 430 /*! @brief Read current value of the DAC_C0_DACBTIEN field. */
 431 #define BR_DAC_C0_DACBTIEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBTIEN))
 432
 433 /*! @brief Format value for bitfield DAC_C0_DACBTIEN. */
 434 #define BF_DAC_C0_DACBTIEN(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACBTIEN) & BM_DAC_C0_DACBTIEN)
 435
 436 /*! @brief Set the DACBTIEN field to a new value. */
 437 #define BW_DAC_C0_DACBTIEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBTIEN) = (v))
 438 /*@}*/
 439
 440 /*!
 441  * @name Register DAC_C0, field DACBWIEN[2] (RW)
 442  *
 443  * Values:
 444  * - 0 - The DAC buffer watermark interrupt is disabled.
 445  * - 1 - The DAC buffer watermark interrupt is enabled.
 446  */
 447 /*@{*/
 448 #define BP_DAC_C0_DACBWIEN   (2U)          /*!< Bit position for DAC_C0_DACBWIEN. */
 449 #define BM_DAC_C0_DACBWIEN   (0x04U)       /*!< Bit mask for DAC_C0_DACBWIEN. */
 450 #define BS_DAC_C0_DACBWIEN   (1U)          /*!< Bit field size in bits for DAC_C0_DACBWIEN. */
 451
 452 /*! @brief Read current value of the DAC_C0_DACBWIEN field. */
 453 #define BR_DAC_C0_DACBWIEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBWIEN))
 454
 455 /*! @brief Format value for bitfield DAC_C0_DACBWIEN. */
 456 #define BF_DAC_C0_DACBWIEN(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACBWIEN) & BM_DAC_C0_DACBWIEN)
 457
 458 /*! @brief Set the DACBWIEN field to a new value. */
 459 #define BW_DAC_C0_DACBWIEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBWIEN) = (v))
 460 /*@}*/
 461
 462 /*!
 463  * @name Register DAC_C0, field LPEN[3] (RW)
 464  *
 465  * See the 12-bit DAC electrical characteristics of the device data sheet for
 466  * details on the impact of the modes below.
 467  *
 468  * Values:
 469  * - 0 - High-Power mode
 470  * - 1 - Low-Power mode
 471  */
 472 /*@{*/
 473 #define BP_DAC_C0_LPEN       (3U)          /*!< Bit position for DAC_C0_LPEN. */
 474 #define BM_DAC_C0_LPEN       (0x08U)       /*!< Bit mask for DAC_C0_LPEN. */
 475 #define BS_DAC_C0_LPEN       (1U)          /*!< Bit field size in bits for DAC_C0_LPEN. */
 476
 477 /*! @brief Read current value of the DAC_C0_LPEN field. */
 478 #define BR_DAC_C0_LPEN(x)    (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_LPEN))
 479
 480 /*! @brief Format value for bitfield DAC_C0_LPEN. */
 481 #define BF_DAC_C0_LPEN(v)    ((uint8_t)((uint8_t)(v) << BP_DAC_C0_LPEN) & BM_DAC_C0_LPEN)
 482
 483 /*! @brief Set the LPEN field to a new value. */
 484 #define BW_DAC_C0_LPEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_LPEN) = (v))
 485 /*@}*/
 486
 487 /*!
 488  * @name Register DAC_C0, field DACSWTRG[4] (WORZ)
 489  *
 490  * Active high. This is a write-only field, which always reads 0. If DAC
 491  * software trigger is selected and buffer is enabled, writing 1 to this field will
 492  * advance the buffer read pointer once.
 493  *
 494  * Values:
 495  * - 0 - The DAC soft trigger is not valid.
 496  * - 1 - The DAC soft trigger is valid.
 497  */
 498 /*@{*/
 499 #define BP_DAC_C0_DACSWTRG   (4U)          /*!< Bit position for DAC_C0_DACSWTRG. */
 500 #define BM_DAC_C0_DACSWTRG   (0x10U)       /*!< Bit mask for DAC_C0_DACSWTRG. */
 501 #define BS_DAC_C0_DACSWTRG   (1U)          /*!< Bit field size in bits for DAC_C0_DACSWTRG. */
 502
 503 /*! @brief Format value for bitfield DAC_C0_DACSWTRG. */
 504 #define BF_DAC_C0_DACSWTRG(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACSWTRG) & BM_DAC_C0_DACSWTRG)
 505
 506 /*! @brief Set the DACSWTRG field to a new value. */
 507 #define BW_DAC_C0_DACSWTRG(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACSWTRG) = (v))
 508 /*@}*/
 509
 510 /*!
 511  * @name Register DAC_C0, field DACTRGSEL[5] (RW)
 512  *
 513  * Values:
 514  * - 0 - The DAC hardware trigger is selected.
 515  * - 1 - The DAC software trigger is selected.
 516  */
 517 /*@{*/
 518 #define BP_DAC_C0_DACTRGSEL  (5U)          /*!< Bit position for DAC_C0_DACTRGSEL. */
 519 #define BM_DAC_C0_DACTRGSEL  (0x20U)       /*!< Bit mask for DAC_C0_DACTRGSEL. */
 520 #define BS_DAC_C0_DACTRGSEL  (1U)          /*!< Bit field size in bits for DAC_C0_DACTRGSEL. */
 521
 522 /*! @brief Read current value of the DAC_C0_DACTRGSEL field. */
 523 #define BR_DAC_C0_DACTRGSEL(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACTRGSEL))
 524
 525 /*! @brief Format value for bitfield DAC_C0_DACTRGSEL. */
 526 #define BF_DAC_C0_DACTRGSEL(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACTRGSEL) & BM_DAC_C0_DACTRGSEL)
 527
 528 /*! @brief Set the DACTRGSEL field to a new value. */
 529 #define BW_DAC_C0_DACTRGSEL(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACTRGSEL) = (v))
 530 /*@}*/
 531
 532 /*!
 533  * @name Register DAC_C0, field DACRFS[6] (RW)
 534  *
 535  * Values:
 536  * - 0 - The DAC selects DACREF_1 as the reference voltage.
 537  * - 1 - The DAC selects DACREF_2 as the reference voltage.
 538  */
 539 /*@{*/
 540 #define BP_DAC_C0_DACRFS     (6U)          /*!< Bit position for DAC_C0_DACRFS. */
 541 #define BM_DAC_C0_DACRFS     (0x40U)       /*!< Bit mask for DAC_C0_DACRFS. */
 542 #define BS_DAC_C0_DACRFS     (1U)          /*!< Bit field size in bits for DAC_C0_DACRFS. */
 543
 544 /*! @brief Read current value of the DAC_C0_DACRFS field. */
 545 #define BR_DAC_C0_DACRFS(x)  (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACRFS))
 546
 547 /*! @brief Format value for bitfield DAC_C0_DACRFS. */
 548 #define BF_DAC_C0_DACRFS(v)  ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACRFS) & BM_DAC_C0_DACRFS)
 549
 550 /*! @brief Set the DACRFS field to a new value. */
 551 #define BW_DAC_C0_DACRFS(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACRFS) = (v))
 552 /*@}*/
 553
 554 /*!
 555  * @name Register DAC_C0, field DACEN[7] (RW)
 556  *
 557  * Starts the Programmable Reference Generator operation.
 558  *
 559  * Values:
 560  * - 0 - The DAC system is disabled.
 561  * - 1 - The DAC system is enabled.
 562  */
 563 /*@{*/
 564 #define BP_DAC_C0_DACEN      (7U)          /*!< Bit position for DAC_C0_DACEN. */
 565 #define BM_DAC_C0_DACEN      (0x80U)       /*!< Bit mask for DAC_C0_DACEN. */
 566 #define BS_DAC_C0_DACEN      (1U)          /*!< Bit field size in bits for DAC_C0_DACEN. */
 567
 568 /*! @brief Read current value of the DAC_C0_DACEN field. */
 569 #define BR_DAC_C0_DACEN(x)   (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACEN))
 570
 571 /*! @brief Format value for bitfield DAC_C0_DACEN. */
 572 #define BF_DAC_C0_DACEN(v)   ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACEN) & BM_DAC_C0_DACEN)
 573
 574 /*! @brief Set the DACEN field to a new value. */
 575 #define BW_DAC_C0_DACEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACEN) = (v))
 576 /*@}*/
 577
 578 /*******************************************************************************
 579  * HW_DAC_C1 - DAC Control Register 1
 580  ******************************************************************************/
 581
 582 /*!
 583  * @brief HW_DAC_C1 - DAC Control Register 1 (RW)
 584  *
 585  * Reset value: 0x00U
 586  */
 587 typedef union _hw_dac_c1
 588 {
 589     uint8_t U;
 590     struct _hw_dac_c1_bitfields
 591     {
 592         uint8_t DACBFEN : 1;           /*!< [0] DAC Buffer Enable */
 593         uint8_t DACBFMD : 2;           /*!< [2:1] DAC Buffer Work Mode Select */
 594         uint8_t DACBFWM : 2;           /*!< [4:3] DAC Buffer Watermark Select */
 595         uint8_t RESERVED0 : 2;         /*!< [6:5]  */
 596         uint8_t DMAEN : 1;             /*!< [7] DMA Enable Select */
 597     } B;
 598 } hw_dac_c1_t;
 599
 600 /*!
 601  * @name Constants and macros for entire DAC_C1 register
 602  */
 603 /*@{*/
 604 #define HW_DAC_C1_ADDR(x)        ((x) + 0x22U)
 605
 606 #define HW_DAC_C1(x)             (*(__IO hw_dac_c1_t *) HW_DAC_C1_ADDR(x))
 607 #define HW_DAC_C1_RD(x)          (HW_DAC_C1(x).U)
 608 #define HW_DAC_C1_WR(x, v)       (HW_DAC_C1(x).U = (v))
 609 #define HW_DAC_C1_SET(x, v)      (HW_DAC_C1_WR(x, HW_DAC_C1_RD(x) |  (v)))
 610 #define HW_DAC_C1_CLR(x, v)      (HW_DAC_C1_WR(x, HW_DAC_C1_RD(x) & ~(v)))
 611 #define HW_DAC_C1_TOG(x, v)      (HW_DAC_C1_WR(x, HW_DAC_C1_RD(x) ^  (v)))
 612 /*@}*/
 613
 614 /*
 615  * Constants & macros for individual DAC_C1 bitfields
 616  */
 617
 618 /*!
 619  * @name Register DAC_C1, field DACBFEN[0] (RW)
 620  *
 621  * Values:
 622  * - 0 - Buffer read pointer is disabled. The converted data is always the first
 623  *     word of the buffer.
 624  * - 1 - Buffer read pointer is enabled. The converted data is the word that the
 625  *     read pointer points to. It means converted data can be from any word of
 626  *     the buffer.
 627  */
 628 /*@{*/
 629 #define BP_DAC_C1_DACBFEN    (0U)          /*!< Bit position for DAC_C1_DACBFEN. */
 630 #define BM_DAC_C1_DACBFEN    (0x01U)       /*!< Bit mask for DAC_C1_DACBFEN. */
 631 #define BS_DAC_C1_DACBFEN    (1U)          /*!< Bit field size in bits for DAC_C1_DACBFEN. */
 632
 633 /*! @brief Read current value of the DAC_C1_DACBFEN field. */
 634 #define BR_DAC_C1_DACBFEN(x) (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DACBFEN))
 635
 636 /*! @brief Format value for bitfield DAC_C1_DACBFEN. */
 637 #define BF_DAC_C1_DACBFEN(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C1_DACBFEN) & BM_DAC_C1_DACBFEN)
 638
 639 /*! @brief Set the DACBFEN field to a new value. */
 640 #define BW_DAC_C1_DACBFEN(x, v) (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DACBFEN) = (v))
 641 /*@}*/
 642
 643 /*!
 644  * @name Register DAC_C1, field DACBFMD[2:1] (RW)
 645  *
 646  * Values:
 647  * - 00 - Normal mode
 648  * - 01 - Swing mode
 649  * - 10 - One-Time Scan mode
 650  * - 11 - FIFO mode
 651  */
 652 /*@{*/
 653 #define BP_DAC_C1_DACBFMD    (1U)          /*!< Bit position for DAC_C1_DACBFMD. */
 654 #define BM_DAC_C1_DACBFMD    (0x06U)       /*!< Bit mask for DAC_C1_DACBFMD. */
 655 #define BS_DAC_C1_DACBFMD    (2U)          /*!< Bit field size in bits for DAC_C1_DACBFMD. */
 656
 657 /*! @brief Read current value of the DAC_C1_DACBFMD field. */
 658 #define BR_DAC_C1_DACBFMD(x) (HW_DAC_C1(x).B.DACBFMD)
 659
 660 /*! @brief Format value for bitfield DAC_C1_DACBFMD. */
 661 #define BF_DAC_C1_DACBFMD(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C1_DACBFMD) & BM_DAC_C1_DACBFMD)
 662
 663 /*! @brief Set the DACBFMD field to a new value. */
 664 #define BW_DAC_C1_DACBFMD(x, v) (HW_DAC_C1_WR(x, (HW_DAC_C1_RD(x) & ~BM_DAC_C1_DACBFMD) | BF_DAC_C1_DACBFMD(v)))
 665 /*@}*/
 666
 667 /*!
 668  * @name Register DAC_C1, field DACBFWM[4:3] (RW)
 669  *
 670  * In normal mode it controls when SR[DACBFWMF] is set. When the DAC buffer read
 671  * pointer reaches the word defined by this field, which is 1-4 words away from
 672  * the upper limit (DACBUP), SR[DACBFWMF] will be set. This allows user
 673  * configuration of the watermark interrupt. In FIFO mode, it is FIFO watermark select
 674  * field.
 675  *
 676  * Values:
 677  * - 00 - In normal mode, 1 word . In FIFO mode, 2 or less than 2 data remaining
 678  *     in FIFO will set watermark status bit.
 679  * - 01 - In normal mode, 2 words . In FIFO mode, Max/4 or less than Max/4 data
 680  *     remaining in FIFO will set watermark status bit.
 681  * - 10 - In normal mode, 3 words . In FIFO mode, Max/2 or less than Max/2 data
 682  *     remaining in FIFO will set watermark status bit.
 683  * - 11 - In normal mode, 4 words . In FIFO mode, Max-2 or less than Max-2 data
 684  *     remaining in FIFO will set watermark status bit.
 685  */
 686 /*@{*/
 687 #define BP_DAC_C1_DACBFWM    (3U)          /*!< Bit position for DAC_C1_DACBFWM. */
 688 #define BM_DAC_C1_DACBFWM    (0x18U)       /*!< Bit mask for DAC_C1_DACBFWM. */
 689 #define BS_DAC_C1_DACBFWM    (2U)          /*!< Bit field size in bits for DAC_C1_DACBFWM. */
 690
 691 /*! @brief Read current value of the DAC_C1_DACBFWM field. */
 692 #define BR_DAC_C1_DACBFWM(x) (HW_DAC_C1(x).B.DACBFWM)
 693
 694 /*! @brief Format value for bitfield DAC_C1_DACBFWM. */
 695 #define BF_DAC_C1_DACBFWM(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C1_DACBFWM) & BM_DAC_C1_DACBFWM)
 696
 697 /*! @brief Set the DACBFWM field to a new value. */
 698 #define BW_DAC_C1_DACBFWM(x, v) (HW_DAC_C1_WR(x, (HW_DAC_C1_RD(x) & ~BM_DAC_C1_DACBFWM) | BF_DAC_C1_DACBFWM(v)))
 699 /*@}*/
 700
 701 /*!
 702  * @name Register DAC_C1, field DMAEN[7] (RW)
 703  *
 704  * Values:
 705  * - 0 - DMA is disabled.
 706  * - 1 - DMA is enabled. When DMA is enabled, the DMA request will be generated
 707  *     by original interrupts. The interrupts will not be presented on this
 708  *     module at the same time.
 709  */
 710 /*@{*/
 711 #define BP_DAC_C1_DMAEN      (7U)          /*!< Bit position for DAC_C1_DMAEN. */
 712 #define BM_DAC_C1_DMAEN      (0x80U)       /*!< Bit mask for DAC_C1_DMAEN. */
 713 #define BS_DAC_C1_DMAEN      (1U)          /*!< Bit field size in bits for DAC_C1_DMAEN. */
 714
 715 /*! @brief Read current value of the DAC_C1_DMAEN field. */
 716 #define BR_DAC_C1_DMAEN(x)   (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DMAEN))
 717
 718 /*! @brief Format value for bitfield DAC_C1_DMAEN. */
 719 #define BF_DAC_C1_DMAEN(v)   ((uint8_t)((uint8_t)(v) << BP_DAC_C1_DMAEN) & BM_DAC_C1_DMAEN)
 720
 721 /*! @brief Set the DMAEN field to a new value. */
 722 #define BW_DAC_C1_DMAEN(x, v) (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DMAEN) = (v))
 723 /*@}*/
 724
 725 /*******************************************************************************
 726  * HW_DAC_C2 - DAC Control Register 2
 727  ******************************************************************************/
 728
 729 /*!
 730  * @brief HW_DAC_C2 - DAC Control Register 2 (RW)
 731  *
 732  * Reset value: 0x0FU
 733  */
 734 typedef union _hw_dac_c2
 735 {
 736     uint8_t U;
 737     struct _hw_dac_c2_bitfields
 738     {
 739         uint8_t DACBFUP : 4;           /*!< [3:0] DAC Buffer Upper Limit */
 740         uint8_t DACBFRP : 4;           /*!< [7:4] DAC Buffer Read Pointer */
 741     } B;
 742 } hw_dac_c2_t;
 743
 744 /*!
 745  * @name Constants and macros for entire DAC_C2 register
 746  */
 747 /*@{*/
 748 #define HW_DAC_C2_ADDR(x)        ((x) + 0x23U)
 749
 750 #define HW_DAC_C2(x)             (*(__IO hw_dac_c2_t *) HW_DAC_C2_ADDR(x))
 751 #define HW_DAC_C2_RD(x)          (HW_DAC_C2(x).U)
 752 #define HW_DAC_C2_WR(x, v)       (HW_DAC_C2(x).U = (v))
 753 #define HW_DAC_C2_SET(x, v)      (HW_DAC_C2_WR(x, HW_DAC_C2_RD(x) |  (v)))
 754 #define HW_DAC_C2_CLR(x, v)      (HW_DAC_C2_WR(x, HW_DAC_C2_RD(x) & ~(v)))
 755 #define HW_DAC_C2_TOG(x, v)      (HW_DAC_C2_WR(x, HW_DAC_C2_RD(x) ^  (v)))
 756 /*@}*/
 757
 758 /*
 759  * Constants & macros for individual DAC_C2 bitfields
 760  */
 761
 762 /*!
 763  * @name Register DAC_C2, field DACBFUP[3:0] (RW)
 764  *
 765  * In normal mode it selects the upper limit of the DAC buffer. The buffer read
 766  * pointer cannot exceed it. In FIFO mode it is the FIFO write pointer. User
 767  * cannot set Buffer Up limit in FIFO mode. In Normal mode its reset value is MAX.
 768  * When IP is configured to FIFO mode, this register becomes Write_Pointer, and its
 769  * value is initially set to equal READ_POINTER automatically, and the FIFO
 770  * status is empty. It is writable and user can configure it to the same address to
 771  * reset FIFO as empty.
 772  */
 773 /*@{*/
 774 #define BP_DAC_C2_DACBFUP    (0U)          /*!< Bit position for DAC_C2_DACBFUP. */
 775 #define BM_DAC_C2_DACBFUP    (0x0FU)       /*!< Bit mask for DAC_C2_DACBFUP. */
 776 #define BS_DAC_C2_DACBFUP    (4U)          /*!< Bit field size in bits for DAC_C2_DACBFUP. */
 777
 778 /*! @brief Read current value of the DAC_C2_DACBFUP field. */
 779 #define BR_DAC_C2_DACBFUP(x) (HW_DAC_C2(x).B.DACBFUP)
 780
 781 /*! @brief Format value for bitfield DAC_C2_DACBFUP. */
 782 #define BF_DAC_C2_DACBFUP(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C2_DACBFUP) & BM_DAC_C2_DACBFUP)
 783
 784 /*! @brief Set the DACBFUP field to a new value. */
 785 #define BW_DAC_C2_DACBFUP(x, v) (HW_DAC_C2_WR(x, (HW_DAC_C2_RD(x) & ~BM_DAC_C2_DACBFUP) | BF_DAC_C2_DACBFUP(v)))
 786 /*@}*/
 787
 788 /*!
 789  * @name Register DAC_C2, field DACBFRP[7:4] (RW)
 790  *
 791  * In normal mode it keeps the current value of the buffer read pointer. FIFO
 792  * mode, it is the FIFO read pointer. It is writable in FIFO mode. User can
 793  * configure it to same address to reset FIFO as empty.
 794  */
 795 /*@{*/
 796 #define BP_DAC_C2_DACBFRP    (4U)          /*!< Bit position for DAC_C2_DACBFRP. */
 797 #define BM_DAC_C2_DACBFRP    (0xF0U)       /*!< Bit mask for DAC_C2_DACBFRP. */
 798 #define BS_DAC_C2_DACBFRP    (4U)          /*!< Bit field size in bits for DAC_C2_DACBFRP. */
 799
 800 /*! @brief Read current value of the DAC_C2_DACBFRP field. */
 801 #define BR_DAC_C2_DACBFRP(x) (HW_DAC_C2(x).B.DACBFRP)
 802
 803 /*! @brief Format value for bitfield DAC_C2_DACBFRP. */
 804 #define BF_DAC_C2_DACBFRP(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C2_DACBFRP) & BM_DAC_C2_DACBFRP)
 805
 806 /*! @brief Set the DACBFRP field to a new value. */
 807 #define BW_DAC_C2_DACBFRP(x, v) (HW_DAC_C2_WR(x, (HW_DAC_C2_RD(x) & ~BM_DAC_C2_DACBFRP) | BF_DAC_C2_DACBFRP(v)))
 808 /*@}*/
 809
 810 /*******************************************************************************
 811  * hw_dac_t - module struct
 812  ******************************************************************************/
 813 /*!
 814  * @brief All DAC module registers.
 815  */
 816 #pragma pack(1)
 817 typedef struct _hw_dac
 818 {
 819     struct {
 820         __IO hw_dac_datnl_t DATnL;         /*!< [0x0] DAC Data Low Register */
 821         __IO hw_dac_datnh_t DATnH;         /*!< [0x1] DAC Data High Register */
 822     } DAT[16];
 823     __IO hw_dac_sr_t SR;                   /*!< [0x20] DAC Status Register */
 824     __IO hw_dac_c0_t C0;                   /*!< [0x21] DAC Control Register */
 825     __IO hw_dac_c1_t C1;                   /*!< [0x22] DAC Control Register 1 */
 826     __IO hw_dac_c2_t C2;                   /*!< [0x23] DAC Control Register 2 */
 827 } hw_dac_t;
 828 #pragma pack()
 829
 830 /*! @brief Macro to access all DAC registers. */
 831 /*! @param x DAC module instance base address. */
 832 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
 833  *     use the '&' operator, like <code>&HW_DAC(DAC0_BASE)</code>. */
 834 #define HW_DAC(x)      (*(hw_dac_t *)(x))
 835
 836 #endif /* __HW_DAC_REGISTERS_H__ */
 837 /* EOF */