2 ** ###################################################################
3 ** Compilers: Keil ARM C/C++ Compiler
4 ** Freescale C/C++ for Embedded ARM
6 ** IAR ANSI C/C++ Compiler for ARM
8 ** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
9 ** Version: rev. 2.5, 2014-05-06
13 ** Extension to the CMSIS register access layer header.
15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
16 ** All rights reserved.
18 ** Redistribution and use in source and binary forms, with or without modification,
19 ** are permitted provided that the following conditions are met:
21 ** o Redistributions of source code must retain the above copyright notice, this list
22 ** of conditions and the following disclaimer.
24 ** o Redistributions in binary form must reproduce the above copyright notice, this
25 ** list of conditions and the following disclaimer in the documentation and/or
26 ** other materials provided with the distribution.
28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
29 ** contributors may be used to endorse or promote products derived from this
30 ** software without specific prior written permission.
32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 ** http: www.freescale.com
44 ** mail: support@freescale.com
47 ** - rev. 1.0 (2013-07-23)
49 ** - rev. 1.1 (2013-09-17)
50 ** RM rev. 0.4 update.
51 ** - rev. 2.0 (2013-10-29)
52 ** Register accessor macros added to the memory map.
53 ** Symbols for Processor Expert memory map compatibility added to the memory map.
54 ** Startup file for gcc has been updated according to CMSIS 3.2.
55 ** System initialization updated.
56 ** - rev. 2.1 (2013-10-30)
57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
58 ** - rev. 2.2 (2013-12-20)
59 ** Update according to reference manual rev. 0.6,
60 ** - rev. 2.3 (2014-01-13)
61 ** Update according to reference manual rev. 0.61,
62 ** - rev. 2.4 (2014-02-10)
63 ** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
64 ** - rev. 2.5 (2014-05-06)
65 ** Update according to reference manual rev. 1.0,
66 ** Update of system and startup files.
67 ** Module access macro module_BASES replaced by module_BASE_PTRS.
69 ** ###################################################################
73 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
75 * This file was generated automatically and any changes may be lost.
77 #ifndef __HW_FTFA_REGISTERS_H__
78 #define __HW_FTFA_REGISTERS_H__
80 #include "MK22F51212.h"
81 #include "fsl_bitaccess.h"
86 * Flash Memory Interface
88 * Registers defined in this header file:
89 * - HW_FTFA_FSTAT - Flash Status Register
90 * - HW_FTFA_FCNFG - Flash Configuration Register
91 * - HW_FTFA_FSEC - Flash Security Register
92 * - HW_FTFA_FOPT - Flash Option Register
93 * - HW_FTFA_FCCOB3 - Flash Common Command Object Registers
94 * - HW_FTFA_FCCOB2 - Flash Common Command Object Registers
95 * - HW_FTFA_FCCOB1 - Flash Common Command Object Registers
96 * - HW_FTFA_FCCOB0 - Flash Common Command Object Registers
97 * - HW_FTFA_FCCOB7 - Flash Common Command Object Registers
98 * - HW_FTFA_FCCOB6 - Flash Common Command Object Registers
99 * - HW_FTFA_FCCOB5 - Flash Common Command Object Registers
100 * - HW_FTFA_FCCOB4 - Flash Common Command Object Registers
101 * - HW_FTFA_FCCOBB - Flash Common Command Object Registers
102 * - HW_FTFA_FCCOBA - Flash Common Command Object Registers
103 * - HW_FTFA_FCCOB9 - Flash Common Command Object Registers
104 * - HW_FTFA_FCCOB8 - Flash Common Command Object Registers
105 * - HW_FTFA_FPROT3 - Program Flash Protection Registers
106 * - HW_FTFA_FPROT2 - Program Flash Protection Registers
107 * - HW_FTFA_FPROT1 - Program Flash Protection Registers
108 * - HW_FTFA_FPROT0 - Program Flash Protection Registers
109 * - HW_FTFA_XACCH3 - Execute-only Access Registers
110 * - HW_FTFA_XACCH2 - Execute-only Access Registers
111 * - HW_FTFA_XACCH1 - Execute-only Access Registers
112 * - HW_FTFA_XACCH0 - Execute-only Access Registers
113 * - HW_FTFA_XACCL3 - Execute-only Access Registers
114 * - HW_FTFA_XACCL2 - Execute-only Access Registers
115 * - HW_FTFA_XACCL1 - Execute-only Access Registers
116 * - HW_FTFA_XACCL0 - Execute-only Access Registers
117 * - HW_FTFA_SACCH3 - Supervisor-only Access Registers
118 * - HW_FTFA_SACCH2 - Supervisor-only Access Registers
119 * - HW_FTFA_SACCH1 - Supervisor-only Access Registers
120 * - HW_FTFA_SACCH0 - Supervisor-only Access Registers
121 * - HW_FTFA_SACCL3 - Supervisor-only Access Registers
122 * - HW_FTFA_SACCL2 - Supervisor-only Access Registers
123 * - HW_FTFA_SACCL1 - Supervisor-only Access Registers
124 * - HW_FTFA_SACCL0 - Supervisor-only Access Registers
125 * - HW_FTFA_FACSS - Flash Access Segment Size Register
126 * - HW_FTFA_FACSN - Flash Access Segment Number Register
128 * - hw_ftfa_t - Struct containing all module registers.
131 #define HW_FTFA_INSTANCE_COUNT (1U) /*!< Number of instances of the FTFA module. */
133 /*******************************************************************************
134 * HW_FTFA_FSTAT - Flash Status Register
135 ******************************************************************************/
138 * @brief HW_FTFA_FSTAT - Flash Status Register (RW)
142 * The FSTAT register reports the operational status of the flash memory module.
143 * The CCIF, RDCOLERR, ACCERR, and FPVIOL bits are readable and writable. The
144 * MGSTAT0 bit is read only. The unassigned bits read 0 and are not writable. When
145 * set, the Access Error (ACCERR) and Flash Protection Violation (FPVIOL) bits in
146 * this register prevent the launch of any more commands until the flag is
147 * cleared (by writing a one to it).
149 typedef union _hw_ftfa_fstat
152 struct _hw_ftfa_fstat_bitfields
154 uint8_t MGSTAT0
: 1; /*!< [0] Memory Controller Command Completion
156 uint8_t RESERVED0
: 3; /*!< [3:1] */
157 uint8_t FPVIOL
: 1; /*!< [4] Flash Protection Violation Flag */
158 uint8_t ACCERR
: 1; /*!< [5] Flash Access Error Flag */
159 uint8_t RDCOLERR
: 1; /*!< [6] Flash Read Collision Error Flag */
160 uint8_t CCIF
: 1; /*!< [7] Command Complete Interrupt Flag */
165 * @name Constants and macros for entire FTFA_FSTAT register
168 #define HW_FTFA_FSTAT_ADDR(x) ((x) + 0x0U)
170 #define HW_FTFA_FSTAT(x) (*(__IO hw_ftfa_fstat_t *) HW_FTFA_FSTAT_ADDR(x))
171 #define HW_FTFA_FSTAT_RD(x) (HW_FTFA_FSTAT(x).U)
172 #define HW_FTFA_FSTAT_WR(x, v) (HW_FTFA_FSTAT(x).U = (v))
173 #define HW_FTFA_FSTAT_SET(x, v) (HW_FTFA_FSTAT_WR(x, HW_FTFA_FSTAT_RD(x) | (v)))
174 #define HW_FTFA_FSTAT_CLR(x, v) (HW_FTFA_FSTAT_WR(x, HW_FTFA_FSTAT_RD(x) & ~(v)))
175 #define HW_FTFA_FSTAT_TOG(x, v) (HW_FTFA_FSTAT_WR(x, HW_FTFA_FSTAT_RD(x) ^ (v)))
179 * Constants & macros for individual FTFA_FSTAT bitfields
183 * @name Register FTFA_FSTAT, field MGSTAT0[0] (RO)
185 * The MGSTAT0 status flag is set if an error is detected during execution of a
186 * flash command or during the flash reset sequence. As a status flag, this field
187 * cannot (and need not) be cleared by the user like the other error flags in
188 * this register. The value of the MGSTAT0 bit for "command-N" is valid only at the
189 * end of the "command-N" execution when CCIF=1 and before the next command has
190 * been launched. At some point during the execution of "command-N+1," the
191 * previous result is discarded and any previous error is cleared.
194 #define BP_FTFA_FSTAT_MGSTAT0 (0U) /*!< Bit position for FTFA_FSTAT_MGSTAT0. */
195 #define BM_FTFA_FSTAT_MGSTAT0 (0x01U) /*!< Bit mask for FTFA_FSTAT_MGSTAT0. */
196 #define BS_FTFA_FSTAT_MGSTAT0 (1U) /*!< Bit field size in bits for FTFA_FSTAT_MGSTAT0. */
198 /*! @brief Read current value of the FTFA_FSTAT_MGSTAT0 field. */
199 #define BR_FTFA_FSTAT_MGSTAT0(x) (BITBAND_ACCESS8(HW_FTFA_FSTAT_ADDR(x), BP_FTFA_FSTAT_MGSTAT0))
203 * @name Register FTFA_FSTAT, field FPVIOL[4] (W1C)
205 * Indicates an attempt was made to program or erase an address in a protected
206 * area of program flash memory during a command write sequence . While FPVIOL is
207 * set, the CCIF flag cannot be cleared to launch a command. The FPVIOL bit is
208 * cleared by writing a 1 to it. Writing a 0 to the FPVIOL bit has no effect.
211 * - 0 - No protection violation detected
212 * - 1 - Protection violation detected
215 #define BP_FTFA_FSTAT_FPVIOL (4U) /*!< Bit position for FTFA_FSTAT_FPVIOL. */
216 #define BM_FTFA_FSTAT_FPVIOL (0x10U) /*!< Bit mask for FTFA_FSTAT_FPVIOL. */
217 #define BS_FTFA_FSTAT_FPVIOL (1U) /*!< Bit field size in bits for FTFA_FSTAT_FPVIOL. */
219 /*! @brief Read current value of the FTFA_FSTAT_FPVIOL field. */
220 #define BR_FTFA_FSTAT_FPVIOL(x) (BITBAND_ACCESS8(HW_FTFA_FSTAT_ADDR(x), BP_FTFA_FSTAT_FPVIOL))
222 /*! @brief Format value for bitfield FTFA_FSTAT_FPVIOL. */
223 #define BF_FTFA_FSTAT_FPVIOL(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FSTAT_FPVIOL) & BM_FTFA_FSTAT_FPVIOL)
225 /*! @brief Set the FPVIOL field to a new value. */
226 #define BW_FTFA_FSTAT_FPVIOL(x, v) (BITBAND_ACCESS8(HW_FTFA_FSTAT_ADDR(x), BP_FTFA_FSTAT_FPVIOL) = (v))
230 * @name Register FTFA_FSTAT, field ACCERR[5] (W1C)
232 * Indicates an illegal access has occurred to a flash memory resource caused by
233 * a violation of the command write sequence or issuing an illegal flash
234 * command. While ACCERR is set, the CCIF flag cannot be cleared to launch a command.
235 * The ACCERR bit is cleared by writing a 1 to it. Writing a 0 to the ACCERR bit
239 * - 0 - No access error detected
240 * - 1 - Access error detected
243 #define BP_FTFA_FSTAT_ACCERR (5U) /*!< Bit position for FTFA_FSTAT_ACCERR. */
244 #define BM_FTFA_FSTAT_ACCERR (0x20U) /*!< Bit mask for FTFA_FSTAT_ACCERR. */
245 #define BS_FTFA_FSTAT_ACCERR (1U) /*!< Bit field size in bits for FTFA_FSTAT_ACCERR. */
247 /*! @brief Read current value of the FTFA_FSTAT_ACCERR field. */
248 #define BR_FTFA_FSTAT_ACCERR(x) (BITBAND_ACCESS8(HW_FTFA_FSTAT_ADDR(x), BP_FTFA_FSTAT_ACCERR))
250 /*! @brief Format value for bitfield FTFA_FSTAT_ACCERR. */
251 #define BF_FTFA_FSTAT_ACCERR(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FSTAT_ACCERR) & BM_FTFA_FSTAT_ACCERR)
253 /*! @brief Set the ACCERR field to a new value. */
254 #define BW_FTFA_FSTAT_ACCERR(x, v) (BITBAND_ACCESS8(HW_FTFA_FSTAT_ADDR(x), BP_FTFA_FSTAT_ACCERR) = (v))
258 * @name Register FTFA_FSTAT, field RDCOLERR[6] (W1C)
260 * Indicates that the MCU attempted a read from a flash memory resource that was
261 * being manipulated by a flash command (CCIF=0). Any simultaneous access is
262 * detected as a collision error by the block arbitration logic. The read data in
263 * this case cannot be guaranteed. The RDCOLERR bit is cleared by writing a 1 to
264 * it. Writing a 0 to RDCOLERR has no effect.
267 * - 0 - No collision error detected
268 * - 1 - Collision error detected
271 #define BP_FTFA_FSTAT_RDCOLERR (6U) /*!< Bit position for FTFA_FSTAT_RDCOLERR. */
272 #define BM_FTFA_FSTAT_RDCOLERR (0x40U) /*!< Bit mask for FTFA_FSTAT_RDCOLERR. */
273 #define BS_FTFA_FSTAT_RDCOLERR (1U) /*!< Bit field size in bits for FTFA_FSTAT_RDCOLERR. */
275 /*! @brief Read current value of the FTFA_FSTAT_RDCOLERR field. */
276 #define BR_FTFA_FSTAT_RDCOLERR(x) (BITBAND_ACCESS8(HW_FTFA_FSTAT_ADDR(x), BP_FTFA_FSTAT_RDCOLERR))
278 /*! @brief Format value for bitfield FTFA_FSTAT_RDCOLERR. */
279 #define BF_FTFA_FSTAT_RDCOLERR(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FSTAT_RDCOLERR) & BM_FTFA_FSTAT_RDCOLERR)
281 /*! @brief Set the RDCOLERR field to a new value. */
282 #define BW_FTFA_FSTAT_RDCOLERR(x, v) (BITBAND_ACCESS8(HW_FTFA_FSTAT_ADDR(x), BP_FTFA_FSTAT_RDCOLERR) = (v))
286 * @name Register FTFA_FSTAT, field CCIF[7] (W1C)
288 * Indicates that a flash command has completed. The CCIF flag is cleared by
289 * writing a 1 to CCIF to launch a command, and CCIF stays low until command
290 * completion or command violation. CCIF is reset to 0 but is set to 1 by the memory
291 * controller at the end of the reset initialization sequence. Depending on how
292 * quickly the read occurs after reset release, the user may or may not see the 0
293 * hardware reset value.
296 * - 0 - Flash command in progress
297 * - 1 - Flash command has completed
300 #define BP_FTFA_FSTAT_CCIF (7U) /*!< Bit position for FTFA_FSTAT_CCIF. */
301 #define BM_FTFA_FSTAT_CCIF (0x80U) /*!< Bit mask for FTFA_FSTAT_CCIF. */
302 #define BS_FTFA_FSTAT_CCIF (1U) /*!< Bit field size in bits for FTFA_FSTAT_CCIF. */
304 /*! @brief Read current value of the FTFA_FSTAT_CCIF field. */
305 #define BR_FTFA_FSTAT_CCIF(x) (BITBAND_ACCESS8(HW_FTFA_FSTAT_ADDR(x), BP_FTFA_FSTAT_CCIF))
307 /*! @brief Format value for bitfield FTFA_FSTAT_CCIF. */
308 #define BF_FTFA_FSTAT_CCIF(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FSTAT_CCIF) & BM_FTFA_FSTAT_CCIF)
310 /*! @brief Set the CCIF field to a new value. */
311 #define BW_FTFA_FSTAT_CCIF(x, v) (BITBAND_ACCESS8(HW_FTFA_FSTAT_ADDR(x), BP_FTFA_FSTAT_CCIF) = (v))
314 /*******************************************************************************
315 * HW_FTFA_FCNFG - Flash Configuration Register
316 ******************************************************************************/
319 * @brief HW_FTFA_FCNFG - Flash Configuration Register (RW)
323 * This register provides information on the current functional state of the
324 * flash memory module. The erase control bits (ERSAREQ and ERSSUSP) have write
325 * restrictions. The unassigned bits read as noted and are not writable.
327 typedef union _hw_ftfa_fcnfg
330 struct _hw_ftfa_fcnfg_bitfields
332 uint8_t RESERVED0
: 4; /*!< [3:0] */
333 uint8_t ERSSUSP
: 1; /*!< [4] Erase Suspend */
334 uint8_t ERSAREQ
: 1; /*!< [5] Erase All Request */
335 uint8_t RDCOLLIE
: 1; /*!< [6] Read Collision Error Interrupt Enable
337 uint8_t CCIE
: 1; /*!< [7] Command Complete Interrupt Enable */
342 * @name Constants and macros for entire FTFA_FCNFG register
345 #define HW_FTFA_FCNFG_ADDR(x) ((x) + 0x1U)
347 #define HW_FTFA_FCNFG(x) (*(__IO hw_ftfa_fcnfg_t *) HW_FTFA_FCNFG_ADDR(x))
348 #define HW_FTFA_FCNFG_RD(x) (HW_FTFA_FCNFG(x).U)
349 #define HW_FTFA_FCNFG_WR(x, v) (HW_FTFA_FCNFG(x).U = (v))
350 #define HW_FTFA_FCNFG_SET(x, v) (HW_FTFA_FCNFG_WR(x, HW_FTFA_FCNFG_RD(x) | (v)))
351 #define HW_FTFA_FCNFG_CLR(x, v) (HW_FTFA_FCNFG_WR(x, HW_FTFA_FCNFG_RD(x) & ~(v)))
352 #define HW_FTFA_FCNFG_TOG(x, v) (HW_FTFA_FCNFG_WR(x, HW_FTFA_FCNFG_RD(x) ^ (v)))
356 * Constants & macros for individual FTFA_FCNFG bitfields
360 * @name Register FTFA_FCNFG, field ERSSUSP[4] (RW)
362 * Allows the user to suspend (interrupt) the Erase Flash Sector command while
366 * - 0 - No suspend requested
367 * - 1 - Suspend the current Erase Flash Sector command execution.
370 #define BP_FTFA_FCNFG_ERSSUSP (4U) /*!< Bit position for FTFA_FCNFG_ERSSUSP. */
371 #define BM_FTFA_FCNFG_ERSSUSP (0x10U) /*!< Bit mask for FTFA_FCNFG_ERSSUSP. */
372 #define BS_FTFA_FCNFG_ERSSUSP (1U) /*!< Bit field size in bits for FTFA_FCNFG_ERSSUSP. */
374 /*! @brief Read current value of the FTFA_FCNFG_ERSSUSP field. */
375 #define BR_FTFA_FCNFG_ERSSUSP(x) (BITBAND_ACCESS8(HW_FTFA_FCNFG_ADDR(x), BP_FTFA_FCNFG_ERSSUSP))
377 /*! @brief Format value for bitfield FTFA_FCNFG_ERSSUSP. */
378 #define BF_FTFA_FCNFG_ERSSUSP(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FCNFG_ERSSUSP) & BM_FTFA_FCNFG_ERSSUSP)
380 /*! @brief Set the ERSSUSP field to a new value. */
381 #define BW_FTFA_FCNFG_ERSSUSP(x, v) (BITBAND_ACCESS8(HW_FTFA_FCNFG_ADDR(x), BP_FTFA_FCNFG_ERSSUSP) = (v))
385 * @name Register FTFA_FCNFG, field ERSAREQ[5] (RO)
387 * Issues a request to the memory controller to execute the Erase All Blocks
388 * command and release security. ERSAREQ is not directly writable but is under
389 * indirect user control. Refer to the device's Chip Configuration details on how to
390 * request this command. ERSAREQ sets when an erase all request is triggered
391 * external to the flash memory module and CCIF is set (no command is currently being
392 * executed). ERSAREQ is cleared by the flash memory module when the operation
396 * - 0 - No request or request complete
397 * - 1 - Request to: run the Erase All Blocks command, verify the erased state,
398 * program the security byte in the Flash Configuration Field to the unsecure
399 * state, and release MCU security by setting the FSEC[SEC] field to the
403 #define BP_FTFA_FCNFG_ERSAREQ (5U) /*!< Bit position for FTFA_FCNFG_ERSAREQ. */
404 #define BM_FTFA_FCNFG_ERSAREQ (0x20U) /*!< Bit mask for FTFA_FCNFG_ERSAREQ. */
405 #define BS_FTFA_FCNFG_ERSAREQ (1U) /*!< Bit field size in bits for FTFA_FCNFG_ERSAREQ. */
407 /*! @brief Read current value of the FTFA_FCNFG_ERSAREQ field. */
408 #define BR_FTFA_FCNFG_ERSAREQ(x) (BITBAND_ACCESS8(HW_FTFA_FCNFG_ADDR(x), BP_FTFA_FCNFG_ERSAREQ))
412 * @name Register FTFA_FCNFG, field RDCOLLIE[6] (RW)
414 * Controls interrupt generation when a flash memory read collision error occurs.
417 * - 0 - Read collision error interrupt disabled
418 * - 1 - Read collision error interrupt enabled. An interrupt request is
419 * generated whenever a flash memory read collision error is detected (see the
420 * description of FSTAT[RDCOLERR]).
423 #define BP_FTFA_FCNFG_RDCOLLIE (6U) /*!< Bit position for FTFA_FCNFG_RDCOLLIE. */
424 #define BM_FTFA_FCNFG_RDCOLLIE (0x40U) /*!< Bit mask for FTFA_FCNFG_RDCOLLIE. */
425 #define BS_FTFA_FCNFG_RDCOLLIE (1U) /*!< Bit field size in bits for FTFA_FCNFG_RDCOLLIE. */
427 /*! @brief Read current value of the FTFA_FCNFG_RDCOLLIE field. */
428 #define BR_FTFA_FCNFG_RDCOLLIE(x) (BITBAND_ACCESS8(HW_FTFA_FCNFG_ADDR(x), BP_FTFA_FCNFG_RDCOLLIE))
430 /*! @brief Format value for bitfield FTFA_FCNFG_RDCOLLIE. */
431 #define BF_FTFA_FCNFG_RDCOLLIE(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FCNFG_RDCOLLIE) & BM_FTFA_FCNFG_RDCOLLIE)
433 /*! @brief Set the RDCOLLIE field to a new value. */
434 #define BW_FTFA_FCNFG_RDCOLLIE(x, v) (BITBAND_ACCESS8(HW_FTFA_FCNFG_ADDR(x), BP_FTFA_FCNFG_RDCOLLIE) = (v))
438 * @name Register FTFA_FCNFG, field CCIE[7] (RW)
440 * Controls interrupt generation when a flash command completes.
443 * - 0 - Command complete interrupt disabled
444 * - 1 - Command complete interrupt enabled. An interrupt request is generated
445 * whenever the FSTAT[CCIF] flag is set.
448 #define BP_FTFA_FCNFG_CCIE (7U) /*!< Bit position for FTFA_FCNFG_CCIE. */
449 #define BM_FTFA_FCNFG_CCIE (0x80U) /*!< Bit mask for FTFA_FCNFG_CCIE. */
450 #define BS_FTFA_FCNFG_CCIE (1U) /*!< Bit field size in bits for FTFA_FCNFG_CCIE. */
452 /*! @brief Read current value of the FTFA_FCNFG_CCIE field. */
453 #define BR_FTFA_FCNFG_CCIE(x) (BITBAND_ACCESS8(HW_FTFA_FCNFG_ADDR(x), BP_FTFA_FCNFG_CCIE))
455 /*! @brief Format value for bitfield FTFA_FCNFG_CCIE. */
456 #define BF_FTFA_FCNFG_CCIE(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FCNFG_CCIE) & BM_FTFA_FCNFG_CCIE)
458 /*! @brief Set the CCIE field to a new value. */
459 #define BW_FTFA_FCNFG_CCIE(x, v) (BITBAND_ACCESS8(HW_FTFA_FCNFG_ADDR(x), BP_FTFA_FCNFG_CCIE) = (v))
462 /*******************************************************************************
463 * HW_FTFA_FSEC - Flash Security Register
464 ******************************************************************************/
467 * @brief HW_FTFA_FSEC - Flash Security Register (RO)
471 * This read-only register holds all bits associated with the security of the
472 * MCU and flash memory module. During the reset sequence, the register is loaded
473 * with the contents of the flash security byte in the Flash Configuration Field
474 * located in program flash memory. The flash basis for the values is signified by
475 * X in the reset value.
477 typedef union _hw_ftfa_fsec
480 struct _hw_ftfa_fsec_bitfields
482 uint8_t SEC
: 2; /*!< [1:0] Flash Security */
483 uint8_t FSLACC
: 2; /*!< [3:2] Freescale Failure Analysis Access Code
485 uint8_t MEEN
: 2; /*!< [5:4] Mass Erase Enable Bits */
486 uint8_t KEYEN
: 2; /*!< [7:6] Backdoor Key Security Enable */
491 * @name Constants and macros for entire FTFA_FSEC register
494 #define HW_FTFA_FSEC_ADDR(x) ((x) + 0x2U)
496 #define HW_FTFA_FSEC(x) (*(__I hw_ftfa_fsec_t *) HW_FTFA_FSEC_ADDR(x))
497 #define HW_FTFA_FSEC_RD(x) (HW_FTFA_FSEC(x).U)
501 * Constants & macros for individual FTFA_FSEC bitfields
505 * @name Register FTFA_FSEC, field SEC[1:0] (RO)
507 * Defines the security state of the MCU. In the secure state, the MCU limits
508 * access to flash memory module resources. The limitations are defined per device
509 * and are detailed in the Chip Configuration details. If the flash memory module
510 * is unsecured using backdoor key access, SEC is forced to 10b.
513 * - 00 - MCU security status is secure.
514 * - 01 - MCU security status is secure.
515 * - 10 - MCU security status is unsecure. (The standard shipping condition of
516 * the flash memory module is unsecure.)
517 * - 11 - MCU security status is secure.
520 #define BP_FTFA_FSEC_SEC (0U) /*!< Bit position for FTFA_FSEC_SEC. */
521 #define BM_FTFA_FSEC_SEC (0x03U) /*!< Bit mask for FTFA_FSEC_SEC. */
522 #define BS_FTFA_FSEC_SEC (2U) /*!< Bit field size in bits for FTFA_FSEC_SEC. */
524 /*! @brief Read current value of the FTFA_FSEC_SEC field. */
525 #define BR_FTFA_FSEC_SEC(x) (HW_FTFA_FSEC(x).B.SEC)
529 * @name Register FTFA_FSEC, field FSLACC[3:2] (RO)
531 * Enables or disables access to the flash memory contents during returned part
532 * failure analysis at Freescale. When SEC is secure and FSLACC is denied, access
533 * to the program flash contents is denied and any failure analysis performed by
534 * Freescale factory test must begin with a full erase to unsecure the part.
535 * When access is granted (SEC is unsecure, or SEC is secure and FSLACC is granted),
536 * Freescale factory testing has visibility of the current flash contents. The
537 * state of the FSLACC bits is only relevant when SEC is set to secure. When SEC
538 * is set to unsecure, the FSLACC setting does not matter.
541 * - 00 - Freescale factory access granted
542 * - 01 - Freescale factory access denied
543 * - 10 - Freescale factory access denied
544 * - 11 - Freescale factory access granted
547 #define BP_FTFA_FSEC_FSLACC (2U) /*!< Bit position for FTFA_FSEC_FSLACC. */
548 #define BM_FTFA_FSEC_FSLACC (0x0CU) /*!< Bit mask for FTFA_FSEC_FSLACC. */
549 #define BS_FTFA_FSEC_FSLACC (2U) /*!< Bit field size in bits for FTFA_FSEC_FSLACC. */
551 /*! @brief Read current value of the FTFA_FSEC_FSLACC field. */
552 #define BR_FTFA_FSEC_FSLACC(x) (HW_FTFA_FSEC(x).B.FSLACC)
556 * @name Register FTFA_FSEC, field MEEN[5:4] (RO)
558 * Enables and disables mass erase capability of the flash memory module. The
559 * state of this field is relevant only when SEC is set to secure outside of NVM
560 * Normal Mode. When SEC is set to unsecure, the MEEN setting does not matter.
563 * - 00 - Mass erase is enabled
564 * - 01 - Mass erase is enabled
565 * - 10 - Mass erase is disabled
566 * - 11 - Mass erase is enabled
569 #define BP_FTFA_FSEC_MEEN (4U) /*!< Bit position for FTFA_FSEC_MEEN. */
570 #define BM_FTFA_FSEC_MEEN (0x30U) /*!< Bit mask for FTFA_FSEC_MEEN. */
571 #define BS_FTFA_FSEC_MEEN (2U) /*!< Bit field size in bits for FTFA_FSEC_MEEN. */
573 /*! @brief Read current value of the FTFA_FSEC_MEEN field. */
574 #define BR_FTFA_FSEC_MEEN(x) (HW_FTFA_FSEC(x).B.MEEN)
578 * @name Register FTFA_FSEC, field KEYEN[7:6] (RO)
580 * Enables or disables backdoor key access to the flash memory module.
583 * - 00 - Backdoor key access disabled
584 * - 01 - Backdoor key access disabled (preferred KEYEN state to disable
585 * backdoor key access)
586 * - 10 - Backdoor key access enabled
587 * - 11 - Backdoor key access disabled
590 #define BP_FTFA_FSEC_KEYEN (6U) /*!< Bit position for FTFA_FSEC_KEYEN. */
591 #define BM_FTFA_FSEC_KEYEN (0xC0U) /*!< Bit mask for FTFA_FSEC_KEYEN. */
592 #define BS_FTFA_FSEC_KEYEN (2U) /*!< Bit field size in bits for FTFA_FSEC_KEYEN. */
594 /*! @brief Read current value of the FTFA_FSEC_KEYEN field. */
595 #define BR_FTFA_FSEC_KEYEN(x) (HW_FTFA_FSEC(x).B.KEYEN)
598 /*******************************************************************************
599 * HW_FTFA_FOPT - Flash Option Register
600 ******************************************************************************/
603 * @brief HW_FTFA_FOPT - Flash Option Register (RO)
607 * The flash option register allows the MCU to customize its operations by
608 * examining the state of these read-only bits, which are loaded from NVM at reset.
609 * The function of the bits is defined in the device's Chip Configuration details.
610 * All bits in the register are read-only . During the reset sequence, the
611 * register is loaded from the flash nonvolatile option byte in the Flash Configuration
612 * Field located in program flash memory. The flash basis for the values is
613 * signified by X in the reset value. However, the register is written to 0xFF if the
614 * contents of the flash nonvolatile option byte are 0x00.
616 typedef union _hw_ftfa_fopt
619 struct _hw_ftfa_fopt_bitfields
621 uint8_t OPT
: 8; /*!< [7:0] Nonvolatile Option */
626 * @name Constants and macros for entire FTFA_FOPT register
629 #define HW_FTFA_FOPT_ADDR(x) ((x) + 0x3U)
631 #define HW_FTFA_FOPT(x) (*(__I hw_ftfa_fopt_t *) HW_FTFA_FOPT_ADDR(x))
632 #define HW_FTFA_FOPT_RD(x) (HW_FTFA_FOPT(x).U)
636 * Constants & macros for individual FTFA_FOPT bitfields
640 * @name Register FTFA_FOPT, field OPT[7:0] (RO)
642 * These bits are loaded from flash to this register at reset. Refer to the
643 * device's Chip Configuration details for the definition and use of these bits.
646 #define BP_FTFA_FOPT_OPT (0U) /*!< Bit position for FTFA_FOPT_OPT. */
647 #define BM_FTFA_FOPT_OPT (0xFFU) /*!< Bit mask for FTFA_FOPT_OPT. */
648 #define BS_FTFA_FOPT_OPT (8U) /*!< Bit field size in bits for FTFA_FOPT_OPT. */
650 /*! @brief Read current value of the FTFA_FOPT_OPT field. */
651 #define BR_FTFA_FOPT_OPT(x) (HW_FTFA_FOPT(x).U)
654 /*******************************************************************************
655 * HW_FTFA_FCCOB3 - Flash Common Command Object Registers
656 ******************************************************************************/
659 * @brief HW_FTFA_FCCOB3 - Flash Common Command Object Registers (RW)
663 * The FCCOB register group provides 12 bytes for command codes and parameters.
664 * The individual bytes within the set append a 0-B hex identifier to the FCCOB
665 * register name: FCCOB0, FCCOB1, ..., FCCOBB.
667 typedef union _hw_ftfa_fccob3
670 struct _hw_ftfa_fccob3_bitfields
672 uint8_t CCOBn
: 8; /*!< [7:0] */
677 * @name Constants and macros for entire FTFA_FCCOB3 register
680 #define HW_FTFA_FCCOB3_ADDR(x) ((x) + 0x4U)
682 #define HW_FTFA_FCCOB3(x) (*(__IO hw_ftfa_fccob3_t *) HW_FTFA_FCCOB3_ADDR(x))
683 #define HW_FTFA_FCCOB3_RD(x) (HW_FTFA_FCCOB3(x).U)
684 #define HW_FTFA_FCCOB3_WR(x, v) (HW_FTFA_FCCOB3(x).U = (v))
685 #define HW_FTFA_FCCOB3_SET(x, v) (HW_FTFA_FCCOB3_WR(x, HW_FTFA_FCCOB3_RD(x) | (v)))
686 #define HW_FTFA_FCCOB3_CLR(x, v) (HW_FTFA_FCCOB3_WR(x, HW_FTFA_FCCOB3_RD(x) & ~(v)))
687 #define HW_FTFA_FCCOB3_TOG(x, v) (HW_FTFA_FCCOB3_WR(x, HW_FTFA_FCCOB3_RD(x) ^ (v)))
691 * Constants & macros for individual FTFA_FCCOB3 bitfields
695 * @name Register FTFA_FCCOB3, field CCOBn[7:0] (RW)
697 * The FCCOB register provides a command code and relevant parameters to the
698 * memory controller. The individual registers that compose the FCCOB data set can
699 * be written in any order, but you must provide all needed values, which vary
700 * from command to command. First, set up all required FCCOB fields and then
701 * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
702 * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
703 * by the user until the command completes (CCIF returns to 1). No command
704 * buffering or queueing is provided; the next command can be loaded only after the
705 * current command completes. Some commands return information to the FCCOB
706 * registers. Any values returned to FCCOB are available for reading after the
707 * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
708 * generic flash command format. The first FCCOB register, FCCOB0, always contains
709 * the command code. This 8-bit value defines the command to be executed. The
710 * command code is followed by the parameters required for this specific flash
711 * command, typically an address and/or data values. The command parameter table is
712 * written in terms of FCCOB Number (which is equivalent to the byte number). This
713 * number is a reference to the FCCOB register name and is not the register
714 * address. FCCOB Number Typical Command Parameter Contents [7:0] 0 FCMD (a code that
715 * defines the flash command) 1 Flash address [23:16] 2 Flash address [15:8] 3
716 * Flash address [7:0] 4 Data Byte 0 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8
717 * Data Byte 4 9 Data Byte 5 A Data Byte 6 B Data Byte 7 FCCOB Endianness : The
718 * FCCOB register group uses a big endian addressing convention. For all command
719 * parameter fields larger than 1 byte, the most significant data resides in the
720 * lowest FCCOB register number.
723 #define BP_FTFA_FCCOB3_CCOBn (0U) /*!< Bit position for FTFA_FCCOB3_CCOBn. */
724 #define BM_FTFA_FCCOB3_CCOBn (0xFFU) /*!< Bit mask for FTFA_FCCOB3_CCOBn. */
725 #define BS_FTFA_FCCOB3_CCOBn (8U) /*!< Bit field size in bits for FTFA_FCCOB3_CCOBn. */
727 /*! @brief Read current value of the FTFA_FCCOB3_CCOBn field. */
728 #define BR_FTFA_FCCOB3_CCOBn(x) (HW_FTFA_FCCOB3(x).U)
730 /*! @brief Format value for bitfield FTFA_FCCOB3_CCOBn. */
731 #define BF_FTFA_FCCOB3_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FCCOB3_CCOBn) & BM_FTFA_FCCOB3_CCOBn)
733 /*! @brief Set the CCOBn field to a new value. */
734 #define BW_FTFA_FCCOB3_CCOBn(x, v) (HW_FTFA_FCCOB3_WR(x, v))
737 /*******************************************************************************
738 * HW_FTFA_FCCOB2 - Flash Common Command Object Registers
739 ******************************************************************************/
742 * @brief HW_FTFA_FCCOB2 - Flash Common Command Object Registers (RW)
746 * The FCCOB register group provides 12 bytes for command codes and parameters.
747 * The individual bytes within the set append a 0-B hex identifier to the FCCOB
748 * register name: FCCOB0, FCCOB1, ..., FCCOBB.
750 typedef union _hw_ftfa_fccob2
753 struct _hw_ftfa_fccob2_bitfields
755 uint8_t CCOBn
: 8; /*!< [7:0] */
760 * @name Constants and macros for entire FTFA_FCCOB2 register
763 #define HW_FTFA_FCCOB2_ADDR(x) ((x) + 0x5U)
765 #define HW_FTFA_FCCOB2(x) (*(__IO hw_ftfa_fccob2_t *) HW_FTFA_FCCOB2_ADDR(x))
766 #define HW_FTFA_FCCOB2_RD(x) (HW_FTFA_FCCOB2(x).U)
767 #define HW_FTFA_FCCOB2_WR(x, v) (HW_FTFA_FCCOB2(x).U = (v))
768 #define HW_FTFA_FCCOB2_SET(x, v) (HW_FTFA_FCCOB2_WR(x, HW_FTFA_FCCOB2_RD(x) | (v)))
769 #define HW_FTFA_FCCOB2_CLR(x, v) (HW_FTFA_FCCOB2_WR(x, HW_FTFA_FCCOB2_RD(x) & ~(v)))
770 #define HW_FTFA_FCCOB2_TOG(x, v) (HW_FTFA_FCCOB2_WR(x, HW_FTFA_FCCOB2_RD(x) ^ (v)))
774 * Constants & macros for individual FTFA_FCCOB2 bitfields
778 * @name Register FTFA_FCCOB2, field CCOBn[7:0] (RW)
780 * The FCCOB register provides a command code and relevant parameters to the
781 * memory controller. The individual registers that compose the FCCOB data set can
782 * be written in any order, but you must provide all needed values, which vary
783 * from command to command. First, set up all required FCCOB fields and then
784 * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
785 * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
786 * by the user until the command completes (CCIF returns to 1). No command
787 * buffering or queueing is provided; the next command can be loaded only after the
788 * current command completes. Some commands return information to the FCCOB
789 * registers. Any values returned to FCCOB are available for reading after the
790 * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
791 * generic flash command format. The first FCCOB register, FCCOB0, always contains
792 * the command code. This 8-bit value defines the command to be executed. The
793 * command code is followed by the parameters required for this specific flash
794 * command, typically an address and/or data values. The command parameter table is
795 * written in terms of FCCOB Number (which is equivalent to the byte number). This
796 * number is a reference to the FCCOB register name and is not the register
797 * address. FCCOB Number Typical Command Parameter Contents [7:0] 0 FCMD (a code that
798 * defines the flash command) 1 Flash address [23:16] 2 Flash address [15:8] 3
799 * Flash address [7:0] 4 Data Byte 0 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8
800 * Data Byte 4 9 Data Byte 5 A Data Byte 6 B Data Byte 7 FCCOB Endianness : The
801 * FCCOB register group uses a big endian addressing convention. For all command
802 * parameter fields larger than 1 byte, the most significant data resides in the
803 * lowest FCCOB register number.
806 #define BP_FTFA_FCCOB2_CCOBn (0U) /*!< Bit position for FTFA_FCCOB2_CCOBn. */
807 #define BM_FTFA_FCCOB2_CCOBn (0xFFU) /*!< Bit mask for FTFA_FCCOB2_CCOBn. */
808 #define BS_FTFA_FCCOB2_CCOBn (8U) /*!< Bit field size in bits for FTFA_FCCOB2_CCOBn. */
810 /*! @brief Read current value of the FTFA_FCCOB2_CCOBn field. */
811 #define BR_FTFA_FCCOB2_CCOBn(x) (HW_FTFA_FCCOB2(x).U)
813 /*! @brief Format value for bitfield FTFA_FCCOB2_CCOBn. */
814 #define BF_FTFA_FCCOB2_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FCCOB2_CCOBn) & BM_FTFA_FCCOB2_CCOBn)
816 /*! @brief Set the CCOBn field to a new value. */
817 #define BW_FTFA_FCCOB2_CCOBn(x, v) (HW_FTFA_FCCOB2_WR(x, v))
820 /*******************************************************************************
821 * HW_FTFA_FCCOB1 - Flash Common Command Object Registers
822 ******************************************************************************/
825 * @brief HW_FTFA_FCCOB1 - Flash Common Command Object Registers (RW)
829 * The FCCOB register group provides 12 bytes for command codes and parameters.
830 * The individual bytes within the set append a 0-B hex identifier to the FCCOB
831 * register name: FCCOB0, FCCOB1, ..., FCCOBB.
833 typedef union _hw_ftfa_fccob1
836 struct _hw_ftfa_fccob1_bitfields
838 uint8_t CCOBn
: 8; /*!< [7:0] */
843 * @name Constants and macros for entire FTFA_FCCOB1 register
846 #define HW_FTFA_FCCOB1_ADDR(x) ((x) + 0x6U)
848 #define HW_FTFA_FCCOB1(x) (*(__IO hw_ftfa_fccob1_t *) HW_FTFA_FCCOB1_ADDR(x))
849 #define HW_FTFA_FCCOB1_RD(x) (HW_FTFA_FCCOB1(x).U)
850 #define HW_FTFA_FCCOB1_WR(x, v) (HW_FTFA_FCCOB1(x).U = (v))
851 #define HW_FTFA_FCCOB1_SET(x, v) (HW_FTFA_FCCOB1_WR(x, HW_FTFA_FCCOB1_RD(x) | (v)))
852 #define HW_FTFA_FCCOB1_CLR(x, v) (HW_FTFA_FCCOB1_WR(x, HW_FTFA_FCCOB1_RD(x) & ~(v)))
853 #define HW_FTFA_FCCOB1_TOG(x, v) (HW_FTFA_FCCOB1_WR(x, HW_FTFA_FCCOB1_RD(x) ^ (v)))
857 * Constants & macros for individual FTFA_FCCOB1 bitfields
861 * @name Register FTFA_FCCOB1, field CCOBn[7:0] (RW)
863 * The FCCOB register provides a command code and relevant parameters to the
864 * memory controller. The individual registers that compose the FCCOB data set can
865 * be written in any order, but you must provide all needed values, which vary
866 * from command to command. First, set up all required FCCOB fields and then
867 * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
868 * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
869 * by the user until the command completes (CCIF returns to 1). No command
870 * buffering or queueing is provided; the next command can be loaded only after the
871 * current command completes. Some commands return information to the FCCOB
872 * registers. Any values returned to FCCOB are available for reading after the
873 * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
874 * generic flash command format. The first FCCOB register, FCCOB0, always contains
875 * the command code. This 8-bit value defines the command to be executed. The
876 * command code is followed by the parameters required for this specific flash
877 * command, typically an address and/or data values. The command parameter table is
878 * written in terms of FCCOB Number (which is equivalent to the byte number). This
879 * number is a reference to the FCCOB register name and is not the register
880 * address. FCCOB Number Typical Command Parameter Contents [7:0] 0 FCMD (a code that
881 * defines the flash command) 1 Flash address [23:16] 2 Flash address [15:8] 3
882 * Flash address [7:0] 4 Data Byte 0 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8
883 * Data Byte 4 9 Data Byte 5 A Data Byte 6 B Data Byte 7 FCCOB Endianness : The
884 * FCCOB register group uses a big endian addressing convention. For all command
885 * parameter fields larger than 1 byte, the most significant data resides in the
886 * lowest FCCOB register number.
889 #define BP_FTFA_FCCOB1_CCOBn (0U) /*!< Bit position for FTFA_FCCOB1_CCOBn. */
890 #define BM_FTFA_FCCOB1_CCOBn (0xFFU) /*!< Bit mask for FTFA_FCCOB1_CCOBn. */
891 #define BS_FTFA_FCCOB1_CCOBn (8U) /*!< Bit field size in bits for FTFA_FCCOB1_CCOBn. */
893 /*! @brief Read current value of the FTFA_FCCOB1_CCOBn field. */
894 #define BR_FTFA_FCCOB1_CCOBn(x) (HW_FTFA_FCCOB1(x).U)
896 /*! @brief Format value for bitfield FTFA_FCCOB1_CCOBn. */
897 #define BF_FTFA_FCCOB1_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FCCOB1_CCOBn) & BM_FTFA_FCCOB1_CCOBn)
899 /*! @brief Set the CCOBn field to a new value. */
900 #define BW_FTFA_FCCOB1_CCOBn(x, v) (HW_FTFA_FCCOB1_WR(x, v))
903 /*******************************************************************************
904 * HW_FTFA_FCCOB0 - Flash Common Command Object Registers
905 ******************************************************************************/
908 * @brief HW_FTFA_FCCOB0 - Flash Common Command Object Registers (RW)
912 * The FCCOB register group provides 12 bytes for command codes and parameters.
913 * The individual bytes within the set append a 0-B hex identifier to the FCCOB
914 * register name: FCCOB0, FCCOB1, ..., FCCOBB.
916 typedef union _hw_ftfa_fccob0
919 struct _hw_ftfa_fccob0_bitfields
921 uint8_t CCOBn
: 8; /*!< [7:0] */
926 * @name Constants and macros for entire FTFA_FCCOB0 register
929 #define HW_FTFA_FCCOB0_ADDR(x) ((x) + 0x7U)
931 #define HW_FTFA_FCCOB0(x) (*(__IO hw_ftfa_fccob0_t *) HW_FTFA_FCCOB0_ADDR(x))
932 #define HW_FTFA_FCCOB0_RD(x) (HW_FTFA_FCCOB0(x).U)
933 #define HW_FTFA_FCCOB0_WR(x, v) (HW_FTFA_FCCOB0(x).U = (v))
934 #define HW_FTFA_FCCOB0_SET(x, v) (HW_FTFA_FCCOB0_WR(x, HW_FTFA_FCCOB0_RD(x) | (v)))
935 #define HW_FTFA_FCCOB0_CLR(x, v) (HW_FTFA_FCCOB0_WR(x, HW_FTFA_FCCOB0_RD(x) & ~(v)))
936 #define HW_FTFA_FCCOB0_TOG(x, v) (HW_FTFA_FCCOB0_WR(x, HW_FTFA_FCCOB0_RD(x) ^ (v)))
940 * Constants & macros for individual FTFA_FCCOB0 bitfields
944 * @name Register FTFA_FCCOB0, field CCOBn[7:0] (RW)
946 * The FCCOB register provides a command code and relevant parameters to the
947 * memory controller. The individual registers that compose the FCCOB data set can
948 * be written in any order, but you must provide all needed values, which vary
949 * from command to command. First, set up all required FCCOB fields and then
950 * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
951 * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
952 * by the user until the command completes (CCIF returns to 1). No command
953 * buffering or queueing is provided; the next command can be loaded only after the
954 * current command completes. Some commands return information to the FCCOB
955 * registers. Any values returned to FCCOB are available for reading after the
956 * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
957 * generic flash command format. The first FCCOB register, FCCOB0, always contains
958 * the command code. This 8-bit value defines the command to be executed. The
959 * command code is followed by the parameters required for this specific flash
960 * command, typically an address and/or data values. The command parameter table is
961 * written in terms of FCCOB Number (which is equivalent to the byte number). This
962 * number is a reference to the FCCOB register name and is not the register
963 * address. FCCOB Number Typical Command Parameter Contents [7:0] 0 FCMD (a code that
964 * defines the flash command) 1 Flash address [23:16] 2 Flash address [15:8] 3
965 * Flash address [7:0] 4 Data Byte 0 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8
966 * Data Byte 4 9 Data Byte 5 A Data Byte 6 B Data Byte 7 FCCOB Endianness : The
967 * FCCOB register group uses a big endian addressing convention. For all command
968 * parameter fields larger than 1 byte, the most significant data resides in the
969 * lowest FCCOB register number.
972 #define BP_FTFA_FCCOB0_CCOBn (0U) /*!< Bit position for FTFA_FCCOB0_CCOBn. */
973 #define BM_FTFA_FCCOB0_CCOBn (0xFFU) /*!< Bit mask for FTFA_FCCOB0_CCOBn. */
974 #define BS_FTFA_FCCOB0_CCOBn (8U) /*!< Bit field size in bits for FTFA_FCCOB0_CCOBn. */
976 /*! @brief Read current value of the FTFA_FCCOB0_CCOBn field. */
977 #define BR_FTFA_FCCOB0_CCOBn(x) (HW_FTFA_FCCOB0(x).U)
979 /*! @brief Format value for bitfield FTFA_FCCOB0_CCOBn. */
980 #define BF_FTFA_FCCOB0_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FCCOB0_CCOBn) & BM_FTFA_FCCOB0_CCOBn)
982 /*! @brief Set the CCOBn field to a new value. */
983 #define BW_FTFA_FCCOB0_CCOBn(x, v) (HW_FTFA_FCCOB0_WR(x, v))
986 /*******************************************************************************
987 * HW_FTFA_FCCOB7 - Flash Common Command Object Registers
988 ******************************************************************************/
991 * @brief HW_FTFA_FCCOB7 - Flash Common Command Object Registers (RW)
995 * The FCCOB register group provides 12 bytes for command codes and parameters.
996 * The individual bytes within the set append a 0-B hex identifier to the FCCOB
997 * register name: FCCOB0, FCCOB1, ..., FCCOBB.
999 typedef union _hw_ftfa_fccob7
1002 struct _hw_ftfa_fccob7_bitfields
1004 uint8_t CCOBn
: 8; /*!< [7:0] */
1009 * @name Constants and macros for entire FTFA_FCCOB7 register
1012 #define HW_FTFA_FCCOB7_ADDR(x) ((x) + 0x8U)
1014 #define HW_FTFA_FCCOB7(x) (*(__IO hw_ftfa_fccob7_t *) HW_FTFA_FCCOB7_ADDR(x))
1015 #define HW_FTFA_FCCOB7_RD(x) (HW_FTFA_FCCOB7(x).U)
1016 #define HW_FTFA_FCCOB7_WR(x, v) (HW_FTFA_FCCOB7(x).U = (v))
1017 #define HW_FTFA_FCCOB7_SET(x, v) (HW_FTFA_FCCOB7_WR(x, HW_FTFA_FCCOB7_RD(x) | (v)))
1018 #define HW_FTFA_FCCOB7_CLR(x, v) (HW_FTFA_FCCOB7_WR(x, HW_FTFA_FCCOB7_RD(x) & ~(v)))
1019 #define HW_FTFA_FCCOB7_TOG(x, v) (HW_FTFA_FCCOB7_WR(x, HW_FTFA_FCCOB7_RD(x) ^ (v)))
1023 * Constants & macros for individual FTFA_FCCOB7 bitfields
1027 * @name Register FTFA_FCCOB7, field CCOBn[7:0] (RW)
1029 * The FCCOB register provides a command code and relevant parameters to the
1030 * memory controller. The individual registers that compose the FCCOB data set can
1031 * be written in any order, but you must provide all needed values, which vary
1032 * from command to command. First, set up all required FCCOB fields and then
1033 * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
1034 * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
1035 * by the user until the command completes (CCIF returns to 1). No command
1036 * buffering or queueing is provided; the next command can be loaded only after the
1037 * current command completes. Some commands return information to the FCCOB
1038 * registers. Any values returned to FCCOB are available for reading after the
1039 * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
1040 * generic flash command format. The first FCCOB register, FCCOB0, always contains
1041 * the command code. This 8-bit value defines the command to be executed. The
1042 * command code is followed by the parameters required for this specific flash
1043 * command, typically an address and/or data values. The command parameter table is
1044 * written in terms of FCCOB Number (which is equivalent to the byte number). This
1045 * number is a reference to the FCCOB register name and is not the register
1046 * address. FCCOB Number Typical Command Parameter Contents [7:0] 0 FCMD (a code that
1047 * defines the flash command) 1 Flash address [23:16] 2 Flash address [15:8] 3
1048 * Flash address [7:0] 4 Data Byte 0 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8
1049 * Data Byte 4 9 Data Byte 5 A Data Byte 6 B Data Byte 7 FCCOB Endianness : The
1050 * FCCOB register group uses a big endian addressing convention. For all command
1051 * parameter fields larger than 1 byte, the most significant data resides in the
1052 * lowest FCCOB register number.
1055 #define BP_FTFA_FCCOB7_CCOBn (0U) /*!< Bit position for FTFA_FCCOB7_CCOBn. */
1056 #define BM_FTFA_FCCOB7_CCOBn (0xFFU) /*!< Bit mask for FTFA_FCCOB7_CCOBn. */
1057 #define BS_FTFA_FCCOB7_CCOBn (8U) /*!< Bit field size in bits for FTFA_FCCOB7_CCOBn. */
1059 /*! @brief Read current value of the FTFA_FCCOB7_CCOBn field. */
1060 #define BR_FTFA_FCCOB7_CCOBn(x) (HW_FTFA_FCCOB7(x).U)
1062 /*! @brief Format value for bitfield FTFA_FCCOB7_CCOBn. */
1063 #define BF_FTFA_FCCOB7_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FCCOB7_CCOBn) & BM_FTFA_FCCOB7_CCOBn)
1065 /*! @brief Set the CCOBn field to a new value. */
1066 #define BW_FTFA_FCCOB7_CCOBn(x, v) (HW_FTFA_FCCOB7_WR(x, v))
1069 /*******************************************************************************
1070 * HW_FTFA_FCCOB6 - Flash Common Command Object Registers
1071 ******************************************************************************/
1074 * @brief HW_FTFA_FCCOB6 - Flash Common Command Object Registers (RW)
1076 * Reset value: 0x00U
1078 * The FCCOB register group provides 12 bytes for command codes and parameters.
1079 * The individual bytes within the set append a 0-B hex identifier to the FCCOB
1080 * register name: FCCOB0, FCCOB1, ..., FCCOBB.
1082 typedef union _hw_ftfa_fccob6
1085 struct _hw_ftfa_fccob6_bitfields
1087 uint8_t CCOBn
: 8; /*!< [7:0] */
1092 * @name Constants and macros for entire FTFA_FCCOB6 register
1095 #define HW_FTFA_FCCOB6_ADDR(x) ((x) + 0x9U)
1097 #define HW_FTFA_FCCOB6(x) (*(__IO hw_ftfa_fccob6_t *) HW_FTFA_FCCOB6_ADDR(x))
1098 #define HW_FTFA_FCCOB6_RD(x) (HW_FTFA_FCCOB6(x).U)
1099 #define HW_FTFA_FCCOB6_WR(x, v) (HW_FTFA_FCCOB6(x).U = (v))
1100 #define HW_FTFA_FCCOB6_SET(x, v) (HW_FTFA_FCCOB6_WR(x, HW_FTFA_FCCOB6_RD(x) | (v)))
1101 #define HW_FTFA_FCCOB6_CLR(x, v) (HW_FTFA_FCCOB6_WR(x, HW_FTFA_FCCOB6_RD(x) & ~(v)))
1102 #define HW_FTFA_FCCOB6_TOG(x, v) (HW_FTFA_FCCOB6_WR(x, HW_FTFA_FCCOB6_RD(x) ^ (v)))
1106 * Constants & macros for individual FTFA_FCCOB6 bitfields
1110 * @name Register FTFA_FCCOB6, field CCOBn[7:0] (RW)
1112 * The FCCOB register provides a command code and relevant parameters to the
1113 * memory controller. The individual registers that compose the FCCOB data set can
1114 * be written in any order, but you must provide all needed values, which vary
1115 * from command to command. First, set up all required FCCOB fields and then
1116 * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
1117 * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
1118 * by the user until the command completes (CCIF returns to 1). No command
1119 * buffering or queueing is provided; the next command can be loaded only after the
1120 * current command completes. Some commands return information to the FCCOB
1121 * registers. Any values returned to FCCOB are available for reading after the
1122 * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
1123 * generic flash command format. The first FCCOB register, FCCOB0, always contains
1124 * the command code. This 8-bit value defines the command to be executed. The
1125 * command code is followed by the parameters required for this specific flash
1126 * command, typically an address and/or data values. The command parameter table is
1127 * written in terms of FCCOB Number (which is equivalent to the byte number). This
1128 * number is a reference to the FCCOB register name and is not the register
1129 * address. FCCOB Number Typical Command Parameter Contents [7:0] 0 FCMD (a code that
1130 * defines the flash command) 1 Flash address [23:16] 2 Flash address [15:8] 3
1131 * Flash address [7:0] 4 Data Byte 0 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8
1132 * Data Byte 4 9 Data Byte 5 A Data Byte 6 B Data Byte 7 FCCOB Endianness : The
1133 * FCCOB register group uses a big endian addressing convention. For all command
1134 * parameter fields larger than 1 byte, the most significant data resides in the
1135 * lowest FCCOB register number.
1138 #define BP_FTFA_FCCOB6_CCOBn (0U) /*!< Bit position for FTFA_FCCOB6_CCOBn. */
1139 #define BM_FTFA_FCCOB6_CCOBn (0xFFU) /*!< Bit mask for FTFA_FCCOB6_CCOBn. */
1140 #define BS_FTFA_FCCOB6_CCOBn (8U) /*!< Bit field size in bits for FTFA_FCCOB6_CCOBn. */
1142 /*! @brief Read current value of the FTFA_FCCOB6_CCOBn field. */
1143 #define BR_FTFA_FCCOB6_CCOBn(x) (HW_FTFA_FCCOB6(x).U)
1145 /*! @brief Format value for bitfield FTFA_FCCOB6_CCOBn. */
1146 #define BF_FTFA_FCCOB6_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FCCOB6_CCOBn) & BM_FTFA_FCCOB6_CCOBn)
1148 /*! @brief Set the CCOBn field to a new value. */
1149 #define BW_FTFA_FCCOB6_CCOBn(x, v) (HW_FTFA_FCCOB6_WR(x, v))
1152 /*******************************************************************************
1153 * HW_FTFA_FCCOB5 - Flash Common Command Object Registers
1154 ******************************************************************************/
1157 * @brief HW_FTFA_FCCOB5 - Flash Common Command Object Registers (RW)
1159 * Reset value: 0x00U
1161 * The FCCOB register group provides 12 bytes for command codes and parameters.
1162 * The individual bytes within the set append a 0-B hex identifier to the FCCOB
1163 * register name: FCCOB0, FCCOB1, ..., FCCOBB.
1165 typedef union _hw_ftfa_fccob5
1168 struct _hw_ftfa_fccob5_bitfields
1170 uint8_t CCOBn
: 8; /*!< [7:0] */
1175 * @name Constants and macros for entire FTFA_FCCOB5 register
1178 #define HW_FTFA_FCCOB5_ADDR(x) ((x) + 0xAU)
1180 #define HW_FTFA_FCCOB5(x) (*(__IO hw_ftfa_fccob5_t *) HW_FTFA_FCCOB5_ADDR(x))
1181 #define HW_FTFA_FCCOB5_RD(x) (HW_FTFA_FCCOB5(x).U)
1182 #define HW_FTFA_FCCOB5_WR(x, v) (HW_FTFA_FCCOB5(x).U = (v))
1183 #define HW_FTFA_FCCOB5_SET(x, v) (HW_FTFA_FCCOB5_WR(x, HW_FTFA_FCCOB5_RD(x) | (v)))
1184 #define HW_FTFA_FCCOB5_CLR(x, v) (HW_FTFA_FCCOB5_WR(x, HW_FTFA_FCCOB5_RD(x) & ~(v)))
1185 #define HW_FTFA_FCCOB5_TOG(x, v) (HW_FTFA_FCCOB5_WR(x, HW_FTFA_FCCOB5_RD(x) ^ (v)))
1189 * Constants & macros for individual FTFA_FCCOB5 bitfields
1193 * @name Register FTFA_FCCOB5, field CCOBn[7:0] (RW)
1195 * The FCCOB register provides a command code and relevant parameters to the
1196 * memory controller. The individual registers that compose the FCCOB data set can
1197 * be written in any order, but you must provide all needed values, which vary
1198 * from command to command. First, set up all required FCCOB fields and then
1199 * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
1200 * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
1201 * by the user until the command completes (CCIF returns to 1). No command
1202 * buffering or queueing is provided; the next command can be loaded only after the
1203 * current command completes. Some commands return information to the FCCOB
1204 * registers. Any values returned to FCCOB are available for reading after the
1205 * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
1206 * generic flash command format. The first FCCOB register, FCCOB0, always contains
1207 * the command code. This 8-bit value defines the command to be executed. The
1208 * command code is followed by the parameters required for this specific flash
1209 * command, typically an address and/or data values. The command parameter table is
1210 * written in terms of FCCOB Number (which is equivalent to the byte number). This
1211 * number is a reference to the FCCOB register name and is not the register
1212 * address. FCCOB Number Typical Command Parameter Contents [7:0] 0 FCMD (a code that
1213 * defines the flash command) 1 Flash address [23:16] 2 Flash address [15:8] 3
1214 * Flash address [7:0] 4 Data Byte 0 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8
1215 * Data Byte 4 9 Data Byte 5 A Data Byte 6 B Data Byte 7 FCCOB Endianness : The
1216 * FCCOB register group uses a big endian addressing convention. For all command
1217 * parameter fields larger than 1 byte, the most significant data resides in the
1218 * lowest FCCOB register number.
1221 #define BP_FTFA_FCCOB5_CCOBn (0U) /*!< Bit position for FTFA_FCCOB5_CCOBn. */
1222 #define BM_FTFA_FCCOB5_CCOBn (0xFFU) /*!< Bit mask for FTFA_FCCOB5_CCOBn. */
1223 #define BS_FTFA_FCCOB5_CCOBn (8U) /*!< Bit field size in bits for FTFA_FCCOB5_CCOBn. */
1225 /*! @brief Read current value of the FTFA_FCCOB5_CCOBn field. */
1226 #define BR_FTFA_FCCOB5_CCOBn(x) (HW_FTFA_FCCOB5(x).U)
1228 /*! @brief Format value for bitfield FTFA_FCCOB5_CCOBn. */
1229 #define BF_FTFA_FCCOB5_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FCCOB5_CCOBn) & BM_FTFA_FCCOB5_CCOBn)
1231 /*! @brief Set the CCOBn field to a new value. */
1232 #define BW_FTFA_FCCOB5_CCOBn(x, v) (HW_FTFA_FCCOB5_WR(x, v))
1235 /*******************************************************************************
1236 * HW_FTFA_FCCOB4 - Flash Common Command Object Registers
1237 ******************************************************************************/
1240 * @brief HW_FTFA_FCCOB4 - Flash Common Command Object Registers (RW)
1242 * Reset value: 0x00U
1244 * The FCCOB register group provides 12 bytes for command codes and parameters.
1245 * The individual bytes within the set append a 0-B hex identifier to the FCCOB
1246 * register name: FCCOB0, FCCOB1, ..., FCCOBB.
1248 typedef union _hw_ftfa_fccob4
1251 struct _hw_ftfa_fccob4_bitfields
1253 uint8_t CCOBn
: 8; /*!< [7:0] */
1258 * @name Constants and macros for entire FTFA_FCCOB4 register
1261 #define HW_FTFA_FCCOB4_ADDR(x) ((x) + 0xBU)
1263 #define HW_FTFA_FCCOB4(x) (*(__IO hw_ftfa_fccob4_t *) HW_FTFA_FCCOB4_ADDR(x))
1264 #define HW_FTFA_FCCOB4_RD(x) (HW_FTFA_FCCOB4(x).U)
1265 #define HW_FTFA_FCCOB4_WR(x, v) (HW_FTFA_FCCOB4(x).U = (v))
1266 #define HW_FTFA_FCCOB4_SET(x, v) (HW_FTFA_FCCOB4_WR(x, HW_FTFA_FCCOB4_RD(x) | (v)))
1267 #define HW_FTFA_FCCOB4_CLR(x, v) (HW_FTFA_FCCOB4_WR(x, HW_FTFA_FCCOB4_RD(x) & ~(v)))
1268 #define HW_FTFA_FCCOB4_TOG(x, v) (HW_FTFA_FCCOB4_WR(x, HW_FTFA_FCCOB4_RD(x) ^ (v)))
1272 * Constants & macros for individual FTFA_FCCOB4 bitfields
1276 * @name Register FTFA_FCCOB4, field CCOBn[7:0] (RW)
1278 * The FCCOB register provides a command code and relevant parameters to the
1279 * memory controller. The individual registers that compose the FCCOB data set can
1280 * be written in any order, but you must provide all needed values, which vary
1281 * from command to command. First, set up all required FCCOB fields and then
1282 * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
1283 * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
1284 * by the user until the command completes (CCIF returns to 1). No command
1285 * buffering or queueing is provided; the next command can be loaded only after the
1286 * current command completes. Some commands return information to the FCCOB
1287 * registers. Any values returned to FCCOB are available for reading after the
1288 * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
1289 * generic flash command format. The first FCCOB register, FCCOB0, always contains
1290 * the command code. This 8-bit value defines the command to be executed. The
1291 * command code is followed by the parameters required for this specific flash
1292 * command, typically an address and/or data values. The command parameter table is
1293 * written in terms of FCCOB Number (which is equivalent to the byte number). This
1294 * number is a reference to the FCCOB register name and is not the register
1295 * address. FCCOB Number Typical Command Parameter Contents [7:0] 0 FCMD (a code that
1296 * defines the flash command) 1 Flash address [23:16] 2 Flash address [15:8] 3
1297 * Flash address [7:0] 4 Data Byte 0 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8
1298 * Data Byte 4 9 Data Byte 5 A Data Byte 6 B Data Byte 7 FCCOB Endianness : The
1299 * FCCOB register group uses a big endian addressing convention. For all command
1300 * parameter fields larger than 1 byte, the most significant data resides in the
1301 * lowest FCCOB register number.
1304 #define BP_FTFA_FCCOB4_CCOBn (0U) /*!< Bit position for FTFA_FCCOB4_CCOBn. */
1305 #define BM_FTFA_FCCOB4_CCOBn (0xFFU) /*!< Bit mask for FTFA_FCCOB4_CCOBn. */
1306 #define BS_FTFA_FCCOB4_CCOBn (8U) /*!< Bit field size in bits for FTFA_FCCOB4_CCOBn. */
1308 /*! @brief Read current value of the FTFA_FCCOB4_CCOBn field. */
1309 #define BR_FTFA_FCCOB4_CCOBn(x) (HW_FTFA_FCCOB4(x).U)
1311 /*! @brief Format value for bitfield FTFA_FCCOB4_CCOBn. */
1312 #define BF_FTFA_FCCOB4_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FCCOB4_CCOBn) & BM_FTFA_FCCOB4_CCOBn)
1314 /*! @brief Set the CCOBn field to a new value. */
1315 #define BW_FTFA_FCCOB4_CCOBn(x, v) (HW_FTFA_FCCOB4_WR(x, v))
1318 /*******************************************************************************
1319 * HW_FTFA_FCCOBB - Flash Common Command Object Registers
1320 ******************************************************************************/
1323 * @brief HW_FTFA_FCCOBB - Flash Common Command Object Registers (RW)
1325 * Reset value: 0x00U
1327 * The FCCOB register group provides 12 bytes for command codes and parameters.
1328 * The individual bytes within the set append a 0-B hex identifier to the FCCOB
1329 * register name: FCCOB0, FCCOB1, ..., FCCOBB.
1331 typedef union _hw_ftfa_fccobb
1334 struct _hw_ftfa_fccobb_bitfields
1336 uint8_t CCOBn
: 8; /*!< [7:0] */
1341 * @name Constants and macros for entire FTFA_FCCOBB register
1344 #define HW_FTFA_FCCOBB_ADDR(x) ((x) + 0xCU)
1346 #define HW_FTFA_FCCOBB(x) (*(__IO hw_ftfa_fccobb_t *) HW_FTFA_FCCOBB_ADDR(x))
1347 #define HW_FTFA_FCCOBB_RD(x) (HW_FTFA_FCCOBB(x).U)
1348 #define HW_FTFA_FCCOBB_WR(x, v) (HW_FTFA_FCCOBB(x).U = (v))
1349 #define HW_FTFA_FCCOBB_SET(x, v) (HW_FTFA_FCCOBB_WR(x, HW_FTFA_FCCOBB_RD(x) | (v)))
1350 #define HW_FTFA_FCCOBB_CLR(x, v) (HW_FTFA_FCCOBB_WR(x, HW_FTFA_FCCOBB_RD(x) & ~(v)))
1351 #define HW_FTFA_FCCOBB_TOG(x, v) (HW_FTFA_FCCOBB_WR(x, HW_FTFA_FCCOBB_RD(x) ^ (v)))
1355 * Constants & macros for individual FTFA_FCCOBB bitfields
1359 * @name Register FTFA_FCCOBB, field CCOBn[7:0] (RW)
1361 * The FCCOB register provides a command code and relevant parameters to the
1362 * memory controller. The individual registers that compose the FCCOB data set can
1363 * be written in any order, but you must provide all needed values, which vary
1364 * from command to command. First, set up all required FCCOB fields and then
1365 * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
1366 * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
1367 * by the user until the command completes (CCIF returns to 1). No command
1368 * buffering or queueing is provided; the next command can be loaded only after the
1369 * current command completes. Some commands return information to the FCCOB
1370 * registers. Any values returned to FCCOB are available for reading after the
1371 * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
1372 * generic flash command format. The first FCCOB register, FCCOB0, always contains
1373 * the command code. This 8-bit value defines the command to be executed. The
1374 * command code is followed by the parameters required for this specific flash
1375 * command, typically an address and/or data values. The command parameter table is
1376 * written in terms of FCCOB Number (which is equivalent to the byte number). This
1377 * number is a reference to the FCCOB register name and is not the register
1378 * address. FCCOB Number Typical Command Parameter Contents [7:0] 0 FCMD (a code that
1379 * defines the flash command) 1 Flash address [23:16] 2 Flash address [15:8] 3
1380 * Flash address [7:0] 4 Data Byte 0 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8
1381 * Data Byte 4 9 Data Byte 5 A Data Byte 6 B Data Byte 7 FCCOB Endianness : The
1382 * FCCOB register group uses a big endian addressing convention. For all command
1383 * parameter fields larger than 1 byte, the most significant data resides in the
1384 * lowest FCCOB register number.
1387 #define BP_FTFA_FCCOBB_CCOBn (0U) /*!< Bit position for FTFA_FCCOBB_CCOBn. */
1388 #define BM_FTFA_FCCOBB_CCOBn (0xFFU) /*!< Bit mask for FTFA_FCCOBB_CCOBn. */
1389 #define BS_FTFA_FCCOBB_CCOBn (8U) /*!< Bit field size in bits for FTFA_FCCOBB_CCOBn. */
1391 /*! @brief Read current value of the FTFA_FCCOBB_CCOBn field. */
1392 #define BR_FTFA_FCCOBB_CCOBn(x) (HW_FTFA_FCCOBB(x).U)
1394 /*! @brief Format value for bitfield FTFA_FCCOBB_CCOBn. */
1395 #define BF_FTFA_FCCOBB_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FCCOBB_CCOBn) & BM_FTFA_FCCOBB_CCOBn)
1397 /*! @brief Set the CCOBn field to a new value. */
1398 #define BW_FTFA_FCCOBB_CCOBn(x, v) (HW_FTFA_FCCOBB_WR(x, v))
1401 /*******************************************************************************
1402 * HW_FTFA_FCCOBA - Flash Common Command Object Registers
1403 ******************************************************************************/
1406 * @brief HW_FTFA_FCCOBA - Flash Common Command Object Registers (RW)
1408 * Reset value: 0x00U
1410 * The FCCOB register group provides 12 bytes for command codes and parameters.
1411 * The individual bytes within the set append a 0-B hex identifier to the FCCOB
1412 * register name: FCCOB0, FCCOB1, ..., FCCOBB.
1414 typedef union _hw_ftfa_fccoba
1417 struct _hw_ftfa_fccoba_bitfields
1419 uint8_t CCOBn
: 8; /*!< [7:0] */
1424 * @name Constants and macros for entire FTFA_FCCOBA register
1427 #define HW_FTFA_FCCOBA_ADDR(x) ((x) + 0xDU)
1429 #define HW_FTFA_FCCOBA(x) (*(__IO hw_ftfa_fccoba_t *) HW_FTFA_FCCOBA_ADDR(x))
1430 #define HW_FTFA_FCCOBA_RD(x) (HW_FTFA_FCCOBA(x).U)
1431 #define HW_FTFA_FCCOBA_WR(x, v) (HW_FTFA_FCCOBA(x).U = (v))
1432 #define HW_FTFA_FCCOBA_SET(x, v) (HW_FTFA_FCCOBA_WR(x, HW_FTFA_FCCOBA_RD(x) | (v)))
1433 #define HW_FTFA_FCCOBA_CLR(x, v) (HW_FTFA_FCCOBA_WR(x, HW_FTFA_FCCOBA_RD(x) & ~(v)))
1434 #define HW_FTFA_FCCOBA_TOG(x, v) (HW_FTFA_FCCOBA_WR(x, HW_FTFA_FCCOBA_RD(x) ^ (v)))
1438 * Constants & macros for individual FTFA_FCCOBA bitfields
1442 * @name Register FTFA_FCCOBA, field CCOBn[7:0] (RW)
1444 * The FCCOB register provides a command code and relevant parameters to the
1445 * memory controller. The individual registers that compose the FCCOB data set can
1446 * be written in any order, but you must provide all needed values, which vary
1447 * from command to command. First, set up all required FCCOB fields and then
1448 * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
1449 * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
1450 * by the user until the command completes (CCIF returns to 1). No command
1451 * buffering or queueing is provided; the next command can be loaded only after the
1452 * current command completes. Some commands return information to the FCCOB
1453 * registers. Any values returned to FCCOB are available for reading after the
1454 * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
1455 * generic flash command format. The first FCCOB register, FCCOB0, always contains
1456 * the command code. This 8-bit value defines the command to be executed. The
1457 * command code is followed by the parameters required for this specific flash
1458 * command, typically an address and/or data values. The command parameter table is
1459 * written in terms of FCCOB Number (which is equivalent to the byte number). This
1460 * number is a reference to the FCCOB register name and is not the register
1461 * address. FCCOB Number Typical Command Parameter Contents [7:0] 0 FCMD (a code that
1462 * defines the flash command) 1 Flash address [23:16] 2 Flash address [15:8] 3
1463 * Flash address [7:0] 4 Data Byte 0 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8
1464 * Data Byte 4 9 Data Byte 5 A Data Byte 6 B Data Byte 7 FCCOB Endianness : The
1465 * FCCOB register group uses a big endian addressing convention. For all command
1466 * parameter fields larger than 1 byte, the most significant data resides in the
1467 * lowest FCCOB register number.
1470 #define BP_FTFA_FCCOBA_CCOBn (0U) /*!< Bit position for FTFA_FCCOBA_CCOBn. */
1471 #define BM_FTFA_FCCOBA_CCOBn (0xFFU) /*!< Bit mask for FTFA_FCCOBA_CCOBn. */
1472 #define BS_FTFA_FCCOBA_CCOBn (8U) /*!< Bit field size in bits for FTFA_FCCOBA_CCOBn. */
1474 /*! @brief Read current value of the FTFA_FCCOBA_CCOBn field. */
1475 #define BR_FTFA_FCCOBA_CCOBn(x) (HW_FTFA_FCCOBA(x).U)
1477 /*! @brief Format value for bitfield FTFA_FCCOBA_CCOBn. */
1478 #define BF_FTFA_FCCOBA_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FCCOBA_CCOBn) & BM_FTFA_FCCOBA_CCOBn)
1480 /*! @brief Set the CCOBn field to a new value. */
1481 #define BW_FTFA_FCCOBA_CCOBn(x, v) (HW_FTFA_FCCOBA_WR(x, v))
1484 /*******************************************************************************
1485 * HW_FTFA_FCCOB9 - Flash Common Command Object Registers
1486 ******************************************************************************/
1489 * @brief HW_FTFA_FCCOB9 - Flash Common Command Object Registers (RW)
1491 * Reset value: 0x00U
1493 * The FCCOB register group provides 12 bytes for command codes and parameters.
1494 * The individual bytes within the set append a 0-B hex identifier to the FCCOB
1495 * register name: FCCOB0, FCCOB1, ..., FCCOBB.
1497 typedef union _hw_ftfa_fccob9
1500 struct _hw_ftfa_fccob9_bitfields
1502 uint8_t CCOBn
: 8; /*!< [7:0] */
1507 * @name Constants and macros for entire FTFA_FCCOB9 register
1510 #define HW_FTFA_FCCOB9_ADDR(x) ((x) + 0xEU)
1512 #define HW_FTFA_FCCOB9(x) (*(__IO hw_ftfa_fccob9_t *) HW_FTFA_FCCOB9_ADDR(x))
1513 #define HW_FTFA_FCCOB9_RD(x) (HW_FTFA_FCCOB9(x).U)
1514 #define HW_FTFA_FCCOB9_WR(x, v) (HW_FTFA_FCCOB9(x).U = (v))
1515 #define HW_FTFA_FCCOB9_SET(x, v) (HW_FTFA_FCCOB9_WR(x, HW_FTFA_FCCOB9_RD(x) | (v)))
1516 #define HW_FTFA_FCCOB9_CLR(x, v) (HW_FTFA_FCCOB9_WR(x, HW_FTFA_FCCOB9_RD(x) & ~(v)))
1517 #define HW_FTFA_FCCOB9_TOG(x, v) (HW_FTFA_FCCOB9_WR(x, HW_FTFA_FCCOB9_RD(x) ^ (v)))
1521 * Constants & macros for individual FTFA_FCCOB9 bitfields
1525 * @name Register FTFA_FCCOB9, field CCOBn[7:0] (RW)
1527 * The FCCOB register provides a command code and relevant parameters to the
1528 * memory controller. The individual registers that compose the FCCOB data set can
1529 * be written in any order, but you must provide all needed values, which vary
1530 * from command to command. First, set up all required FCCOB fields and then
1531 * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
1532 * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
1533 * by the user until the command completes (CCIF returns to 1). No command
1534 * buffering or queueing is provided; the next command can be loaded only after the
1535 * current command completes. Some commands return information to the FCCOB
1536 * registers. Any values returned to FCCOB are available for reading after the
1537 * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
1538 * generic flash command format. The first FCCOB register, FCCOB0, always contains
1539 * the command code. This 8-bit value defines the command to be executed. The
1540 * command code is followed by the parameters required for this specific flash
1541 * command, typically an address and/or data values. The command parameter table is
1542 * written in terms of FCCOB Number (which is equivalent to the byte number). This
1543 * number is a reference to the FCCOB register name and is not the register
1544 * address. FCCOB Number Typical Command Parameter Contents [7:0] 0 FCMD (a code that
1545 * defines the flash command) 1 Flash address [23:16] 2 Flash address [15:8] 3
1546 * Flash address [7:0] 4 Data Byte 0 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8
1547 * Data Byte 4 9 Data Byte 5 A Data Byte 6 B Data Byte 7 FCCOB Endianness : The
1548 * FCCOB register group uses a big endian addressing convention. For all command
1549 * parameter fields larger than 1 byte, the most significant data resides in the
1550 * lowest FCCOB register number.
1553 #define BP_FTFA_FCCOB9_CCOBn (0U) /*!< Bit position for FTFA_FCCOB9_CCOBn. */
1554 #define BM_FTFA_FCCOB9_CCOBn (0xFFU) /*!< Bit mask for FTFA_FCCOB9_CCOBn. */
1555 #define BS_FTFA_FCCOB9_CCOBn (8U) /*!< Bit field size in bits for FTFA_FCCOB9_CCOBn. */
1557 /*! @brief Read current value of the FTFA_FCCOB9_CCOBn field. */
1558 #define BR_FTFA_FCCOB9_CCOBn(x) (HW_FTFA_FCCOB9(x).U)
1560 /*! @brief Format value for bitfield FTFA_FCCOB9_CCOBn. */
1561 #define BF_FTFA_FCCOB9_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FCCOB9_CCOBn) & BM_FTFA_FCCOB9_CCOBn)
1563 /*! @brief Set the CCOBn field to a new value. */
1564 #define BW_FTFA_FCCOB9_CCOBn(x, v) (HW_FTFA_FCCOB9_WR(x, v))
1567 /*******************************************************************************
1568 * HW_FTFA_FCCOB8 - Flash Common Command Object Registers
1569 ******************************************************************************/
1572 * @brief HW_FTFA_FCCOB8 - Flash Common Command Object Registers (RW)
1574 * Reset value: 0x00U
1576 * The FCCOB register group provides 12 bytes for command codes and parameters.
1577 * The individual bytes within the set append a 0-B hex identifier to the FCCOB
1578 * register name: FCCOB0, FCCOB1, ..., FCCOBB.
1580 typedef union _hw_ftfa_fccob8
1583 struct _hw_ftfa_fccob8_bitfields
1585 uint8_t CCOBn
: 8; /*!< [7:0] */
1590 * @name Constants and macros for entire FTFA_FCCOB8 register
1593 #define HW_FTFA_FCCOB8_ADDR(x) ((x) + 0xFU)
1595 #define HW_FTFA_FCCOB8(x) (*(__IO hw_ftfa_fccob8_t *) HW_FTFA_FCCOB8_ADDR(x))
1596 #define HW_FTFA_FCCOB8_RD(x) (HW_FTFA_FCCOB8(x).U)
1597 #define HW_FTFA_FCCOB8_WR(x, v) (HW_FTFA_FCCOB8(x).U = (v))
1598 #define HW_FTFA_FCCOB8_SET(x, v) (HW_FTFA_FCCOB8_WR(x, HW_FTFA_FCCOB8_RD(x) | (v)))
1599 #define HW_FTFA_FCCOB8_CLR(x, v) (HW_FTFA_FCCOB8_WR(x, HW_FTFA_FCCOB8_RD(x) & ~(v)))
1600 #define HW_FTFA_FCCOB8_TOG(x, v) (HW_FTFA_FCCOB8_WR(x, HW_FTFA_FCCOB8_RD(x) ^ (v)))
1604 * Constants & macros for individual FTFA_FCCOB8 bitfields
1608 * @name Register FTFA_FCCOB8, field CCOBn[7:0] (RW)
1610 * The FCCOB register provides a command code and relevant parameters to the
1611 * memory controller. The individual registers that compose the FCCOB data set can
1612 * be written in any order, but you must provide all needed values, which vary
1613 * from command to command. First, set up all required FCCOB fields and then
1614 * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
1615 * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
1616 * by the user until the command completes (CCIF returns to 1). No command
1617 * buffering or queueing is provided; the next command can be loaded only after the
1618 * current command completes. Some commands return information to the FCCOB
1619 * registers. Any values returned to FCCOB are available for reading after the
1620 * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
1621 * generic flash command format. The first FCCOB register, FCCOB0, always contains
1622 * the command code. This 8-bit value defines the command to be executed. The
1623 * command code is followed by the parameters required for this specific flash
1624 * command, typically an address and/or data values. The command parameter table is
1625 * written in terms of FCCOB Number (which is equivalent to the byte number). This
1626 * number is a reference to the FCCOB register name and is not the register
1627 * address. FCCOB Number Typical Command Parameter Contents [7:0] 0 FCMD (a code that
1628 * defines the flash command) 1 Flash address [23:16] 2 Flash address [15:8] 3
1629 * Flash address [7:0] 4 Data Byte 0 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8
1630 * Data Byte 4 9 Data Byte 5 A Data Byte 6 B Data Byte 7 FCCOB Endianness : The
1631 * FCCOB register group uses a big endian addressing convention. For all command
1632 * parameter fields larger than 1 byte, the most significant data resides in the
1633 * lowest FCCOB register number.
1636 #define BP_FTFA_FCCOB8_CCOBn (0U) /*!< Bit position for FTFA_FCCOB8_CCOBn. */
1637 #define BM_FTFA_FCCOB8_CCOBn (0xFFU) /*!< Bit mask for FTFA_FCCOB8_CCOBn. */
1638 #define BS_FTFA_FCCOB8_CCOBn (8U) /*!< Bit field size in bits for FTFA_FCCOB8_CCOBn. */
1640 /*! @brief Read current value of the FTFA_FCCOB8_CCOBn field. */
1641 #define BR_FTFA_FCCOB8_CCOBn(x) (HW_FTFA_FCCOB8(x).U)
1643 /*! @brief Format value for bitfield FTFA_FCCOB8_CCOBn. */
1644 #define BF_FTFA_FCCOB8_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FCCOB8_CCOBn) & BM_FTFA_FCCOB8_CCOBn)
1646 /*! @brief Set the CCOBn field to a new value. */
1647 #define BW_FTFA_FCCOB8_CCOBn(x, v) (HW_FTFA_FCCOB8_WR(x, v))
1650 /*******************************************************************************
1651 * HW_FTFA_FPROT3 - Program Flash Protection Registers
1652 ******************************************************************************/
1655 * @brief HW_FTFA_FPROT3 - Program Flash Protection Registers (RW)
1657 * Reset value: 0x00U
1659 * The FPROT registers define which logical program flash regions are protected
1660 * from program and erase operations. Protected flash regions cannot have their
1661 * content changed; that is, these regions cannot be programmed and cannot be
1662 * erased by any flash command. Unprotected regions can be changed by program and
1663 * erase operations. The four FPROT registers allow up to 32 protectable regions.
1664 * Each bit protects a 1/32 region of the program flash memory except for memory
1665 * configurations with less than 32 KB of program flash where each assigned bit
1666 * protects 1 KB . For configurations with 24 KB of program flash memory or less,
1667 * FPROT0 is not used. For configurations with 16 KB of program flash memory or
1668 * less, FPROT1 is not used. For configurations with 8 KB of program flash memory,
1669 * FPROT2 is not used. The bitfields are defined in each register as follows:
1670 * Program flash protection register Program flash protection bits FPROT0 PROT[31:24]
1671 * FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During the reset
1672 * sequence, the FPROT registers are loaded with the contents of the program flash
1673 * protection bytes in the Flash Configuration Field as indicated in the following
1674 * table. Program flash protection register Flash Configuration Field offset
1675 * address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To change the
1676 * program flash protection that is loaded during the reset sequence, unprotect the
1677 * sector of program flash memory that contains the Flash Configuration Field. Then,
1678 * reprogram the program flash protection byte.
1680 typedef union _hw_ftfa_fprot3
1683 struct _hw_ftfa_fprot3_bitfields
1685 uint8_t PROT
: 8; /*!< [7:0] Program Flash Region Protect */
1690 * @name Constants and macros for entire FTFA_FPROT3 register
1693 #define HW_FTFA_FPROT3_ADDR(x) ((x) + 0x10U)
1695 #define HW_FTFA_FPROT3(x) (*(__IO hw_ftfa_fprot3_t *) HW_FTFA_FPROT3_ADDR(x))
1696 #define HW_FTFA_FPROT3_RD(x) (HW_FTFA_FPROT3(x).U)
1697 #define HW_FTFA_FPROT3_WR(x, v) (HW_FTFA_FPROT3(x).U = (v))
1698 #define HW_FTFA_FPROT3_SET(x, v) (HW_FTFA_FPROT3_WR(x, HW_FTFA_FPROT3_RD(x) | (v)))
1699 #define HW_FTFA_FPROT3_CLR(x, v) (HW_FTFA_FPROT3_WR(x, HW_FTFA_FPROT3_RD(x) & ~(v)))
1700 #define HW_FTFA_FPROT3_TOG(x, v) (HW_FTFA_FPROT3_WR(x, HW_FTFA_FPROT3_RD(x) ^ (v)))
1704 * Constants & macros for individual FTFA_FPROT3 bitfields
1708 * @name Register FTFA_FPROT3, field PROT[7:0] (RW)
1710 * Each program flash region can be protected from program and erase operations
1711 * by setting the associated PROT bit. In NVM Normal mode: The protection can
1712 * only be increased, meaning that currently unprotected memory can be protected,
1713 * but currently protected memory cannot be unprotected. Since unprotected regions
1714 * are marked with a 1 and protected regions use a 0, only writes changing 1s to
1715 * 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit
1716 * basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with
1717 * 0-to-1 transitions are ignored. In NVM Special mode: All bits of FPROT are
1718 * writable without restriction. Unprotected areas can be protected and protected
1719 * areas can be unprotected. The user must never write to any FPROT register while
1720 * a command is running (CCIF=0). Trying to alter data in any protected area in
1721 * the program flash memory results in a protection violation error and sets the
1722 * FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible
1723 * if it contains any protected region. Each bit in the 32-bit protection
1724 * register represents 1/32 of the total program flash except for configurations where
1725 * program flash memory is less than 32 KB. For configurations with less than 32
1726 * KB of program flash memory, each assigned bit represents 1 KB.
1729 * - 0 - Program flash region is protected.
1730 * - 1 - Program flash region is not protected
1733 #define BP_FTFA_FPROT3_PROT (0U) /*!< Bit position for FTFA_FPROT3_PROT. */
1734 #define BM_FTFA_FPROT3_PROT (0xFFU) /*!< Bit mask for FTFA_FPROT3_PROT. */
1735 #define BS_FTFA_FPROT3_PROT (8U) /*!< Bit field size in bits for FTFA_FPROT3_PROT. */
1737 /*! @brief Read current value of the FTFA_FPROT3_PROT field. */
1738 #define BR_FTFA_FPROT3_PROT(x) (HW_FTFA_FPROT3(x).U)
1740 /*! @brief Format value for bitfield FTFA_FPROT3_PROT. */
1741 #define BF_FTFA_FPROT3_PROT(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FPROT3_PROT) & BM_FTFA_FPROT3_PROT)
1743 /*! @brief Set the PROT field to a new value. */
1744 #define BW_FTFA_FPROT3_PROT(x, v) (HW_FTFA_FPROT3_WR(x, v))
1747 /*******************************************************************************
1748 * HW_FTFA_FPROT2 - Program Flash Protection Registers
1749 ******************************************************************************/
1752 * @brief HW_FTFA_FPROT2 - Program Flash Protection Registers (RW)
1754 * Reset value: 0x00U
1756 * The FPROT registers define which logical program flash regions are protected
1757 * from program and erase operations. Protected flash regions cannot have their
1758 * content changed; that is, these regions cannot be programmed and cannot be
1759 * erased by any flash command. Unprotected regions can be changed by program and
1760 * erase operations. The four FPROT registers allow up to 32 protectable regions.
1761 * Each bit protects a 1/32 region of the program flash memory except for memory
1762 * configurations with less than 32 KB of program flash where each assigned bit
1763 * protects 1 KB . For configurations with 24 KB of program flash memory or less,
1764 * FPROT0 is not used. For configurations with 16 KB of program flash memory or
1765 * less, FPROT1 is not used. For configurations with 8 KB of program flash memory,
1766 * FPROT2 is not used. The bitfields are defined in each register as follows:
1767 * Program flash protection register Program flash protection bits FPROT0 PROT[31:24]
1768 * FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During the reset
1769 * sequence, the FPROT registers are loaded with the contents of the program flash
1770 * protection bytes in the Flash Configuration Field as indicated in the following
1771 * table. Program flash protection register Flash Configuration Field offset
1772 * address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To change the
1773 * program flash protection that is loaded during the reset sequence, unprotect the
1774 * sector of program flash memory that contains the Flash Configuration Field. Then,
1775 * reprogram the program flash protection byte.
1777 typedef union _hw_ftfa_fprot2
1780 struct _hw_ftfa_fprot2_bitfields
1782 uint8_t PROT
: 8; /*!< [7:0] Program Flash Region Protect */
1787 * @name Constants and macros for entire FTFA_FPROT2 register
1790 #define HW_FTFA_FPROT2_ADDR(x) ((x) + 0x11U)
1792 #define HW_FTFA_FPROT2(x) (*(__IO hw_ftfa_fprot2_t *) HW_FTFA_FPROT2_ADDR(x))
1793 #define HW_FTFA_FPROT2_RD(x) (HW_FTFA_FPROT2(x).U)
1794 #define HW_FTFA_FPROT2_WR(x, v) (HW_FTFA_FPROT2(x).U = (v))
1795 #define HW_FTFA_FPROT2_SET(x, v) (HW_FTFA_FPROT2_WR(x, HW_FTFA_FPROT2_RD(x) | (v)))
1796 #define HW_FTFA_FPROT2_CLR(x, v) (HW_FTFA_FPROT2_WR(x, HW_FTFA_FPROT2_RD(x) & ~(v)))
1797 #define HW_FTFA_FPROT2_TOG(x, v) (HW_FTFA_FPROT2_WR(x, HW_FTFA_FPROT2_RD(x) ^ (v)))
1801 * Constants & macros for individual FTFA_FPROT2 bitfields
1805 * @name Register FTFA_FPROT2, field PROT[7:0] (RW)
1807 * Each program flash region can be protected from program and erase operations
1808 * by setting the associated PROT bit. In NVM Normal mode: The protection can
1809 * only be increased, meaning that currently unprotected memory can be protected,
1810 * but currently protected memory cannot be unprotected. Since unprotected regions
1811 * are marked with a 1 and protected regions use a 0, only writes changing 1s to
1812 * 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit
1813 * basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with
1814 * 0-to-1 transitions are ignored. In NVM Special mode: All bits of FPROT are
1815 * writable without restriction. Unprotected areas can be protected and protected
1816 * areas can be unprotected. The user must never write to any FPROT register while
1817 * a command is running (CCIF=0). Trying to alter data in any protected area in
1818 * the program flash memory results in a protection violation error and sets the
1819 * FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible
1820 * if it contains any protected region. Each bit in the 32-bit protection
1821 * register represents 1/32 of the total program flash except for configurations where
1822 * program flash memory is less than 32 KB. For configurations with less than 32
1823 * KB of program flash memory, each assigned bit represents 1 KB.
1826 * - 0 - Program flash region is protected.
1827 * - 1 - Program flash region is not protected
1830 #define BP_FTFA_FPROT2_PROT (0U) /*!< Bit position for FTFA_FPROT2_PROT. */
1831 #define BM_FTFA_FPROT2_PROT (0xFFU) /*!< Bit mask for FTFA_FPROT2_PROT. */
1832 #define BS_FTFA_FPROT2_PROT (8U) /*!< Bit field size in bits for FTFA_FPROT2_PROT. */
1834 /*! @brief Read current value of the FTFA_FPROT2_PROT field. */
1835 #define BR_FTFA_FPROT2_PROT(x) (HW_FTFA_FPROT2(x).U)
1837 /*! @brief Format value for bitfield FTFA_FPROT2_PROT. */
1838 #define BF_FTFA_FPROT2_PROT(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FPROT2_PROT) & BM_FTFA_FPROT2_PROT)
1840 /*! @brief Set the PROT field to a new value. */
1841 #define BW_FTFA_FPROT2_PROT(x, v) (HW_FTFA_FPROT2_WR(x, v))
1844 /*******************************************************************************
1845 * HW_FTFA_FPROT1 - Program Flash Protection Registers
1846 ******************************************************************************/
1849 * @brief HW_FTFA_FPROT1 - Program Flash Protection Registers (RW)
1851 * Reset value: 0x00U
1853 * The FPROT registers define which logical program flash regions are protected
1854 * from program and erase operations. Protected flash regions cannot have their
1855 * content changed; that is, these regions cannot be programmed and cannot be
1856 * erased by any flash command. Unprotected regions can be changed by program and
1857 * erase operations. The four FPROT registers allow up to 32 protectable regions.
1858 * Each bit protects a 1/32 region of the program flash memory except for memory
1859 * configurations with less than 32 KB of program flash where each assigned bit
1860 * protects 1 KB . For configurations with 24 KB of program flash memory or less,
1861 * FPROT0 is not used. For configurations with 16 KB of program flash memory or
1862 * less, FPROT1 is not used. For configurations with 8 KB of program flash memory,
1863 * FPROT2 is not used. The bitfields are defined in each register as follows:
1864 * Program flash protection register Program flash protection bits FPROT0 PROT[31:24]
1865 * FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During the reset
1866 * sequence, the FPROT registers are loaded with the contents of the program flash
1867 * protection bytes in the Flash Configuration Field as indicated in the following
1868 * table. Program flash protection register Flash Configuration Field offset
1869 * address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To change the
1870 * program flash protection that is loaded during the reset sequence, unprotect the
1871 * sector of program flash memory that contains the Flash Configuration Field. Then,
1872 * reprogram the program flash protection byte.
1874 typedef union _hw_ftfa_fprot1
1877 struct _hw_ftfa_fprot1_bitfields
1879 uint8_t PROT
: 8; /*!< [7:0] Program Flash Region Protect */
1884 * @name Constants and macros for entire FTFA_FPROT1 register
1887 #define HW_FTFA_FPROT1_ADDR(x) ((x) + 0x12U)
1889 #define HW_FTFA_FPROT1(x) (*(__IO hw_ftfa_fprot1_t *) HW_FTFA_FPROT1_ADDR(x))
1890 #define HW_FTFA_FPROT1_RD(x) (HW_FTFA_FPROT1(x).U)
1891 #define HW_FTFA_FPROT1_WR(x, v) (HW_FTFA_FPROT1(x).U = (v))
1892 #define HW_FTFA_FPROT1_SET(x, v) (HW_FTFA_FPROT1_WR(x, HW_FTFA_FPROT1_RD(x) | (v)))
1893 #define HW_FTFA_FPROT1_CLR(x, v) (HW_FTFA_FPROT1_WR(x, HW_FTFA_FPROT1_RD(x) & ~(v)))
1894 #define HW_FTFA_FPROT1_TOG(x, v) (HW_FTFA_FPROT1_WR(x, HW_FTFA_FPROT1_RD(x) ^ (v)))
1898 * Constants & macros for individual FTFA_FPROT1 bitfields
1902 * @name Register FTFA_FPROT1, field PROT[7:0] (RW)
1904 * Each program flash region can be protected from program and erase operations
1905 * by setting the associated PROT bit. In NVM Normal mode: The protection can
1906 * only be increased, meaning that currently unprotected memory can be protected,
1907 * but currently protected memory cannot be unprotected. Since unprotected regions
1908 * are marked with a 1 and protected regions use a 0, only writes changing 1s to
1909 * 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit
1910 * basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with
1911 * 0-to-1 transitions are ignored. In NVM Special mode: All bits of FPROT are
1912 * writable without restriction. Unprotected areas can be protected and protected
1913 * areas can be unprotected. The user must never write to any FPROT register while
1914 * a command is running (CCIF=0). Trying to alter data in any protected area in
1915 * the program flash memory results in a protection violation error and sets the
1916 * FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible
1917 * if it contains any protected region. Each bit in the 32-bit protection
1918 * register represents 1/32 of the total program flash except for configurations where
1919 * program flash memory is less than 32 KB. For configurations with less than 32
1920 * KB of program flash memory, each assigned bit represents 1 KB.
1923 * - 0 - Program flash region is protected.
1924 * - 1 - Program flash region is not protected
1927 #define BP_FTFA_FPROT1_PROT (0U) /*!< Bit position for FTFA_FPROT1_PROT. */
1928 #define BM_FTFA_FPROT1_PROT (0xFFU) /*!< Bit mask for FTFA_FPROT1_PROT. */
1929 #define BS_FTFA_FPROT1_PROT (8U) /*!< Bit field size in bits for FTFA_FPROT1_PROT. */
1931 /*! @brief Read current value of the FTFA_FPROT1_PROT field. */
1932 #define BR_FTFA_FPROT1_PROT(x) (HW_FTFA_FPROT1(x).U)
1934 /*! @brief Format value for bitfield FTFA_FPROT1_PROT. */
1935 #define BF_FTFA_FPROT1_PROT(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FPROT1_PROT) & BM_FTFA_FPROT1_PROT)
1937 /*! @brief Set the PROT field to a new value. */
1938 #define BW_FTFA_FPROT1_PROT(x, v) (HW_FTFA_FPROT1_WR(x, v))
1941 /*******************************************************************************
1942 * HW_FTFA_FPROT0 - Program Flash Protection Registers
1943 ******************************************************************************/
1946 * @brief HW_FTFA_FPROT0 - Program Flash Protection Registers (RW)
1948 * Reset value: 0x00U
1950 * The FPROT registers define which logical program flash regions are protected
1951 * from program and erase operations. Protected flash regions cannot have their
1952 * content changed; that is, these regions cannot be programmed and cannot be
1953 * erased by any flash command. Unprotected regions can be changed by program and
1954 * erase operations. The four FPROT registers allow up to 32 protectable regions.
1955 * Each bit protects a 1/32 region of the program flash memory except for memory
1956 * configurations with less than 32 KB of program flash where each assigned bit
1957 * protects 1 KB . For configurations with 24 KB of program flash memory or less,
1958 * FPROT0 is not used. For configurations with 16 KB of program flash memory or
1959 * less, FPROT1 is not used. For configurations with 8 KB of program flash memory,
1960 * FPROT2 is not used. The bitfields are defined in each register as follows:
1961 * Program flash protection register Program flash protection bits FPROT0 PROT[31:24]
1962 * FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During the reset
1963 * sequence, the FPROT registers are loaded with the contents of the program flash
1964 * protection bytes in the Flash Configuration Field as indicated in the following
1965 * table. Program flash protection register Flash Configuration Field offset
1966 * address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To change the
1967 * program flash protection that is loaded during the reset sequence, unprotect the
1968 * sector of program flash memory that contains the Flash Configuration Field. Then,
1969 * reprogram the program flash protection byte.
1971 typedef union _hw_ftfa_fprot0
1974 struct _hw_ftfa_fprot0_bitfields
1976 uint8_t PROT
: 8; /*!< [7:0] Program Flash Region Protect */
1981 * @name Constants and macros for entire FTFA_FPROT0 register
1984 #define HW_FTFA_FPROT0_ADDR(x) ((x) + 0x13U)
1986 #define HW_FTFA_FPROT0(x) (*(__IO hw_ftfa_fprot0_t *) HW_FTFA_FPROT0_ADDR(x))
1987 #define HW_FTFA_FPROT0_RD(x) (HW_FTFA_FPROT0(x).U)
1988 #define HW_FTFA_FPROT0_WR(x, v) (HW_FTFA_FPROT0(x).U = (v))
1989 #define HW_FTFA_FPROT0_SET(x, v) (HW_FTFA_FPROT0_WR(x, HW_FTFA_FPROT0_RD(x) | (v)))
1990 #define HW_FTFA_FPROT0_CLR(x, v) (HW_FTFA_FPROT0_WR(x, HW_FTFA_FPROT0_RD(x) & ~(v)))
1991 #define HW_FTFA_FPROT0_TOG(x, v) (HW_FTFA_FPROT0_WR(x, HW_FTFA_FPROT0_RD(x) ^ (v)))
1995 * Constants & macros for individual FTFA_FPROT0 bitfields
1999 * @name Register FTFA_FPROT0, field PROT[7:0] (RW)
2001 * Each program flash region can be protected from program and erase operations
2002 * by setting the associated PROT bit. In NVM Normal mode: The protection can
2003 * only be increased, meaning that currently unprotected memory can be protected,
2004 * but currently protected memory cannot be unprotected. Since unprotected regions
2005 * are marked with a 1 and protected regions use a 0, only writes changing 1s to
2006 * 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit
2007 * basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with
2008 * 0-to-1 transitions are ignored. In NVM Special mode: All bits of FPROT are
2009 * writable without restriction. Unprotected areas can be protected and protected
2010 * areas can be unprotected. The user must never write to any FPROT register while
2011 * a command is running (CCIF=0). Trying to alter data in any protected area in
2012 * the program flash memory results in a protection violation error and sets the
2013 * FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible
2014 * if it contains any protected region. Each bit in the 32-bit protection
2015 * register represents 1/32 of the total program flash except for configurations where
2016 * program flash memory is less than 32 KB. For configurations with less than 32
2017 * KB of program flash memory, each assigned bit represents 1 KB.
2020 * - 0 - Program flash region is protected.
2021 * - 1 - Program flash region is not protected
2024 #define BP_FTFA_FPROT0_PROT (0U) /*!< Bit position for FTFA_FPROT0_PROT. */
2025 #define BM_FTFA_FPROT0_PROT (0xFFU) /*!< Bit mask for FTFA_FPROT0_PROT. */
2026 #define BS_FTFA_FPROT0_PROT (8U) /*!< Bit field size in bits for FTFA_FPROT0_PROT. */
2028 /*! @brief Read current value of the FTFA_FPROT0_PROT field. */
2029 #define BR_FTFA_FPROT0_PROT(x) (HW_FTFA_FPROT0(x).U)
2031 /*! @brief Format value for bitfield FTFA_FPROT0_PROT. */
2032 #define BF_FTFA_FPROT0_PROT(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FPROT0_PROT) & BM_FTFA_FPROT0_PROT)
2034 /*! @brief Set the PROT field to a new value. */
2035 #define BW_FTFA_FPROT0_PROT(x, v) (HW_FTFA_FPROT0_WR(x, v))
2038 /*******************************************************************************
2039 * HW_FTFA_XACCH3 - Execute-only Access Registers
2040 ******************************************************************************/
2043 * @brief HW_FTFA_XACCH3 - Execute-only Access Registers (RO)
2045 * Reset value: 0x00U
2047 * The XACC registers define which logical program flash segments are restricted
2048 * to data read or execute only or both data and instruction fetches. The eight
2049 * XACC registers allow up to 64 restricted segments of equal memory size.
2050 * Execute-only access register Program flash execute-only access bits XACCH0 XA[63:56]
2051 * XACCH1 XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1
2052 * XA[23:16] XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC
2053 * registers are loaded with the logical AND of Program Flash IFR addresses A and B
2054 * as indicated in the following table. Execute-only access register Program
2055 * Flash IFR address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA
2056 * XACCH2 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2
2057 * 0xA5 0xAD XACCL3 0xA4 0xAC Use the Program Once command to program the
2058 * execute-only access control fields that are loaded during the reset sequence.
2060 typedef union _hw_ftfa_xacch3
2063 struct _hw_ftfa_xacch3_bitfields
2065 uint8_t XA
: 8; /*!< [7:0] Execute-only access control */
2070 * @name Constants and macros for entire FTFA_XACCH3 register
2073 #define HW_FTFA_XACCH3_ADDR(x) ((x) + 0x18U)
2075 #define HW_FTFA_XACCH3(x) (*(__I hw_ftfa_xacch3_t *) HW_FTFA_XACCH3_ADDR(x))
2076 #define HW_FTFA_XACCH3_RD(x) (HW_FTFA_XACCH3(x).U)
2080 * Constants & macros for individual FTFA_XACCH3 bitfields
2084 * @name Register FTFA_XACCH3, field XA[7:0] (RO)
2087 * - 0 - Associated segment is accessible in execute mode only (as an
2088 * instruction fetch)
2089 * - 1 - Associated segment is accessible as data or in execute mode
2092 #define BP_FTFA_XACCH3_XA (0U) /*!< Bit position for FTFA_XACCH3_XA. */
2093 #define BM_FTFA_XACCH3_XA (0xFFU) /*!< Bit mask for FTFA_XACCH3_XA. */
2094 #define BS_FTFA_XACCH3_XA (8U) /*!< Bit field size in bits for FTFA_XACCH3_XA. */
2096 /*! @brief Read current value of the FTFA_XACCH3_XA field. */
2097 #define BR_FTFA_XACCH3_XA(x) (HW_FTFA_XACCH3(x).U)
2100 /*******************************************************************************
2101 * HW_FTFA_XACCH2 - Execute-only Access Registers
2102 ******************************************************************************/
2105 * @brief HW_FTFA_XACCH2 - Execute-only Access Registers (RO)
2107 * Reset value: 0x00U
2109 * The XACC registers define which logical program flash segments are restricted
2110 * to data read or execute only or both data and instruction fetches. The eight
2111 * XACC registers allow up to 64 restricted segments of equal memory size.
2112 * Execute-only access register Program flash execute-only access bits XACCH0 XA[63:56]
2113 * XACCH1 XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1
2114 * XA[23:16] XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC
2115 * registers are loaded with the logical AND of Program Flash IFR addresses A and B
2116 * as indicated in the following table. Execute-only access register Program
2117 * Flash IFR address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA
2118 * XACCH2 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2
2119 * 0xA5 0xAD XACCL3 0xA4 0xAC Use the Program Once command to program the
2120 * execute-only access control fields that are loaded during the reset sequence.
2122 typedef union _hw_ftfa_xacch2
2125 struct _hw_ftfa_xacch2_bitfields
2127 uint8_t XA
: 8; /*!< [7:0] Execute-only access control */
2132 * @name Constants and macros for entire FTFA_XACCH2 register
2135 #define HW_FTFA_XACCH2_ADDR(x) ((x) + 0x19U)
2137 #define HW_FTFA_XACCH2(x) (*(__I hw_ftfa_xacch2_t *) HW_FTFA_XACCH2_ADDR(x))
2138 #define HW_FTFA_XACCH2_RD(x) (HW_FTFA_XACCH2(x).U)
2142 * Constants & macros for individual FTFA_XACCH2 bitfields
2146 * @name Register FTFA_XACCH2, field XA[7:0] (RO)
2149 * - 0 - Associated segment is accessible in execute mode only (as an
2150 * instruction fetch)
2151 * - 1 - Associated segment is accessible as data or in execute mode
2154 #define BP_FTFA_XACCH2_XA (0U) /*!< Bit position for FTFA_XACCH2_XA. */
2155 #define BM_FTFA_XACCH2_XA (0xFFU) /*!< Bit mask for FTFA_XACCH2_XA. */
2156 #define BS_FTFA_XACCH2_XA (8U) /*!< Bit field size in bits for FTFA_XACCH2_XA. */
2158 /*! @brief Read current value of the FTFA_XACCH2_XA field. */
2159 #define BR_FTFA_XACCH2_XA(x) (HW_FTFA_XACCH2(x).U)
2162 /*******************************************************************************
2163 * HW_FTFA_XACCH1 - Execute-only Access Registers
2164 ******************************************************************************/
2167 * @brief HW_FTFA_XACCH1 - Execute-only Access Registers (RO)
2169 * Reset value: 0x00U
2171 * The XACC registers define which logical program flash segments are restricted
2172 * to data read or execute only or both data and instruction fetches. The eight
2173 * XACC registers allow up to 64 restricted segments of equal memory size.
2174 * Execute-only access register Program flash execute-only access bits XACCH0 XA[63:56]
2175 * XACCH1 XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1
2176 * XA[23:16] XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC
2177 * registers are loaded with the logical AND of Program Flash IFR addresses A and B
2178 * as indicated in the following table. Execute-only access register Program
2179 * Flash IFR address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA
2180 * XACCH2 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2
2181 * 0xA5 0xAD XACCL3 0xA4 0xAC Use the Program Once command to program the
2182 * execute-only access control fields that are loaded during the reset sequence.
2184 typedef union _hw_ftfa_xacch1
2187 struct _hw_ftfa_xacch1_bitfields
2189 uint8_t XA
: 8; /*!< [7:0] Execute-only access control */
2194 * @name Constants and macros for entire FTFA_XACCH1 register
2197 #define HW_FTFA_XACCH1_ADDR(x) ((x) + 0x1AU)
2199 #define HW_FTFA_XACCH1(x) (*(__I hw_ftfa_xacch1_t *) HW_FTFA_XACCH1_ADDR(x))
2200 #define HW_FTFA_XACCH1_RD(x) (HW_FTFA_XACCH1(x).U)
2204 * Constants & macros for individual FTFA_XACCH1 bitfields
2208 * @name Register FTFA_XACCH1, field XA[7:0] (RO)
2211 * - 0 - Associated segment is accessible in execute mode only (as an
2212 * instruction fetch)
2213 * - 1 - Associated segment is accessible as data or in execute mode
2216 #define BP_FTFA_XACCH1_XA (0U) /*!< Bit position for FTFA_XACCH1_XA. */
2217 #define BM_FTFA_XACCH1_XA (0xFFU) /*!< Bit mask for FTFA_XACCH1_XA. */
2218 #define BS_FTFA_XACCH1_XA (8U) /*!< Bit field size in bits for FTFA_XACCH1_XA. */
2220 /*! @brief Read current value of the FTFA_XACCH1_XA field. */
2221 #define BR_FTFA_XACCH1_XA(x) (HW_FTFA_XACCH1(x).U)
2224 /*******************************************************************************
2225 * HW_FTFA_XACCH0 - Execute-only Access Registers
2226 ******************************************************************************/
2229 * @brief HW_FTFA_XACCH0 - Execute-only Access Registers (RO)
2231 * Reset value: 0x00U
2233 * The XACC registers define which logical program flash segments are restricted
2234 * to data read or execute only or both data and instruction fetches. The eight
2235 * XACC registers allow up to 64 restricted segments of equal memory size.
2236 * Execute-only access register Program flash execute-only access bits XACCH0 XA[63:56]
2237 * XACCH1 XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1
2238 * XA[23:16] XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC
2239 * registers are loaded with the logical AND of Program Flash IFR addresses A and B
2240 * as indicated in the following table. Execute-only access register Program
2241 * Flash IFR address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA
2242 * XACCH2 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2
2243 * 0xA5 0xAD XACCL3 0xA4 0xAC Use the Program Once command to program the
2244 * execute-only access control fields that are loaded during the reset sequence.
2246 typedef union _hw_ftfa_xacch0
2249 struct _hw_ftfa_xacch0_bitfields
2251 uint8_t XA
: 8; /*!< [7:0] Execute-only access control */
2256 * @name Constants and macros for entire FTFA_XACCH0 register
2259 #define HW_FTFA_XACCH0_ADDR(x) ((x) + 0x1BU)
2261 #define HW_FTFA_XACCH0(x) (*(__I hw_ftfa_xacch0_t *) HW_FTFA_XACCH0_ADDR(x))
2262 #define HW_FTFA_XACCH0_RD(x) (HW_FTFA_XACCH0(x).U)
2266 * Constants & macros for individual FTFA_XACCH0 bitfields
2270 * @name Register FTFA_XACCH0, field XA[7:0] (RO)
2273 * - 0 - Associated segment is accessible in execute mode only (as an
2274 * instruction fetch)
2275 * - 1 - Associated segment is accessible as data or in execute mode
2278 #define BP_FTFA_XACCH0_XA (0U) /*!< Bit position for FTFA_XACCH0_XA. */
2279 #define BM_FTFA_XACCH0_XA (0xFFU) /*!< Bit mask for FTFA_XACCH0_XA. */
2280 #define BS_FTFA_XACCH0_XA (8U) /*!< Bit field size in bits for FTFA_XACCH0_XA. */
2282 /*! @brief Read current value of the FTFA_XACCH0_XA field. */
2283 #define BR_FTFA_XACCH0_XA(x) (HW_FTFA_XACCH0(x).U)
2286 /*******************************************************************************
2287 * HW_FTFA_XACCL3 - Execute-only Access Registers
2288 ******************************************************************************/
2291 * @brief HW_FTFA_XACCL3 - Execute-only Access Registers (RO)
2293 * Reset value: 0x00U
2295 * The XACC registers define which logical program flash segments are restricted
2296 * to data read or execute only or both data and instruction fetches. The eight
2297 * XACC registers allow up to 64 restricted segments of equal memory size.
2298 * Execute-only access register Program flash execute-only access bits XACCH0 XA[63:56]
2299 * XACCH1 XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1
2300 * XA[23:16] XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC
2301 * registers are loaded with the logical AND of Program Flash IFR addresses A and B
2302 * as indicated in the following table. Execute-only access register Program
2303 * Flash IFR address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA
2304 * XACCH2 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2
2305 * 0xA5 0xAD XACCL3 0xA4 0xAC Use the Program Once command to program the
2306 * execute-only access control fields that are loaded during the reset sequence.
2308 typedef union _hw_ftfa_xaccl3
2311 struct _hw_ftfa_xaccl3_bitfields
2313 uint8_t XA
: 8; /*!< [7:0] Execute-only access control */
2318 * @name Constants and macros for entire FTFA_XACCL3 register
2321 #define HW_FTFA_XACCL3_ADDR(x) ((x) + 0x1CU)
2323 #define HW_FTFA_XACCL3(x) (*(__I hw_ftfa_xaccl3_t *) HW_FTFA_XACCL3_ADDR(x))
2324 #define HW_FTFA_XACCL3_RD(x) (HW_FTFA_XACCL3(x).U)
2328 * Constants & macros for individual FTFA_XACCL3 bitfields
2332 * @name Register FTFA_XACCL3, field XA[7:0] (RO)
2335 * - 0 - Associated segment is accessible in execute mode only (as an
2336 * instruction fetch)
2337 * - 1 - Associated segment is accessible as data or in execute mode
2340 #define BP_FTFA_XACCL3_XA (0U) /*!< Bit position for FTFA_XACCL3_XA. */
2341 #define BM_FTFA_XACCL3_XA (0xFFU) /*!< Bit mask for FTFA_XACCL3_XA. */
2342 #define BS_FTFA_XACCL3_XA (8U) /*!< Bit field size in bits for FTFA_XACCL3_XA. */
2344 /*! @brief Read current value of the FTFA_XACCL3_XA field. */
2345 #define BR_FTFA_XACCL3_XA(x) (HW_FTFA_XACCL3(x).U)
2348 /*******************************************************************************
2349 * HW_FTFA_XACCL2 - Execute-only Access Registers
2350 ******************************************************************************/
2353 * @brief HW_FTFA_XACCL2 - Execute-only Access Registers (RO)
2355 * Reset value: 0x00U
2357 * The XACC registers define which logical program flash segments are restricted
2358 * to data read or execute only or both data and instruction fetches. The eight
2359 * XACC registers allow up to 64 restricted segments of equal memory size.
2360 * Execute-only access register Program flash execute-only access bits XACCH0 XA[63:56]
2361 * XACCH1 XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1
2362 * XA[23:16] XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC
2363 * registers are loaded with the logical AND of Program Flash IFR addresses A and B
2364 * as indicated in the following table. Execute-only access register Program
2365 * Flash IFR address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA
2366 * XACCH2 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2
2367 * 0xA5 0xAD XACCL3 0xA4 0xAC Use the Program Once command to program the
2368 * execute-only access control fields that are loaded during the reset sequence.
2370 typedef union _hw_ftfa_xaccl2
2373 struct _hw_ftfa_xaccl2_bitfields
2375 uint8_t XA
: 8; /*!< [7:0] Execute-only access control */
2380 * @name Constants and macros for entire FTFA_XACCL2 register
2383 #define HW_FTFA_XACCL2_ADDR(x) ((x) + 0x1DU)
2385 #define HW_FTFA_XACCL2(x) (*(__I hw_ftfa_xaccl2_t *) HW_FTFA_XACCL2_ADDR(x))
2386 #define HW_FTFA_XACCL2_RD(x) (HW_FTFA_XACCL2(x).U)
2390 * Constants & macros for individual FTFA_XACCL2 bitfields
2394 * @name Register FTFA_XACCL2, field XA[7:0] (RO)
2397 * - 0 - Associated segment is accessible in execute mode only (as an
2398 * instruction fetch)
2399 * - 1 - Associated segment is accessible as data or in execute mode
2402 #define BP_FTFA_XACCL2_XA (0U) /*!< Bit position for FTFA_XACCL2_XA. */
2403 #define BM_FTFA_XACCL2_XA (0xFFU) /*!< Bit mask for FTFA_XACCL2_XA. */
2404 #define BS_FTFA_XACCL2_XA (8U) /*!< Bit field size in bits for FTFA_XACCL2_XA. */
2406 /*! @brief Read current value of the FTFA_XACCL2_XA field. */
2407 #define BR_FTFA_XACCL2_XA(x) (HW_FTFA_XACCL2(x).U)
2410 /*******************************************************************************
2411 * HW_FTFA_XACCL1 - Execute-only Access Registers
2412 ******************************************************************************/
2415 * @brief HW_FTFA_XACCL1 - Execute-only Access Registers (RO)
2417 * Reset value: 0x00U
2419 * The XACC registers define which logical program flash segments are restricted
2420 * to data read or execute only or both data and instruction fetches. The eight
2421 * XACC registers allow up to 64 restricted segments of equal memory size.
2422 * Execute-only access register Program flash execute-only access bits XACCH0 XA[63:56]
2423 * XACCH1 XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1
2424 * XA[23:16] XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC
2425 * registers are loaded with the logical AND of Program Flash IFR addresses A and B
2426 * as indicated in the following table. Execute-only access register Program
2427 * Flash IFR address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA
2428 * XACCH2 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2
2429 * 0xA5 0xAD XACCL3 0xA4 0xAC Use the Program Once command to program the
2430 * execute-only access control fields that are loaded during the reset sequence.
2432 typedef union _hw_ftfa_xaccl1
2435 struct _hw_ftfa_xaccl1_bitfields
2437 uint8_t XA
: 8; /*!< [7:0] Execute-only access control */
2442 * @name Constants and macros for entire FTFA_XACCL1 register
2445 #define HW_FTFA_XACCL1_ADDR(x) ((x) + 0x1EU)
2447 #define HW_FTFA_XACCL1(x) (*(__I hw_ftfa_xaccl1_t *) HW_FTFA_XACCL1_ADDR(x))
2448 #define HW_FTFA_XACCL1_RD(x) (HW_FTFA_XACCL1(x).U)
2452 * Constants & macros for individual FTFA_XACCL1 bitfields
2456 * @name Register FTFA_XACCL1, field XA[7:0] (RO)
2459 * - 0 - Associated segment is accessible in execute mode only (as an
2460 * instruction fetch)
2461 * - 1 - Associated segment is accessible as data or in execute mode
2464 #define BP_FTFA_XACCL1_XA (0U) /*!< Bit position for FTFA_XACCL1_XA. */
2465 #define BM_FTFA_XACCL1_XA (0xFFU) /*!< Bit mask for FTFA_XACCL1_XA. */
2466 #define BS_FTFA_XACCL1_XA (8U) /*!< Bit field size in bits for FTFA_XACCL1_XA. */
2468 /*! @brief Read current value of the FTFA_XACCL1_XA field. */
2469 #define BR_FTFA_XACCL1_XA(x) (HW_FTFA_XACCL1(x).U)
2472 /*******************************************************************************
2473 * HW_FTFA_XACCL0 - Execute-only Access Registers
2474 ******************************************************************************/
2477 * @brief HW_FTFA_XACCL0 - Execute-only Access Registers (RO)
2479 * Reset value: 0x00U
2481 * The XACC registers define which logical program flash segments are restricted
2482 * to data read or execute only or both data and instruction fetches. The eight
2483 * XACC registers allow up to 64 restricted segments of equal memory size.
2484 * Execute-only access register Program flash execute-only access bits XACCH0 XA[63:56]
2485 * XACCH1 XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1
2486 * XA[23:16] XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC
2487 * registers are loaded with the logical AND of Program Flash IFR addresses A and B
2488 * as indicated in the following table. Execute-only access register Program
2489 * Flash IFR address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA
2490 * XACCH2 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2
2491 * 0xA5 0xAD XACCL3 0xA4 0xAC Use the Program Once command to program the
2492 * execute-only access control fields that are loaded during the reset sequence.
2494 typedef union _hw_ftfa_xaccl0
2497 struct _hw_ftfa_xaccl0_bitfields
2499 uint8_t XA
: 8; /*!< [7:0] Execute-only access control */
2504 * @name Constants and macros for entire FTFA_XACCL0 register
2507 #define HW_FTFA_XACCL0_ADDR(x) ((x) + 0x1FU)
2509 #define HW_FTFA_XACCL0(x) (*(__I hw_ftfa_xaccl0_t *) HW_FTFA_XACCL0_ADDR(x))
2510 #define HW_FTFA_XACCL0_RD(x) (HW_FTFA_XACCL0(x).U)
2514 * Constants & macros for individual FTFA_XACCL0 bitfields
2518 * @name Register FTFA_XACCL0, field XA[7:0] (RO)
2521 * - 0 - Associated segment is accessible in execute mode only (as an
2522 * instruction fetch)
2523 * - 1 - Associated segment is accessible as data or in execute mode
2526 #define BP_FTFA_XACCL0_XA (0U) /*!< Bit position for FTFA_XACCL0_XA. */
2527 #define BM_FTFA_XACCL0_XA (0xFFU) /*!< Bit mask for FTFA_XACCL0_XA. */
2528 #define BS_FTFA_XACCL0_XA (8U) /*!< Bit field size in bits for FTFA_XACCL0_XA. */
2530 /*! @brief Read current value of the FTFA_XACCL0_XA field. */
2531 #define BR_FTFA_XACCL0_XA(x) (HW_FTFA_XACCL0(x).U)
2534 /*******************************************************************************
2535 * HW_FTFA_SACCH3 - Supervisor-only Access Registers
2536 ******************************************************************************/
2539 * @brief HW_FTFA_SACCH3 - Supervisor-only Access Registers (RO)
2541 * Reset value: 0x00U
2543 * The SACC registers define which logical program flash segments are restricted
2544 * to supervisor only or user and supervisor access. The eight SACC registers
2545 * allow up to 64 restricted segments of equal memory size. Supervisor-only access
2546 * register Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1
2547 * SA[55:48] SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16]
2548 * SACCL2 SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are
2549 * loaded with the logical AND of Program Flash IFR addresses A and B as
2550 * indicated in the following table. Supervisor-only access register Program Flash IFR
2551 * address A Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2
2552 * 0xB1 0xB9 SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD
2553 * SACCL3 0xB4 0xBC Use the Program Once command to program the supervisor-only
2554 * access control fields that are loaded during the reset sequence.
2556 typedef union _hw_ftfa_sacch3
2559 struct _hw_ftfa_sacch3_bitfields
2561 uint8_t SA
: 8; /*!< [7:0] Supervisor-only access control */
2566 * @name Constants and macros for entire FTFA_SACCH3 register
2569 #define HW_FTFA_SACCH3_ADDR(x) ((x) + 0x20U)
2571 #define HW_FTFA_SACCH3(x) (*(__I hw_ftfa_sacch3_t *) HW_FTFA_SACCH3_ADDR(x))
2572 #define HW_FTFA_SACCH3_RD(x) (HW_FTFA_SACCH3(x).U)
2576 * Constants & macros for individual FTFA_SACCH3 bitfields
2580 * @name Register FTFA_SACCH3, field SA[7:0] (RO)
2583 * - 0 - Associated segment is accessible in supervisor mode only
2584 * - 1 - Associated segment is accessible in user or supervisor mode
2587 #define BP_FTFA_SACCH3_SA (0U) /*!< Bit position for FTFA_SACCH3_SA. */
2588 #define BM_FTFA_SACCH3_SA (0xFFU) /*!< Bit mask for FTFA_SACCH3_SA. */
2589 #define BS_FTFA_SACCH3_SA (8U) /*!< Bit field size in bits for FTFA_SACCH3_SA. */
2591 /*! @brief Read current value of the FTFA_SACCH3_SA field. */
2592 #define BR_FTFA_SACCH3_SA(x) (HW_FTFA_SACCH3(x).U)
2595 /*******************************************************************************
2596 * HW_FTFA_SACCH2 - Supervisor-only Access Registers
2597 ******************************************************************************/
2600 * @brief HW_FTFA_SACCH2 - Supervisor-only Access Registers (RO)
2602 * Reset value: 0x00U
2604 * The SACC registers define which logical program flash segments are restricted
2605 * to supervisor only or user and supervisor access. The eight SACC registers
2606 * allow up to 64 restricted segments of equal memory size. Supervisor-only access
2607 * register Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1
2608 * SA[55:48] SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16]
2609 * SACCL2 SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are
2610 * loaded with the logical AND of Program Flash IFR addresses A and B as
2611 * indicated in the following table. Supervisor-only access register Program Flash IFR
2612 * address A Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2
2613 * 0xB1 0xB9 SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD
2614 * SACCL3 0xB4 0xBC Use the Program Once command to program the supervisor-only
2615 * access control fields that are loaded during the reset sequence.
2617 typedef union _hw_ftfa_sacch2
2620 struct _hw_ftfa_sacch2_bitfields
2622 uint8_t SA
: 8; /*!< [7:0] Supervisor-only access control */
2627 * @name Constants and macros for entire FTFA_SACCH2 register
2630 #define HW_FTFA_SACCH2_ADDR(x) ((x) + 0x21U)
2632 #define HW_FTFA_SACCH2(x) (*(__I hw_ftfa_sacch2_t *) HW_FTFA_SACCH2_ADDR(x))
2633 #define HW_FTFA_SACCH2_RD(x) (HW_FTFA_SACCH2(x).U)
2637 * Constants & macros for individual FTFA_SACCH2 bitfields
2641 * @name Register FTFA_SACCH2, field SA[7:0] (RO)
2644 * - 0 - Associated segment is accessible in supervisor mode only
2645 * - 1 - Associated segment is accessible in user or supervisor mode
2648 #define BP_FTFA_SACCH2_SA (0U) /*!< Bit position for FTFA_SACCH2_SA. */
2649 #define BM_FTFA_SACCH2_SA (0xFFU) /*!< Bit mask for FTFA_SACCH2_SA. */
2650 #define BS_FTFA_SACCH2_SA (8U) /*!< Bit field size in bits for FTFA_SACCH2_SA. */
2652 /*! @brief Read current value of the FTFA_SACCH2_SA field. */
2653 #define BR_FTFA_SACCH2_SA(x) (HW_FTFA_SACCH2(x).U)
2656 /*******************************************************************************
2657 * HW_FTFA_SACCH1 - Supervisor-only Access Registers
2658 ******************************************************************************/
2661 * @brief HW_FTFA_SACCH1 - Supervisor-only Access Registers (RO)
2663 * Reset value: 0x00U
2665 * The SACC registers define which logical program flash segments are restricted
2666 * to supervisor only or user and supervisor access. The eight SACC registers
2667 * allow up to 64 restricted segments of equal memory size. Supervisor-only access
2668 * register Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1
2669 * SA[55:48] SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16]
2670 * SACCL2 SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are
2671 * loaded with the logical AND of Program Flash IFR addresses A and B as
2672 * indicated in the following table. Supervisor-only access register Program Flash IFR
2673 * address A Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2
2674 * 0xB1 0xB9 SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD
2675 * SACCL3 0xB4 0xBC Use the Program Once command to program the supervisor-only
2676 * access control fields that are loaded during the reset sequence.
2678 typedef union _hw_ftfa_sacch1
2681 struct _hw_ftfa_sacch1_bitfields
2683 uint8_t SA
: 8; /*!< [7:0] Supervisor-only access control */
2688 * @name Constants and macros for entire FTFA_SACCH1 register
2691 #define HW_FTFA_SACCH1_ADDR(x) ((x) + 0x22U)
2693 #define HW_FTFA_SACCH1(x) (*(__I hw_ftfa_sacch1_t *) HW_FTFA_SACCH1_ADDR(x))
2694 #define HW_FTFA_SACCH1_RD(x) (HW_FTFA_SACCH1(x).U)
2698 * Constants & macros for individual FTFA_SACCH1 bitfields
2702 * @name Register FTFA_SACCH1, field SA[7:0] (RO)
2705 * - 0 - Associated segment is accessible in supervisor mode only
2706 * - 1 - Associated segment is accessible in user or supervisor mode
2709 #define BP_FTFA_SACCH1_SA (0U) /*!< Bit position for FTFA_SACCH1_SA. */
2710 #define BM_FTFA_SACCH1_SA (0xFFU) /*!< Bit mask for FTFA_SACCH1_SA. */
2711 #define BS_FTFA_SACCH1_SA (8U) /*!< Bit field size in bits for FTFA_SACCH1_SA. */
2713 /*! @brief Read current value of the FTFA_SACCH1_SA field. */
2714 #define BR_FTFA_SACCH1_SA(x) (HW_FTFA_SACCH1(x).U)
2717 /*******************************************************************************
2718 * HW_FTFA_SACCH0 - Supervisor-only Access Registers
2719 ******************************************************************************/
2722 * @brief HW_FTFA_SACCH0 - Supervisor-only Access Registers (RO)
2724 * Reset value: 0x00U
2726 * The SACC registers define which logical program flash segments are restricted
2727 * to supervisor only or user and supervisor access. The eight SACC registers
2728 * allow up to 64 restricted segments of equal memory size. Supervisor-only access
2729 * register Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1
2730 * SA[55:48] SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16]
2731 * SACCL2 SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are
2732 * loaded with the logical AND of Program Flash IFR addresses A and B as
2733 * indicated in the following table. Supervisor-only access register Program Flash IFR
2734 * address A Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2
2735 * 0xB1 0xB9 SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD
2736 * SACCL3 0xB4 0xBC Use the Program Once command to program the supervisor-only
2737 * access control fields that are loaded during the reset sequence.
2739 typedef union _hw_ftfa_sacch0
2742 struct _hw_ftfa_sacch0_bitfields
2744 uint8_t SA
: 8; /*!< [7:0] Supervisor-only access control */
2749 * @name Constants and macros for entire FTFA_SACCH0 register
2752 #define HW_FTFA_SACCH0_ADDR(x) ((x) + 0x23U)
2754 #define HW_FTFA_SACCH0(x) (*(__I hw_ftfa_sacch0_t *) HW_FTFA_SACCH0_ADDR(x))
2755 #define HW_FTFA_SACCH0_RD(x) (HW_FTFA_SACCH0(x).U)
2759 * Constants & macros for individual FTFA_SACCH0 bitfields
2763 * @name Register FTFA_SACCH0, field SA[7:0] (RO)
2766 * - 0 - Associated segment is accessible in supervisor mode only
2767 * - 1 - Associated segment is accessible in user or supervisor mode
2770 #define BP_FTFA_SACCH0_SA (0U) /*!< Bit position for FTFA_SACCH0_SA. */
2771 #define BM_FTFA_SACCH0_SA (0xFFU) /*!< Bit mask for FTFA_SACCH0_SA. */
2772 #define BS_FTFA_SACCH0_SA (8U) /*!< Bit field size in bits for FTFA_SACCH0_SA. */
2774 /*! @brief Read current value of the FTFA_SACCH0_SA field. */
2775 #define BR_FTFA_SACCH0_SA(x) (HW_FTFA_SACCH0(x).U)
2778 /*******************************************************************************
2779 * HW_FTFA_SACCL3 - Supervisor-only Access Registers
2780 ******************************************************************************/
2783 * @brief HW_FTFA_SACCL3 - Supervisor-only Access Registers (RO)
2785 * Reset value: 0x00U
2787 * The SACC registers define which logical program flash segments are restricted
2788 * to supervisor only or user and supervisor access. The eight SACC registers
2789 * allow up to 64 restricted segments of equal memory size. Supervisor-only access
2790 * register Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1
2791 * SA[55:48] SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16]
2792 * SACCL2 SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are
2793 * loaded with the logical AND of Program Flash IFR addresses A and B as
2794 * indicated in the following table. Supervisor-only access register Program Flash IFR
2795 * address A Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2
2796 * 0xB1 0xB9 SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD
2797 * SACCL3 0xB4 0xBC Use the Program Once command to program the supervisor-only
2798 * access control fields that are loaded during the reset sequence.
2800 typedef union _hw_ftfa_saccl3
2803 struct _hw_ftfa_saccl3_bitfields
2805 uint8_t SA
: 8; /*!< [7:0] Supervisor-only access control */
2810 * @name Constants and macros for entire FTFA_SACCL3 register
2813 #define HW_FTFA_SACCL3_ADDR(x) ((x) + 0x24U)
2815 #define HW_FTFA_SACCL3(x) (*(__I hw_ftfa_saccl3_t *) HW_FTFA_SACCL3_ADDR(x))
2816 #define HW_FTFA_SACCL3_RD(x) (HW_FTFA_SACCL3(x).U)
2820 * Constants & macros for individual FTFA_SACCL3 bitfields
2824 * @name Register FTFA_SACCL3, field SA[7:0] (RO)
2827 * - 0 - Associated segment is accessible in supervisor mode only
2828 * - 1 - Associated segment is accessible in user or supervisor mode
2831 #define BP_FTFA_SACCL3_SA (0U) /*!< Bit position for FTFA_SACCL3_SA. */
2832 #define BM_FTFA_SACCL3_SA (0xFFU) /*!< Bit mask for FTFA_SACCL3_SA. */
2833 #define BS_FTFA_SACCL3_SA (8U) /*!< Bit field size in bits for FTFA_SACCL3_SA. */
2835 /*! @brief Read current value of the FTFA_SACCL3_SA field. */
2836 #define BR_FTFA_SACCL3_SA(x) (HW_FTFA_SACCL3(x).U)
2839 /*******************************************************************************
2840 * HW_FTFA_SACCL2 - Supervisor-only Access Registers
2841 ******************************************************************************/
2844 * @brief HW_FTFA_SACCL2 - Supervisor-only Access Registers (RO)
2846 * Reset value: 0x00U
2848 * The SACC registers define which logical program flash segments are restricted
2849 * to supervisor only or user and supervisor access. The eight SACC registers
2850 * allow up to 64 restricted segments of equal memory size. Supervisor-only access
2851 * register Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1
2852 * SA[55:48] SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16]
2853 * SACCL2 SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are
2854 * loaded with the logical AND of Program Flash IFR addresses A and B as
2855 * indicated in the following table. Supervisor-only access register Program Flash IFR
2856 * address A Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2
2857 * 0xB1 0xB9 SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD
2858 * SACCL3 0xB4 0xBC Use the Program Once command to program the supervisor-only
2859 * access control fields that are loaded during the reset sequence.
2861 typedef union _hw_ftfa_saccl2
2864 struct _hw_ftfa_saccl2_bitfields
2866 uint8_t SA
: 8; /*!< [7:0] Supervisor-only access control */
2871 * @name Constants and macros for entire FTFA_SACCL2 register
2874 #define HW_FTFA_SACCL2_ADDR(x) ((x) + 0x25U)
2876 #define HW_FTFA_SACCL2(x) (*(__I hw_ftfa_saccl2_t *) HW_FTFA_SACCL2_ADDR(x))
2877 #define HW_FTFA_SACCL2_RD(x) (HW_FTFA_SACCL2(x).U)
2881 * Constants & macros for individual FTFA_SACCL2 bitfields
2885 * @name Register FTFA_SACCL2, field SA[7:0] (RO)
2888 * - 0 - Associated segment is accessible in supervisor mode only
2889 * - 1 - Associated segment is accessible in user or supervisor mode
2892 #define BP_FTFA_SACCL2_SA (0U) /*!< Bit position for FTFA_SACCL2_SA. */
2893 #define BM_FTFA_SACCL2_SA (0xFFU) /*!< Bit mask for FTFA_SACCL2_SA. */
2894 #define BS_FTFA_SACCL2_SA (8U) /*!< Bit field size in bits for FTFA_SACCL2_SA. */
2896 /*! @brief Read current value of the FTFA_SACCL2_SA field. */
2897 #define BR_FTFA_SACCL2_SA(x) (HW_FTFA_SACCL2(x).U)
2900 /*******************************************************************************
2901 * HW_FTFA_SACCL1 - Supervisor-only Access Registers
2902 ******************************************************************************/
2905 * @brief HW_FTFA_SACCL1 - Supervisor-only Access Registers (RO)
2907 * Reset value: 0x00U
2909 * The SACC registers define which logical program flash segments are restricted
2910 * to supervisor only or user and supervisor access. The eight SACC registers
2911 * allow up to 64 restricted segments of equal memory size. Supervisor-only access
2912 * register Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1
2913 * SA[55:48] SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16]
2914 * SACCL2 SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are
2915 * loaded with the logical AND of Program Flash IFR addresses A and B as
2916 * indicated in the following table. Supervisor-only access register Program Flash IFR
2917 * address A Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2
2918 * 0xB1 0xB9 SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD
2919 * SACCL3 0xB4 0xBC Use the Program Once command to program the supervisor-only
2920 * access control fields that are loaded during the reset sequence.
2922 typedef union _hw_ftfa_saccl1
2925 struct _hw_ftfa_saccl1_bitfields
2927 uint8_t SA
: 8; /*!< [7:0] Supervisor-only access control */
2932 * @name Constants and macros for entire FTFA_SACCL1 register
2935 #define HW_FTFA_SACCL1_ADDR(x) ((x) + 0x26U)
2937 #define HW_FTFA_SACCL1(x) (*(__I hw_ftfa_saccl1_t *) HW_FTFA_SACCL1_ADDR(x))
2938 #define HW_FTFA_SACCL1_RD(x) (HW_FTFA_SACCL1(x).U)
2942 * Constants & macros for individual FTFA_SACCL1 bitfields
2946 * @name Register FTFA_SACCL1, field SA[7:0] (RO)
2949 * - 0 - Associated segment is accessible in supervisor mode only
2950 * - 1 - Associated segment is accessible in user or supervisor mode
2953 #define BP_FTFA_SACCL1_SA (0U) /*!< Bit position for FTFA_SACCL1_SA. */
2954 #define BM_FTFA_SACCL1_SA (0xFFU) /*!< Bit mask for FTFA_SACCL1_SA. */
2955 #define BS_FTFA_SACCL1_SA (8U) /*!< Bit field size in bits for FTFA_SACCL1_SA. */
2957 /*! @brief Read current value of the FTFA_SACCL1_SA field. */
2958 #define BR_FTFA_SACCL1_SA(x) (HW_FTFA_SACCL1(x).U)
2961 /*******************************************************************************
2962 * HW_FTFA_SACCL0 - Supervisor-only Access Registers
2963 ******************************************************************************/
2966 * @brief HW_FTFA_SACCL0 - Supervisor-only Access Registers (RO)
2968 * Reset value: 0x00U
2970 * The SACC registers define which logical program flash segments are restricted
2971 * to supervisor only or user and supervisor access. The eight SACC registers
2972 * allow up to 64 restricted segments of equal memory size. Supervisor-only access
2973 * register Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1
2974 * SA[55:48] SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16]
2975 * SACCL2 SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are
2976 * loaded with the logical AND of Program Flash IFR addresses A and B as
2977 * indicated in the following table. Supervisor-only access register Program Flash IFR
2978 * address A Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2
2979 * 0xB1 0xB9 SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD
2980 * SACCL3 0xB4 0xBC Use the Program Once command to program the supervisor-only
2981 * access control fields that are loaded during the reset sequence.
2983 typedef union _hw_ftfa_saccl0
2986 struct _hw_ftfa_saccl0_bitfields
2988 uint8_t SA
: 8; /*!< [7:0] Supervisor-only access control */
2993 * @name Constants and macros for entire FTFA_SACCL0 register
2996 #define HW_FTFA_SACCL0_ADDR(x) ((x) + 0x27U)
2998 #define HW_FTFA_SACCL0(x) (*(__I hw_ftfa_saccl0_t *) HW_FTFA_SACCL0_ADDR(x))
2999 #define HW_FTFA_SACCL0_RD(x) (HW_FTFA_SACCL0(x).U)
3003 * Constants & macros for individual FTFA_SACCL0 bitfields
3007 * @name Register FTFA_SACCL0, field SA[7:0] (RO)
3010 * - 0 - Associated segment is accessible in supervisor mode only
3011 * - 1 - Associated segment is accessible in user or supervisor mode
3014 #define BP_FTFA_SACCL0_SA (0U) /*!< Bit position for FTFA_SACCL0_SA. */
3015 #define BM_FTFA_SACCL0_SA (0xFFU) /*!< Bit mask for FTFA_SACCL0_SA. */
3016 #define BS_FTFA_SACCL0_SA (8U) /*!< Bit field size in bits for FTFA_SACCL0_SA. */
3018 /*! @brief Read current value of the FTFA_SACCL0_SA field. */
3019 #define BR_FTFA_SACCL0_SA(x) (HW_FTFA_SACCL0(x).U)
3022 /*******************************************************************************
3023 * HW_FTFA_FACSS - Flash Access Segment Size Register
3024 ******************************************************************************/
3027 * @brief HW_FTFA_FACSS - Flash Access Segment Size Register (RO)
3029 * Reset value: 0x00U
3031 * The flash access segment size register determines which bits in the address
3032 * are used to index into the SACC and XACC bitmaps to get the appropriate
3033 * permission flags. All bits in the register are read-only. The contents of this
3034 * register are loaded during the reset sequence.
3036 typedef union _hw_ftfa_facss
3039 struct _hw_ftfa_facss_bitfields
3041 uint8_t SGSIZE
: 8; /*!< [7:0] Segment Size */
3046 * @name Constants and macros for entire FTFA_FACSS register
3049 #define HW_FTFA_FACSS_ADDR(x) ((x) + 0x28U)
3051 #define HW_FTFA_FACSS(x) (*(__I hw_ftfa_facss_t *) HW_FTFA_FACSS_ADDR(x))
3052 #define HW_FTFA_FACSS_RD(x) (HW_FTFA_FACSS(x).U)
3056 * Constants & macros for individual FTFA_FACSS bitfields
3060 * @name Register FTFA_FACSS, field SGSIZE[7:0] (RO)
3062 * The segment size is a fixed value based on the available program flash size
3063 * divided by NUMSG. Program Flash Size Segment Size Segment Size Encoding 64
3064 * KBytes 2 KBytes 0x3 128 KBytes 4 KBytes 0x4 160 KBytes 4 KBytes 0x4 256 KBytes 4
3065 * KBytes 0x4 512 KBytes 8 KBytes 0x5
3068 #define BP_FTFA_FACSS_SGSIZE (0U) /*!< Bit position for FTFA_FACSS_SGSIZE. */
3069 #define BM_FTFA_FACSS_SGSIZE (0xFFU) /*!< Bit mask for FTFA_FACSS_SGSIZE. */
3070 #define BS_FTFA_FACSS_SGSIZE (8U) /*!< Bit field size in bits for FTFA_FACSS_SGSIZE. */
3072 /*! @brief Read current value of the FTFA_FACSS_SGSIZE field. */
3073 #define BR_FTFA_FACSS_SGSIZE(x) (HW_FTFA_FACSS(x).U)
3076 /*******************************************************************************
3077 * HW_FTFA_FACSN - Flash Access Segment Number Register
3078 ******************************************************************************/
3081 * @brief HW_FTFA_FACSN - Flash Access Segment Number Register (RO)
3083 * Reset value: 0x00U
3085 * The flash access segment number register provides the number of program flash
3086 * segments that are available for XACC and SACC permissions. All bits in the
3087 * register are read-only. The contents of this register are loaded during the
3090 typedef union _hw_ftfa_facsn
3093 struct _hw_ftfa_facsn_bitfields
3095 uint8_t NUMSG
: 8; /*!< [7:0] Number of Segments Indicator */
3100 * @name Constants and macros for entire FTFA_FACSN register
3103 #define HW_FTFA_FACSN_ADDR(x) ((x) + 0x2BU)
3105 #define HW_FTFA_FACSN(x) (*(__I hw_ftfa_facsn_t *) HW_FTFA_FACSN_ADDR(x))
3106 #define HW_FTFA_FACSN_RD(x) (HW_FTFA_FACSN(x).U)
3110 * Constants & macros for individual FTFA_FACSN bitfields
3114 * @name Register FTFA_FACSN, field NUMSG[7:0] (RO)
3116 * The NUMSG field indicates the number of equal-sized segments in the program
3120 * - 100000 - Program flash memory is divided into 32 segments (64 Kbytes, 128
3122 * - 101000 - Program flash memory is divided into 40 segments (160 Kbytes)
3123 * - 1000000 - Program flash memory is divided into 64 segments (256 Kbytes, 512
3127 #define BP_FTFA_FACSN_NUMSG (0U) /*!< Bit position for FTFA_FACSN_NUMSG. */
3128 #define BM_FTFA_FACSN_NUMSG (0xFFU) /*!< Bit mask for FTFA_FACSN_NUMSG. */
3129 #define BS_FTFA_FACSN_NUMSG (8U) /*!< Bit field size in bits for FTFA_FACSN_NUMSG. */
3131 /*! @brief Read current value of the FTFA_FACSN_NUMSG field. */
3132 #define BR_FTFA_FACSN_NUMSG(x) (HW_FTFA_FACSN(x).U)
3135 /*******************************************************************************
3136 * hw_ftfa_t - module struct
3137 ******************************************************************************/
3139 * @brief All FTFA module registers.
3142 typedef struct _hw_ftfa
3144 __IO hw_ftfa_fstat_t FSTAT
; /*!< [0x0] Flash Status Register */
3145 __IO hw_ftfa_fcnfg_t FCNFG
; /*!< [0x1] Flash Configuration Register */
3146 __I hw_ftfa_fsec_t FSEC
; /*!< [0x2] Flash Security Register */
3147 __I hw_ftfa_fopt_t FOPT
; /*!< [0x3] Flash Option Register */
3148 __IO hw_ftfa_fccob3_t FCCOB3
; /*!< [0x4] Flash Common Command Object Registers */
3149 __IO hw_ftfa_fccob2_t FCCOB2
; /*!< [0x5] Flash Common Command Object Registers */
3150 __IO hw_ftfa_fccob1_t FCCOB1
; /*!< [0x6] Flash Common Command Object Registers */
3151 __IO hw_ftfa_fccob0_t FCCOB0
; /*!< [0x7] Flash Common Command Object Registers */
3152 __IO hw_ftfa_fccob7_t FCCOB7
; /*!< [0x8] Flash Common Command Object Registers */
3153 __IO hw_ftfa_fccob6_t FCCOB6
; /*!< [0x9] Flash Common Command Object Registers */
3154 __IO hw_ftfa_fccob5_t FCCOB5
; /*!< [0xA] Flash Common Command Object Registers */
3155 __IO hw_ftfa_fccob4_t FCCOB4
; /*!< [0xB] Flash Common Command Object Registers */
3156 __IO hw_ftfa_fccobb_t FCCOBB
; /*!< [0xC] Flash Common Command Object Registers */
3157 __IO hw_ftfa_fccoba_t FCCOBA
; /*!< [0xD] Flash Common Command Object Registers */
3158 __IO hw_ftfa_fccob9_t FCCOB9
; /*!< [0xE] Flash Common Command Object Registers */
3159 __IO hw_ftfa_fccob8_t FCCOB8
; /*!< [0xF] Flash Common Command Object Registers */
3160 __IO hw_ftfa_fprot3_t FPROT3
; /*!< [0x10] Program Flash Protection Registers */
3161 __IO hw_ftfa_fprot2_t FPROT2
; /*!< [0x11] Program Flash Protection Registers */
3162 __IO hw_ftfa_fprot1_t FPROT1
; /*!< [0x12] Program Flash Protection Registers */
3163 __IO hw_ftfa_fprot0_t FPROT0
; /*!< [0x13] Program Flash Protection Registers */
3164 uint8_t _reserved0
[4];
3165 __I hw_ftfa_xacch3_t XACCH3
; /*!< [0x18] Execute-only Access Registers */
3166 __I hw_ftfa_xacch2_t XACCH2
; /*!< [0x19] Execute-only Access Registers */
3167 __I hw_ftfa_xacch1_t XACCH1
; /*!< [0x1A] Execute-only Access Registers */
3168 __I hw_ftfa_xacch0_t XACCH0
; /*!< [0x1B] Execute-only Access Registers */
3169 __I hw_ftfa_xaccl3_t XACCL3
; /*!< [0x1C] Execute-only Access Registers */
3170 __I hw_ftfa_xaccl2_t XACCL2
; /*!< [0x1D] Execute-only Access Registers */
3171 __I hw_ftfa_xaccl1_t XACCL1
; /*!< [0x1E] Execute-only Access Registers */
3172 __I hw_ftfa_xaccl0_t XACCL0
; /*!< [0x1F] Execute-only Access Registers */
3173 __I hw_ftfa_sacch3_t SACCH3
; /*!< [0x20] Supervisor-only Access Registers */
3174 __I hw_ftfa_sacch2_t SACCH2
; /*!< [0x21] Supervisor-only Access Registers */
3175 __I hw_ftfa_sacch1_t SACCH1
; /*!< [0x22] Supervisor-only Access Registers */
3176 __I hw_ftfa_sacch0_t SACCH0
; /*!< [0x23] Supervisor-only Access Registers */
3177 __I hw_ftfa_saccl3_t SACCL3
; /*!< [0x24] Supervisor-only Access Registers */
3178 __I hw_ftfa_saccl2_t SACCL2
; /*!< [0x25] Supervisor-only Access Registers */
3179 __I hw_ftfa_saccl1_t SACCL1
; /*!< [0x26] Supervisor-only Access Registers */
3180 __I hw_ftfa_saccl0_t SACCL0
; /*!< [0x27] Supervisor-only Access Registers */
3181 __I hw_ftfa_facss_t FACSS
; /*!< [0x28] Flash Access Segment Size Register */
3182 uint8_t _reserved1
[2];
3183 __I hw_ftfa_facsn_t FACSN
; /*!< [0x2B] Flash Access Segment Number Register */
3187 /*! @brief Macro to access all FTFA registers. */
3188 /*! @param x FTFA module instance base address. */
3189 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
3190 * use the '&' operator, like <code>&HW_FTFA(FTFA_BASE)</code>. */
3191 #define HW_FTFA(x) (*(hw_ftfa_t *)(x))
3193 #endif /* __HW_FTFA_REGISTERS_H__ */