2 ** ###################################################################
3 ** Compilers: Keil ARM C/C++ Compiler
4 ** Freescale C/C++ for Embedded ARM
6 ** IAR ANSI C/C++ Compiler for ARM
8 ** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
9 ** Version: rev. 2.5, 2014-05-06
13 ** Extension to the CMSIS register access layer header.
15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
16 ** All rights reserved.
18 ** Redistribution and use in source and binary forms, with or without modification,
19 ** are permitted provided that the following conditions are met:
21 ** o Redistributions of source code must retain the above copyright notice, this list
22 ** of conditions and the following disclaimer.
24 ** o Redistributions in binary form must reproduce the above copyright notice, this
25 ** list of conditions and the following disclaimer in the documentation and/or
26 ** other materials provided with the distribution.
28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
29 ** contributors may be used to endorse or promote products derived from this
30 ** software without specific prior written permission.
32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 ** http: www.freescale.com
44 ** mail: support@freescale.com
47 ** - rev. 1.0 (2013-07-23)
49 ** - rev. 1.1 (2013-09-17)
50 ** RM rev. 0.4 update.
51 ** - rev. 2.0 (2013-10-29)
52 ** Register accessor macros added to the memory map.
53 ** Symbols for Processor Expert memory map compatibility added to the memory map.
54 ** Startup file for gcc has been updated according to CMSIS 3.2.
55 ** System initialization updated.
56 ** - rev. 2.1 (2013-10-30)
57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
58 ** - rev. 2.2 (2013-12-20)
59 ** Update according to reference manual rev. 0.6,
60 ** - rev. 2.3 (2014-01-13)
61 ** Update according to reference manual rev. 0.61,
62 ** - rev. 2.4 (2014-02-10)
63 ** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
64 ** - rev. 2.5 (2014-05-06)
65 ** Update according to reference manual rev. 1.0,
66 ** Update of system and startup files.
67 ** Module access macro module_BASES replaced by module_BASE_PTRS.
69 ** ###################################################################
73 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
75 * This file was generated automatically and any changes may be lost.
77 #ifndef __HW_FTM_REGISTERS_H__
78 #define __HW_FTM_REGISTERS_H__
80 #include "MK22F51212.h"
81 #include "fsl_bitaccess.h"
88 * Registers defined in this header file:
89 * - HW_FTM_SC - Status And Control
90 * - HW_FTM_CNT - Counter
91 * - HW_FTM_MOD - Modulo
92 * - HW_FTM_CnSC - Channel (n) Status And Control
93 * - HW_FTM_CnV - Channel (n) Value
94 * - HW_FTM_CNTIN - Counter Initial Value
95 * - HW_FTM_STATUS - Capture And Compare Status
96 * - HW_FTM_MODE - Features Mode Selection
97 * - HW_FTM_SYNC - Synchronization
98 * - HW_FTM_OUTINIT - Initial State For Channels Output
99 * - HW_FTM_OUTMASK - Output Mask
100 * - HW_FTM_COMBINE - Function For Linked Channels
101 * - HW_FTM_DEADTIME - Deadtime Insertion Control
102 * - HW_FTM_EXTTRIG - FTM External Trigger
103 * - HW_FTM_POL - Channels Polarity
104 * - HW_FTM_FMS - Fault Mode Status
105 * - HW_FTM_FILTER - Input Capture Filter Control
106 * - HW_FTM_FLTCTRL - Fault Control
107 * - HW_FTM_QDCTRL - Quadrature Decoder Control And Status
108 * - HW_FTM_CONF - Configuration
109 * - HW_FTM_FLTPOL - FTM Fault Input Polarity
110 * - HW_FTM_SYNCONF - Synchronization Configuration
111 * - HW_FTM_INVCTRL - FTM Inverting Control
112 * - HW_FTM_SWOCTRL - FTM Software Output Control
113 * - HW_FTM_PWMLOAD - FTM PWM Load
115 * - hw_ftm_t - Struct containing all module registers.
118 #define HW_FTM_INSTANCE_COUNT (4U) /*!< Number of instances of the FTM module. */
119 #define HW_FTM0 (0U) /*!< Instance number for FTM0. */
120 #define HW_FTM1 (1U) /*!< Instance number for FTM1. */
121 #define HW_FTM2 (2U) /*!< Instance number for FTM2. */
122 #define HW_FTM3 (3U) /*!< Instance number for FTM3. */
124 /*******************************************************************************
125 * HW_FTM_SC - Status And Control
126 ******************************************************************************/
129 * @brief HW_FTM_SC - Status And Control (RW)
131 * Reset value: 0x00000000U
133 * SC contains the overflow status flag and control bits used to configure the
134 * interrupt enable, FTM configuration, clock source, and prescaler factor. These
135 * controls relate to all channels within this module.
137 typedef union _hw_ftm_sc
140 struct _hw_ftm_sc_bitfields
142 uint32_t PS
: 3; /*!< [2:0] Prescale Factor Selection */
143 uint32_t CLKS
: 2; /*!< [4:3] Clock Source Selection */
144 uint32_t CPWMS
: 1; /*!< [5] Center-Aligned PWM Select */
145 uint32_t TOIE
: 1; /*!< [6] Timer Overflow Interrupt Enable */
146 uint32_t TOF
: 1; /*!< [7] Timer Overflow Flag */
147 uint32_t RESERVED0
: 24; /*!< [31:8] */
152 * @name Constants and macros for entire FTM_SC register
155 #define HW_FTM_SC_ADDR(x) ((x) + 0x0U)
157 #define HW_FTM_SC(x) (*(__IO hw_ftm_sc_t *) HW_FTM_SC_ADDR(x))
158 #define HW_FTM_SC_RD(x) (HW_FTM_SC(x).U)
159 #define HW_FTM_SC_WR(x, v) (HW_FTM_SC(x).U = (v))
160 #define HW_FTM_SC_SET(x, v) (HW_FTM_SC_WR(x, HW_FTM_SC_RD(x) | (v)))
161 #define HW_FTM_SC_CLR(x, v) (HW_FTM_SC_WR(x, HW_FTM_SC_RD(x) & ~(v)))
162 #define HW_FTM_SC_TOG(x, v) (HW_FTM_SC_WR(x, HW_FTM_SC_RD(x) ^ (v)))
166 * Constants & macros for individual FTM_SC bitfields
170 * @name Register FTM_SC, field PS[2:0] (RW)
172 * Selects one of 8 division factors for the clock source selected by CLKS. The
173 * new prescaler factor affects the clock source on the next system clock cycle
174 * after the new value is updated into the register bits. This field is write
175 * protected. It can be written only when MODE[WPDIS] = 1.
178 * - 000 - Divide by 1
179 * - 001 - Divide by 2
180 * - 010 - Divide by 4
181 * - 011 - Divide by 8
182 * - 100 - Divide by 16
183 * - 101 - Divide by 32
184 * - 110 - Divide by 64
185 * - 111 - Divide by 128
188 #define BP_FTM_SC_PS (0U) /*!< Bit position for FTM_SC_PS. */
189 #define BM_FTM_SC_PS (0x00000007U) /*!< Bit mask for FTM_SC_PS. */
190 #define BS_FTM_SC_PS (3U) /*!< Bit field size in bits for FTM_SC_PS. */
192 /*! @brief Read current value of the FTM_SC_PS field. */
193 #define BR_FTM_SC_PS(x) (HW_FTM_SC(x).B.PS)
195 /*! @brief Format value for bitfield FTM_SC_PS. */
196 #define BF_FTM_SC_PS(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SC_PS) & BM_FTM_SC_PS)
198 /*! @brief Set the PS field to a new value. */
199 #define BW_FTM_SC_PS(x, v) (HW_FTM_SC_WR(x, (HW_FTM_SC_RD(x) & ~BM_FTM_SC_PS) | BF_FTM_SC_PS(v)))
203 * @name Register FTM_SC, field CLKS[4:3] (RW)
205 * Selects one of the three FTM counter clock sources. This field is write
206 * protected. It can be written only when MODE[WPDIS] = 1.
209 * - 00 - No clock selected. This in effect disables the FTM counter.
210 * - 01 - System clock
211 * - 10 - Fixed frequency clock
212 * - 11 - External clock
215 #define BP_FTM_SC_CLKS (3U) /*!< Bit position for FTM_SC_CLKS. */
216 #define BM_FTM_SC_CLKS (0x00000018U) /*!< Bit mask for FTM_SC_CLKS. */
217 #define BS_FTM_SC_CLKS (2U) /*!< Bit field size in bits for FTM_SC_CLKS. */
219 /*! @brief Read current value of the FTM_SC_CLKS field. */
220 #define BR_FTM_SC_CLKS(x) (HW_FTM_SC(x).B.CLKS)
222 /*! @brief Format value for bitfield FTM_SC_CLKS. */
223 #define BF_FTM_SC_CLKS(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SC_CLKS) & BM_FTM_SC_CLKS)
225 /*! @brief Set the CLKS field to a new value. */
226 #define BW_FTM_SC_CLKS(x, v) (HW_FTM_SC_WR(x, (HW_FTM_SC_RD(x) & ~BM_FTM_SC_CLKS) | BF_FTM_SC_CLKS(v)))
230 * @name Register FTM_SC, field CPWMS[5] (RW)
232 * Selects CPWM mode. This mode configures the FTM to operate in Up-Down
233 * Counting mode. This field is write protected. It can be written only when MODE[WPDIS]
237 * - 0 - FTM counter operates in Up Counting mode.
238 * - 1 - FTM counter operates in Up-Down Counting mode.
241 #define BP_FTM_SC_CPWMS (5U) /*!< Bit position for FTM_SC_CPWMS. */
242 #define BM_FTM_SC_CPWMS (0x00000020U) /*!< Bit mask for FTM_SC_CPWMS. */
243 #define BS_FTM_SC_CPWMS (1U) /*!< Bit field size in bits for FTM_SC_CPWMS. */
245 /*! @brief Read current value of the FTM_SC_CPWMS field. */
246 #define BR_FTM_SC_CPWMS(x) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_CPWMS))
248 /*! @brief Format value for bitfield FTM_SC_CPWMS. */
249 #define BF_FTM_SC_CPWMS(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SC_CPWMS) & BM_FTM_SC_CPWMS)
251 /*! @brief Set the CPWMS field to a new value. */
252 #define BW_FTM_SC_CPWMS(x, v) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_CPWMS) = (v))
256 * @name Register FTM_SC, field TOIE[6] (RW)
258 * Enables FTM overflow interrupts.
261 * - 0 - Disable TOF interrupts. Use software polling.
262 * - 1 - Enable TOF interrupts. An interrupt is generated when TOF equals one.
265 #define BP_FTM_SC_TOIE (6U) /*!< Bit position for FTM_SC_TOIE. */
266 #define BM_FTM_SC_TOIE (0x00000040U) /*!< Bit mask for FTM_SC_TOIE. */
267 #define BS_FTM_SC_TOIE (1U) /*!< Bit field size in bits for FTM_SC_TOIE. */
269 /*! @brief Read current value of the FTM_SC_TOIE field. */
270 #define BR_FTM_SC_TOIE(x) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_TOIE))
272 /*! @brief Format value for bitfield FTM_SC_TOIE. */
273 #define BF_FTM_SC_TOIE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SC_TOIE) & BM_FTM_SC_TOIE)
275 /*! @brief Set the TOIE field to a new value. */
276 #define BW_FTM_SC_TOIE(x, v) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_TOIE) = (v))
280 * @name Register FTM_SC, field TOF[7] (ROWZ)
282 * Set by hardware when the FTM counter passes the value in the MOD register.
283 * The TOF bit is cleared by reading the SC register while TOF is set and then
284 * writing a 0 to TOF bit. Writing a 1 to TOF has no effect. If another FTM overflow
285 * occurs between the read and write operations, the write operation has no
286 * effect; therefore, TOF remains set indicating an overflow has occurred. In this
287 * case, a TOF interrupt request is not lost due to the clearing sequence for a
291 * - 0 - FTM counter has not overflowed.
292 * - 1 - FTM counter has overflowed.
295 #define BP_FTM_SC_TOF (7U) /*!< Bit position for FTM_SC_TOF. */
296 #define BM_FTM_SC_TOF (0x00000080U) /*!< Bit mask for FTM_SC_TOF. */
297 #define BS_FTM_SC_TOF (1U) /*!< Bit field size in bits for FTM_SC_TOF. */
299 /*! @brief Read current value of the FTM_SC_TOF field. */
300 #define BR_FTM_SC_TOF(x) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_TOF))
302 /*! @brief Format value for bitfield FTM_SC_TOF. */
303 #define BF_FTM_SC_TOF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SC_TOF) & BM_FTM_SC_TOF)
305 /*! @brief Set the TOF field to a new value. */
306 #define BW_FTM_SC_TOF(x, v) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_TOF) = (v))
309 /*******************************************************************************
310 * HW_FTM_CNT - Counter
311 ******************************************************************************/
314 * @brief HW_FTM_CNT - Counter (RW)
316 * Reset value: 0x00000000U
318 * The CNT register contains the FTM counter value. Reset clears the CNT
319 * register. Writing any value to COUNT updates the counter with its initial value,
320 * CNTIN. When BDM is active, the FTM counter is frozen. This is the value that you
323 typedef union _hw_ftm_cnt
326 struct _hw_ftm_cnt_bitfields
328 uint32_t COUNT
: 16; /*!< [15:0] Counter Value */
329 uint32_t RESERVED0
: 16; /*!< [31:16] */
334 * @name Constants and macros for entire FTM_CNT register
337 #define HW_FTM_CNT_ADDR(x) ((x) + 0x4U)
339 #define HW_FTM_CNT(x) (*(__IO hw_ftm_cnt_t *) HW_FTM_CNT_ADDR(x))
340 #define HW_FTM_CNT_RD(x) (HW_FTM_CNT(x).U)
341 #define HW_FTM_CNT_WR(x, v) (HW_FTM_CNT(x).U = (v))
342 #define HW_FTM_CNT_SET(x, v) (HW_FTM_CNT_WR(x, HW_FTM_CNT_RD(x) | (v)))
343 #define HW_FTM_CNT_CLR(x, v) (HW_FTM_CNT_WR(x, HW_FTM_CNT_RD(x) & ~(v)))
344 #define HW_FTM_CNT_TOG(x, v) (HW_FTM_CNT_WR(x, HW_FTM_CNT_RD(x) ^ (v)))
348 * Constants & macros for individual FTM_CNT bitfields
352 * @name Register FTM_CNT, field COUNT[15:0] (RW)
355 #define BP_FTM_CNT_COUNT (0U) /*!< Bit position for FTM_CNT_COUNT. */
356 #define BM_FTM_CNT_COUNT (0x0000FFFFU) /*!< Bit mask for FTM_CNT_COUNT. */
357 #define BS_FTM_CNT_COUNT (16U) /*!< Bit field size in bits for FTM_CNT_COUNT. */
359 /*! @brief Read current value of the FTM_CNT_COUNT field. */
360 #define BR_FTM_CNT_COUNT(x) (HW_FTM_CNT(x).B.COUNT)
362 /*! @brief Format value for bitfield FTM_CNT_COUNT. */
363 #define BF_FTM_CNT_COUNT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CNT_COUNT) & BM_FTM_CNT_COUNT)
365 /*! @brief Set the COUNT field to a new value. */
366 #define BW_FTM_CNT_COUNT(x, v) (HW_FTM_CNT_WR(x, (HW_FTM_CNT_RD(x) & ~BM_FTM_CNT_COUNT) | BF_FTM_CNT_COUNT(v)))
369 /*******************************************************************************
370 * HW_FTM_MOD - Modulo
371 ******************************************************************************/
374 * @brief HW_FTM_MOD - Modulo (RW)
376 * Reset value: 0x00000000U
378 * The Modulo register contains the modulo value for the FTM counter. After the
379 * FTM counter reaches the modulo value, the overflow flag (TOF) becomes set at
380 * the next clock, and the next value of FTM counter depends on the selected
381 * counting method; see Counter. Writing to the MOD register latches the value into a
382 * buffer. The MOD register is updated with the value of its write buffer
383 * according to Registers updated from write buffers. If FTMEN = 0, this write coherency
384 * mechanism may be manually reset by writing to the SC register whether BDM is
385 * active or not. Initialize the FTM counter, by writing to CNT, before writing
386 * to the MOD register to avoid confusion about when the first counter overflow
389 typedef union _hw_ftm_mod
392 struct _hw_ftm_mod_bitfields
394 uint32_t MOD
: 16; /*!< [15:0] */
395 uint32_t RESERVED0
: 16; /*!< [31:16] */
400 * @name Constants and macros for entire FTM_MOD register
403 #define HW_FTM_MOD_ADDR(x) ((x) + 0x8U)
405 #define HW_FTM_MOD(x) (*(__IO hw_ftm_mod_t *) HW_FTM_MOD_ADDR(x))
406 #define HW_FTM_MOD_RD(x) (HW_FTM_MOD(x).U)
407 #define HW_FTM_MOD_WR(x, v) (HW_FTM_MOD(x).U = (v))
408 #define HW_FTM_MOD_SET(x, v) (HW_FTM_MOD_WR(x, HW_FTM_MOD_RD(x) | (v)))
409 #define HW_FTM_MOD_CLR(x, v) (HW_FTM_MOD_WR(x, HW_FTM_MOD_RD(x) & ~(v)))
410 #define HW_FTM_MOD_TOG(x, v) (HW_FTM_MOD_WR(x, HW_FTM_MOD_RD(x) ^ (v)))
414 * Constants & macros for individual FTM_MOD bitfields
418 * @name Register FTM_MOD, field MOD[15:0] (RW)
423 #define BP_FTM_MOD_MOD (0U) /*!< Bit position for FTM_MOD_MOD. */
424 #define BM_FTM_MOD_MOD (0x0000FFFFU) /*!< Bit mask for FTM_MOD_MOD. */
425 #define BS_FTM_MOD_MOD (16U) /*!< Bit field size in bits for FTM_MOD_MOD. */
427 /*! @brief Read current value of the FTM_MOD_MOD field. */
428 #define BR_FTM_MOD_MOD(x) (HW_FTM_MOD(x).B.MOD)
430 /*! @brief Format value for bitfield FTM_MOD_MOD. */
431 #define BF_FTM_MOD_MOD(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MOD_MOD) & BM_FTM_MOD_MOD)
433 /*! @brief Set the MOD field to a new value. */
434 #define BW_FTM_MOD_MOD(x, v) (HW_FTM_MOD_WR(x, (HW_FTM_MOD_RD(x) & ~BM_FTM_MOD_MOD) | BF_FTM_MOD_MOD(v)))
437 /*******************************************************************************
438 * HW_FTM_CnSC - Channel (n) Status And Control
439 ******************************************************************************/
442 * @brief HW_FTM_CnSC - Channel (n) Status And Control (RW)
444 * Reset value: 0x00000000U
446 * CnSC contains the channel-interrupt-status flag and control bits used to
447 * configure the interrupt enable, channel configuration, and pin function. Mode,
448 * edge, and level selection DECAPEN COMBINE CPWMS MSnB:MSnA ELSnB:ELSnA Mode
449 * Configuration X X X XX 0 Pin not used for FTM-revert the channel pin to general
450 * purpose I/O or other peripheral control 0 0 0 0 1 Input Capture Capture on Rising
451 * Edge Only 10 Capture on Falling Edge Only 11 Capture on Rising or Falling Edge
452 * 1 1 Output Compare Toggle Output on match 10 Clear Output on match 11 Set
453 * Output on match 1X 10 Edge-Aligned PWM High-true pulses (clear Output on match)
454 * X1 Low-true pulses (set Output on match) 1 XX 10 Center-Aligned PWM High-true
455 * pulses (clear Output on match-up) X1 Low-true pulses (set Output on match-up) 1
456 * 0 XX 10 Combine PWM High-true pulses (set on channel (n) match, and clear on
457 * channel (n+1) match) X1 Low-true pulses (clear on channel (n) match, and set
458 * on channel (n+1) match) 1 0 0 X0 See the following table (#ModeSel2Table). Dual
459 * Edge Capture One-Shot Capture mode X1 Continuous Capture mode Dual Edge
460 * Capture mode - edge polarity selection ELSnB ELSnA Channel Port Enable Detected
461 * Edges 0 0 Disabled No edge 0 1 Enabled Rising edge 1 0 Enabled Falling edge 1 1
462 * Enabled Rising and falling edges
464 typedef union _hw_ftm_cnsc
467 struct _hw_ftm_cnsc_bitfields
469 uint32_t DMA
: 1; /*!< [0] DMA Enable */
470 uint32_t ICRST
: 1; /*!< [1] FTM counter reset by the selected input
472 uint32_t ELSA
: 1; /*!< [2] Edge or Level Select */
473 uint32_t ELSB
: 1; /*!< [3] Edge or Level Select */
474 uint32_t MSA
: 1; /*!< [4] Channel Mode Select */
475 uint32_t MSB
: 1; /*!< [5] Channel Mode Select */
476 uint32_t CHIE
: 1; /*!< [6] Channel Interrupt Enable */
477 uint32_t CHF
: 1; /*!< [7] Channel Flag */
478 uint32_t RESERVED0
: 24; /*!< [31:8] */
483 * @name Constants and macros for entire FTM_CnSC register
486 #define HW_FTM_CnSC_COUNT (8U)
488 #define HW_FTM_CnSC_ADDR(x, n) ((x) + 0xCU + (0x8U * (n)))
490 #define HW_FTM_CnSC(x, n) (*(__IO hw_ftm_cnsc_t *) HW_FTM_CnSC_ADDR(x, n))
491 #define HW_FTM_CnSC_RD(x, n) (HW_FTM_CnSC(x, n).U)
492 #define HW_FTM_CnSC_WR(x, n, v) (HW_FTM_CnSC(x, n).U = (v))
493 #define HW_FTM_CnSC_SET(x, n, v) (HW_FTM_CnSC_WR(x, n, HW_FTM_CnSC_RD(x, n) | (v)))
494 #define HW_FTM_CnSC_CLR(x, n, v) (HW_FTM_CnSC_WR(x, n, HW_FTM_CnSC_RD(x, n) & ~(v)))
495 #define HW_FTM_CnSC_TOG(x, n, v) (HW_FTM_CnSC_WR(x, n, HW_FTM_CnSC_RD(x, n) ^ (v)))
499 * Constants & macros for individual FTM_CnSC bitfields
503 * @name Register FTM_CnSC, field DMA[0] (RW)
505 * Enables DMA transfers for the channel.
508 * - 0 - Disable DMA transfers.
509 * - 1 - Enable DMA transfers.
512 #define BP_FTM_CnSC_DMA (0U) /*!< Bit position for FTM_CnSC_DMA. */
513 #define BM_FTM_CnSC_DMA (0x00000001U) /*!< Bit mask for FTM_CnSC_DMA. */
514 #define BS_FTM_CnSC_DMA (1U) /*!< Bit field size in bits for FTM_CnSC_DMA. */
516 /*! @brief Read current value of the FTM_CnSC_DMA field. */
517 #define BR_FTM_CnSC_DMA(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_DMA))
519 /*! @brief Format value for bitfield FTM_CnSC_DMA. */
520 #define BF_FTM_CnSC_DMA(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_DMA) & BM_FTM_CnSC_DMA)
522 /*! @brief Set the DMA field to a new value. */
523 #define BW_FTM_CnSC_DMA(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_DMA) = (v))
527 * @name Register FTM_CnSC, field ICRST[1] (RW)
529 * FTM counter reset is driven by the selected event of the channel (n) in the
530 * Input Capture mode. This field is write protected. It can be written only when
534 * - 0 - FTM counter is not reset when the selected channel (n) input event is
536 * - 1 - FTM counter is reset when the selected channel (n) input event is
540 #define BP_FTM_CnSC_ICRST (1U) /*!< Bit position for FTM_CnSC_ICRST. */
541 #define BM_FTM_CnSC_ICRST (0x00000002U) /*!< Bit mask for FTM_CnSC_ICRST. */
542 #define BS_FTM_CnSC_ICRST (1U) /*!< Bit field size in bits for FTM_CnSC_ICRST. */
544 /*! @brief Read current value of the FTM_CnSC_ICRST field. */
545 #define BR_FTM_CnSC_ICRST(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ICRST))
547 /*! @brief Format value for bitfield FTM_CnSC_ICRST. */
548 #define BF_FTM_CnSC_ICRST(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_ICRST) & BM_FTM_CnSC_ICRST)
550 /*! @brief Set the ICRST field to a new value. */
551 #define BW_FTM_CnSC_ICRST(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ICRST) = (v))
555 * @name Register FTM_CnSC, field ELSA[2] (RW)
557 * The functionality of ELSB and ELSA depends on the channel mode. See
558 * #ModeSel1Table. This field is write protected. It can be written only when MODE[WPDIS]
562 #define BP_FTM_CnSC_ELSA (2U) /*!< Bit position for FTM_CnSC_ELSA. */
563 #define BM_FTM_CnSC_ELSA (0x00000004U) /*!< Bit mask for FTM_CnSC_ELSA. */
564 #define BS_FTM_CnSC_ELSA (1U) /*!< Bit field size in bits for FTM_CnSC_ELSA. */
566 /*! @brief Read current value of the FTM_CnSC_ELSA field. */
567 #define BR_FTM_CnSC_ELSA(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSA))
569 /*! @brief Format value for bitfield FTM_CnSC_ELSA. */
570 #define BF_FTM_CnSC_ELSA(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_ELSA) & BM_FTM_CnSC_ELSA)
572 /*! @brief Set the ELSA field to a new value. */
573 #define BW_FTM_CnSC_ELSA(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSA) = (v))
577 * @name Register FTM_CnSC, field ELSB[3] (RW)
579 * The functionality of ELSB and ELSA depends on the channel mode. See
580 * #ModeSel1Table. This field is write protected. It can be written only when MODE[WPDIS]
584 #define BP_FTM_CnSC_ELSB (3U) /*!< Bit position for FTM_CnSC_ELSB. */
585 #define BM_FTM_CnSC_ELSB (0x00000008U) /*!< Bit mask for FTM_CnSC_ELSB. */
586 #define BS_FTM_CnSC_ELSB (1U) /*!< Bit field size in bits for FTM_CnSC_ELSB. */
588 /*! @brief Read current value of the FTM_CnSC_ELSB field. */
589 #define BR_FTM_CnSC_ELSB(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSB))
591 /*! @brief Format value for bitfield FTM_CnSC_ELSB. */
592 #define BF_FTM_CnSC_ELSB(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_ELSB) & BM_FTM_CnSC_ELSB)
594 /*! @brief Set the ELSB field to a new value. */
595 #define BW_FTM_CnSC_ELSB(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSB) = (v))
599 * @name Register FTM_CnSC, field MSA[4] (RW)
601 * Used for further selections in the channel logic. Its functionality is
602 * dependent on the channel mode. See #ModeSel1Table. This field is write protected. It
603 * can be written only when MODE[WPDIS] = 1.
606 #define BP_FTM_CnSC_MSA (4U) /*!< Bit position for FTM_CnSC_MSA. */
607 #define BM_FTM_CnSC_MSA (0x00000010U) /*!< Bit mask for FTM_CnSC_MSA. */
608 #define BS_FTM_CnSC_MSA (1U) /*!< Bit field size in bits for FTM_CnSC_MSA. */
610 /*! @brief Read current value of the FTM_CnSC_MSA field. */
611 #define BR_FTM_CnSC_MSA(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSA))
613 /*! @brief Format value for bitfield FTM_CnSC_MSA. */
614 #define BF_FTM_CnSC_MSA(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_MSA) & BM_FTM_CnSC_MSA)
616 /*! @brief Set the MSA field to a new value. */
617 #define BW_FTM_CnSC_MSA(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSA) = (v))
621 * @name Register FTM_CnSC, field MSB[5] (RW)
623 * Used for further selections in the channel logic. Its functionality is
624 * dependent on the channel mode. See #ModeSel1Table. This field is write protected. It
625 * can be written only when MODE[WPDIS] = 1.
628 #define BP_FTM_CnSC_MSB (5U) /*!< Bit position for FTM_CnSC_MSB. */
629 #define BM_FTM_CnSC_MSB (0x00000020U) /*!< Bit mask for FTM_CnSC_MSB. */
630 #define BS_FTM_CnSC_MSB (1U) /*!< Bit field size in bits for FTM_CnSC_MSB. */
632 /*! @brief Read current value of the FTM_CnSC_MSB field. */
633 #define BR_FTM_CnSC_MSB(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSB))
635 /*! @brief Format value for bitfield FTM_CnSC_MSB. */
636 #define BF_FTM_CnSC_MSB(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_MSB) & BM_FTM_CnSC_MSB)
638 /*! @brief Set the MSB field to a new value. */
639 #define BW_FTM_CnSC_MSB(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSB) = (v))
643 * @name Register FTM_CnSC, field CHIE[6] (RW)
645 * Enables channel interrupts.
648 * - 0 - Disable channel interrupts. Use software polling.
649 * - 1 - Enable channel interrupts.
652 #define BP_FTM_CnSC_CHIE (6U) /*!< Bit position for FTM_CnSC_CHIE. */
653 #define BM_FTM_CnSC_CHIE (0x00000040U) /*!< Bit mask for FTM_CnSC_CHIE. */
654 #define BS_FTM_CnSC_CHIE (1U) /*!< Bit field size in bits for FTM_CnSC_CHIE. */
656 /*! @brief Read current value of the FTM_CnSC_CHIE field. */
657 #define BR_FTM_CnSC_CHIE(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_CHIE))
659 /*! @brief Format value for bitfield FTM_CnSC_CHIE. */
660 #define BF_FTM_CnSC_CHIE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_CHIE) & BM_FTM_CnSC_CHIE)
662 /*! @brief Set the CHIE field to a new value. */
663 #define BW_FTM_CnSC_CHIE(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_CHIE) = (v))
667 * @name Register FTM_CnSC, field CHF[7] (ROWZ)
669 * Set by hardware when an event occurs on the channel. CHF is cleared by
670 * reading the CSC register while CHnF is set and then writing a 0 to the CHF bit.
671 * Writing a 1 to CHF has no effect. If another event occurs between the read and
672 * write operations, the write operation has no effect; therefore, CHF remains set
673 * indicating an event has occurred. In this case a CHF interrupt request is not
674 * lost due to the clearing sequence for a previous CHF.
677 * - 0 - No channel event has occurred.
678 * - 1 - A channel event has occurred.
681 #define BP_FTM_CnSC_CHF (7U) /*!< Bit position for FTM_CnSC_CHF. */
682 #define BM_FTM_CnSC_CHF (0x00000080U) /*!< Bit mask for FTM_CnSC_CHF. */
683 #define BS_FTM_CnSC_CHF (1U) /*!< Bit field size in bits for FTM_CnSC_CHF. */
685 /*! @brief Read current value of the FTM_CnSC_CHF field. */
686 #define BR_FTM_CnSC_CHF(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_CHF))
688 /*! @brief Format value for bitfield FTM_CnSC_CHF. */
689 #define BF_FTM_CnSC_CHF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_CHF) & BM_FTM_CnSC_CHF)
691 /*! @brief Set the CHF field to a new value. */
692 #define BW_FTM_CnSC_CHF(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_CHF) = (v))
694 /*******************************************************************************
695 * HW_FTM_CnV - Channel (n) Value
696 ******************************************************************************/
699 * @brief HW_FTM_CnV - Channel (n) Value (RW)
701 * Reset value: 0x00000000U
703 * These registers contain the captured FTM counter value for the input modes or
704 * the match value for the output modes. In Input Capture, Capture Test, and
705 * Dual Edge Capture modes, any write to a CnV register is ignored. In output modes,
706 * writing to a CnV register latches the value into a buffer. A CnV register is
707 * updated with the value of its write buffer according to Registers updated from
708 * write buffers. If FTMEN = 0, this write coherency mechanism may be manually
709 * reset by writing to the CnSC register whether BDM mode is active or not.
711 typedef union _hw_ftm_cnv
714 struct _hw_ftm_cnv_bitfields
716 uint32_t VAL
: 16; /*!< [15:0] Channel Value */
717 uint32_t RESERVED0
: 16; /*!< [31:16] */
722 * @name Constants and macros for entire FTM_CnV register
725 #define HW_FTM_CnV_COUNT (8U)
727 #define HW_FTM_CnV_ADDR(x, n) ((x) + 0x10U + (0x8U * (n)))
729 #define HW_FTM_CnV(x, n) (*(__IO hw_ftm_cnv_t *) HW_FTM_CnV_ADDR(x, n))
730 #define HW_FTM_CnV_RD(x, n) (HW_FTM_CnV(x, n).U)
731 #define HW_FTM_CnV_WR(x, n, v) (HW_FTM_CnV(x, n).U = (v))
732 #define HW_FTM_CnV_SET(x, n, v) (HW_FTM_CnV_WR(x, n, HW_FTM_CnV_RD(x, n) | (v)))
733 #define HW_FTM_CnV_CLR(x, n, v) (HW_FTM_CnV_WR(x, n, HW_FTM_CnV_RD(x, n) & ~(v)))
734 #define HW_FTM_CnV_TOG(x, n, v) (HW_FTM_CnV_WR(x, n, HW_FTM_CnV_RD(x, n) ^ (v)))
738 * Constants & macros for individual FTM_CnV bitfields
742 * @name Register FTM_CnV, field VAL[15:0] (RW)
744 * Captured FTM counter value of the input modes or the match value for the
748 #define BP_FTM_CnV_VAL (0U) /*!< Bit position for FTM_CnV_VAL. */
749 #define BM_FTM_CnV_VAL (0x0000FFFFU) /*!< Bit mask for FTM_CnV_VAL. */
750 #define BS_FTM_CnV_VAL (16U) /*!< Bit field size in bits for FTM_CnV_VAL. */
752 /*! @brief Read current value of the FTM_CnV_VAL field. */
753 #define BR_FTM_CnV_VAL(x, n) (HW_FTM_CnV(x, n).B.VAL)
755 /*! @brief Format value for bitfield FTM_CnV_VAL. */
756 #define BF_FTM_CnV_VAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnV_VAL) & BM_FTM_CnV_VAL)
758 /*! @brief Set the VAL field to a new value. */
759 #define BW_FTM_CnV_VAL(x, n, v) (HW_FTM_CnV_WR(x, n, (HW_FTM_CnV_RD(x, n) & ~BM_FTM_CnV_VAL) | BF_FTM_CnV_VAL(v)))
762 /*******************************************************************************
763 * HW_FTM_CNTIN - Counter Initial Value
764 ******************************************************************************/
767 * @brief HW_FTM_CNTIN - Counter Initial Value (RW)
769 * Reset value: 0x00000000U
771 * The Counter Initial Value register contains the initial value for the FTM
772 * counter. Writing to the CNTIN register latches the value into a buffer. The CNTIN
773 * register is updated with the value of its write buffer according to Registers
774 * updated from write buffers. When the FTM clock is initially selected, by
775 * writing a non-zero value to the CLKS bits, the FTM counter starts with the value
776 * 0x0000. To avoid this behavior, before the first write to select the FTM clock,
777 * write the new value to the the CNTIN register and then initialize the FTM
778 * counter by writing any value to the CNT register.
780 typedef union _hw_ftm_cntin
783 struct _hw_ftm_cntin_bitfields
785 uint32_t INIT
: 16; /*!< [15:0] */
786 uint32_t RESERVED0
: 16; /*!< [31:16] */
791 * @name Constants and macros for entire FTM_CNTIN register
794 #define HW_FTM_CNTIN_ADDR(x) ((x) + 0x4CU)
796 #define HW_FTM_CNTIN(x) (*(__IO hw_ftm_cntin_t *) HW_FTM_CNTIN_ADDR(x))
797 #define HW_FTM_CNTIN_RD(x) (HW_FTM_CNTIN(x).U)
798 #define HW_FTM_CNTIN_WR(x, v) (HW_FTM_CNTIN(x).U = (v))
799 #define HW_FTM_CNTIN_SET(x, v) (HW_FTM_CNTIN_WR(x, HW_FTM_CNTIN_RD(x) | (v)))
800 #define HW_FTM_CNTIN_CLR(x, v) (HW_FTM_CNTIN_WR(x, HW_FTM_CNTIN_RD(x) & ~(v)))
801 #define HW_FTM_CNTIN_TOG(x, v) (HW_FTM_CNTIN_WR(x, HW_FTM_CNTIN_RD(x) ^ (v)))
805 * Constants & macros for individual FTM_CNTIN bitfields
809 * @name Register FTM_CNTIN, field INIT[15:0] (RW)
811 * Initial Value Of The FTM Counter
814 #define BP_FTM_CNTIN_INIT (0U) /*!< Bit position for FTM_CNTIN_INIT. */
815 #define BM_FTM_CNTIN_INIT (0x0000FFFFU) /*!< Bit mask for FTM_CNTIN_INIT. */
816 #define BS_FTM_CNTIN_INIT (16U) /*!< Bit field size in bits for FTM_CNTIN_INIT. */
818 /*! @brief Read current value of the FTM_CNTIN_INIT field. */
819 #define BR_FTM_CNTIN_INIT(x) (HW_FTM_CNTIN(x).B.INIT)
821 /*! @brief Format value for bitfield FTM_CNTIN_INIT. */
822 #define BF_FTM_CNTIN_INIT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CNTIN_INIT) & BM_FTM_CNTIN_INIT)
824 /*! @brief Set the INIT field to a new value. */
825 #define BW_FTM_CNTIN_INIT(x, v) (HW_FTM_CNTIN_WR(x, (HW_FTM_CNTIN_RD(x) & ~BM_FTM_CNTIN_INIT) | BF_FTM_CNTIN_INIT(v)))
828 /*******************************************************************************
829 * HW_FTM_STATUS - Capture And Compare Status
830 ******************************************************************************/
833 * @brief HW_FTM_STATUS - Capture And Compare Status (RW)
835 * Reset value: 0x00000000U
837 * The STATUS register contains a copy of the status flag CHnF bit in CnSC for
838 * each FTM channel for software convenience. Each CHnF bit in STATUS is a mirror
839 * of CHnF bit in CnSC. All CHnF bits can be checked using only one read of
840 * STATUS. All CHnF bits can be cleared by reading STATUS followed by writing 0x00 to
841 * STATUS. Hardware sets the individual channel flags when an event occurs on the
842 * channel. CHnF is cleared by reading STATUS while CHnF is set and then writing
843 * a 0 to the CHnF bit. Writing a 1 to CHnF has no effect. If another event
844 * occurs between the read and write operations, the write operation has no effect;
845 * therefore, CHnF remains set indicating an event has occurred. In this case, a
846 * CHnF interrupt request is not lost due to the clearing sequence for a previous
847 * CHnF. The STATUS register should be used only in Combine mode.
849 typedef union _hw_ftm_status
852 struct _hw_ftm_status_bitfields
854 uint32_t CH0F
: 1; /*!< [0] Channel 0 Flag */
855 uint32_t CH1F
: 1; /*!< [1] Channel 1 Flag */
856 uint32_t CH2F
: 1; /*!< [2] Channel 2 Flag */
857 uint32_t CH3F
: 1; /*!< [3] Channel 3 Flag */
858 uint32_t CH4F
: 1; /*!< [4] Channel 4 Flag */
859 uint32_t CH5F
: 1; /*!< [5] Channel 5 Flag */
860 uint32_t CH6F
: 1; /*!< [6] Channel 6 Flag */
861 uint32_t CH7F
: 1; /*!< [7] Channel 7 Flag */
862 uint32_t RESERVED0
: 24; /*!< [31:8] */
867 * @name Constants and macros for entire FTM_STATUS register
870 #define HW_FTM_STATUS_ADDR(x) ((x) + 0x50U)
872 #define HW_FTM_STATUS(x) (*(__IO hw_ftm_status_t *) HW_FTM_STATUS_ADDR(x))
873 #define HW_FTM_STATUS_RD(x) (HW_FTM_STATUS(x).U)
874 #define HW_FTM_STATUS_WR(x, v) (HW_FTM_STATUS(x).U = (v))
875 #define HW_FTM_STATUS_SET(x, v) (HW_FTM_STATUS_WR(x, HW_FTM_STATUS_RD(x) | (v)))
876 #define HW_FTM_STATUS_CLR(x, v) (HW_FTM_STATUS_WR(x, HW_FTM_STATUS_RD(x) & ~(v)))
877 #define HW_FTM_STATUS_TOG(x, v) (HW_FTM_STATUS_WR(x, HW_FTM_STATUS_RD(x) ^ (v)))
881 * Constants & macros for individual FTM_STATUS bitfields
885 * @name Register FTM_STATUS, field CH0F[0] (W1C)
887 * See the register description.
890 * - 0 - No channel event has occurred.
891 * - 1 - A channel event has occurred.
894 #define BP_FTM_STATUS_CH0F (0U) /*!< Bit position for FTM_STATUS_CH0F. */
895 #define BM_FTM_STATUS_CH0F (0x00000001U) /*!< Bit mask for FTM_STATUS_CH0F. */
896 #define BS_FTM_STATUS_CH0F (1U) /*!< Bit field size in bits for FTM_STATUS_CH0F. */
898 /*! @brief Read current value of the FTM_STATUS_CH0F field. */
899 #define BR_FTM_STATUS_CH0F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH0F))
901 /*! @brief Format value for bitfield FTM_STATUS_CH0F. */
902 #define BF_FTM_STATUS_CH0F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH0F) & BM_FTM_STATUS_CH0F)
904 /*! @brief Set the CH0F field to a new value. */
905 #define BW_FTM_STATUS_CH0F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH0F) = (v))
909 * @name Register FTM_STATUS, field CH1F[1] (W1C)
911 * See the register description.
914 * - 0 - No channel event has occurred.
915 * - 1 - A channel event has occurred.
918 #define BP_FTM_STATUS_CH1F (1U) /*!< Bit position for FTM_STATUS_CH1F. */
919 #define BM_FTM_STATUS_CH1F (0x00000002U) /*!< Bit mask for FTM_STATUS_CH1F. */
920 #define BS_FTM_STATUS_CH1F (1U) /*!< Bit field size in bits for FTM_STATUS_CH1F. */
922 /*! @brief Read current value of the FTM_STATUS_CH1F field. */
923 #define BR_FTM_STATUS_CH1F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH1F))
925 /*! @brief Format value for bitfield FTM_STATUS_CH1F. */
926 #define BF_FTM_STATUS_CH1F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH1F) & BM_FTM_STATUS_CH1F)
928 /*! @brief Set the CH1F field to a new value. */
929 #define BW_FTM_STATUS_CH1F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH1F) = (v))
933 * @name Register FTM_STATUS, field CH2F[2] (W1C)
935 * See the register description.
938 * - 0 - No channel event has occurred.
939 * - 1 - A channel event has occurred.
942 #define BP_FTM_STATUS_CH2F (2U) /*!< Bit position for FTM_STATUS_CH2F. */
943 #define BM_FTM_STATUS_CH2F (0x00000004U) /*!< Bit mask for FTM_STATUS_CH2F. */
944 #define BS_FTM_STATUS_CH2F (1U) /*!< Bit field size in bits for FTM_STATUS_CH2F. */
946 /*! @brief Read current value of the FTM_STATUS_CH2F field. */
947 #define BR_FTM_STATUS_CH2F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH2F))
949 /*! @brief Format value for bitfield FTM_STATUS_CH2F. */
950 #define BF_FTM_STATUS_CH2F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH2F) & BM_FTM_STATUS_CH2F)
952 /*! @brief Set the CH2F field to a new value. */
953 #define BW_FTM_STATUS_CH2F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH2F) = (v))
957 * @name Register FTM_STATUS, field CH3F[3] (W1C)
959 * See the register description.
962 * - 0 - No channel event has occurred.
963 * - 1 - A channel event has occurred.
966 #define BP_FTM_STATUS_CH3F (3U) /*!< Bit position for FTM_STATUS_CH3F. */
967 #define BM_FTM_STATUS_CH3F (0x00000008U) /*!< Bit mask for FTM_STATUS_CH3F. */
968 #define BS_FTM_STATUS_CH3F (1U) /*!< Bit field size in bits for FTM_STATUS_CH3F. */
970 /*! @brief Read current value of the FTM_STATUS_CH3F field. */
971 #define BR_FTM_STATUS_CH3F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH3F))
973 /*! @brief Format value for bitfield FTM_STATUS_CH3F. */
974 #define BF_FTM_STATUS_CH3F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH3F) & BM_FTM_STATUS_CH3F)
976 /*! @brief Set the CH3F field to a new value. */
977 #define BW_FTM_STATUS_CH3F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH3F) = (v))
981 * @name Register FTM_STATUS, field CH4F[4] (W1C)
983 * See the register description.
986 * - 0 - No channel event has occurred.
987 * - 1 - A channel event has occurred.
990 #define BP_FTM_STATUS_CH4F (4U) /*!< Bit position for FTM_STATUS_CH4F. */
991 #define BM_FTM_STATUS_CH4F (0x00000010U) /*!< Bit mask for FTM_STATUS_CH4F. */
992 #define BS_FTM_STATUS_CH4F (1U) /*!< Bit field size in bits for FTM_STATUS_CH4F. */
994 /*! @brief Read current value of the FTM_STATUS_CH4F field. */
995 #define BR_FTM_STATUS_CH4F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH4F))
997 /*! @brief Format value for bitfield FTM_STATUS_CH4F. */
998 #define BF_FTM_STATUS_CH4F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH4F) & BM_FTM_STATUS_CH4F)
1000 /*! @brief Set the CH4F field to a new value. */
1001 #define BW_FTM_STATUS_CH4F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH4F) = (v))
1005 * @name Register FTM_STATUS, field CH5F[5] (W1C)
1007 * See the register description.
1010 * - 0 - No channel event has occurred.
1011 * - 1 - A channel event has occurred.
1014 #define BP_FTM_STATUS_CH5F (5U) /*!< Bit position for FTM_STATUS_CH5F. */
1015 #define BM_FTM_STATUS_CH5F (0x00000020U) /*!< Bit mask for FTM_STATUS_CH5F. */
1016 #define BS_FTM_STATUS_CH5F (1U) /*!< Bit field size in bits for FTM_STATUS_CH5F. */
1018 /*! @brief Read current value of the FTM_STATUS_CH5F field. */
1019 #define BR_FTM_STATUS_CH5F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH5F))
1021 /*! @brief Format value for bitfield FTM_STATUS_CH5F. */
1022 #define BF_FTM_STATUS_CH5F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH5F) & BM_FTM_STATUS_CH5F)
1024 /*! @brief Set the CH5F field to a new value. */
1025 #define BW_FTM_STATUS_CH5F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH5F) = (v))
1029 * @name Register FTM_STATUS, field CH6F[6] (W1C)
1031 * See the register description.
1034 * - 0 - No channel event has occurred.
1035 * - 1 - A channel event has occurred.
1038 #define BP_FTM_STATUS_CH6F (6U) /*!< Bit position for FTM_STATUS_CH6F. */
1039 #define BM_FTM_STATUS_CH6F (0x00000040U) /*!< Bit mask for FTM_STATUS_CH6F. */
1040 #define BS_FTM_STATUS_CH6F (1U) /*!< Bit field size in bits for FTM_STATUS_CH6F. */
1042 /*! @brief Read current value of the FTM_STATUS_CH6F field. */
1043 #define BR_FTM_STATUS_CH6F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH6F))
1045 /*! @brief Format value for bitfield FTM_STATUS_CH6F. */
1046 #define BF_FTM_STATUS_CH6F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH6F) & BM_FTM_STATUS_CH6F)
1048 /*! @brief Set the CH6F field to a new value. */
1049 #define BW_FTM_STATUS_CH6F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH6F) = (v))
1053 * @name Register FTM_STATUS, field CH7F[7] (W1C)
1055 * See the register description.
1058 * - 0 - No channel event has occurred.
1059 * - 1 - A channel event has occurred.
1062 #define BP_FTM_STATUS_CH7F (7U) /*!< Bit position for FTM_STATUS_CH7F. */
1063 #define BM_FTM_STATUS_CH7F (0x00000080U) /*!< Bit mask for FTM_STATUS_CH7F. */
1064 #define BS_FTM_STATUS_CH7F (1U) /*!< Bit field size in bits for FTM_STATUS_CH7F. */
1066 /*! @brief Read current value of the FTM_STATUS_CH7F field. */
1067 #define BR_FTM_STATUS_CH7F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH7F))
1069 /*! @brief Format value for bitfield FTM_STATUS_CH7F. */
1070 #define BF_FTM_STATUS_CH7F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH7F) & BM_FTM_STATUS_CH7F)
1072 /*! @brief Set the CH7F field to a new value. */
1073 #define BW_FTM_STATUS_CH7F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH7F) = (v))
1076 /*******************************************************************************
1077 * HW_FTM_MODE - Features Mode Selection
1078 ******************************************************************************/
1081 * @brief HW_FTM_MODE - Features Mode Selection (RW)
1083 * Reset value: 0x00000004U
1085 * This register contains the global enable bit for FTM-specific features and
1086 * the control bits used to configure: Fault control mode and interrupt Capture
1087 * Test mode PWM synchronization Write protection Channel output initialization
1088 * These controls relate to all channels within this module.
1090 typedef union _hw_ftm_mode
1093 struct _hw_ftm_mode_bitfields
1095 uint32_t FTMEN
: 1; /*!< [0] FTM Enable */
1096 uint32_t INIT
: 1; /*!< [1] Initialize The Channels Output */
1097 uint32_t WPDIS
: 1; /*!< [2] Write Protection Disable */
1098 uint32_t PWMSYNC
: 1; /*!< [3] PWM Synchronization Mode */
1099 uint32_t CAPTEST
: 1; /*!< [4] Capture Test Mode Enable */
1100 uint32_t FAULTM
: 2; /*!< [6:5] Fault Control Mode */
1101 uint32_t FAULTIE
: 1; /*!< [7] Fault Interrupt Enable */
1102 uint32_t RESERVED0
: 24; /*!< [31:8] */
1107 * @name Constants and macros for entire FTM_MODE register
1110 #define HW_FTM_MODE_ADDR(x) ((x) + 0x54U)
1112 #define HW_FTM_MODE(x) (*(__IO hw_ftm_mode_t *) HW_FTM_MODE_ADDR(x))
1113 #define HW_FTM_MODE_RD(x) (HW_FTM_MODE(x).U)
1114 #define HW_FTM_MODE_WR(x, v) (HW_FTM_MODE(x).U = (v))
1115 #define HW_FTM_MODE_SET(x, v) (HW_FTM_MODE_WR(x, HW_FTM_MODE_RD(x) | (v)))
1116 #define HW_FTM_MODE_CLR(x, v) (HW_FTM_MODE_WR(x, HW_FTM_MODE_RD(x) & ~(v)))
1117 #define HW_FTM_MODE_TOG(x, v) (HW_FTM_MODE_WR(x, HW_FTM_MODE_RD(x) ^ (v)))
1121 * Constants & macros for individual FTM_MODE bitfields
1125 * @name Register FTM_MODE, field FTMEN[0] (RW)
1127 * This field is write protected. It can be written only when MODE[WPDIS] = 1.
1130 * - 0 - Only the TPM-compatible registers (first set of registers) can be used
1131 * without any restriction. Do not use the FTM-specific registers.
1132 * - 1 - All registers including the FTM-specific registers (second set of
1133 * registers) are available for use with no restrictions.
1136 #define BP_FTM_MODE_FTMEN (0U) /*!< Bit position for FTM_MODE_FTMEN. */
1137 #define BM_FTM_MODE_FTMEN (0x00000001U) /*!< Bit mask for FTM_MODE_FTMEN. */
1138 #define BS_FTM_MODE_FTMEN (1U) /*!< Bit field size in bits for FTM_MODE_FTMEN. */
1140 /*! @brief Read current value of the FTM_MODE_FTMEN field. */
1141 #define BR_FTM_MODE_FTMEN(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FTMEN))
1143 /*! @brief Format value for bitfield FTM_MODE_FTMEN. */
1144 #define BF_FTM_MODE_FTMEN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_FTMEN) & BM_FTM_MODE_FTMEN)
1146 /*! @brief Set the FTMEN field to a new value. */
1147 #define BW_FTM_MODE_FTMEN(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FTMEN) = (v))
1151 * @name Register FTM_MODE, field INIT[1] (RW)
1153 * When a 1 is written to INIT bit the channels output is initialized according
1154 * to the state of their corresponding bit in the OUTINIT register. Writing a 0
1155 * to INIT bit has no effect. The INIT bit is always read as 0.
1158 #define BP_FTM_MODE_INIT (1U) /*!< Bit position for FTM_MODE_INIT. */
1159 #define BM_FTM_MODE_INIT (0x00000002U) /*!< Bit mask for FTM_MODE_INIT. */
1160 #define BS_FTM_MODE_INIT (1U) /*!< Bit field size in bits for FTM_MODE_INIT. */
1162 /*! @brief Read current value of the FTM_MODE_INIT field. */
1163 #define BR_FTM_MODE_INIT(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_INIT))
1165 /*! @brief Format value for bitfield FTM_MODE_INIT. */
1166 #define BF_FTM_MODE_INIT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_INIT) & BM_FTM_MODE_INIT)
1168 /*! @brief Set the INIT field to a new value. */
1169 #define BW_FTM_MODE_INIT(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_INIT) = (v))
1173 * @name Register FTM_MODE, field WPDIS[2] (RW)
1175 * When write protection is enabled (WPDIS = 0), write protected bits cannot be
1176 * written. When write protection is disabled (WPDIS = 1), write protected bits
1177 * can be written. The WPDIS bit is the negation of the WPEN bit. WPDIS is cleared
1178 * when 1 is written to WPEN. WPDIS is set when WPEN bit is read as a 1 and then
1179 * 1 is written to WPDIS. Writing 0 to WPDIS has no effect.
1182 * - 0 - Write protection is enabled.
1183 * - 1 - Write protection is disabled.
1186 #define BP_FTM_MODE_WPDIS (2U) /*!< Bit position for FTM_MODE_WPDIS. */
1187 #define BM_FTM_MODE_WPDIS (0x00000004U) /*!< Bit mask for FTM_MODE_WPDIS. */
1188 #define BS_FTM_MODE_WPDIS (1U) /*!< Bit field size in bits for FTM_MODE_WPDIS. */
1190 /*! @brief Read current value of the FTM_MODE_WPDIS field. */
1191 #define BR_FTM_MODE_WPDIS(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_WPDIS))
1193 /*! @brief Format value for bitfield FTM_MODE_WPDIS. */
1194 #define BF_FTM_MODE_WPDIS(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_WPDIS) & BM_FTM_MODE_WPDIS)
1196 /*! @brief Set the WPDIS field to a new value. */
1197 #define BW_FTM_MODE_WPDIS(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_WPDIS) = (v))
1201 * @name Register FTM_MODE, field PWMSYNC[3] (RW)
1203 * Selects which triggers can be used by MOD, CnV, OUTMASK, and FTM counter
1204 * synchronization. See PWM synchronization. The PWMSYNC bit configures the
1205 * synchronization when SYNCMODE is 0.
1208 * - 0 - No restrictions. Software and hardware triggers can be used by MOD,
1209 * CnV, OUTMASK, and FTM counter synchronization.
1210 * - 1 - Software trigger can only be used by MOD and CnV synchronization, and
1211 * hardware triggers can only be used by OUTMASK and FTM counter
1215 #define BP_FTM_MODE_PWMSYNC (3U) /*!< Bit position for FTM_MODE_PWMSYNC. */
1216 #define BM_FTM_MODE_PWMSYNC (0x00000008U) /*!< Bit mask for FTM_MODE_PWMSYNC. */
1217 #define BS_FTM_MODE_PWMSYNC (1U) /*!< Bit field size in bits for FTM_MODE_PWMSYNC. */
1219 /*! @brief Read current value of the FTM_MODE_PWMSYNC field. */
1220 #define BR_FTM_MODE_PWMSYNC(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_PWMSYNC))
1222 /*! @brief Format value for bitfield FTM_MODE_PWMSYNC. */
1223 #define BF_FTM_MODE_PWMSYNC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_PWMSYNC) & BM_FTM_MODE_PWMSYNC)
1225 /*! @brief Set the PWMSYNC field to a new value. */
1226 #define BW_FTM_MODE_PWMSYNC(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_PWMSYNC) = (v))
1230 * @name Register FTM_MODE, field CAPTEST[4] (RW)
1232 * Enables the capture test mode. This field is write protected. It can be
1233 * written only when MODE[WPDIS] = 1.
1236 * - 0 - Capture test mode is disabled.
1237 * - 1 - Capture test mode is enabled.
1240 #define BP_FTM_MODE_CAPTEST (4U) /*!< Bit position for FTM_MODE_CAPTEST. */
1241 #define BM_FTM_MODE_CAPTEST (0x00000010U) /*!< Bit mask for FTM_MODE_CAPTEST. */
1242 #define BS_FTM_MODE_CAPTEST (1U) /*!< Bit field size in bits for FTM_MODE_CAPTEST. */
1244 /*! @brief Read current value of the FTM_MODE_CAPTEST field. */
1245 #define BR_FTM_MODE_CAPTEST(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_CAPTEST))
1247 /*! @brief Format value for bitfield FTM_MODE_CAPTEST. */
1248 #define BF_FTM_MODE_CAPTEST(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_CAPTEST) & BM_FTM_MODE_CAPTEST)
1250 /*! @brief Set the CAPTEST field to a new value. */
1251 #define BW_FTM_MODE_CAPTEST(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_CAPTEST) = (v))
1255 * @name Register FTM_MODE, field FAULTM[6:5] (RW)
1257 * Defines the FTM fault control mode. This field is write protected. It can be
1258 * written only when MODE[WPDIS] = 1.
1261 * - 00 - Fault control is disabled for all channels.
1262 * - 01 - Fault control is enabled for even channels only (channels 0, 2, 4, and
1263 * 6), and the selected mode is the manual fault clearing.
1264 * - 10 - Fault control is enabled for all channels, and the selected mode is
1265 * the manual fault clearing.
1266 * - 11 - Fault control is enabled for all channels, and the selected mode is
1267 * the automatic fault clearing.
1270 #define BP_FTM_MODE_FAULTM (5U) /*!< Bit position for FTM_MODE_FAULTM. */
1271 #define BM_FTM_MODE_FAULTM (0x00000060U) /*!< Bit mask for FTM_MODE_FAULTM. */
1272 #define BS_FTM_MODE_FAULTM (2U) /*!< Bit field size in bits for FTM_MODE_FAULTM. */
1274 /*! @brief Read current value of the FTM_MODE_FAULTM field. */
1275 #define BR_FTM_MODE_FAULTM(x) (HW_FTM_MODE(x).B.FAULTM)
1277 /*! @brief Format value for bitfield FTM_MODE_FAULTM. */
1278 #define BF_FTM_MODE_FAULTM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_FAULTM) & BM_FTM_MODE_FAULTM)
1280 /*! @brief Set the FAULTM field to a new value. */
1281 #define BW_FTM_MODE_FAULTM(x, v) (HW_FTM_MODE_WR(x, (HW_FTM_MODE_RD(x) & ~BM_FTM_MODE_FAULTM) | BF_FTM_MODE_FAULTM(v)))
1285 * @name Register FTM_MODE, field FAULTIE[7] (RW)
1287 * Enables the generation of an interrupt when a fault is detected by FTM and
1288 * the FTM fault control is enabled.
1291 * - 0 - Fault control interrupt is disabled.
1292 * - 1 - Fault control interrupt is enabled.
1295 #define BP_FTM_MODE_FAULTIE (7U) /*!< Bit position for FTM_MODE_FAULTIE. */
1296 #define BM_FTM_MODE_FAULTIE (0x00000080U) /*!< Bit mask for FTM_MODE_FAULTIE. */
1297 #define BS_FTM_MODE_FAULTIE (1U) /*!< Bit field size in bits for FTM_MODE_FAULTIE. */
1299 /*! @brief Read current value of the FTM_MODE_FAULTIE field. */
1300 #define BR_FTM_MODE_FAULTIE(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FAULTIE))
1302 /*! @brief Format value for bitfield FTM_MODE_FAULTIE. */
1303 #define BF_FTM_MODE_FAULTIE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_FAULTIE) & BM_FTM_MODE_FAULTIE)
1305 /*! @brief Set the FAULTIE field to a new value. */
1306 #define BW_FTM_MODE_FAULTIE(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FAULTIE) = (v))
1309 /*******************************************************************************
1310 * HW_FTM_SYNC - Synchronization
1311 ******************************************************************************/
1314 * @brief HW_FTM_SYNC - Synchronization (RW)
1316 * Reset value: 0x00000000U
1318 * This register configures the PWM synchronization. A synchronization event can
1319 * perform the synchronized update of MOD, CV, and OUTMASK registers with the
1320 * value of their write buffer and the FTM counter initialization. The software
1321 * trigger, SWSYNC bit, and hardware triggers TRIG0, TRIG1, and TRIG2 bits have a
1322 * potential conflict if used together when SYNCMODE = 0. Use only hardware or
1323 * software triggers but not both at the same time, otherwise unpredictable behavior
1324 * is likely to happen. The selection of the loading point, CNTMAX and CNTMIN
1325 * bits, is intended to provide the update of MOD, CNTIN, and CnV registers across
1326 * all enabled channels simultaneously. The use of the loading point selection
1327 * together with SYNCMODE = 0 and hardware trigger selection, TRIG0, TRIG1, or TRIG2
1328 * bits, is likely to result in unpredictable behavior. The synchronization
1329 * event selection also depends on the PWMSYNC (MODE register) and SYNCMODE (SYNCONF
1330 * register) bits. See PWM synchronization.
1332 typedef union _hw_ftm_sync
1335 struct _hw_ftm_sync_bitfields
1337 uint32_t CNTMIN
: 1; /*!< [0] Minimum Loading Point Enable */
1338 uint32_t CNTMAX
: 1; /*!< [1] Maximum Loading Point Enable */
1339 uint32_t REINIT
: 1; /*!< [2] FTM Counter Reinitialization By
1340 * Synchronization (FTM counter synchronization) */
1341 uint32_t SYNCHOM
: 1; /*!< [3] Output Mask Synchronization */
1342 uint32_t TRIG0
: 1; /*!< [4] PWM Synchronization Hardware Trigger 0 */
1343 uint32_t TRIG1
: 1; /*!< [5] PWM Synchronization Hardware Trigger 1 */
1344 uint32_t TRIG2
: 1; /*!< [6] PWM Synchronization Hardware Trigger 2 */
1345 uint32_t SWSYNC
: 1; /*!< [7] PWM Synchronization Software Trigger */
1346 uint32_t RESERVED0
: 24; /*!< [31:8] */
1351 * @name Constants and macros for entire FTM_SYNC register
1354 #define HW_FTM_SYNC_ADDR(x) ((x) + 0x58U)
1356 #define HW_FTM_SYNC(x) (*(__IO hw_ftm_sync_t *) HW_FTM_SYNC_ADDR(x))
1357 #define HW_FTM_SYNC_RD(x) (HW_FTM_SYNC(x).U)
1358 #define HW_FTM_SYNC_WR(x, v) (HW_FTM_SYNC(x).U = (v))
1359 #define HW_FTM_SYNC_SET(x, v) (HW_FTM_SYNC_WR(x, HW_FTM_SYNC_RD(x) | (v)))
1360 #define HW_FTM_SYNC_CLR(x, v) (HW_FTM_SYNC_WR(x, HW_FTM_SYNC_RD(x) & ~(v)))
1361 #define HW_FTM_SYNC_TOG(x, v) (HW_FTM_SYNC_WR(x, HW_FTM_SYNC_RD(x) ^ (v)))
1365 * Constants & macros for individual FTM_SYNC bitfields
1369 * @name Register FTM_SYNC, field CNTMIN[0] (RW)
1371 * Selects the minimum loading point to PWM synchronization. See Boundary cycle
1372 * and loading points. If CNTMIN is one, the selected loading point is when the
1373 * FTM counter reaches its minimum value (CNTIN register).
1376 * - 0 - The minimum loading point is disabled.
1377 * - 1 - The minimum loading point is enabled.
1380 #define BP_FTM_SYNC_CNTMIN (0U) /*!< Bit position for FTM_SYNC_CNTMIN. */
1381 #define BM_FTM_SYNC_CNTMIN (0x00000001U) /*!< Bit mask for FTM_SYNC_CNTMIN. */
1382 #define BS_FTM_SYNC_CNTMIN (1U) /*!< Bit field size in bits for FTM_SYNC_CNTMIN. */
1384 /*! @brief Read current value of the FTM_SYNC_CNTMIN field. */
1385 #define BR_FTM_SYNC_CNTMIN(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMIN))
1387 /*! @brief Format value for bitfield FTM_SYNC_CNTMIN. */
1388 #define BF_FTM_SYNC_CNTMIN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_CNTMIN) & BM_FTM_SYNC_CNTMIN)
1390 /*! @brief Set the CNTMIN field to a new value. */
1391 #define BW_FTM_SYNC_CNTMIN(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMIN) = (v))
1395 * @name Register FTM_SYNC, field CNTMAX[1] (RW)
1397 * Selects the maximum loading point to PWM synchronization. See Boundary cycle
1398 * and loading points. If CNTMAX is 1, the selected loading point is when the FTM
1399 * counter reaches its maximum value (MOD register).
1402 * - 0 - The maximum loading point is disabled.
1403 * - 1 - The maximum loading point is enabled.
1406 #define BP_FTM_SYNC_CNTMAX (1U) /*!< Bit position for FTM_SYNC_CNTMAX. */
1407 #define BM_FTM_SYNC_CNTMAX (0x00000002U) /*!< Bit mask for FTM_SYNC_CNTMAX. */
1408 #define BS_FTM_SYNC_CNTMAX (1U) /*!< Bit field size in bits for FTM_SYNC_CNTMAX. */
1410 /*! @brief Read current value of the FTM_SYNC_CNTMAX field. */
1411 #define BR_FTM_SYNC_CNTMAX(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMAX))
1413 /*! @brief Format value for bitfield FTM_SYNC_CNTMAX. */
1414 #define BF_FTM_SYNC_CNTMAX(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_CNTMAX) & BM_FTM_SYNC_CNTMAX)
1416 /*! @brief Set the CNTMAX field to a new value. */
1417 #define BW_FTM_SYNC_CNTMAX(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMAX) = (v))
1421 * @name Register FTM_SYNC, field REINIT[2] (RW)
1423 * Determines if the FTM counter is reinitialized when the selected trigger for
1424 * the synchronization is detected. The REINIT bit configures the synchronization
1425 * when SYNCMODE is zero.
1428 * - 0 - FTM counter continues to count normally.
1429 * - 1 - FTM counter is updated with its initial value when the selected trigger
1433 #define BP_FTM_SYNC_REINIT (2U) /*!< Bit position for FTM_SYNC_REINIT. */
1434 #define BM_FTM_SYNC_REINIT (0x00000004U) /*!< Bit mask for FTM_SYNC_REINIT. */
1435 #define BS_FTM_SYNC_REINIT (1U) /*!< Bit field size in bits for FTM_SYNC_REINIT. */
1437 /*! @brief Read current value of the FTM_SYNC_REINIT field. */
1438 #define BR_FTM_SYNC_REINIT(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_REINIT))
1440 /*! @brief Format value for bitfield FTM_SYNC_REINIT. */
1441 #define BF_FTM_SYNC_REINIT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_REINIT) & BM_FTM_SYNC_REINIT)
1443 /*! @brief Set the REINIT field to a new value. */
1444 #define BW_FTM_SYNC_REINIT(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_REINIT) = (v))
1448 * @name Register FTM_SYNC, field SYNCHOM[3] (RW)
1450 * Selects when the OUTMASK register is updated with the value of its buffer.
1453 * - 0 - OUTMASK register is updated with the value of its buffer in all rising
1454 * edges of the system clock.
1455 * - 1 - OUTMASK register is updated with the value of its buffer only by the
1456 * PWM synchronization.
1459 #define BP_FTM_SYNC_SYNCHOM (3U) /*!< Bit position for FTM_SYNC_SYNCHOM. */
1460 #define BM_FTM_SYNC_SYNCHOM (0x00000008U) /*!< Bit mask for FTM_SYNC_SYNCHOM. */
1461 #define BS_FTM_SYNC_SYNCHOM (1U) /*!< Bit field size in bits for FTM_SYNC_SYNCHOM. */
1463 /*! @brief Read current value of the FTM_SYNC_SYNCHOM field. */
1464 #define BR_FTM_SYNC_SYNCHOM(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SYNCHOM))
1466 /*! @brief Format value for bitfield FTM_SYNC_SYNCHOM. */
1467 #define BF_FTM_SYNC_SYNCHOM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_SYNCHOM) & BM_FTM_SYNC_SYNCHOM)
1469 /*! @brief Set the SYNCHOM field to a new value. */
1470 #define BW_FTM_SYNC_SYNCHOM(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SYNCHOM) = (v))
1474 * @name Register FTM_SYNC, field TRIG0[4] (RW)
1476 * Enables hardware trigger 0 to the PWM synchronization. Hardware trigger 0
1477 * occurs when a rising edge is detected at the trigger 0 input signal.
1480 * - 0 - Trigger is disabled.
1481 * - 1 - Trigger is enabled.
1484 #define BP_FTM_SYNC_TRIG0 (4U) /*!< Bit position for FTM_SYNC_TRIG0. */
1485 #define BM_FTM_SYNC_TRIG0 (0x00000010U) /*!< Bit mask for FTM_SYNC_TRIG0. */
1486 #define BS_FTM_SYNC_TRIG0 (1U) /*!< Bit field size in bits for FTM_SYNC_TRIG0. */
1488 /*! @brief Read current value of the FTM_SYNC_TRIG0 field. */
1489 #define BR_FTM_SYNC_TRIG0(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG0))
1491 /*! @brief Format value for bitfield FTM_SYNC_TRIG0. */
1492 #define BF_FTM_SYNC_TRIG0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_TRIG0) & BM_FTM_SYNC_TRIG0)
1494 /*! @brief Set the TRIG0 field to a new value. */
1495 #define BW_FTM_SYNC_TRIG0(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG0) = (v))
1499 * @name Register FTM_SYNC, field TRIG1[5] (RW)
1501 * Enables hardware trigger 1 to the PWM synchronization. Hardware trigger 1
1502 * happens when a rising edge is detected at the trigger 1 input signal.
1505 * - 0 - Trigger is disabled.
1506 * - 1 - Trigger is enabled.
1509 #define BP_FTM_SYNC_TRIG1 (5U) /*!< Bit position for FTM_SYNC_TRIG1. */
1510 #define BM_FTM_SYNC_TRIG1 (0x00000020U) /*!< Bit mask for FTM_SYNC_TRIG1. */
1511 #define BS_FTM_SYNC_TRIG1 (1U) /*!< Bit field size in bits for FTM_SYNC_TRIG1. */
1513 /*! @brief Read current value of the FTM_SYNC_TRIG1 field. */
1514 #define BR_FTM_SYNC_TRIG1(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG1))
1516 /*! @brief Format value for bitfield FTM_SYNC_TRIG1. */
1517 #define BF_FTM_SYNC_TRIG1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_TRIG1) & BM_FTM_SYNC_TRIG1)
1519 /*! @brief Set the TRIG1 field to a new value. */
1520 #define BW_FTM_SYNC_TRIG1(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG1) = (v))
1524 * @name Register FTM_SYNC, field TRIG2[6] (RW)
1526 * Enables hardware trigger 2 to the PWM synchronization. Hardware trigger 2
1527 * happens when a rising edge is detected at the trigger 2 input signal.
1530 * - 0 - Trigger is disabled.
1531 * - 1 - Trigger is enabled.
1534 #define BP_FTM_SYNC_TRIG2 (6U) /*!< Bit position for FTM_SYNC_TRIG2. */
1535 #define BM_FTM_SYNC_TRIG2 (0x00000040U) /*!< Bit mask for FTM_SYNC_TRIG2. */
1536 #define BS_FTM_SYNC_TRIG2 (1U) /*!< Bit field size in bits for FTM_SYNC_TRIG2. */
1538 /*! @brief Read current value of the FTM_SYNC_TRIG2 field. */
1539 #define BR_FTM_SYNC_TRIG2(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG2))
1541 /*! @brief Format value for bitfield FTM_SYNC_TRIG2. */
1542 #define BF_FTM_SYNC_TRIG2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_TRIG2) & BM_FTM_SYNC_TRIG2)
1544 /*! @brief Set the TRIG2 field to a new value. */
1545 #define BW_FTM_SYNC_TRIG2(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG2) = (v))
1549 * @name Register FTM_SYNC, field SWSYNC[7] (RW)
1551 * Selects the software trigger as the PWM synchronization trigger. The software
1552 * trigger happens when a 1 is written to SWSYNC bit.
1555 * - 0 - Software trigger is not selected.
1556 * - 1 - Software trigger is selected.
1559 #define BP_FTM_SYNC_SWSYNC (7U) /*!< Bit position for FTM_SYNC_SWSYNC. */
1560 #define BM_FTM_SYNC_SWSYNC (0x00000080U) /*!< Bit mask for FTM_SYNC_SWSYNC. */
1561 #define BS_FTM_SYNC_SWSYNC (1U) /*!< Bit field size in bits for FTM_SYNC_SWSYNC. */
1563 /*! @brief Read current value of the FTM_SYNC_SWSYNC field. */
1564 #define BR_FTM_SYNC_SWSYNC(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SWSYNC))
1566 /*! @brief Format value for bitfield FTM_SYNC_SWSYNC. */
1567 #define BF_FTM_SYNC_SWSYNC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_SWSYNC) & BM_FTM_SYNC_SWSYNC)
1569 /*! @brief Set the SWSYNC field to a new value. */
1570 #define BW_FTM_SYNC_SWSYNC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SWSYNC) = (v))
1573 /*******************************************************************************
1574 * HW_FTM_OUTINIT - Initial State For Channels Output
1575 ******************************************************************************/
1578 * @brief HW_FTM_OUTINIT - Initial State For Channels Output (RW)
1580 * Reset value: 0x00000000U
1582 typedef union _hw_ftm_outinit
1585 struct _hw_ftm_outinit_bitfields
1587 uint32_t CH0OI
: 1; /*!< [0] Channel 0 Output Initialization Value */
1588 uint32_t CH1OI
: 1; /*!< [1] Channel 1 Output Initialization Value */
1589 uint32_t CH2OI
: 1; /*!< [2] Channel 2 Output Initialization Value */
1590 uint32_t CH3OI
: 1; /*!< [3] Channel 3 Output Initialization Value */
1591 uint32_t CH4OI
: 1; /*!< [4] Channel 4 Output Initialization Value */
1592 uint32_t CH5OI
: 1; /*!< [5] Channel 5 Output Initialization Value */
1593 uint32_t CH6OI
: 1; /*!< [6] Channel 6 Output Initialization Value */
1594 uint32_t CH7OI
: 1; /*!< [7] Channel 7 Output Initialization Value */
1595 uint32_t RESERVED0
: 24; /*!< [31:8] */
1600 * @name Constants and macros for entire FTM_OUTINIT register
1603 #define HW_FTM_OUTINIT_ADDR(x) ((x) + 0x5CU)
1605 #define HW_FTM_OUTINIT(x) (*(__IO hw_ftm_outinit_t *) HW_FTM_OUTINIT_ADDR(x))
1606 #define HW_FTM_OUTINIT_RD(x) (HW_FTM_OUTINIT(x).U)
1607 #define HW_FTM_OUTINIT_WR(x, v) (HW_FTM_OUTINIT(x).U = (v))
1608 #define HW_FTM_OUTINIT_SET(x, v) (HW_FTM_OUTINIT_WR(x, HW_FTM_OUTINIT_RD(x) | (v)))
1609 #define HW_FTM_OUTINIT_CLR(x, v) (HW_FTM_OUTINIT_WR(x, HW_FTM_OUTINIT_RD(x) & ~(v)))
1610 #define HW_FTM_OUTINIT_TOG(x, v) (HW_FTM_OUTINIT_WR(x, HW_FTM_OUTINIT_RD(x) ^ (v)))
1614 * Constants & macros for individual FTM_OUTINIT bitfields
1618 * @name Register FTM_OUTINIT, field CH0OI[0] (RW)
1620 * Selects the value that is forced into the channel output when the
1621 * initialization occurs.
1624 * - 0 - The initialization value is 0.
1625 * - 1 - The initialization value is 1.
1628 #define BP_FTM_OUTINIT_CH0OI (0U) /*!< Bit position for FTM_OUTINIT_CH0OI. */
1629 #define BM_FTM_OUTINIT_CH0OI (0x00000001U) /*!< Bit mask for FTM_OUTINIT_CH0OI. */
1630 #define BS_FTM_OUTINIT_CH0OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH0OI. */
1632 /*! @brief Read current value of the FTM_OUTINIT_CH0OI field. */
1633 #define BR_FTM_OUTINIT_CH0OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH0OI))
1635 /*! @brief Format value for bitfield FTM_OUTINIT_CH0OI. */
1636 #define BF_FTM_OUTINIT_CH0OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH0OI) & BM_FTM_OUTINIT_CH0OI)
1638 /*! @brief Set the CH0OI field to a new value. */
1639 #define BW_FTM_OUTINIT_CH0OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH0OI) = (v))
1643 * @name Register FTM_OUTINIT, field CH1OI[1] (RW)
1645 * Selects the value that is forced into the channel output when the
1646 * initialization occurs.
1649 * - 0 - The initialization value is 0.
1650 * - 1 - The initialization value is 1.
1653 #define BP_FTM_OUTINIT_CH1OI (1U) /*!< Bit position for FTM_OUTINIT_CH1OI. */
1654 #define BM_FTM_OUTINIT_CH1OI (0x00000002U) /*!< Bit mask for FTM_OUTINIT_CH1OI. */
1655 #define BS_FTM_OUTINIT_CH1OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH1OI. */
1657 /*! @brief Read current value of the FTM_OUTINIT_CH1OI field. */
1658 #define BR_FTM_OUTINIT_CH1OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH1OI))
1660 /*! @brief Format value for bitfield FTM_OUTINIT_CH1OI. */
1661 #define BF_FTM_OUTINIT_CH1OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH1OI) & BM_FTM_OUTINIT_CH1OI)
1663 /*! @brief Set the CH1OI field to a new value. */
1664 #define BW_FTM_OUTINIT_CH1OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH1OI) = (v))
1668 * @name Register FTM_OUTINIT, field CH2OI[2] (RW)
1670 * Selects the value that is forced into the channel output when the
1671 * initialization occurs.
1674 * - 0 - The initialization value is 0.
1675 * - 1 - The initialization value is 1.
1678 #define BP_FTM_OUTINIT_CH2OI (2U) /*!< Bit position for FTM_OUTINIT_CH2OI. */
1679 #define BM_FTM_OUTINIT_CH2OI (0x00000004U) /*!< Bit mask for FTM_OUTINIT_CH2OI. */
1680 #define BS_FTM_OUTINIT_CH2OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH2OI. */
1682 /*! @brief Read current value of the FTM_OUTINIT_CH2OI field. */
1683 #define BR_FTM_OUTINIT_CH2OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH2OI))
1685 /*! @brief Format value for bitfield FTM_OUTINIT_CH2OI. */
1686 #define BF_FTM_OUTINIT_CH2OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH2OI) & BM_FTM_OUTINIT_CH2OI)
1688 /*! @brief Set the CH2OI field to a new value. */
1689 #define BW_FTM_OUTINIT_CH2OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH2OI) = (v))
1693 * @name Register FTM_OUTINIT, field CH3OI[3] (RW)
1695 * Selects the value that is forced into the channel output when the
1696 * initialization occurs.
1699 * - 0 - The initialization value is 0.
1700 * - 1 - The initialization value is 1.
1703 #define BP_FTM_OUTINIT_CH3OI (3U) /*!< Bit position for FTM_OUTINIT_CH3OI. */
1704 #define BM_FTM_OUTINIT_CH3OI (0x00000008U) /*!< Bit mask for FTM_OUTINIT_CH3OI. */
1705 #define BS_FTM_OUTINIT_CH3OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH3OI. */
1707 /*! @brief Read current value of the FTM_OUTINIT_CH3OI field. */
1708 #define BR_FTM_OUTINIT_CH3OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH3OI))
1710 /*! @brief Format value for bitfield FTM_OUTINIT_CH3OI. */
1711 #define BF_FTM_OUTINIT_CH3OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH3OI) & BM_FTM_OUTINIT_CH3OI)
1713 /*! @brief Set the CH3OI field to a new value. */
1714 #define BW_FTM_OUTINIT_CH3OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH3OI) = (v))
1718 * @name Register FTM_OUTINIT, field CH4OI[4] (RW)
1720 * Selects the value that is forced into the channel output when the
1721 * initialization occurs.
1724 * - 0 - The initialization value is 0.
1725 * - 1 - The initialization value is 1.
1728 #define BP_FTM_OUTINIT_CH4OI (4U) /*!< Bit position for FTM_OUTINIT_CH4OI. */
1729 #define BM_FTM_OUTINIT_CH4OI (0x00000010U) /*!< Bit mask for FTM_OUTINIT_CH4OI. */
1730 #define BS_FTM_OUTINIT_CH4OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH4OI. */
1732 /*! @brief Read current value of the FTM_OUTINIT_CH4OI field. */
1733 #define BR_FTM_OUTINIT_CH4OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH4OI))
1735 /*! @brief Format value for bitfield FTM_OUTINIT_CH4OI. */
1736 #define BF_FTM_OUTINIT_CH4OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH4OI) & BM_FTM_OUTINIT_CH4OI)
1738 /*! @brief Set the CH4OI field to a new value. */
1739 #define BW_FTM_OUTINIT_CH4OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH4OI) = (v))
1743 * @name Register FTM_OUTINIT, field CH5OI[5] (RW)
1745 * Selects the value that is forced into the channel output when the
1746 * initialization occurs.
1749 * - 0 - The initialization value is 0.
1750 * - 1 - The initialization value is 1.
1753 #define BP_FTM_OUTINIT_CH5OI (5U) /*!< Bit position for FTM_OUTINIT_CH5OI. */
1754 #define BM_FTM_OUTINIT_CH5OI (0x00000020U) /*!< Bit mask for FTM_OUTINIT_CH5OI. */
1755 #define BS_FTM_OUTINIT_CH5OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH5OI. */
1757 /*! @brief Read current value of the FTM_OUTINIT_CH5OI field. */
1758 #define BR_FTM_OUTINIT_CH5OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH5OI))
1760 /*! @brief Format value for bitfield FTM_OUTINIT_CH5OI. */
1761 #define BF_FTM_OUTINIT_CH5OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH5OI) & BM_FTM_OUTINIT_CH5OI)
1763 /*! @brief Set the CH5OI field to a new value. */
1764 #define BW_FTM_OUTINIT_CH5OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH5OI) = (v))
1768 * @name Register FTM_OUTINIT, field CH6OI[6] (RW)
1770 * Selects the value that is forced into the channel output when the
1771 * initialization occurs.
1774 * - 0 - The initialization value is 0.
1775 * - 1 - The initialization value is 1.
1778 #define BP_FTM_OUTINIT_CH6OI (6U) /*!< Bit position for FTM_OUTINIT_CH6OI. */
1779 #define BM_FTM_OUTINIT_CH6OI (0x00000040U) /*!< Bit mask for FTM_OUTINIT_CH6OI. */
1780 #define BS_FTM_OUTINIT_CH6OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH6OI. */
1782 /*! @brief Read current value of the FTM_OUTINIT_CH6OI field. */
1783 #define BR_FTM_OUTINIT_CH6OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH6OI))
1785 /*! @brief Format value for bitfield FTM_OUTINIT_CH6OI. */
1786 #define BF_FTM_OUTINIT_CH6OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH6OI) & BM_FTM_OUTINIT_CH6OI)
1788 /*! @brief Set the CH6OI field to a new value. */
1789 #define BW_FTM_OUTINIT_CH6OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH6OI) = (v))
1793 * @name Register FTM_OUTINIT, field CH7OI[7] (RW)
1795 * Selects the value that is forced into the channel output when the
1796 * initialization occurs.
1799 * - 0 - The initialization value is 0.
1800 * - 1 - The initialization value is 1.
1803 #define BP_FTM_OUTINIT_CH7OI (7U) /*!< Bit position for FTM_OUTINIT_CH7OI. */
1804 #define BM_FTM_OUTINIT_CH7OI (0x00000080U) /*!< Bit mask for FTM_OUTINIT_CH7OI. */
1805 #define BS_FTM_OUTINIT_CH7OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH7OI. */
1807 /*! @brief Read current value of the FTM_OUTINIT_CH7OI field. */
1808 #define BR_FTM_OUTINIT_CH7OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH7OI))
1810 /*! @brief Format value for bitfield FTM_OUTINIT_CH7OI. */
1811 #define BF_FTM_OUTINIT_CH7OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH7OI) & BM_FTM_OUTINIT_CH7OI)
1813 /*! @brief Set the CH7OI field to a new value. */
1814 #define BW_FTM_OUTINIT_CH7OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH7OI) = (v))
1817 /*******************************************************************************
1818 * HW_FTM_OUTMASK - Output Mask
1819 ******************************************************************************/
1822 * @brief HW_FTM_OUTMASK - Output Mask (RW)
1824 * Reset value: 0x00000000U
1826 * This register provides a mask for each FTM channel. The mask of a channel
1827 * determines if its output responds, that is, it is masked or not, when a match
1828 * occurs. This feature is used for BLDC control where the PWM signal is presented
1829 * to an electric motor at specific times to provide electronic commutation. Any
1830 * write to the OUTMASK register, stores the value in its write buffer. The
1831 * register is updated with the value of its write buffer according to PWM
1834 typedef union _hw_ftm_outmask
1837 struct _hw_ftm_outmask_bitfields
1839 uint32_t CH0OM
: 1; /*!< [0] Channel 0 Output Mask */
1840 uint32_t CH1OM
: 1; /*!< [1] Channel 1 Output Mask */
1841 uint32_t CH2OM
: 1; /*!< [2] Channel 2 Output Mask */
1842 uint32_t CH3OM
: 1; /*!< [3] Channel 3 Output Mask */
1843 uint32_t CH4OM
: 1; /*!< [4] Channel 4 Output Mask */
1844 uint32_t CH5OM
: 1; /*!< [5] Channel 5 Output Mask */
1845 uint32_t CH6OM
: 1; /*!< [6] Channel 6 Output Mask */
1846 uint32_t CH7OM
: 1; /*!< [7] Channel 7 Output Mask */
1847 uint32_t RESERVED0
: 24; /*!< [31:8] */
1852 * @name Constants and macros for entire FTM_OUTMASK register
1855 #define HW_FTM_OUTMASK_ADDR(x) ((x) + 0x60U)
1857 #define HW_FTM_OUTMASK(x) (*(__IO hw_ftm_outmask_t *) HW_FTM_OUTMASK_ADDR(x))
1858 #define HW_FTM_OUTMASK_RD(x) (HW_FTM_OUTMASK(x).U)
1859 #define HW_FTM_OUTMASK_WR(x, v) (HW_FTM_OUTMASK(x).U = (v))
1860 #define HW_FTM_OUTMASK_SET(x, v) (HW_FTM_OUTMASK_WR(x, HW_FTM_OUTMASK_RD(x) | (v)))
1861 #define HW_FTM_OUTMASK_CLR(x, v) (HW_FTM_OUTMASK_WR(x, HW_FTM_OUTMASK_RD(x) & ~(v)))
1862 #define HW_FTM_OUTMASK_TOG(x, v) (HW_FTM_OUTMASK_WR(x, HW_FTM_OUTMASK_RD(x) ^ (v)))
1866 * Constants & macros for individual FTM_OUTMASK bitfields
1870 * @name Register FTM_OUTMASK, field CH0OM[0] (RW)
1872 * Defines if the channel output is masked or unmasked.
1875 * - 0 - Channel output is not masked. It continues to operate normally.
1876 * - 1 - Channel output is masked. It is forced to its inactive state.
1879 #define BP_FTM_OUTMASK_CH0OM (0U) /*!< Bit position for FTM_OUTMASK_CH0OM. */
1880 #define BM_FTM_OUTMASK_CH0OM (0x00000001U) /*!< Bit mask for FTM_OUTMASK_CH0OM. */
1881 #define BS_FTM_OUTMASK_CH0OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH0OM. */
1883 /*! @brief Read current value of the FTM_OUTMASK_CH0OM field. */
1884 #define BR_FTM_OUTMASK_CH0OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH0OM))
1886 /*! @brief Format value for bitfield FTM_OUTMASK_CH0OM. */
1887 #define BF_FTM_OUTMASK_CH0OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH0OM) & BM_FTM_OUTMASK_CH0OM)
1889 /*! @brief Set the CH0OM field to a new value. */
1890 #define BW_FTM_OUTMASK_CH0OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH0OM) = (v))
1894 * @name Register FTM_OUTMASK, field CH1OM[1] (RW)
1896 * Defines if the channel output is masked or unmasked.
1899 * - 0 - Channel output is not masked. It continues to operate normally.
1900 * - 1 - Channel output is masked. It is forced to its inactive state.
1903 #define BP_FTM_OUTMASK_CH1OM (1U) /*!< Bit position for FTM_OUTMASK_CH1OM. */
1904 #define BM_FTM_OUTMASK_CH1OM (0x00000002U) /*!< Bit mask for FTM_OUTMASK_CH1OM. */
1905 #define BS_FTM_OUTMASK_CH1OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH1OM. */
1907 /*! @brief Read current value of the FTM_OUTMASK_CH1OM field. */
1908 #define BR_FTM_OUTMASK_CH1OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH1OM))
1910 /*! @brief Format value for bitfield FTM_OUTMASK_CH1OM. */
1911 #define BF_FTM_OUTMASK_CH1OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH1OM) & BM_FTM_OUTMASK_CH1OM)
1913 /*! @brief Set the CH1OM field to a new value. */
1914 #define BW_FTM_OUTMASK_CH1OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH1OM) = (v))
1918 * @name Register FTM_OUTMASK, field CH2OM[2] (RW)
1920 * Defines if the channel output is masked or unmasked.
1923 * - 0 - Channel output is not masked. It continues to operate normally.
1924 * - 1 - Channel output is masked. It is forced to its inactive state.
1927 #define BP_FTM_OUTMASK_CH2OM (2U) /*!< Bit position for FTM_OUTMASK_CH2OM. */
1928 #define BM_FTM_OUTMASK_CH2OM (0x00000004U) /*!< Bit mask for FTM_OUTMASK_CH2OM. */
1929 #define BS_FTM_OUTMASK_CH2OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH2OM. */
1931 /*! @brief Read current value of the FTM_OUTMASK_CH2OM field. */
1932 #define BR_FTM_OUTMASK_CH2OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH2OM))
1934 /*! @brief Format value for bitfield FTM_OUTMASK_CH2OM. */
1935 #define BF_FTM_OUTMASK_CH2OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH2OM) & BM_FTM_OUTMASK_CH2OM)
1937 /*! @brief Set the CH2OM field to a new value. */
1938 #define BW_FTM_OUTMASK_CH2OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH2OM) = (v))
1942 * @name Register FTM_OUTMASK, field CH3OM[3] (RW)
1944 * Defines if the channel output is masked or unmasked.
1947 * - 0 - Channel output is not masked. It continues to operate normally.
1948 * - 1 - Channel output is masked. It is forced to its inactive state.
1951 #define BP_FTM_OUTMASK_CH3OM (3U) /*!< Bit position for FTM_OUTMASK_CH3OM. */
1952 #define BM_FTM_OUTMASK_CH3OM (0x00000008U) /*!< Bit mask for FTM_OUTMASK_CH3OM. */
1953 #define BS_FTM_OUTMASK_CH3OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH3OM. */
1955 /*! @brief Read current value of the FTM_OUTMASK_CH3OM field. */
1956 #define BR_FTM_OUTMASK_CH3OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH3OM))
1958 /*! @brief Format value for bitfield FTM_OUTMASK_CH3OM. */
1959 #define BF_FTM_OUTMASK_CH3OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH3OM) & BM_FTM_OUTMASK_CH3OM)
1961 /*! @brief Set the CH3OM field to a new value. */
1962 #define BW_FTM_OUTMASK_CH3OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH3OM) = (v))
1966 * @name Register FTM_OUTMASK, field CH4OM[4] (RW)
1968 * Defines if the channel output is masked or unmasked.
1971 * - 0 - Channel output is not masked. It continues to operate normally.
1972 * - 1 - Channel output is masked. It is forced to its inactive state.
1975 #define BP_FTM_OUTMASK_CH4OM (4U) /*!< Bit position for FTM_OUTMASK_CH4OM. */
1976 #define BM_FTM_OUTMASK_CH4OM (0x00000010U) /*!< Bit mask for FTM_OUTMASK_CH4OM. */
1977 #define BS_FTM_OUTMASK_CH4OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH4OM. */
1979 /*! @brief Read current value of the FTM_OUTMASK_CH4OM field. */
1980 #define BR_FTM_OUTMASK_CH4OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH4OM))
1982 /*! @brief Format value for bitfield FTM_OUTMASK_CH4OM. */
1983 #define BF_FTM_OUTMASK_CH4OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH4OM) & BM_FTM_OUTMASK_CH4OM)
1985 /*! @brief Set the CH4OM field to a new value. */
1986 #define BW_FTM_OUTMASK_CH4OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH4OM) = (v))
1990 * @name Register FTM_OUTMASK, field CH5OM[5] (RW)
1992 * Defines if the channel output is masked or unmasked.
1995 * - 0 - Channel output is not masked. It continues to operate normally.
1996 * - 1 - Channel output is masked. It is forced to its inactive state.
1999 #define BP_FTM_OUTMASK_CH5OM (5U) /*!< Bit position for FTM_OUTMASK_CH5OM. */
2000 #define BM_FTM_OUTMASK_CH5OM (0x00000020U) /*!< Bit mask for FTM_OUTMASK_CH5OM. */
2001 #define BS_FTM_OUTMASK_CH5OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH5OM. */
2003 /*! @brief Read current value of the FTM_OUTMASK_CH5OM field. */
2004 #define BR_FTM_OUTMASK_CH5OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH5OM))
2006 /*! @brief Format value for bitfield FTM_OUTMASK_CH5OM. */
2007 #define BF_FTM_OUTMASK_CH5OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH5OM) & BM_FTM_OUTMASK_CH5OM)
2009 /*! @brief Set the CH5OM field to a new value. */
2010 #define BW_FTM_OUTMASK_CH5OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH5OM) = (v))
2014 * @name Register FTM_OUTMASK, field CH6OM[6] (RW)
2016 * Defines if the channel output is masked or unmasked.
2019 * - 0 - Channel output is not masked. It continues to operate normally.
2020 * - 1 - Channel output is masked. It is forced to its inactive state.
2023 #define BP_FTM_OUTMASK_CH6OM (6U) /*!< Bit position for FTM_OUTMASK_CH6OM. */
2024 #define BM_FTM_OUTMASK_CH6OM (0x00000040U) /*!< Bit mask for FTM_OUTMASK_CH6OM. */
2025 #define BS_FTM_OUTMASK_CH6OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH6OM. */
2027 /*! @brief Read current value of the FTM_OUTMASK_CH6OM field. */
2028 #define BR_FTM_OUTMASK_CH6OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH6OM))
2030 /*! @brief Format value for bitfield FTM_OUTMASK_CH6OM. */
2031 #define BF_FTM_OUTMASK_CH6OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH6OM) & BM_FTM_OUTMASK_CH6OM)
2033 /*! @brief Set the CH6OM field to a new value. */
2034 #define BW_FTM_OUTMASK_CH6OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH6OM) = (v))
2038 * @name Register FTM_OUTMASK, field CH7OM[7] (RW)
2040 * Defines if the channel output is masked or unmasked.
2043 * - 0 - Channel output is not masked. It continues to operate normally.
2044 * - 1 - Channel output is masked. It is forced to its inactive state.
2047 #define BP_FTM_OUTMASK_CH7OM (7U) /*!< Bit position for FTM_OUTMASK_CH7OM. */
2048 #define BM_FTM_OUTMASK_CH7OM (0x00000080U) /*!< Bit mask for FTM_OUTMASK_CH7OM. */
2049 #define BS_FTM_OUTMASK_CH7OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH7OM. */
2051 /*! @brief Read current value of the FTM_OUTMASK_CH7OM field. */
2052 #define BR_FTM_OUTMASK_CH7OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH7OM))
2054 /*! @brief Format value for bitfield FTM_OUTMASK_CH7OM. */
2055 #define BF_FTM_OUTMASK_CH7OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH7OM) & BM_FTM_OUTMASK_CH7OM)
2057 /*! @brief Set the CH7OM field to a new value. */
2058 #define BW_FTM_OUTMASK_CH7OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH7OM) = (v))
2061 /*******************************************************************************
2062 * HW_FTM_COMBINE - Function For Linked Channels
2063 ******************************************************************************/
2066 * @brief HW_FTM_COMBINE - Function For Linked Channels (RW)
2068 * Reset value: 0x00000000U
2070 * This register contains the control bits used to configure the fault control,
2071 * synchronization, deadtime insertion, Dual Edge Capture mode, Complementary,
2072 * and Combine mode for each pair of channels (n) and (n+1), where n equals 0, 2,
2075 typedef union _hw_ftm_combine
2078 struct _hw_ftm_combine_bitfields
2080 uint32_t COMBINE0
: 1; /*!< [0] Combine Channels For n = 0 */
2081 uint32_t COMP0
: 1; /*!< [1] Complement Of Channel (n) For n = 0 */
2082 uint32_t DECAPEN0
: 1; /*!< [2] Dual Edge Capture Mode Enable For n =
2084 uint32_t DECAP0
: 1; /*!< [3] Dual Edge Capture Mode Captures For n =
2086 uint32_t DTEN0
: 1; /*!< [4] Deadtime Enable For n = 0 */
2087 uint32_t SYNCEN0
: 1; /*!< [5] Synchronization Enable For n = 0 */
2088 uint32_t FAULTEN0
: 1; /*!< [6] Fault Control Enable For n = 0 */
2089 uint32_t RESERVED0
: 1; /*!< [7] */
2090 uint32_t COMBINE1
: 1; /*!< [8] Combine Channels For n = 2 */
2091 uint32_t COMP1
: 1; /*!< [9] Complement Of Channel (n) For n = 2 */
2092 uint32_t DECAPEN1
: 1; /*!< [10] Dual Edge Capture Mode Enable For n
2094 uint32_t DECAP1
: 1; /*!< [11] Dual Edge Capture Mode Captures For n
2096 uint32_t DTEN1
: 1; /*!< [12] Deadtime Enable For n = 2 */
2097 uint32_t SYNCEN1
: 1; /*!< [13] Synchronization Enable For n = 2 */
2098 uint32_t FAULTEN1
: 1; /*!< [14] Fault Control Enable For n = 2 */
2099 uint32_t RESERVED1
: 1; /*!< [15] */
2100 uint32_t COMBINE2
: 1; /*!< [16] Combine Channels For n = 4 */
2101 uint32_t COMP2
: 1; /*!< [17] Complement Of Channel (n) For n = 4 */
2102 uint32_t DECAPEN2
: 1; /*!< [18] Dual Edge Capture Mode Enable For n
2104 uint32_t DECAP2
: 1; /*!< [19] Dual Edge Capture Mode Captures For n
2106 uint32_t DTEN2
: 1; /*!< [20] Deadtime Enable For n = 4 */
2107 uint32_t SYNCEN2
: 1; /*!< [21] Synchronization Enable For n = 4 */
2108 uint32_t FAULTEN2
: 1; /*!< [22] Fault Control Enable For n = 4 */
2109 uint32_t RESERVED2
: 1; /*!< [23] */
2110 uint32_t COMBINE3
: 1; /*!< [24] Combine Channels For n = 6 */
2111 uint32_t COMP3
: 1; /*!< [25] Complement Of Channel (n) for n = 6 */
2112 uint32_t DECAPEN3
: 1; /*!< [26] Dual Edge Capture Mode Enable For n
2114 uint32_t DECAP3
: 1; /*!< [27] Dual Edge Capture Mode Captures For n
2116 uint32_t DTEN3
: 1; /*!< [28] Deadtime Enable For n = 6 */
2117 uint32_t SYNCEN3
: 1; /*!< [29] Synchronization Enable For n = 6 */
2118 uint32_t FAULTEN3
: 1; /*!< [30] Fault Control Enable For n = 6 */
2119 uint32_t RESERVED3
: 1; /*!< [31] */
2124 * @name Constants and macros for entire FTM_COMBINE register
2127 #define HW_FTM_COMBINE_ADDR(x) ((x) + 0x64U)
2129 #define HW_FTM_COMBINE(x) (*(__IO hw_ftm_combine_t *) HW_FTM_COMBINE_ADDR(x))
2130 #define HW_FTM_COMBINE_RD(x) (HW_FTM_COMBINE(x).U)
2131 #define HW_FTM_COMBINE_WR(x, v) (HW_FTM_COMBINE(x).U = (v))
2132 #define HW_FTM_COMBINE_SET(x, v) (HW_FTM_COMBINE_WR(x, HW_FTM_COMBINE_RD(x) | (v)))
2133 #define HW_FTM_COMBINE_CLR(x, v) (HW_FTM_COMBINE_WR(x, HW_FTM_COMBINE_RD(x) & ~(v)))
2134 #define HW_FTM_COMBINE_TOG(x, v) (HW_FTM_COMBINE_WR(x, HW_FTM_COMBINE_RD(x) ^ (v)))
2138 * Constants & macros for individual FTM_COMBINE bitfields
2142 * @name Register FTM_COMBINE, field COMBINE0[0] (RW)
2144 * Enables the combine feature for channels (n) and (n+1). This field is write
2145 * protected. It can be written only when MODE[WPDIS] = 1.
2148 * - 0 - Channels (n) and (n+1) are independent.
2149 * - 1 - Channels (n) and (n+1) are combined.
2152 #define BP_FTM_COMBINE_COMBINE0 (0U) /*!< Bit position for FTM_COMBINE_COMBINE0. */
2153 #define BM_FTM_COMBINE_COMBINE0 (0x00000001U) /*!< Bit mask for FTM_COMBINE_COMBINE0. */
2154 #define BS_FTM_COMBINE_COMBINE0 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMBINE0. */
2156 /*! @brief Read current value of the FTM_COMBINE_COMBINE0 field. */
2157 #define BR_FTM_COMBINE_COMBINE0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE0))
2159 /*! @brief Format value for bitfield FTM_COMBINE_COMBINE0. */
2160 #define BF_FTM_COMBINE_COMBINE0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMBINE0) & BM_FTM_COMBINE_COMBINE0)
2162 /*! @brief Set the COMBINE0 field to a new value. */
2163 #define BW_FTM_COMBINE_COMBINE0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE0) = (v))
2167 * @name Register FTM_COMBINE, field COMP0[1] (RW)
2169 * Enables Complementary mode for the combined channels. In Complementary mode
2170 * the channel (n+1) output is the inverse of the channel (n) output. This field
2171 * is write protected. It can be written only when MODE[WPDIS] = 1.
2174 * - 0 - The channel (n+1) output is the same as the channel (n) output.
2175 * - 1 - The channel (n+1) output is the complement of the channel (n) output.
2178 #define BP_FTM_COMBINE_COMP0 (1U) /*!< Bit position for FTM_COMBINE_COMP0. */
2179 #define BM_FTM_COMBINE_COMP0 (0x00000002U) /*!< Bit mask for FTM_COMBINE_COMP0. */
2180 #define BS_FTM_COMBINE_COMP0 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMP0. */
2182 /*! @brief Read current value of the FTM_COMBINE_COMP0 field. */
2183 #define BR_FTM_COMBINE_COMP0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP0))
2185 /*! @brief Format value for bitfield FTM_COMBINE_COMP0. */
2186 #define BF_FTM_COMBINE_COMP0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMP0) & BM_FTM_COMBINE_COMP0)
2188 /*! @brief Set the COMP0 field to a new value. */
2189 #define BW_FTM_COMBINE_COMP0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP0) = (v))
2193 * @name Register FTM_COMBINE, field DECAPEN0[2] (RW)
2195 * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
2196 * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
2197 * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
2198 * when FTMEN = 1. This field is write protected. It can be written only when
2202 * - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
2203 * - 1 - The Dual Edge Capture mode in this pair of channels is enabled.
2206 #define BP_FTM_COMBINE_DECAPEN0 (2U) /*!< Bit position for FTM_COMBINE_DECAPEN0. */
2207 #define BM_FTM_COMBINE_DECAPEN0 (0x00000004U) /*!< Bit mask for FTM_COMBINE_DECAPEN0. */
2208 #define BS_FTM_COMBINE_DECAPEN0 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAPEN0. */
2210 /*! @brief Read current value of the FTM_COMBINE_DECAPEN0 field. */
2211 #define BR_FTM_COMBINE_DECAPEN0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN0))
2213 /*! @brief Format value for bitfield FTM_COMBINE_DECAPEN0. */
2214 #define BF_FTM_COMBINE_DECAPEN0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAPEN0) & BM_FTM_COMBINE_DECAPEN0)
2216 /*! @brief Set the DECAPEN0 field to a new value. */
2217 #define BW_FTM_COMBINE_DECAPEN0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN0) = (v))
2221 * @name Register FTM_COMBINE, field DECAP0[3] (RW)
2223 * Enables the capture of the FTM counter value according to the channel (n)
2224 * input event and the configuration of the dual edge capture bits. This field
2225 * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
2226 * hardware if dual edge capture - one-shot mode is selected and when the capture
2227 * of channel (n+1) event is made.
2230 * - 0 - The dual edge captures are inactive.
2231 * - 1 - The dual edge captures are active.
2234 #define BP_FTM_COMBINE_DECAP0 (3U) /*!< Bit position for FTM_COMBINE_DECAP0. */
2235 #define BM_FTM_COMBINE_DECAP0 (0x00000008U) /*!< Bit mask for FTM_COMBINE_DECAP0. */
2236 #define BS_FTM_COMBINE_DECAP0 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAP0. */
2238 /*! @brief Read current value of the FTM_COMBINE_DECAP0 field. */
2239 #define BR_FTM_COMBINE_DECAP0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP0))
2241 /*! @brief Format value for bitfield FTM_COMBINE_DECAP0. */
2242 #define BF_FTM_COMBINE_DECAP0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAP0) & BM_FTM_COMBINE_DECAP0)
2244 /*! @brief Set the DECAP0 field to a new value. */
2245 #define BW_FTM_COMBINE_DECAP0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP0) = (v))
2249 * @name Register FTM_COMBINE, field DTEN0[4] (RW)
2251 * Enables the deadtime insertion in the channels (n) and (n+1). This field is
2252 * write protected. It can be written only when MODE[WPDIS] = 1.
2255 * - 0 - The deadtime insertion in this pair of channels is disabled.
2256 * - 1 - The deadtime insertion in this pair of channels is enabled.
2259 #define BP_FTM_COMBINE_DTEN0 (4U) /*!< Bit position for FTM_COMBINE_DTEN0. */
2260 #define BM_FTM_COMBINE_DTEN0 (0x00000010U) /*!< Bit mask for FTM_COMBINE_DTEN0. */
2261 #define BS_FTM_COMBINE_DTEN0 (1U) /*!< Bit field size in bits for FTM_COMBINE_DTEN0. */
2263 /*! @brief Read current value of the FTM_COMBINE_DTEN0 field. */
2264 #define BR_FTM_COMBINE_DTEN0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN0))
2266 /*! @brief Format value for bitfield FTM_COMBINE_DTEN0. */
2267 #define BF_FTM_COMBINE_DTEN0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DTEN0) & BM_FTM_COMBINE_DTEN0)
2269 /*! @brief Set the DTEN0 field to a new value. */
2270 #define BW_FTM_COMBINE_DTEN0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN0) = (v))
2274 * @name Register FTM_COMBINE, field SYNCEN0[5] (RW)
2276 * Enables PWM synchronization of registers C(n)V and C(n+1)V.
2279 * - 0 - The PWM synchronization in this pair of channels is disabled.
2280 * - 1 - The PWM synchronization in this pair of channels is enabled.
2283 #define BP_FTM_COMBINE_SYNCEN0 (5U) /*!< Bit position for FTM_COMBINE_SYNCEN0. */
2284 #define BM_FTM_COMBINE_SYNCEN0 (0x00000020U) /*!< Bit mask for FTM_COMBINE_SYNCEN0. */
2285 #define BS_FTM_COMBINE_SYNCEN0 (1U) /*!< Bit field size in bits for FTM_COMBINE_SYNCEN0. */
2287 /*! @brief Read current value of the FTM_COMBINE_SYNCEN0 field. */
2288 #define BR_FTM_COMBINE_SYNCEN0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN0))
2290 /*! @brief Format value for bitfield FTM_COMBINE_SYNCEN0. */
2291 #define BF_FTM_COMBINE_SYNCEN0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_SYNCEN0) & BM_FTM_COMBINE_SYNCEN0)
2293 /*! @brief Set the SYNCEN0 field to a new value. */
2294 #define BW_FTM_COMBINE_SYNCEN0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN0) = (v))
2298 * @name Register FTM_COMBINE, field FAULTEN0[6] (RW)
2300 * Enables the fault control in channels (n) and (n+1). This field is write
2301 * protected. It can be written only when MODE[WPDIS] = 1.
2304 * - 0 - The fault control in this pair of channels is disabled.
2305 * - 1 - The fault control in this pair of channels is enabled.
2308 #define BP_FTM_COMBINE_FAULTEN0 (6U) /*!< Bit position for FTM_COMBINE_FAULTEN0. */
2309 #define BM_FTM_COMBINE_FAULTEN0 (0x00000040U) /*!< Bit mask for FTM_COMBINE_FAULTEN0. */
2310 #define BS_FTM_COMBINE_FAULTEN0 (1U) /*!< Bit field size in bits for FTM_COMBINE_FAULTEN0. */
2312 /*! @brief Read current value of the FTM_COMBINE_FAULTEN0 field. */
2313 #define BR_FTM_COMBINE_FAULTEN0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN0))
2315 /*! @brief Format value for bitfield FTM_COMBINE_FAULTEN0. */
2316 #define BF_FTM_COMBINE_FAULTEN0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_FAULTEN0) & BM_FTM_COMBINE_FAULTEN0)
2318 /*! @brief Set the FAULTEN0 field to a new value. */
2319 #define BW_FTM_COMBINE_FAULTEN0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN0) = (v))
2323 * @name Register FTM_COMBINE, field COMBINE1[8] (RW)
2325 * Enables the combine feature for channels (n) and (n+1). This field is write
2326 * protected. It can be written only when MODE[WPDIS] = 1.
2329 * - 0 - Channels (n) and (n+1) are independent.
2330 * - 1 - Channels (n) and (n+1) are combined.
2333 #define BP_FTM_COMBINE_COMBINE1 (8U) /*!< Bit position for FTM_COMBINE_COMBINE1. */
2334 #define BM_FTM_COMBINE_COMBINE1 (0x00000100U) /*!< Bit mask for FTM_COMBINE_COMBINE1. */
2335 #define BS_FTM_COMBINE_COMBINE1 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMBINE1. */
2337 /*! @brief Read current value of the FTM_COMBINE_COMBINE1 field. */
2338 #define BR_FTM_COMBINE_COMBINE1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE1))
2340 /*! @brief Format value for bitfield FTM_COMBINE_COMBINE1. */
2341 #define BF_FTM_COMBINE_COMBINE1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMBINE1) & BM_FTM_COMBINE_COMBINE1)
2343 /*! @brief Set the COMBINE1 field to a new value. */
2344 #define BW_FTM_COMBINE_COMBINE1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE1) = (v))
2348 * @name Register FTM_COMBINE, field COMP1[9] (RW)
2350 * Enables Complementary mode for the combined channels. In Complementary mode
2351 * the channel (n+1) output is the inverse of the channel (n) output. This field
2352 * is write protected. It can be written only when MODE[WPDIS] = 1.
2355 * - 0 - The channel (n+1) output is the same as the channel (n) output.
2356 * - 1 - The channel (n+1) output is the complement of the channel (n) output.
2359 #define BP_FTM_COMBINE_COMP1 (9U) /*!< Bit position for FTM_COMBINE_COMP1. */
2360 #define BM_FTM_COMBINE_COMP1 (0x00000200U) /*!< Bit mask for FTM_COMBINE_COMP1. */
2361 #define BS_FTM_COMBINE_COMP1 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMP1. */
2363 /*! @brief Read current value of the FTM_COMBINE_COMP1 field. */
2364 #define BR_FTM_COMBINE_COMP1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP1))
2366 /*! @brief Format value for bitfield FTM_COMBINE_COMP1. */
2367 #define BF_FTM_COMBINE_COMP1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMP1) & BM_FTM_COMBINE_COMP1)
2369 /*! @brief Set the COMP1 field to a new value. */
2370 #define BW_FTM_COMBINE_COMP1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP1) = (v))
2374 * @name Register FTM_COMBINE, field DECAPEN1[10] (RW)
2376 * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
2377 * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
2378 * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
2379 * when FTMEN = 1. This field is write protected. It can be written only when
2383 * - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
2384 * - 1 - The Dual Edge Capture mode in this pair of channels is enabled.
2387 #define BP_FTM_COMBINE_DECAPEN1 (10U) /*!< Bit position for FTM_COMBINE_DECAPEN1. */
2388 #define BM_FTM_COMBINE_DECAPEN1 (0x00000400U) /*!< Bit mask for FTM_COMBINE_DECAPEN1. */
2389 #define BS_FTM_COMBINE_DECAPEN1 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAPEN1. */
2391 /*! @brief Read current value of the FTM_COMBINE_DECAPEN1 field. */
2392 #define BR_FTM_COMBINE_DECAPEN1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN1))
2394 /*! @brief Format value for bitfield FTM_COMBINE_DECAPEN1. */
2395 #define BF_FTM_COMBINE_DECAPEN1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAPEN1) & BM_FTM_COMBINE_DECAPEN1)
2397 /*! @brief Set the DECAPEN1 field to a new value. */
2398 #define BW_FTM_COMBINE_DECAPEN1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN1) = (v))
2402 * @name Register FTM_COMBINE, field DECAP1[11] (RW)
2404 * Enables the capture of the FTM counter value according to the channel (n)
2405 * input event and the configuration of the dual edge capture bits. This field
2406 * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
2407 * hardware if Dual Edge Capture - One-Shot mode is selected and when the capture
2408 * of channel (n+1) event is made.
2411 * - 0 - The dual edge captures are inactive.
2412 * - 1 - The dual edge captures are active.
2415 #define BP_FTM_COMBINE_DECAP1 (11U) /*!< Bit position for FTM_COMBINE_DECAP1. */
2416 #define BM_FTM_COMBINE_DECAP1 (0x00000800U) /*!< Bit mask for FTM_COMBINE_DECAP1. */
2417 #define BS_FTM_COMBINE_DECAP1 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAP1. */
2419 /*! @brief Read current value of the FTM_COMBINE_DECAP1 field. */
2420 #define BR_FTM_COMBINE_DECAP1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP1))
2422 /*! @brief Format value for bitfield FTM_COMBINE_DECAP1. */
2423 #define BF_FTM_COMBINE_DECAP1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAP1) & BM_FTM_COMBINE_DECAP1)
2425 /*! @brief Set the DECAP1 field to a new value. */
2426 #define BW_FTM_COMBINE_DECAP1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP1) = (v))
2430 * @name Register FTM_COMBINE, field DTEN1[12] (RW)
2432 * Enables the deadtime insertion in the channels (n) and (n+1). This field is
2433 * write protected. It can be written only when MODE[WPDIS] = 1.
2436 * - 0 - The deadtime insertion in this pair of channels is disabled.
2437 * - 1 - The deadtime insertion in this pair of channels is enabled.
2440 #define BP_FTM_COMBINE_DTEN1 (12U) /*!< Bit position for FTM_COMBINE_DTEN1. */
2441 #define BM_FTM_COMBINE_DTEN1 (0x00001000U) /*!< Bit mask for FTM_COMBINE_DTEN1. */
2442 #define BS_FTM_COMBINE_DTEN1 (1U) /*!< Bit field size in bits for FTM_COMBINE_DTEN1. */
2444 /*! @brief Read current value of the FTM_COMBINE_DTEN1 field. */
2445 #define BR_FTM_COMBINE_DTEN1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN1))
2447 /*! @brief Format value for bitfield FTM_COMBINE_DTEN1. */
2448 #define BF_FTM_COMBINE_DTEN1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DTEN1) & BM_FTM_COMBINE_DTEN1)
2450 /*! @brief Set the DTEN1 field to a new value. */
2451 #define BW_FTM_COMBINE_DTEN1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN1) = (v))
2455 * @name Register FTM_COMBINE, field SYNCEN1[13] (RW)
2457 * Enables PWM synchronization of registers C(n)V and C(n+1)V.
2460 * - 0 - The PWM synchronization in this pair of channels is disabled.
2461 * - 1 - The PWM synchronization in this pair of channels is enabled.
2464 #define BP_FTM_COMBINE_SYNCEN1 (13U) /*!< Bit position for FTM_COMBINE_SYNCEN1. */
2465 #define BM_FTM_COMBINE_SYNCEN1 (0x00002000U) /*!< Bit mask for FTM_COMBINE_SYNCEN1. */
2466 #define BS_FTM_COMBINE_SYNCEN1 (1U) /*!< Bit field size in bits for FTM_COMBINE_SYNCEN1. */
2468 /*! @brief Read current value of the FTM_COMBINE_SYNCEN1 field. */
2469 #define BR_FTM_COMBINE_SYNCEN1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN1))
2471 /*! @brief Format value for bitfield FTM_COMBINE_SYNCEN1. */
2472 #define BF_FTM_COMBINE_SYNCEN1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_SYNCEN1) & BM_FTM_COMBINE_SYNCEN1)
2474 /*! @brief Set the SYNCEN1 field to a new value. */
2475 #define BW_FTM_COMBINE_SYNCEN1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN1) = (v))
2479 * @name Register FTM_COMBINE, field FAULTEN1[14] (RW)
2481 * Enables the fault control in channels (n) and (n+1). This field is write
2482 * protected. It can be written only when MODE[WPDIS] = 1.
2485 * - 0 - The fault control in this pair of channels is disabled.
2486 * - 1 - The fault control in this pair of channels is enabled.
2489 #define BP_FTM_COMBINE_FAULTEN1 (14U) /*!< Bit position for FTM_COMBINE_FAULTEN1. */
2490 #define BM_FTM_COMBINE_FAULTEN1 (0x00004000U) /*!< Bit mask for FTM_COMBINE_FAULTEN1. */
2491 #define BS_FTM_COMBINE_FAULTEN1 (1U) /*!< Bit field size in bits for FTM_COMBINE_FAULTEN1. */
2493 /*! @brief Read current value of the FTM_COMBINE_FAULTEN1 field. */
2494 #define BR_FTM_COMBINE_FAULTEN1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN1))
2496 /*! @brief Format value for bitfield FTM_COMBINE_FAULTEN1. */
2497 #define BF_FTM_COMBINE_FAULTEN1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_FAULTEN1) & BM_FTM_COMBINE_FAULTEN1)
2499 /*! @brief Set the FAULTEN1 field to a new value. */
2500 #define BW_FTM_COMBINE_FAULTEN1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN1) = (v))
2504 * @name Register FTM_COMBINE, field COMBINE2[16] (RW)
2506 * Enables the combine feature for channels (n) and (n+1). This field is write
2507 * protected. It can be written only when MODE[WPDIS] = 1.
2510 * - 0 - Channels (n) and (n+1) are independent.
2511 * - 1 - Channels (n) and (n+1) are combined.
2514 #define BP_FTM_COMBINE_COMBINE2 (16U) /*!< Bit position for FTM_COMBINE_COMBINE2. */
2515 #define BM_FTM_COMBINE_COMBINE2 (0x00010000U) /*!< Bit mask for FTM_COMBINE_COMBINE2. */
2516 #define BS_FTM_COMBINE_COMBINE2 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMBINE2. */
2518 /*! @brief Read current value of the FTM_COMBINE_COMBINE2 field. */
2519 #define BR_FTM_COMBINE_COMBINE2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE2))
2521 /*! @brief Format value for bitfield FTM_COMBINE_COMBINE2. */
2522 #define BF_FTM_COMBINE_COMBINE2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMBINE2) & BM_FTM_COMBINE_COMBINE2)
2524 /*! @brief Set the COMBINE2 field to a new value. */
2525 #define BW_FTM_COMBINE_COMBINE2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE2) = (v))
2529 * @name Register FTM_COMBINE, field COMP2[17] (RW)
2531 * Enables Complementary mode for the combined channels. In Complementary mode
2532 * the channel (n+1) output is the inverse of the channel (n) output. This field
2533 * is write protected. It can be written only when MODE[WPDIS] = 1.
2536 * - 0 - The channel (n+1) output is the same as the channel (n) output.
2537 * - 1 - The channel (n+1) output is the complement of the channel (n) output.
2540 #define BP_FTM_COMBINE_COMP2 (17U) /*!< Bit position for FTM_COMBINE_COMP2. */
2541 #define BM_FTM_COMBINE_COMP2 (0x00020000U) /*!< Bit mask for FTM_COMBINE_COMP2. */
2542 #define BS_FTM_COMBINE_COMP2 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMP2. */
2544 /*! @brief Read current value of the FTM_COMBINE_COMP2 field. */
2545 #define BR_FTM_COMBINE_COMP2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP2))
2547 /*! @brief Format value for bitfield FTM_COMBINE_COMP2. */
2548 #define BF_FTM_COMBINE_COMP2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMP2) & BM_FTM_COMBINE_COMP2)
2550 /*! @brief Set the COMP2 field to a new value. */
2551 #define BW_FTM_COMBINE_COMP2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP2) = (v))
2555 * @name Register FTM_COMBINE, field DECAPEN2[18] (RW)
2557 * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
2558 * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
2559 * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
2560 * when FTMEN = 1. This field is write protected. It can be written only when
2564 * - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
2565 * - 1 - The Dual Edge Capture mode in this pair of channels is enabled.
2568 #define BP_FTM_COMBINE_DECAPEN2 (18U) /*!< Bit position for FTM_COMBINE_DECAPEN2. */
2569 #define BM_FTM_COMBINE_DECAPEN2 (0x00040000U) /*!< Bit mask for FTM_COMBINE_DECAPEN2. */
2570 #define BS_FTM_COMBINE_DECAPEN2 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAPEN2. */
2572 /*! @brief Read current value of the FTM_COMBINE_DECAPEN2 field. */
2573 #define BR_FTM_COMBINE_DECAPEN2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN2))
2575 /*! @brief Format value for bitfield FTM_COMBINE_DECAPEN2. */
2576 #define BF_FTM_COMBINE_DECAPEN2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAPEN2) & BM_FTM_COMBINE_DECAPEN2)
2578 /*! @brief Set the DECAPEN2 field to a new value. */
2579 #define BW_FTM_COMBINE_DECAPEN2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN2) = (v))
2583 * @name Register FTM_COMBINE, field DECAP2[19] (RW)
2585 * Enables the capture of the FTM counter value according to the channel (n)
2586 * input event and the configuration of the dual edge capture bits. This field
2587 * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
2588 * hardware if dual edge capture - one-shot mode is selected and when the capture
2589 * of channel (n+1) event is made.
2592 * - 0 - The dual edge captures are inactive.
2593 * - 1 - The dual edge captures are active.
2596 #define BP_FTM_COMBINE_DECAP2 (19U) /*!< Bit position for FTM_COMBINE_DECAP2. */
2597 #define BM_FTM_COMBINE_DECAP2 (0x00080000U) /*!< Bit mask for FTM_COMBINE_DECAP2. */
2598 #define BS_FTM_COMBINE_DECAP2 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAP2. */
2600 /*! @brief Read current value of the FTM_COMBINE_DECAP2 field. */
2601 #define BR_FTM_COMBINE_DECAP2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP2))
2603 /*! @brief Format value for bitfield FTM_COMBINE_DECAP2. */
2604 #define BF_FTM_COMBINE_DECAP2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAP2) & BM_FTM_COMBINE_DECAP2)
2606 /*! @brief Set the DECAP2 field to a new value. */
2607 #define BW_FTM_COMBINE_DECAP2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP2) = (v))
2611 * @name Register FTM_COMBINE, field DTEN2[20] (RW)
2613 * Enables the deadtime insertion in the channels (n) and (n+1). This field is
2614 * write protected. It can be written only when MODE[WPDIS] = 1.
2617 * - 0 - The deadtime insertion in this pair of channels is disabled.
2618 * - 1 - The deadtime insertion in this pair of channels is enabled.
2621 #define BP_FTM_COMBINE_DTEN2 (20U) /*!< Bit position for FTM_COMBINE_DTEN2. */
2622 #define BM_FTM_COMBINE_DTEN2 (0x00100000U) /*!< Bit mask for FTM_COMBINE_DTEN2. */
2623 #define BS_FTM_COMBINE_DTEN2 (1U) /*!< Bit field size in bits for FTM_COMBINE_DTEN2. */
2625 /*! @brief Read current value of the FTM_COMBINE_DTEN2 field. */
2626 #define BR_FTM_COMBINE_DTEN2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN2))
2628 /*! @brief Format value for bitfield FTM_COMBINE_DTEN2. */
2629 #define BF_FTM_COMBINE_DTEN2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DTEN2) & BM_FTM_COMBINE_DTEN2)
2631 /*! @brief Set the DTEN2 field to a new value. */
2632 #define BW_FTM_COMBINE_DTEN2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN2) = (v))
2636 * @name Register FTM_COMBINE, field SYNCEN2[21] (RW)
2638 * Enables PWM synchronization of registers C(n)V and C(n+1)V.
2641 * - 0 - The PWM synchronization in this pair of channels is disabled.
2642 * - 1 - The PWM synchronization in this pair of channels is enabled.
2645 #define BP_FTM_COMBINE_SYNCEN2 (21U) /*!< Bit position for FTM_COMBINE_SYNCEN2. */
2646 #define BM_FTM_COMBINE_SYNCEN2 (0x00200000U) /*!< Bit mask for FTM_COMBINE_SYNCEN2. */
2647 #define BS_FTM_COMBINE_SYNCEN2 (1U) /*!< Bit field size in bits for FTM_COMBINE_SYNCEN2. */
2649 /*! @brief Read current value of the FTM_COMBINE_SYNCEN2 field. */
2650 #define BR_FTM_COMBINE_SYNCEN2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN2))
2652 /*! @brief Format value for bitfield FTM_COMBINE_SYNCEN2. */
2653 #define BF_FTM_COMBINE_SYNCEN2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_SYNCEN2) & BM_FTM_COMBINE_SYNCEN2)
2655 /*! @brief Set the SYNCEN2 field to a new value. */
2656 #define BW_FTM_COMBINE_SYNCEN2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN2) = (v))
2660 * @name Register FTM_COMBINE, field FAULTEN2[22] (RW)
2662 * Enables the fault control in channels (n) and (n+1). This field is write
2663 * protected. It can be written only when MODE[WPDIS] = 1.
2666 * - 0 - The fault control in this pair of channels is disabled.
2667 * - 1 - The fault control in this pair of channels is enabled.
2670 #define BP_FTM_COMBINE_FAULTEN2 (22U) /*!< Bit position for FTM_COMBINE_FAULTEN2. */
2671 #define BM_FTM_COMBINE_FAULTEN2 (0x00400000U) /*!< Bit mask for FTM_COMBINE_FAULTEN2. */
2672 #define BS_FTM_COMBINE_FAULTEN2 (1U) /*!< Bit field size in bits for FTM_COMBINE_FAULTEN2. */
2674 /*! @brief Read current value of the FTM_COMBINE_FAULTEN2 field. */
2675 #define BR_FTM_COMBINE_FAULTEN2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN2))
2677 /*! @brief Format value for bitfield FTM_COMBINE_FAULTEN2. */
2678 #define BF_FTM_COMBINE_FAULTEN2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_FAULTEN2) & BM_FTM_COMBINE_FAULTEN2)
2680 /*! @brief Set the FAULTEN2 field to a new value. */
2681 #define BW_FTM_COMBINE_FAULTEN2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN2) = (v))
2685 * @name Register FTM_COMBINE, field COMBINE3[24] (RW)
2687 * Enables the combine feature for channels (n) and (n+1). This field is write
2688 * protected. It can be written only when MODE[WPDIS] = 1.
2691 * - 0 - Channels (n) and (n+1) are independent.
2692 * - 1 - Channels (n) and (n+1) are combined.
2695 #define BP_FTM_COMBINE_COMBINE3 (24U) /*!< Bit position for FTM_COMBINE_COMBINE3. */
2696 #define BM_FTM_COMBINE_COMBINE3 (0x01000000U) /*!< Bit mask for FTM_COMBINE_COMBINE3. */
2697 #define BS_FTM_COMBINE_COMBINE3 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMBINE3. */
2699 /*! @brief Read current value of the FTM_COMBINE_COMBINE3 field. */
2700 #define BR_FTM_COMBINE_COMBINE3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE3))
2702 /*! @brief Format value for bitfield FTM_COMBINE_COMBINE3. */
2703 #define BF_FTM_COMBINE_COMBINE3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMBINE3) & BM_FTM_COMBINE_COMBINE3)
2705 /*! @brief Set the COMBINE3 field to a new value. */
2706 #define BW_FTM_COMBINE_COMBINE3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE3) = (v))
2710 * @name Register FTM_COMBINE, field COMP3[25] (RW)
2712 * Enables Complementary mode for the combined channels. In Complementary mode
2713 * the channel (n+1) output is the inverse of the channel (n) output. This field
2714 * is write protected. It can be written only when MODE[WPDIS] = 1.
2717 * - 0 - The channel (n+1) output is the same as the channel (n) output.
2718 * - 1 - The channel (n+1) output is the complement of the channel (n) output.
2721 #define BP_FTM_COMBINE_COMP3 (25U) /*!< Bit position for FTM_COMBINE_COMP3. */
2722 #define BM_FTM_COMBINE_COMP3 (0x02000000U) /*!< Bit mask for FTM_COMBINE_COMP3. */
2723 #define BS_FTM_COMBINE_COMP3 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMP3. */
2725 /*! @brief Read current value of the FTM_COMBINE_COMP3 field. */
2726 #define BR_FTM_COMBINE_COMP3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP3))
2728 /*! @brief Format value for bitfield FTM_COMBINE_COMP3. */
2729 #define BF_FTM_COMBINE_COMP3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMP3) & BM_FTM_COMBINE_COMP3)
2731 /*! @brief Set the COMP3 field to a new value. */
2732 #define BW_FTM_COMBINE_COMP3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP3) = (v))
2736 * @name Register FTM_COMBINE, field DECAPEN3[26] (RW)
2738 * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
2739 * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
2740 * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
2741 * when FTMEN = 1. This field is write protected. It can be written only when
2745 * - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
2746 * - 1 - The Dual Edge Capture mode in this pair of channels is enabled.
2749 #define BP_FTM_COMBINE_DECAPEN3 (26U) /*!< Bit position for FTM_COMBINE_DECAPEN3. */
2750 #define BM_FTM_COMBINE_DECAPEN3 (0x04000000U) /*!< Bit mask for FTM_COMBINE_DECAPEN3. */
2751 #define BS_FTM_COMBINE_DECAPEN3 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAPEN3. */
2753 /*! @brief Read current value of the FTM_COMBINE_DECAPEN3 field. */
2754 #define BR_FTM_COMBINE_DECAPEN3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN3))
2756 /*! @brief Format value for bitfield FTM_COMBINE_DECAPEN3. */
2757 #define BF_FTM_COMBINE_DECAPEN3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAPEN3) & BM_FTM_COMBINE_DECAPEN3)
2759 /*! @brief Set the DECAPEN3 field to a new value. */
2760 #define BW_FTM_COMBINE_DECAPEN3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN3) = (v))
2764 * @name Register FTM_COMBINE, field DECAP3[27] (RW)
2766 * Enables the capture of the FTM counter value according to the channel (n)
2767 * input event and the configuration of the dual edge capture bits. This field
2768 * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
2769 * hardware if dual edge capture - one-shot mode is selected and when the capture
2770 * of channel (n+1) event is made.
2773 * - 0 - The dual edge captures are inactive.
2774 * - 1 - The dual edge captures are active.
2777 #define BP_FTM_COMBINE_DECAP3 (27U) /*!< Bit position for FTM_COMBINE_DECAP3. */
2778 #define BM_FTM_COMBINE_DECAP3 (0x08000000U) /*!< Bit mask for FTM_COMBINE_DECAP3. */
2779 #define BS_FTM_COMBINE_DECAP3 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAP3. */
2781 /*! @brief Read current value of the FTM_COMBINE_DECAP3 field. */
2782 #define BR_FTM_COMBINE_DECAP3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP3))
2784 /*! @brief Format value for bitfield FTM_COMBINE_DECAP3. */
2785 #define BF_FTM_COMBINE_DECAP3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAP3) & BM_FTM_COMBINE_DECAP3)
2787 /*! @brief Set the DECAP3 field to a new value. */
2788 #define BW_FTM_COMBINE_DECAP3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP3) = (v))
2792 * @name Register FTM_COMBINE, field DTEN3[28] (RW)
2794 * Enables the deadtime insertion in the channels (n) and (n+1). This field is
2795 * write protected. It can be written only when MODE[WPDIS] = 1.
2798 * - 0 - The deadtime insertion in this pair of channels is disabled.
2799 * - 1 - The deadtime insertion in this pair of channels is enabled.
2802 #define BP_FTM_COMBINE_DTEN3 (28U) /*!< Bit position for FTM_COMBINE_DTEN3. */
2803 #define BM_FTM_COMBINE_DTEN3 (0x10000000U) /*!< Bit mask for FTM_COMBINE_DTEN3. */
2804 #define BS_FTM_COMBINE_DTEN3 (1U) /*!< Bit field size in bits for FTM_COMBINE_DTEN3. */
2806 /*! @brief Read current value of the FTM_COMBINE_DTEN3 field. */
2807 #define BR_FTM_COMBINE_DTEN3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN3))
2809 /*! @brief Format value for bitfield FTM_COMBINE_DTEN3. */
2810 #define BF_FTM_COMBINE_DTEN3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DTEN3) & BM_FTM_COMBINE_DTEN3)
2812 /*! @brief Set the DTEN3 field to a new value. */
2813 #define BW_FTM_COMBINE_DTEN3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN3) = (v))
2817 * @name Register FTM_COMBINE, field SYNCEN3[29] (RW)
2819 * Enables PWM synchronization of registers C(n)V and C(n+1)V.
2822 * - 0 - The PWM synchronization in this pair of channels is disabled.
2823 * - 1 - The PWM synchronization in this pair of channels is enabled.
2826 #define BP_FTM_COMBINE_SYNCEN3 (29U) /*!< Bit position for FTM_COMBINE_SYNCEN3. */
2827 #define BM_FTM_COMBINE_SYNCEN3 (0x20000000U) /*!< Bit mask for FTM_COMBINE_SYNCEN3. */
2828 #define BS_FTM_COMBINE_SYNCEN3 (1U) /*!< Bit field size in bits for FTM_COMBINE_SYNCEN3. */
2830 /*! @brief Read current value of the FTM_COMBINE_SYNCEN3 field. */
2831 #define BR_FTM_COMBINE_SYNCEN3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN3))
2833 /*! @brief Format value for bitfield FTM_COMBINE_SYNCEN3. */
2834 #define BF_FTM_COMBINE_SYNCEN3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_SYNCEN3) & BM_FTM_COMBINE_SYNCEN3)
2836 /*! @brief Set the SYNCEN3 field to a new value. */
2837 #define BW_FTM_COMBINE_SYNCEN3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN3) = (v))
2841 * @name Register FTM_COMBINE, field FAULTEN3[30] (RW)
2843 * Enables the fault control in channels (n) and (n+1). This field is write
2844 * protected. It can be written only when MODE[WPDIS] = 1.
2847 * - 0 - The fault control in this pair of channels is disabled.
2848 * - 1 - The fault control in this pair of channels is enabled.
2851 #define BP_FTM_COMBINE_FAULTEN3 (30U) /*!< Bit position for FTM_COMBINE_FAULTEN3. */
2852 #define BM_FTM_COMBINE_FAULTEN3 (0x40000000U) /*!< Bit mask for FTM_COMBINE_FAULTEN3. */
2853 #define BS_FTM_COMBINE_FAULTEN3 (1U) /*!< Bit field size in bits for FTM_COMBINE_FAULTEN3. */
2855 /*! @brief Read current value of the FTM_COMBINE_FAULTEN3 field. */
2856 #define BR_FTM_COMBINE_FAULTEN3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN3))
2858 /*! @brief Format value for bitfield FTM_COMBINE_FAULTEN3. */
2859 #define BF_FTM_COMBINE_FAULTEN3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_FAULTEN3) & BM_FTM_COMBINE_FAULTEN3)
2861 /*! @brief Set the FAULTEN3 field to a new value. */
2862 #define BW_FTM_COMBINE_FAULTEN3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN3) = (v))
2865 /*******************************************************************************
2866 * HW_FTM_DEADTIME - Deadtime Insertion Control
2867 ******************************************************************************/
2870 * @brief HW_FTM_DEADTIME - Deadtime Insertion Control (RW)
2872 * Reset value: 0x00000000U
2874 * This register selects the deadtime prescaler factor and deadtime value. All
2875 * FTM channels use this clock prescaler and this deadtime value for the deadtime
2878 typedef union _hw_ftm_deadtime
2881 struct _hw_ftm_deadtime_bitfields
2883 uint32_t DTVAL
: 6; /*!< [5:0] Deadtime Value */
2884 uint32_t DTPS
: 2; /*!< [7:6] Deadtime Prescaler Value */
2885 uint32_t RESERVED0
: 24; /*!< [31:8] */
2887 } hw_ftm_deadtime_t
;
2890 * @name Constants and macros for entire FTM_DEADTIME register
2893 #define HW_FTM_DEADTIME_ADDR(x) ((x) + 0x68U)
2895 #define HW_FTM_DEADTIME(x) (*(__IO hw_ftm_deadtime_t *) HW_FTM_DEADTIME_ADDR(x))
2896 #define HW_FTM_DEADTIME_RD(x) (HW_FTM_DEADTIME(x).U)
2897 #define HW_FTM_DEADTIME_WR(x, v) (HW_FTM_DEADTIME(x).U = (v))
2898 #define HW_FTM_DEADTIME_SET(x, v) (HW_FTM_DEADTIME_WR(x, HW_FTM_DEADTIME_RD(x) | (v)))
2899 #define HW_FTM_DEADTIME_CLR(x, v) (HW_FTM_DEADTIME_WR(x, HW_FTM_DEADTIME_RD(x) & ~(v)))
2900 #define HW_FTM_DEADTIME_TOG(x, v) (HW_FTM_DEADTIME_WR(x, HW_FTM_DEADTIME_RD(x) ^ (v)))
2904 * Constants & macros for individual FTM_DEADTIME bitfields
2908 * @name Register FTM_DEADTIME, field DTVAL[5:0] (RW)
2910 * Selects the deadtime insertion value for the deadtime counter. The deadtime
2911 * counter is clocked by a scaled version of the system clock. See the description
2912 * of DTPS. Deadtime insert value = (DTPS * DTVAL). DTVAL selects the number of
2913 * deadtime counts inserted as follows: When DTVAL is 0, no counts are inserted.
2914 * When DTVAL is 1, 1 count is inserted. When DTVAL is 2, 2 counts are inserted.
2915 * This pattern continues up to a possible 63 counts. This field is write
2916 * protected. It can be written only when MODE[WPDIS] = 1.
2919 #define BP_FTM_DEADTIME_DTVAL (0U) /*!< Bit position for FTM_DEADTIME_DTVAL. */
2920 #define BM_FTM_DEADTIME_DTVAL (0x0000003FU) /*!< Bit mask for FTM_DEADTIME_DTVAL. */
2921 #define BS_FTM_DEADTIME_DTVAL (6U) /*!< Bit field size in bits for FTM_DEADTIME_DTVAL. */
2923 /*! @brief Read current value of the FTM_DEADTIME_DTVAL field. */
2924 #define BR_FTM_DEADTIME_DTVAL(x) (HW_FTM_DEADTIME(x).B.DTVAL)
2926 /*! @brief Format value for bitfield FTM_DEADTIME_DTVAL. */
2927 #define BF_FTM_DEADTIME_DTVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_DEADTIME_DTVAL) & BM_FTM_DEADTIME_DTVAL)
2929 /*! @brief Set the DTVAL field to a new value. */
2930 #define BW_FTM_DEADTIME_DTVAL(x, v) (HW_FTM_DEADTIME_WR(x, (HW_FTM_DEADTIME_RD(x) & ~BM_FTM_DEADTIME_DTVAL) | BF_FTM_DEADTIME_DTVAL(v)))
2934 * @name Register FTM_DEADTIME, field DTPS[7:6] (RW)
2936 * Selects the division factor of the system clock. This prescaled clock is used
2937 * by the deadtime counter. This field is write protected. It can be written
2938 * only when MODE[WPDIS] = 1.
2941 * - 0x - Divide the system clock by 1.
2942 * - 10 - Divide the system clock by 4.
2943 * - 11 - Divide the system clock by 16.
2946 #define BP_FTM_DEADTIME_DTPS (6U) /*!< Bit position for FTM_DEADTIME_DTPS. */
2947 #define BM_FTM_DEADTIME_DTPS (0x000000C0U) /*!< Bit mask for FTM_DEADTIME_DTPS. */
2948 #define BS_FTM_DEADTIME_DTPS (2U) /*!< Bit field size in bits for FTM_DEADTIME_DTPS. */
2950 /*! @brief Read current value of the FTM_DEADTIME_DTPS field. */
2951 #define BR_FTM_DEADTIME_DTPS(x) (HW_FTM_DEADTIME(x).B.DTPS)
2953 /*! @brief Format value for bitfield FTM_DEADTIME_DTPS. */
2954 #define BF_FTM_DEADTIME_DTPS(v) ((uint32_t)((uint32_t)(v) << BP_FTM_DEADTIME_DTPS) & BM_FTM_DEADTIME_DTPS)
2956 /*! @brief Set the DTPS field to a new value. */
2957 #define BW_FTM_DEADTIME_DTPS(x, v) (HW_FTM_DEADTIME_WR(x, (HW_FTM_DEADTIME_RD(x) & ~BM_FTM_DEADTIME_DTPS) | BF_FTM_DEADTIME_DTPS(v)))
2960 /*******************************************************************************
2961 * HW_FTM_EXTTRIG - FTM External Trigger
2962 ******************************************************************************/
2965 * @brief HW_FTM_EXTTRIG - FTM External Trigger (RW)
2967 * Reset value: 0x00000000U
2969 * This register: Indicates when a channel trigger was generated Enables the
2970 * generation of a trigger when the FTM counter is equal to its initial value
2971 * Selects which channels are used in the generation of the channel triggers Several
2972 * channels can be selected to generate multiple triggers in one PWM period.
2973 * Channels 6 and 7 are not used to generate channel triggers.
2975 typedef union _hw_ftm_exttrig
2978 struct _hw_ftm_exttrig_bitfields
2980 uint32_t CH2TRIG
: 1; /*!< [0] Channel 2 Trigger Enable */
2981 uint32_t CH3TRIG
: 1; /*!< [1] Channel 3 Trigger Enable */
2982 uint32_t CH4TRIG
: 1; /*!< [2] Channel 4 Trigger Enable */
2983 uint32_t CH5TRIG
: 1; /*!< [3] Channel 5 Trigger Enable */
2984 uint32_t CH0TRIG
: 1; /*!< [4] Channel 0 Trigger Enable */
2985 uint32_t CH1TRIG
: 1; /*!< [5] Channel 1 Trigger Enable */
2986 uint32_t INITTRIGEN
: 1; /*!< [6] Initialization Trigger Enable */
2987 uint32_t TRIGF
: 1; /*!< [7] Channel Trigger Flag */
2988 uint32_t RESERVED0
: 24; /*!< [31:8] */
2993 * @name Constants and macros for entire FTM_EXTTRIG register
2996 #define HW_FTM_EXTTRIG_ADDR(x) ((x) + 0x6CU)
2998 #define HW_FTM_EXTTRIG(x) (*(__IO hw_ftm_exttrig_t *) HW_FTM_EXTTRIG_ADDR(x))
2999 #define HW_FTM_EXTTRIG_RD(x) (HW_FTM_EXTTRIG(x).U)
3000 #define HW_FTM_EXTTRIG_WR(x, v) (HW_FTM_EXTTRIG(x).U = (v))
3001 #define HW_FTM_EXTTRIG_SET(x, v) (HW_FTM_EXTTRIG_WR(x, HW_FTM_EXTTRIG_RD(x) | (v)))
3002 #define HW_FTM_EXTTRIG_CLR(x, v) (HW_FTM_EXTTRIG_WR(x, HW_FTM_EXTTRIG_RD(x) & ~(v)))
3003 #define HW_FTM_EXTTRIG_TOG(x, v) (HW_FTM_EXTTRIG_WR(x, HW_FTM_EXTTRIG_RD(x) ^ (v)))
3007 * Constants & macros for individual FTM_EXTTRIG bitfields
3011 * @name Register FTM_EXTTRIG, field CH2TRIG[0] (RW)
3013 * Enables the generation of the channel trigger when the FTM counter is equal
3014 * to the CnV register.
3017 * - 0 - The generation of the channel trigger is disabled.
3018 * - 1 - The generation of the channel trigger is enabled.
3021 #define BP_FTM_EXTTRIG_CH2TRIG (0U) /*!< Bit position for FTM_EXTTRIG_CH2TRIG. */
3022 #define BM_FTM_EXTTRIG_CH2TRIG (0x00000001U) /*!< Bit mask for FTM_EXTTRIG_CH2TRIG. */
3023 #define BS_FTM_EXTTRIG_CH2TRIG (1U) /*!< Bit field size in bits for FTM_EXTTRIG_CH2TRIG. */
3025 /*! @brief Read current value of the FTM_EXTTRIG_CH2TRIG field. */
3026 #define BR_FTM_EXTTRIG_CH2TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH2TRIG))
3028 /*! @brief Format value for bitfield FTM_EXTTRIG_CH2TRIG. */
3029 #define BF_FTM_EXTTRIG_CH2TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH2TRIG) & BM_FTM_EXTTRIG_CH2TRIG)
3031 /*! @brief Set the CH2TRIG field to a new value. */
3032 #define BW_FTM_EXTTRIG_CH2TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH2TRIG) = (v))
3036 * @name Register FTM_EXTTRIG, field CH3TRIG[1] (RW)
3038 * Enables the generation of the channel trigger when the FTM counter is equal
3039 * to the CnV register.
3042 * - 0 - The generation of the channel trigger is disabled.
3043 * - 1 - The generation of the channel trigger is enabled.
3046 #define BP_FTM_EXTTRIG_CH3TRIG (1U) /*!< Bit position for FTM_EXTTRIG_CH3TRIG. */
3047 #define BM_FTM_EXTTRIG_CH3TRIG (0x00000002U) /*!< Bit mask for FTM_EXTTRIG_CH3TRIG. */
3048 #define BS_FTM_EXTTRIG_CH3TRIG (1U) /*!< Bit field size in bits for FTM_EXTTRIG_CH3TRIG. */
3050 /*! @brief Read current value of the FTM_EXTTRIG_CH3TRIG field. */
3051 #define BR_FTM_EXTTRIG_CH3TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH3TRIG))
3053 /*! @brief Format value for bitfield FTM_EXTTRIG_CH3TRIG. */
3054 #define BF_FTM_EXTTRIG_CH3TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH3TRIG) & BM_FTM_EXTTRIG_CH3TRIG)
3056 /*! @brief Set the CH3TRIG field to a new value. */
3057 #define BW_FTM_EXTTRIG_CH3TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH3TRIG) = (v))
3061 * @name Register FTM_EXTTRIG, field CH4TRIG[2] (RW)
3063 * Enables the generation of the channel trigger when the FTM counter is equal
3064 * to the CnV register.
3067 * - 0 - The generation of the channel trigger is disabled.
3068 * - 1 - The generation of the channel trigger is enabled.
3071 #define BP_FTM_EXTTRIG_CH4TRIG (2U) /*!< Bit position for FTM_EXTTRIG_CH4TRIG. */
3072 #define BM_FTM_EXTTRIG_CH4TRIG (0x00000004U) /*!< Bit mask for FTM_EXTTRIG_CH4TRIG. */
3073 #define BS_FTM_EXTTRIG_CH4TRIG (1U) /*!< Bit field size in bits for FTM_EXTTRIG_CH4TRIG. */
3075 /*! @brief Read current value of the FTM_EXTTRIG_CH4TRIG field. */
3076 #define BR_FTM_EXTTRIG_CH4TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH4TRIG))
3078 /*! @brief Format value for bitfield FTM_EXTTRIG_CH4TRIG. */
3079 #define BF_FTM_EXTTRIG_CH4TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH4TRIG) & BM_FTM_EXTTRIG_CH4TRIG)
3081 /*! @brief Set the CH4TRIG field to a new value. */
3082 #define BW_FTM_EXTTRIG_CH4TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH4TRIG) = (v))
3086 * @name Register FTM_EXTTRIG, field CH5TRIG[3] (RW)
3088 * Enables the generation of the channel trigger when the FTM counter is equal
3089 * to the CnV register.
3092 * - 0 - The generation of the channel trigger is disabled.
3093 * - 1 - The generation of the channel trigger is enabled.
3096 #define BP_FTM_EXTTRIG_CH5TRIG (3U) /*!< Bit position for FTM_EXTTRIG_CH5TRIG. */
3097 #define BM_FTM_EXTTRIG_CH5TRIG (0x00000008U) /*!< Bit mask for FTM_EXTTRIG_CH5TRIG. */
3098 #define BS_FTM_EXTTRIG_CH5TRIG (1U) /*!< Bit field size in bits for FTM_EXTTRIG_CH5TRIG. */
3100 /*! @brief Read current value of the FTM_EXTTRIG_CH5TRIG field. */
3101 #define BR_FTM_EXTTRIG_CH5TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH5TRIG))
3103 /*! @brief Format value for bitfield FTM_EXTTRIG_CH5TRIG. */
3104 #define BF_FTM_EXTTRIG_CH5TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH5TRIG) & BM_FTM_EXTTRIG_CH5TRIG)
3106 /*! @brief Set the CH5TRIG field to a new value. */
3107 #define BW_FTM_EXTTRIG_CH5TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH5TRIG) = (v))
3111 * @name Register FTM_EXTTRIG, field CH0TRIG[4] (RW)
3113 * Enables the generation of the channel trigger when the FTM counter is equal
3114 * to the CnV register.
3117 * - 0 - The generation of the channel trigger is disabled.
3118 * - 1 - The generation of the channel trigger is enabled.
3121 #define BP_FTM_EXTTRIG_CH0TRIG (4U) /*!< Bit position for FTM_EXTTRIG_CH0TRIG. */
3122 #define BM_FTM_EXTTRIG_CH0TRIG (0x00000010U) /*!< Bit mask for FTM_EXTTRIG_CH0TRIG. */
3123 #define BS_FTM_EXTTRIG_CH0TRIG (1U) /*!< Bit field size in bits for FTM_EXTTRIG_CH0TRIG. */
3125 /*! @brief Read current value of the FTM_EXTTRIG_CH0TRIG field. */
3126 #define BR_FTM_EXTTRIG_CH0TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH0TRIG))
3128 /*! @brief Format value for bitfield FTM_EXTTRIG_CH0TRIG. */
3129 #define BF_FTM_EXTTRIG_CH0TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH0TRIG) & BM_FTM_EXTTRIG_CH0TRIG)
3131 /*! @brief Set the CH0TRIG field to a new value. */
3132 #define BW_FTM_EXTTRIG_CH0TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH0TRIG) = (v))
3136 * @name Register FTM_EXTTRIG, field CH1TRIG[5] (RW)
3138 * Enables the generation of the channel trigger when the FTM counter is equal
3139 * to the CnV register.
3142 * - 0 - The generation of the channel trigger is disabled.
3143 * - 1 - The generation of the channel trigger is enabled.
3146 #define BP_FTM_EXTTRIG_CH1TRIG (5U) /*!< Bit position for FTM_EXTTRIG_CH1TRIG. */
3147 #define BM_FTM_EXTTRIG_CH1TRIG (0x00000020U) /*!< Bit mask for FTM_EXTTRIG_CH1TRIG. */
3148 #define BS_FTM_EXTTRIG_CH1TRIG (1U) /*!< Bit field size in bits for FTM_EXTTRIG_CH1TRIG. */
3150 /*! @brief Read current value of the FTM_EXTTRIG_CH1TRIG field. */
3151 #define BR_FTM_EXTTRIG_CH1TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH1TRIG))
3153 /*! @brief Format value for bitfield FTM_EXTTRIG_CH1TRIG. */
3154 #define BF_FTM_EXTTRIG_CH1TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH1TRIG) & BM_FTM_EXTTRIG_CH1TRIG)
3156 /*! @brief Set the CH1TRIG field to a new value. */
3157 #define BW_FTM_EXTTRIG_CH1TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH1TRIG) = (v))
3161 * @name Register FTM_EXTTRIG, field INITTRIGEN[6] (RW)
3163 * Enables the generation of the trigger when the FTM counter is equal to the
3167 * - 0 - The generation of initialization trigger is disabled.
3168 * - 1 - The generation of initialization trigger is enabled.
3171 #define BP_FTM_EXTTRIG_INITTRIGEN (6U) /*!< Bit position for FTM_EXTTRIG_INITTRIGEN. */
3172 #define BM_FTM_EXTTRIG_INITTRIGEN (0x00000040U) /*!< Bit mask for FTM_EXTTRIG_INITTRIGEN. */
3173 #define BS_FTM_EXTTRIG_INITTRIGEN (1U) /*!< Bit field size in bits for FTM_EXTTRIG_INITTRIGEN. */
3175 /*! @brief Read current value of the FTM_EXTTRIG_INITTRIGEN field. */
3176 #define BR_FTM_EXTTRIG_INITTRIGEN(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_INITTRIGEN))
3178 /*! @brief Format value for bitfield FTM_EXTTRIG_INITTRIGEN. */
3179 #define BF_FTM_EXTTRIG_INITTRIGEN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_INITTRIGEN) & BM_FTM_EXTTRIG_INITTRIGEN)
3181 /*! @brief Set the INITTRIGEN field to a new value. */
3182 #define BW_FTM_EXTTRIG_INITTRIGEN(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_INITTRIGEN) = (v))
3186 * @name Register FTM_EXTTRIG, field TRIGF[7] (ROWZ)
3188 * Set by hardware when a channel trigger is generated. Clear TRIGF by reading
3189 * EXTTRIG while TRIGF is set and then writing a 0 to TRIGF. Writing a 1 to TRIGF
3190 * has no effect. If another channel trigger is generated before the clearing
3191 * sequence is completed, the sequence is reset so TRIGF remains set after the clear
3192 * sequence is completed for the earlier TRIGF.
3195 * - 0 - No channel trigger was generated.
3196 * - 1 - A channel trigger was generated.
3199 #define BP_FTM_EXTTRIG_TRIGF (7U) /*!< Bit position for FTM_EXTTRIG_TRIGF. */
3200 #define BM_FTM_EXTTRIG_TRIGF (0x00000080U) /*!< Bit mask for FTM_EXTTRIG_TRIGF. */
3201 #define BS_FTM_EXTTRIG_TRIGF (1U) /*!< Bit field size in bits for FTM_EXTTRIG_TRIGF. */
3203 /*! @brief Read current value of the FTM_EXTTRIG_TRIGF field. */
3204 #define BR_FTM_EXTTRIG_TRIGF(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_TRIGF))
3206 /*! @brief Format value for bitfield FTM_EXTTRIG_TRIGF. */
3207 #define BF_FTM_EXTTRIG_TRIGF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_TRIGF) & BM_FTM_EXTTRIG_TRIGF)
3209 /*! @brief Set the TRIGF field to a new value. */
3210 #define BW_FTM_EXTTRIG_TRIGF(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_TRIGF) = (v))
3213 /*******************************************************************************
3214 * HW_FTM_POL - Channels Polarity
3215 ******************************************************************************/
3218 * @brief HW_FTM_POL - Channels Polarity (RW)
3220 * Reset value: 0x00000000U
3222 * This register defines the output polarity of the FTM channels. The safe value
3223 * that is driven in a channel output when the fault control is enabled and a
3224 * fault condition is detected is the inactive state of the channel. That is, the
3225 * safe value of a channel is the value of its POL bit.
3227 typedef union _hw_ftm_pol
3230 struct _hw_ftm_pol_bitfields
3232 uint32_t POL0
: 1; /*!< [0] Channel 0 Polarity */
3233 uint32_t POL1
: 1; /*!< [1] Channel 1 Polarity */
3234 uint32_t POL2
: 1; /*!< [2] Channel 2 Polarity */
3235 uint32_t POL3
: 1; /*!< [3] Channel 3 Polarity */
3236 uint32_t POL4
: 1; /*!< [4] Channel 4 Polarity */
3237 uint32_t POL5
: 1; /*!< [5] Channel 5 Polarity */
3238 uint32_t POL6
: 1; /*!< [6] Channel 6 Polarity */
3239 uint32_t POL7
: 1; /*!< [7] Channel 7 Polarity */
3240 uint32_t RESERVED0
: 24; /*!< [31:8] */
3245 * @name Constants and macros for entire FTM_POL register
3248 #define HW_FTM_POL_ADDR(x) ((x) + 0x70U)
3250 #define HW_FTM_POL(x) (*(__IO hw_ftm_pol_t *) HW_FTM_POL_ADDR(x))
3251 #define HW_FTM_POL_RD(x) (HW_FTM_POL(x).U)
3252 #define HW_FTM_POL_WR(x, v) (HW_FTM_POL(x).U = (v))
3253 #define HW_FTM_POL_SET(x, v) (HW_FTM_POL_WR(x, HW_FTM_POL_RD(x) | (v)))
3254 #define HW_FTM_POL_CLR(x, v) (HW_FTM_POL_WR(x, HW_FTM_POL_RD(x) & ~(v)))
3255 #define HW_FTM_POL_TOG(x, v) (HW_FTM_POL_WR(x, HW_FTM_POL_RD(x) ^ (v)))
3259 * Constants & macros for individual FTM_POL bitfields
3263 * @name Register FTM_POL, field POL0[0] (RW)
3265 * Defines the polarity of the channel output. This field is write protected. It
3266 * can be written only when MODE[WPDIS] = 1.
3269 * - 0 - The channel polarity is active high.
3270 * - 1 - The channel polarity is active low.
3273 #define BP_FTM_POL_POL0 (0U) /*!< Bit position for FTM_POL_POL0. */
3274 #define BM_FTM_POL_POL0 (0x00000001U) /*!< Bit mask for FTM_POL_POL0. */
3275 #define BS_FTM_POL_POL0 (1U) /*!< Bit field size in bits for FTM_POL_POL0. */
3277 /*! @brief Read current value of the FTM_POL_POL0 field. */
3278 #define BR_FTM_POL_POL0(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL0))
3280 /*! @brief Format value for bitfield FTM_POL_POL0. */
3281 #define BF_FTM_POL_POL0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL0) & BM_FTM_POL_POL0)
3283 /*! @brief Set the POL0 field to a new value. */
3284 #define BW_FTM_POL_POL0(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL0) = (v))
3288 * @name Register FTM_POL, field POL1[1] (RW)
3290 * Defines the polarity of the channel output. This field is write protected. It
3291 * can be written only when MODE[WPDIS] = 1.
3294 * - 0 - The channel polarity is active high.
3295 * - 1 - The channel polarity is active low.
3298 #define BP_FTM_POL_POL1 (1U) /*!< Bit position for FTM_POL_POL1. */
3299 #define BM_FTM_POL_POL1 (0x00000002U) /*!< Bit mask for FTM_POL_POL1. */
3300 #define BS_FTM_POL_POL1 (1U) /*!< Bit field size in bits for FTM_POL_POL1. */
3302 /*! @brief Read current value of the FTM_POL_POL1 field. */
3303 #define BR_FTM_POL_POL1(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL1))
3305 /*! @brief Format value for bitfield FTM_POL_POL1. */
3306 #define BF_FTM_POL_POL1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL1) & BM_FTM_POL_POL1)
3308 /*! @brief Set the POL1 field to a new value. */
3309 #define BW_FTM_POL_POL1(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL1) = (v))
3313 * @name Register FTM_POL, field POL2[2] (RW)
3315 * Defines the polarity of the channel output. This field is write protected. It
3316 * can be written only when MODE[WPDIS] = 1.
3319 * - 0 - The channel polarity is active high.
3320 * - 1 - The channel polarity is active low.
3323 #define BP_FTM_POL_POL2 (2U) /*!< Bit position for FTM_POL_POL2. */
3324 #define BM_FTM_POL_POL2 (0x00000004U) /*!< Bit mask for FTM_POL_POL2. */
3325 #define BS_FTM_POL_POL2 (1U) /*!< Bit field size in bits for FTM_POL_POL2. */
3327 /*! @brief Read current value of the FTM_POL_POL2 field. */
3328 #define BR_FTM_POL_POL2(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL2))
3330 /*! @brief Format value for bitfield FTM_POL_POL2. */
3331 #define BF_FTM_POL_POL2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL2) & BM_FTM_POL_POL2)
3333 /*! @brief Set the POL2 field to a new value. */
3334 #define BW_FTM_POL_POL2(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL2) = (v))
3338 * @name Register FTM_POL, field POL3[3] (RW)
3340 * Defines the polarity of the channel output. This field is write protected. It
3341 * can be written only when MODE[WPDIS] = 1.
3344 * - 0 - The channel polarity is active high.
3345 * - 1 - The channel polarity is active low.
3348 #define BP_FTM_POL_POL3 (3U) /*!< Bit position for FTM_POL_POL3. */
3349 #define BM_FTM_POL_POL3 (0x00000008U) /*!< Bit mask for FTM_POL_POL3. */
3350 #define BS_FTM_POL_POL3 (1U) /*!< Bit field size in bits for FTM_POL_POL3. */
3352 /*! @brief Read current value of the FTM_POL_POL3 field. */
3353 #define BR_FTM_POL_POL3(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL3))
3355 /*! @brief Format value for bitfield FTM_POL_POL3. */
3356 #define BF_FTM_POL_POL3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL3) & BM_FTM_POL_POL3)
3358 /*! @brief Set the POL3 field to a new value. */
3359 #define BW_FTM_POL_POL3(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL3) = (v))
3363 * @name Register FTM_POL, field POL4[4] (RW)
3365 * Defines the polarity of the channel output. This field is write protected. It
3366 * can be written only when MODE[WPDIS] = 1.
3369 * - 0 - The channel polarity is active high.
3370 * - 1 - The channel polarity is active low.
3373 #define BP_FTM_POL_POL4 (4U) /*!< Bit position for FTM_POL_POL4. */
3374 #define BM_FTM_POL_POL4 (0x00000010U) /*!< Bit mask for FTM_POL_POL4. */
3375 #define BS_FTM_POL_POL4 (1U) /*!< Bit field size in bits for FTM_POL_POL4. */
3377 /*! @brief Read current value of the FTM_POL_POL4 field. */
3378 #define BR_FTM_POL_POL4(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL4))
3380 /*! @brief Format value for bitfield FTM_POL_POL4. */
3381 #define BF_FTM_POL_POL4(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL4) & BM_FTM_POL_POL4)
3383 /*! @brief Set the POL4 field to a new value. */
3384 #define BW_FTM_POL_POL4(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL4) = (v))
3388 * @name Register FTM_POL, field POL5[5] (RW)
3390 * Defines the polarity of the channel output. This field is write protected. It
3391 * can be written only when MODE[WPDIS] = 1.
3394 * - 0 - The channel polarity is active high.
3395 * - 1 - The channel polarity is active low.
3398 #define BP_FTM_POL_POL5 (5U) /*!< Bit position for FTM_POL_POL5. */
3399 #define BM_FTM_POL_POL5 (0x00000020U) /*!< Bit mask for FTM_POL_POL5. */
3400 #define BS_FTM_POL_POL5 (1U) /*!< Bit field size in bits for FTM_POL_POL5. */
3402 /*! @brief Read current value of the FTM_POL_POL5 field. */
3403 #define BR_FTM_POL_POL5(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL5))
3405 /*! @brief Format value for bitfield FTM_POL_POL5. */
3406 #define BF_FTM_POL_POL5(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL5) & BM_FTM_POL_POL5)
3408 /*! @brief Set the POL5 field to a new value. */
3409 #define BW_FTM_POL_POL5(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL5) = (v))
3413 * @name Register FTM_POL, field POL6[6] (RW)
3415 * Defines the polarity of the channel output. This field is write protected. It
3416 * can be written only when MODE[WPDIS] = 1.
3419 * - 0 - The channel polarity is active high.
3420 * - 1 - The channel polarity is active low.
3423 #define BP_FTM_POL_POL6 (6U) /*!< Bit position for FTM_POL_POL6. */
3424 #define BM_FTM_POL_POL6 (0x00000040U) /*!< Bit mask for FTM_POL_POL6. */
3425 #define BS_FTM_POL_POL6 (1U) /*!< Bit field size in bits for FTM_POL_POL6. */
3427 /*! @brief Read current value of the FTM_POL_POL6 field. */
3428 #define BR_FTM_POL_POL6(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL6))
3430 /*! @brief Format value for bitfield FTM_POL_POL6. */
3431 #define BF_FTM_POL_POL6(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL6) & BM_FTM_POL_POL6)
3433 /*! @brief Set the POL6 field to a new value. */
3434 #define BW_FTM_POL_POL6(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL6) = (v))
3438 * @name Register FTM_POL, field POL7[7] (RW)
3440 * Defines the polarity of the channel output. This field is write protected. It
3441 * can be written only when MODE[WPDIS] = 1.
3444 * - 0 - The channel polarity is active high.
3445 * - 1 - The channel polarity is active low.
3448 #define BP_FTM_POL_POL7 (7U) /*!< Bit position for FTM_POL_POL7. */
3449 #define BM_FTM_POL_POL7 (0x00000080U) /*!< Bit mask for FTM_POL_POL7. */
3450 #define BS_FTM_POL_POL7 (1U) /*!< Bit field size in bits for FTM_POL_POL7. */
3452 /*! @brief Read current value of the FTM_POL_POL7 field. */
3453 #define BR_FTM_POL_POL7(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL7))
3455 /*! @brief Format value for bitfield FTM_POL_POL7. */
3456 #define BF_FTM_POL_POL7(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL7) & BM_FTM_POL_POL7)
3458 /*! @brief Set the POL7 field to a new value. */
3459 #define BW_FTM_POL_POL7(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL7) = (v))
3462 /*******************************************************************************
3463 * HW_FTM_FMS - Fault Mode Status
3464 ******************************************************************************/
3467 * @brief HW_FTM_FMS - Fault Mode Status (RW)
3469 * Reset value: 0x00000000U
3471 * This register contains the fault detection flags, write protection enable
3472 * bit, and the logic OR of the enabled fault inputs.
3474 typedef union _hw_ftm_fms
3477 struct _hw_ftm_fms_bitfields
3479 uint32_t FAULTF0
: 1; /*!< [0] Fault Detection Flag 0 */
3480 uint32_t FAULTF1
: 1; /*!< [1] Fault Detection Flag 1 */
3481 uint32_t FAULTF2
: 1; /*!< [2] Fault Detection Flag 2 */
3482 uint32_t FAULTF3
: 1; /*!< [3] Fault Detection Flag 3 */
3483 uint32_t RESERVED0
: 1; /*!< [4] */
3484 uint32_t FAULTIN
: 1; /*!< [5] Fault Inputs */
3485 uint32_t WPEN
: 1; /*!< [6] Write Protection Enable */
3486 uint32_t FAULTF
: 1; /*!< [7] Fault Detection Flag */
3487 uint32_t RESERVED1
: 24; /*!< [31:8] */
3492 * @name Constants and macros for entire FTM_FMS register
3495 #define HW_FTM_FMS_ADDR(x) ((x) + 0x74U)
3497 #define HW_FTM_FMS(x) (*(__IO hw_ftm_fms_t *) HW_FTM_FMS_ADDR(x))
3498 #define HW_FTM_FMS_RD(x) (HW_FTM_FMS(x).U)
3499 #define HW_FTM_FMS_WR(x, v) (HW_FTM_FMS(x).U = (v))
3500 #define HW_FTM_FMS_SET(x, v) (HW_FTM_FMS_WR(x, HW_FTM_FMS_RD(x) | (v)))
3501 #define HW_FTM_FMS_CLR(x, v) (HW_FTM_FMS_WR(x, HW_FTM_FMS_RD(x) & ~(v)))
3502 #define HW_FTM_FMS_TOG(x, v) (HW_FTM_FMS_WR(x, HW_FTM_FMS_RD(x) ^ (v)))
3506 * Constants & macros for individual FTM_FMS bitfields
3510 * @name Register FTM_FMS, field FAULTF0[0] (ROWZ)
3512 * Set by hardware when fault control is enabled, the corresponding fault input
3513 * is enabled and a fault condition is detected at the fault input. Clear FAULTF0
3514 * by reading the FMS register while FAULTF0 is set and then writing a 0 to
3515 * FAULTF0 while there is no existing fault condition at the corresponding fault
3516 * input. Writing a 1 to FAULTF0 has no effect. FAULTF0 bit is also cleared when
3517 * FAULTF bit is cleared. If another fault condition is detected at the corresponding
3518 * fault input before the clearing sequence is completed, the sequence is reset
3519 * so FAULTF0 remains set after the clearing sequence is completed for the
3520 * earlier fault condition.
3523 * - 0 - No fault condition was detected at the fault input.
3524 * - 1 - A fault condition was detected at the fault input.
3527 #define BP_FTM_FMS_FAULTF0 (0U) /*!< Bit position for FTM_FMS_FAULTF0. */
3528 #define BM_FTM_FMS_FAULTF0 (0x00000001U) /*!< Bit mask for FTM_FMS_FAULTF0. */
3529 #define BS_FTM_FMS_FAULTF0 (1U) /*!< Bit field size in bits for FTM_FMS_FAULTF0. */
3531 /*! @brief Read current value of the FTM_FMS_FAULTF0 field. */
3532 #define BR_FTM_FMS_FAULTF0(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF0))
3534 /*! @brief Format value for bitfield FTM_FMS_FAULTF0. */
3535 #define BF_FTM_FMS_FAULTF0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_FAULTF0) & BM_FTM_FMS_FAULTF0)
3537 /*! @brief Set the FAULTF0 field to a new value. */
3538 #define BW_FTM_FMS_FAULTF0(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF0) = (v))
3542 * @name Register FTM_FMS, field FAULTF1[1] (ROWZ)
3544 * Set by hardware when fault control is enabled, the corresponding fault input
3545 * is enabled and a fault condition is detected at the fault input. Clear FAULTF1
3546 * by reading the FMS register while FAULTF1 is set and then writing a 0 to
3547 * FAULTF1 while there is no existing fault condition at the corresponding fault
3548 * input. Writing a 1 to FAULTF1 has no effect. FAULTF1 bit is also cleared when
3549 * FAULTF bit is cleared. If another fault condition is detected at the corresponding
3550 * fault input before the clearing sequence is completed, the sequence is reset
3551 * so FAULTF1 remains set after the clearing sequence is completed for the
3552 * earlier fault condition.
3555 * - 0 - No fault condition was detected at the fault input.
3556 * - 1 - A fault condition was detected at the fault input.
3559 #define BP_FTM_FMS_FAULTF1 (1U) /*!< Bit position for FTM_FMS_FAULTF1. */
3560 #define BM_FTM_FMS_FAULTF1 (0x00000002U) /*!< Bit mask for FTM_FMS_FAULTF1. */
3561 #define BS_FTM_FMS_FAULTF1 (1U) /*!< Bit field size in bits for FTM_FMS_FAULTF1. */
3563 /*! @brief Read current value of the FTM_FMS_FAULTF1 field. */
3564 #define BR_FTM_FMS_FAULTF1(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF1))
3566 /*! @brief Format value for bitfield FTM_FMS_FAULTF1. */
3567 #define BF_FTM_FMS_FAULTF1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_FAULTF1) & BM_FTM_FMS_FAULTF1)
3569 /*! @brief Set the FAULTF1 field to a new value. */
3570 #define BW_FTM_FMS_FAULTF1(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF1) = (v))
3574 * @name Register FTM_FMS, field FAULTF2[2] (ROWZ)
3576 * Set by hardware when fault control is enabled, the corresponding fault input
3577 * is enabled and a fault condition is detected at the fault input. Clear FAULTF2
3578 * by reading the FMS register while FAULTF2 is set and then writing a 0 to
3579 * FAULTF2 while there is no existing fault condition at the corresponding fault
3580 * input. Writing a 1 to FAULTF2 has no effect. FAULTF2 bit is also cleared when
3581 * FAULTF bit is cleared. If another fault condition is detected at the corresponding
3582 * fault input before the clearing sequence is completed, the sequence is reset
3583 * so FAULTF2 remains set after the clearing sequence is completed for the
3584 * earlier fault condition.
3587 * - 0 - No fault condition was detected at the fault input.
3588 * - 1 - A fault condition was detected at the fault input.
3591 #define BP_FTM_FMS_FAULTF2 (2U) /*!< Bit position for FTM_FMS_FAULTF2. */
3592 #define BM_FTM_FMS_FAULTF2 (0x00000004U) /*!< Bit mask for FTM_FMS_FAULTF2. */
3593 #define BS_FTM_FMS_FAULTF2 (1U) /*!< Bit field size in bits for FTM_FMS_FAULTF2. */
3595 /*! @brief Read current value of the FTM_FMS_FAULTF2 field. */
3596 #define BR_FTM_FMS_FAULTF2(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF2))
3598 /*! @brief Format value for bitfield FTM_FMS_FAULTF2. */
3599 #define BF_FTM_FMS_FAULTF2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_FAULTF2) & BM_FTM_FMS_FAULTF2)
3601 /*! @brief Set the FAULTF2 field to a new value. */
3602 #define BW_FTM_FMS_FAULTF2(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF2) = (v))
3606 * @name Register FTM_FMS, field FAULTF3[3] (ROWZ)
3608 * Set by hardware when fault control is enabled, the corresponding fault input
3609 * is enabled and a fault condition is detected at the fault input. Clear FAULTF3
3610 * by reading the FMS register while FAULTF3 is set and then writing a 0 to
3611 * FAULTF3 while there is no existing fault condition at the corresponding fault
3612 * input. Writing a 1 to FAULTF3 has no effect. FAULTF3 bit is also cleared when
3613 * FAULTF bit is cleared. If another fault condition is detected at the corresponding
3614 * fault input before the clearing sequence is completed, the sequence is reset
3615 * so FAULTF3 remains set after the clearing sequence is completed for the
3616 * earlier fault condition.
3619 * - 0 - No fault condition was detected at the fault input.
3620 * - 1 - A fault condition was detected at the fault input.
3623 #define BP_FTM_FMS_FAULTF3 (3U) /*!< Bit position for FTM_FMS_FAULTF3. */
3624 #define BM_FTM_FMS_FAULTF3 (0x00000008U) /*!< Bit mask for FTM_FMS_FAULTF3. */
3625 #define BS_FTM_FMS_FAULTF3 (1U) /*!< Bit field size in bits for FTM_FMS_FAULTF3. */
3627 /*! @brief Read current value of the FTM_FMS_FAULTF3 field. */
3628 #define BR_FTM_FMS_FAULTF3(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF3))
3630 /*! @brief Format value for bitfield FTM_FMS_FAULTF3. */
3631 #define BF_FTM_FMS_FAULTF3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_FAULTF3) & BM_FTM_FMS_FAULTF3)
3633 /*! @brief Set the FAULTF3 field to a new value. */
3634 #define BW_FTM_FMS_FAULTF3(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF3) = (v))
3638 * @name Register FTM_FMS, field FAULTIN[5] (RO)
3640 * Represents the logic OR of the enabled fault inputs after their filter (if
3641 * their filter is enabled) when fault control is enabled.
3644 * - 0 - The logic OR of the enabled fault inputs is 0.
3645 * - 1 - The logic OR of the enabled fault inputs is 1.
3648 #define BP_FTM_FMS_FAULTIN (5U) /*!< Bit position for FTM_FMS_FAULTIN. */
3649 #define BM_FTM_FMS_FAULTIN (0x00000020U) /*!< Bit mask for FTM_FMS_FAULTIN. */
3650 #define BS_FTM_FMS_FAULTIN (1U) /*!< Bit field size in bits for FTM_FMS_FAULTIN. */
3652 /*! @brief Read current value of the FTM_FMS_FAULTIN field. */
3653 #define BR_FTM_FMS_FAULTIN(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTIN))
3657 * @name Register FTM_FMS, field WPEN[6] (RW)
3659 * The WPEN bit is the negation of the WPDIS bit. WPEN is set when 1 is written
3660 * to it. WPEN is cleared when WPEN bit is read as a 1 and then 1 is written to
3661 * WPDIS. Writing 0 to WPEN has no effect.
3664 * - 0 - Write protection is disabled. Write protected bits can be written.
3665 * - 1 - Write protection is enabled. Write protected bits cannot be written.
3668 #define BP_FTM_FMS_WPEN (6U) /*!< Bit position for FTM_FMS_WPEN. */
3669 #define BM_FTM_FMS_WPEN (0x00000040U) /*!< Bit mask for FTM_FMS_WPEN. */
3670 #define BS_FTM_FMS_WPEN (1U) /*!< Bit field size in bits for FTM_FMS_WPEN. */
3672 /*! @brief Read current value of the FTM_FMS_WPEN field. */
3673 #define BR_FTM_FMS_WPEN(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_WPEN))
3675 /*! @brief Format value for bitfield FTM_FMS_WPEN. */
3676 #define BF_FTM_FMS_WPEN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_WPEN) & BM_FTM_FMS_WPEN)
3678 /*! @brief Set the WPEN field to a new value. */
3679 #define BW_FTM_FMS_WPEN(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_WPEN) = (v))
3683 * @name Register FTM_FMS, field FAULTF[7] (ROWZ)
3685 * Represents the logic OR of the individual FAULTFj bits where j = 3, 2, 1, 0.
3686 * Clear FAULTF by reading the FMS register while FAULTF is set and then writing
3687 * a 0 to FAULTF while there is no existing fault condition at the enabled fault
3688 * inputs. Writing a 1 to FAULTF has no effect. If another fault condition is
3689 * detected in an enabled fault input before the clearing sequence is completed, the
3690 * sequence is reset so FAULTF remains set after the clearing sequence is
3691 * completed for the earlier fault condition. FAULTF is also cleared when FAULTFj bits
3692 * are cleared individually.
3695 * - 0 - No fault condition was detected.
3696 * - 1 - A fault condition was detected.
3699 #define BP_FTM_FMS_FAULTF (7U) /*!< Bit position for FTM_FMS_FAULTF. */
3700 #define BM_FTM_FMS_FAULTF (0x00000080U) /*!< Bit mask for FTM_FMS_FAULTF. */
3701 #define BS_FTM_FMS_FAULTF (1U) /*!< Bit field size in bits for FTM_FMS_FAULTF. */
3703 /*! @brief Read current value of the FTM_FMS_FAULTF field. */
3704 #define BR_FTM_FMS_FAULTF(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF))
3706 /*! @brief Format value for bitfield FTM_FMS_FAULTF. */
3707 #define BF_FTM_FMS_FAULTF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_FAULTF) & BM_FTM_FMS_FAULTF)
3709 /*! @brief Set the FAULTF field to a new value. */
3710 #define BW_FTM_FMS_FAULTF(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF) = (v))
3713 /*******************************************************************************
3714 * HW_FTM_FILTER - Input Capture Filter Control
3715 ******************************************************************************/
3718 * @brief HW_FTM_FILTER - Input Capture Filter Control (RW)
3720 * Reset value: 0x00000000U
3722 * This register selects the filter value for the inputs of channels. Channels
3723 * 4, 5, 6 and 7 do not have an input filter. Writing to the FILTER register has
3724 * immediate effect and must be done only when the channels 0, 1, 2, and 3 are not
3725 * in input modes. Failure to do this could result in a missing valid signal.
3727 typedef union _hw_ftm_filter
3730 struct _hw_ftm_filter_bitfields
3732 uint32_t CH0FVAL
: 4; /*!< [3:0] Channel 0 Input Filter */
3733 uint32_t CH1FVAL
: 4; /*!< [7:4] Channel 1 Input Filter */
3734 uint32_t CH2FVAL
: 4; /*!< [11:8] Channel 2 Input Filter */
3735 uint32_t CH3FVAL
: 4; /*!< [15:12] Channel 3 Input Filter */
3736 uint32_t RESERVED0
: 16; /*!< [31:16] */
3741 * @name Constants and macros for entire FTM_FILTER register
3744 #define HW_FTM_FILTER_ADDR(x) ((x) + 0x78U)
3746 #define HW_FTM_FILTER(x) (*(__IO hw_ftm_filter_t *) HW_FTM_FILTER_ADDR(x))
3747 #define HW_FTM_FILTER_RD(x) (HW_FTM_FILTER(x).U)
3748 #define HW_FTM_FILTER_WR(x, v) (HW_FTM_FILTER(x).U = (v))
3749 #define HW_FTM_FILTER_SET(x, v) (HW_FTM_FILTER_WR(x, HW_FTM_FILTER_RD(x) | (v)))
3750 #define HW_FTM_FILTER_CLR(x, v) (HW_FTM_FILTER_WR(x, HW_FTM_FILTER_RD(x) & ~(v)))
3751 #define HW_FTM_FILTER_TOG(x, v) (HW_FTM_FILTER_WR(x, HW_FTM_FILTER_RD(x) ^ (v)))
3755 * Constants & macros for individual FTM_FILTER bitfields
3759 * @name Register FTM_FILTER, field CH0FVAL[3:0] (RW)
3761 * Selects the filter value for the channel input. The filter is disabled when
3762 * the value is zero.
3765 #define BP_FTM_FILTER_CH0FVAL (0U) /*!< Bit position for FTM_FILTER_CH0FVAL. */
3766 #define BM_FTM_FILTER_CH0FVAL (0x0000000FU) /*!< Bit mask for FTM_FILTER_CH0FVAL. */
3767 #define BS_FTM_FILTER_CH0FVAL (4U) /*!< Bit field size in bits for FTM_FILTER_CH0FVAL. */
3769 /*! @brief Read current value of the FTM_FILTER_CH0FVAL field. */
3770 #define BR_FTM_FILTER_CH0FVAL(x) (HW_FTM_FILTER(x).B.CH0FVAL)
3772 /*! @brief Format value for bitfield FTM_FILTER_CH0FVAL. */
3773 #define BF_FTM_FILTER_CH0FVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FILTER_CH0FVAL) & BM_FTM_FILTER_CH0FVAL)
3775 /*! @brief Set the CH0FVAL field to a new value. */
3776 #define BW_FTM_FILTER_CH0FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH0FVAL) | BF_FTM_FILTER_CH0FVAL(v)))
3780 * @name Register FTM_FILTER, field CH1FVAL[7:4] (RW)
3782 * Selects the filter value for the channel input. The filter is disabled when
3783 * the value is zero.
3786 #define BP_FTM_FILTER_CH1FVAL (4U) /*!< Bit position for FTM_FILTER_CH1FVAL. */
3787 #define BM_FTM_FILTER_CH1FVAL (0x000000F0U) /*!< Bit mask for FTM_FILTER_CH1FVAL. */
3788 #define BS_FTM_FILTER_CH1FVAL (4U) /*!< Bit field size in bits for FTM_FILTER_CH1FVAL. */
3790 /*! @brief Read current value of the FTM_FILTER_CH1FVAL field. */
3791 #define BR_FTM_FILTER_CH1FVAL(x) (HW_FTM_FILTER(x).B.CH1FVAL)
3793 /*! @brief Format value for bitfield FTM_FILTER_CH1FVAL. */
3794 #define BF_FTM_FILTER_CH1FVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FILTER_CH1FVAL) & BM_FTM_FILTER_CH1FVAL)
3796 /*! @brief Set the CH1FVAL field to a new value. */
3797 #define BW_FTM_FILTER_CH1FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH1FVAL) | BF_FTM_FILTER_CH1FVAL(v)))
3801 * @name Register FTM_FILTER, field CH2FVAL[11:8] (RW)
3803 * Selects the filter value for the channel input. The filter is disabled when
3804 * the value is zero.
3807 #define BP_FTM_FILTER_CH2FVAL (8U) /*!< Bit position for FTM_FILTER_CH2FVAL. */
3808 #define BM_FTM_FILTER_CH2FVAL (0x00000F00U) /*!< Bit mask for FTM_FILTER_CH2FVAL. */
3809 #define BS_FTM_FILTER_CH2FVAL (4U) /*!< Bit field size in bits for FTM_FILTER_CH2FVAL. */
3811 /*! @brief Read current value of the FTM_FILTER_CH2FVAL field. */
3812 #define BR_FTM_FILTER_CH2FVAL(x) (HW_FTM_FILTER(x).B.CH2FVAL)
3814 /*! @brief Format value for bitfield FTM_FILTER_CH2FVAL. */
3815 #define BF_FTM_FILTER_CH2FVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FILTER_CH2FVAL) & BM_FTM_FILTER_CH2FVAL)
3817 /*! @brief Set the CH2FVAL field to a new value. */
3818 #define BW_FTM_FILTER_CH2FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH2FVAL) | BF_FTM_FILTER_CH2FVAL(v)))
3822 * @name Register FTM_FILTER, field CH3FVAL[15:12] (RW)
3824 * Selects the filter value for the channel input. The filter is disabled when
3825 * the value is zero.
3828 #define BP_FTM_FILTER_CH3FVAL (12U) /*!< Bit position for FTM_FILTER_CH3FVAL. */
3829 #define BM_FTM_FILTER_CH3FVAL (0x0000F000U) /*!< Bit mask for FTM_FILTER_CH3FVAL. */
3830 #define BS_FTM_FILTER_CH3FVAL (4U) /*!< Bit field size in bits for FTM_FILTER_CH3FVAL. */
3832 /*! @brief Read current value of the FTM_FILTER_CH3FVAL field. */
3833 #define BR_FTM_FILTER_CH3FVAL(x) (HW_FTM_FILTER(x).B.CH3FVAL)
3835 /*! @brief Format value for bitfield FTM_FILTER_CH3FVAL. */
3836 #define BF_FTM_FILTER_CH3FVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FILTER_CH3FVAL) & BM_FTM_FILTER_CH3FVAL)
3838 /*! @brief Set the CH3FVAL field to a new value. */
3839 #define BW_FTM_FILTER_CH3FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH3FVAL) | BF_FTM_FILTER_CH3FVAL(v)))
3842 /*******************************************************************************
3843 * HW_FTM_FLTCTRL - Fault Control
3844 ******************************************************************************/
3847 * @brief HW_FTM_FLTCTRL - Fault Control (RW)
3849 * Reset value: 0x00000000U
3851 * This register selects the filter value for the fault inputs, enables the
3852 * fault inputs and the fault inputs filter.
3854 typedef union _hw_ftm_fltctrl
3857 struct _hw_ftm_fltctrl_bitfields
3859 uint32_t FAULT0EN
: 1; /*!< [0] Fault Input 0 Enable */
3860 uint32_t FAULT1EN
: 1; /*!< [1] Fault Input 1 Enable */
3861 uint32_t FAULT2EN
: 1; /*!< [2] Fault Input 2 Enable */
3862 uint32_t FAULT3EN
: 1; /*!< [3] Fault Input 3 Enable */
3863 uint32_t FFLTR0EN
: 1; /*!< [4] Fault Input 0 Filter Enable */
3864 uint32_t FFLTR1EN
: 1; /*!< [5] Fault Input 1 Filter Enable */
3865 uint32_t FFLTR2EN
: 1; /*!< [6] Fault Input 2 Filter Enable */
3866 uint32_t FFLTR3EN
: 1; /*!< [7] Fault Input 3 Filter Enable */
3867 uint32_t FFVAL
: 4; /*!< [11:8] Fault Input Filter */
3868 uint32_t RESERVED0
: 20; /*!< [31:12] */
3873 * @name Constants and macros for entire FTM_FLTCTRL register
3876 #define HW_FTM_FLTCTRL_ADDR(x) ((x) + 0x7CU)
3878 #define HW_FTM_FLTCTRL(x) (*(__IO hw_ftm_fltctrl_t *) HW_FTM_FLTCTRL_ADDR(x))
3879 #define HW_FTM_FLTCTRL_RD(x) (HW_FTM_FLTCTRL(x).U)
3880 #define HW_FTM_FLTCTRL_WR(x, v) (HW_FTM_FLTCTRL(x).U = (v))
3881 #define HW_FTM_FLTCTRL_SET(x, v) (HW_FTM_FLTCTRL_WR(x, HW_FTM_FLTCTRL_RD(x) | (v)))
3882 #define HW_FTM_FLTCTRL_CLR(x, v) (HW_FTM_FLTCTRL_WR(x, HW_FTM_FLTCTRL_RD(x) & ~(v)))
3883 #define HW_FTM_FLTCTRL_TOG(x, v) (HW_FTM_FLTCTRL_WR(x, HW_FTM_FLTCTRL_RD(x) ^ (v)))
3887 * Constants & macros for individual FTM_FLTCTRL bitfields
3891 * @name Register FTM_FLTCTRL, field FAULT0EN[0] (RW)
3893 * Enables the fault input. This field is write protected. It can be written
3894 * only when MODE[WPDIS] = 1.
3897 * - 0 - Fault input is disabled.
3898 * - 1 - Fault input is enabled.
3901 #define BP_FTM_FLTCTRL_FAULT0EN (0U) /*!< Bit position for FTM_FLTCTRL_FAULT0EN. */
3902 #define BM_FTM_FLTCTRL_FAULT0EN (0x00000001U) /*!< Bit mask for FTM_FLTCTRL_FAULT0EN. */
3903 #define BS_FTM_FLTCTRL_FAULT0EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FAULT0EN. */
3905 /*! @brief Read current value of the FTM_FLTCTRL_FAULT0EN field. */
3906 #define BR_FTM_FLTCTRL_FAULT0EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT0EN))
3908 /*! @brief Format value for bitfield FTM_FLTCTRL_FAULT0EN. */
3909 #define BF_FTM_FLTCTRL_FAULT0EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FAULT0EN) & BM_FTM_FLTCTRL_FAULT0EN)
3911 /*! @brief Set the FAULT0EN field to a new value. */
3912 #define BW_FTM_FLTCTRL_FAULT0EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT0EN) = (v))
3916 * @name Register FTM_FLTCTRL, field FAULT1EN[1] (RW)
3918 * Enables the fault input. This field is write protected. It can be written
3919 * only when MODE[WPDIS] = 1.
3922 * - 0 - Fault input is disabled.
3923 * - 1 - Fault input is enabled.
3926 #define BP_FTM_FLTCTRL_FAULT1EN (1U) /*!< Bit position for FTM_FLTCTRL_FAULT1EN. */
3927 #define BM_FTM_FLTCTRL_FAULT1EN (0x00000002U) /*!< Bit mask for FTM_FLTCTRL_FAULT1EN. */
3928 #define BS_FTM_FLTCTRL_FAULT1EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FAULT1EN. */
3930 /*! @brief Read current value of the FTM_FLTCTRL_FAULT1EN field. */
3931 #define BR_FTM_FLTCTRL_FAULT1EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT1EN))
3933 /*! @brief Format value for bitfield FTM_FLTCTRL_FAULT1EN. */
3934 #define BF_FTM_FLTCTRL_FAULT1EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FAULT1EN) & BM_FTM_FLTCTRL_FAULT1EN)
3936 /*! @brief Set the FAULT1EN field to a new value. */
3937 #define BW_FTM_FLTCTRL_FAULT1EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT1EN) = (v))
3941 * @name Register FTM_FLTCTRL, field FAULT2EN[2] (RW)
3943 * Enables the fault input. This field is write protected. It can be written
3944 * only when MODE[WPDIS] = 1.
3947 * - 0 - Fault input is disabled.
3948 * - 1 - Fault input is enabled.
3951 #define BP_FTM_FLTCTRL_FAULT2EN (2U) /*!< Bit position for FTM_FLTCTRL_FAULT2EN. */
3952 #define BM_FTM_FLTCTRL_FAULT2EN (0x00000004U) /*!< Bit mask for FTM_FLTCTRL_FAULT2EN. */
3953 #define BS_FTM_FLTCTRL_FAULT2EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FAULT2EN. */
3955 /*! @brief Read current value of the FTM_FLTCTRL_FAULT2EN field. */
3956 #define BR_FTM_FLTCTRL_FAULT2EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT2EN))
3958 /*! @brief Format value for bitfield FTM_FLTCTRL_FAULT2EN. */
3959 #define BF_FTM_FLTCTRL_FAULT2EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FAULT2EN) & BM_FTM_FLTCTRL_FAULT2EN)
3961 /*! @brief Set the FAULT2EN field to a new value. */
3962 #define BW_FTM_FLTCTRL_FAULT2EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT2EN) = (v))
3966 * @name Register FTM_FLTCTRL, field FAULT3EN[3] (RW)
3968 * Enables the fault input. This field is write protected. It can be written
3969 * only when MODE[WPDIS] = 1.
3972 * - 0 - Fault input is disabled.
3973 * - 1 - Fault input is enabled.
3976 #define BP_FTM_FLTCTRL_FAULT3EN (3U) /*!< Bit position for FTM_FLTCTRL_FAULT3EN. */
3977 #define BM_FTM_FLTCTRL_FAULT3EN (0x00000008U) /*!< Bit mask for FTM_FLTCTRL_FAULT3EN. */
3978 #define BS_FTM_FLTCTRL_FAULT3EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FAULT3EN. */
3980 /*! @brief Read current value of the FTM_FLTCTRL_FAULT3EN field. */
3981 #define BR_FTM_FLTCTRL_FAULT3EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT3EN))
3983 /*! @brief Format value for bitfield FTM_FLTCTRL_FAULT3EN. */
3984 #define BF_FTM_FLTCTRL_FAULT3EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FAULT3EN) & BM_FTM_FLTCTRL_FAULT3EN)
3986 /*! @brief Set the FAULT3EN field to a new value. */
3987 #define BW_FTM_FLTCTRL_FAULT3EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT3EN) = (v))
3991 * @name Register FTM_FLTCTRL, field FFLTR0EN[4] (RW)
3993 * Enables the filter for the fault input. This field is write protected. It can
3994 * be written only when MODE[WPDIS] = 1.
3997 * - 0 - Fault input filter is disabled.
3998 * - 1 - Fault input filter is enabled.
4001 #define BP_FTM_FLTCTRL_FFLTR0EN (4U) /*!< Bit position for FTM_FLTCTRL_FFLTR0EN. */
4002 #define BM_FTM_FLTCTRL_FFLTR0EN (0x00000010U) /*!< Bit mask for FTM_FLTCTRL_FFLTR0EN. */
4003 #define BS_FTM_FLTCTRL_FFLTR0EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FFLTR0EN. */
4005 /*! @brief Read current value of the FTM_FLTCTRL_FFLTR0EN field. */
4006 #define BR_FTM_FLTCTRL_FFLTR0EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR0EN))
4008 /*! @brief Format value for bitfield FTM_FLTCTRL_FFLTR0EN. */
4009 #define BF_FTM_FLTCTRL_FFLTR0EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FFLTR0EN) & BM_FTM_FLTCTRL_FFLTR0EN)
4011 /*! @brief Set the FFLTR0EN field to a new value. */
4012 #define BW_FTM_FLTCTRL_FFLTR0EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR0EN) = (v))
4016 * @name Register FTM_FLTCTRL, field FFLTR1EN[5] (RW)
4018 * Enables the filter for the fault input. This field is write protected. It can
4019 * be written only when MODE[WPDIS] = 1.
4022 * - 0 - Fault input filter is disabled.
4023 * - 1 - Fault input filter is enabled.
4026 #define BP_FTM_FLTCTRL_FFLTR1EN (5U) /*!< Bit position for FTM_FLTCTRL_FFLTR1EN. */
4027 #define BM_FTM_FLTCTRL_FFLTR1EN (0x00000020U) /*!< Bit mask for FTM_FLTCTRL_FFLTR1EN. */
4028 #define BS_FTM_FLTCTRL_FFLTR1EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FFLTR1EN. */
4030 /*! @brief Read current value of the FTM_FLTCTRL_FFLTR1EN field. */
4031 #define BR_FTM_FLTCTRL_FFLTR1EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR1EN))
4033 /*! @brief Format value for bitfield FTM_FLTCTRL_FFLTR1EN. */
4034 #define BF_FTM_FLTCTRL_FFLTR1EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FFLTR1EN) & BM_FTM_FLTCTRL_FFLTR1EN)
4036 /*! @brief Set the FFLTR1EN field to a new value. */
4037 #define BW_FTM_FLTCTRL_FFLTR1EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR1EN) = (v))
4041 * @name Register FTM_FLTCTRL, field FFLTR2EN[6] (RW)
4043 * Enables the filter for the fault input. This field is write protected. It can
4044 * be written only when MODE[WPDIS] = 1.
4047 * - 0 - Fault input filter is disabled.
4048 * - 1 - Fault input filter is enabled.
4051 #define BP_FTM_FLTCTRL_FFLTR2EN (6U) /*!< Bit position for FTM_FLTCTRL_FFLTR2EN. */
4052 #define BM_FTM_FLTCTRL_FFLTR2EN (0x00000040U) /*!< Bit mask for FTM_FLTCTRL_FFLTR2EN. */
4053 #define BS_FTM_FLTCTRL_FFLTR2EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FFLTR2EN. */
4055 /*! @brief Read current value of the FTM_FLTCTRL_FFLTR2EN field. */
4056 #define BR_FTM_FLTCTRL_FFLTR2EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR2EN))
4058 /*! @brief Format value for bitfield FTM_FLTCTRL_FFLTR2EN. */
4059 #define BF_FTM_FLTCTRL_FFLTR2EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FFLTR2EN) & BM_FTM_FLTCTRL_FFLTR2EN)
4061 /*! @brief Set the FFLTR2EN field to a new value. */
4062 #define BW_FTM_FLTCTRL_FFLTR2EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR2EN) = (v))
4066 * @name Register FTM_FLTCTRL, field FFLTR3EN[7] (RW)
4068 * Enables the filter for the fault input. This field is write protected. It can
4069 * be written only when MODE[WPDIS] = 1.
4072 * - 0 - Fault input filter is disabled.
4073 * - 1 - Fault input filter is enabled.
4076 #define BP_FTM_FLTCTRL_FFLTR3EN (7U) /*!< Bit position for FTM_FLTCTRL_FFLTR3EN. */
4077 #define BM_FTM_FLTCTRL_FFLTR3EN (0x00000080U) /*!< Bit mask for FTM_FLTCTRL_FFLTR3EN. */
4078 #define BS_FTM_FLTCTRL_FFLTR3EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FFLTR3EN. */
4080 /*! @brief Read current value of the FTM_FLTCTRL_FFLTR3EN field. */
4081 #define BR_FTM_FLTCTRL_FFLTR3EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR3EN))
4083 /*! @brief Format value for bitfield FTM_FLTCTRL_FFLTR3EN. */
4084 #define BF_FTM_FLTCTRL_FFLTR3EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FFLTR3EN) & BM_FTM_FLTCTRL_FFLTR3EN)
4086 /*! @brief Set the FFLTR3EN field to a new value. */
4087 #define BW_FTM_FLTCTRL_FFLTR3EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR3EN) = (v))
4091 * @name Register FTM_FLTCTRL, field FFVAL[11:8] (RW)
4093 * Selects the filter value for the fault inputs. The fault filter is disabled
4094 * when the value is zero. Writing to this field has immediate effect and must be
4095 * done only when the fault control or all fault inputs are disabled. Failure to
4096 * do this could result in a missing fault detection.
4099 #define BP_FTM_FLTCTRL_FFVAL (8U) /*!< Bit position for FTM_FLTCTRL_FFVAL. */
4100 #define BM_FTM_FLTCTRL_FFVAL (0x00000F00U) /*!< Bit mask for FTM_FLTCTRL_FFVAL. */
4101 #define BS_FTM_FLTCTRL_FFVAL (4U) /*!< Bit field size in bits for FTM_FLTCTRL_FFVAL. */
4103 /*! @brief Read current value of the FTM_FLTCTRL_FFVAL field. */
4104 #define BR_FTM_FLTCTRL_FFVAL(x) (HW_FTM_FLTCTRL(x).B.FFVAL)
4106 /*! @brief Format value for bitfield FTM_FLTCTRL_FFVAL. */
4107 #define BF_FTM_FLTCTRL_FFVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FFVAL) & BM_FTM_FLTCTRL_FFVAL)
4109 /*! @brief Set the FFVAL field to a new value. */
4110 #define BW_FTM_FLTCTRL_FFVAL(x, v) (HW_FTM_FLTCTRL_WR(x, (HW_FTM_FLTCTRL_RD(x) & ~BM_FTM_FLTCTRL_FFVAL) | BF_FTM_FLTCTRL_FFVAL(v)))
4113 /*******************************************************************************
4114 * HW_FTM_QDCTRL - Quadrature Decoder Control And Status
4115 ******************************************************************************/
4118 * @brief HW_FTM_QDCTRL - Quadrature Decoder Control And Status (RW)
4120 * Reset value: 0x00000000U
4122 * This register has the control and status bits for the Quadrature Decoder mode.
4124 typedef union _hw_ftm_qdctrl
4127 struct _hw_ftm_qdctrl_bitfields
4129 uint32_t QUADEN
: 1; /*!< [0] Quadrature Decoder Mode Enable */
4130 uint32_t TOFDIR
: 1; /*!< [1] Timer Overflow Direction In Quadrature
4132 uint32_t QUADIR
: 1; /*!< [2] FTM Counter Direction In Quadrature
4134 uint32_t QUADMODE
: 1; /*!< [3] Quadrature Decoder Mode */
4135 uint32_t PHBPOL
: 1; /*!< [4] Phase B Input Polarity */
4136 uint32_t PHAPOL
: 1; /*!< [5] Phase A Input Polarity */
4137 uint32_t PHBFLTREN
: 1; /*!< [6] Phase B Input Filter Enable */
4138 uint32_t PHAFLTREN
: 1; /*!< [7] Phase A Input Filter Enable */
4139 uint32_t RESERVED0
: 24; /*!< [31:8] */
4144 * @name Constants and macros for entire FTM_QDCTRL register
4147 #define HW_FTM_QDCTRL_ADDR(x) ((x) + 0x80U)
4149 #define HW_FTM_QDCTRL(x) (*(__IO hw_ftm_qdctrl_t *) HW_FTM_QDCTRL_ADDR(x))
4150 #define HW_FTM_QDCTRL_RD(x) (HW_FTM_QDCTRL(x).U)
4151 #define HW_FTM_QDCTRL_WR(x, v) (HW_FTM_QDCTRL(x).U = (v))
4152 #define HW_FTM_QDCTRL_SET(x, v) (HW_FTM_QDCTRL_WR(x, HW_FTM_QDCTRL_RD(x) | (v)))
4153 #define HW_FTM_QDCTRL_CLR(x, v) (HW_FTM_QDCTRL_WR(x, HW_FTM_QDCTRL_RD(x) & ~(v)))
4154 #define HW_FTM_QDCTRL_TOG(x, v) (HW_FTM_QDCTRL_WR(x, HW_FTM_QDCTRL_RD(x) ^ (v)))
4158 * Constants & macros for individual FTM_QDCTRL bitfields
4162 * @name Register FTM_QDCTRL, field QUADEN[0] (RW)
4164 * Enables the Quadrature Decoder mode. In this mode, the phase A and B input
4165 * signals control the FTM counter direction. The Quadrature Decoder mode has
4166 * precedence over the other modes. See #ModeSel1Table. This field is write protected.
4167 * It can be written only when MODE[WPDIS] = 1.
4170 * - 0 - Quadrature Decoder mode is disabled.
4171 * - 1 - Quadrature Decoder mode is enabled.
4174 #define BP_FTM_QDCTRL_QUADEN (0U) /*!< Bit position for FTM_QDCTRL_QUADEN. */
4175 #define BM_FTM_QDCTRL_QUADEN (0x00000001U) /*!< Bit mask for FTM_QDCTRL_QUADEN. */
4176 #define BS_FTM_QDCTRL_QUADEN (1U) /*!< Bit field size in bits for FTM_QDCTRL_QUADEN. */
4178 /*! @brief Read current value of the FTM_QDCTRL_QUADEN field. */
4179 #define BR_FTM_QDCTRL_QUADEN(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADEN))
4181 /*! @brief Format value for bitfield FTM_QDCTRL_QUADEN. */
4182 #define BF_FTM_QDCTRL_QUADEN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_QUADEN) & BM_FTM_QDCTRL_QUADEN)
4184 /*! @brief Set the QUADEN field to a new value. */
4185 #define BW_FTM_QDCTRL_QUADEN(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADEN) = (v))
4189 * @name Register FTM_QDCTRL, field TOFDIR[1] (RO)
4191 * Indicates if the TOF bit was set on the top or the bottom of counting.
4194 * - 0 - TOF bit was set on the bottom of counting. There was an FTM counter
4195 * decrement and FTM counter changes from its minimum value (CNTIN register) to
4196 * its maximum value (MOD register).
4197 * - 1 - TOF bit was set on the top of counting. There was an FTM counter
4198 * increment and FTM counter changes from its maximum value (MOD register) to its
4199 * minimum value (CNTIN register).
4202 #define BP_FTM_QDCTRL_TOFDIR (1U) /*!< Bit position for FTM_QDCTRL_TOFDIR. */
4203 #define BM_FTM_QDCTRL_TOFDIR (0x00000002U) /*!< Bit mask for FTM_QDCTRL_TOFDIR. */
4204 #define BS_FTM_QDCTRL_TOFDIR (1U) /*!< Bit field size in bits for FTM_QDCTRL_TOFDIR. */
4206 /*! @brief Read current value of the FTM_QDCTRL_TOFDIR field. */
4207 #define BR_FTM_QDCTRL_TOFDIR(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_TOFDIR))
4211 * @name Register FTM_QDCTRL, field QUADIR[2] (RO)
4213 * Indicates the counting direction.
4216 * - 0 - Counting direction is decreasing (FTM counter decrement).
4217 * - 1 - Counting direction is increasing (FTM counter increment).
4220 #define BP_FTM_QDCTRL_QUADIR (2U) /*!< Bit position for FTM_QDCTRL_QUADIR. */
4221 #define BM_FTM_QDCTRL_QUADIR (0x00000004U) /*!< Bit mask for FTM_QDCTRL_QUADIR. */
4222 #define BS_FTM_QDCTRL_QUADIR (1U) /*!< Bit field size in bits for FTM_QDCTRL_QUADIR. */
4224 /*! @brief Read current value of the FTM_QDCTRL_QUADIR field. */
4225 #define BR_FTM_QDCTRL_QUADIR(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADIR))
4229 * @name Register FTM_QDCTRL, field QUADMODE[3] (RW)
4231 * Selects the encoding mode used in the Quadrature Decoder mode.
4234 * - 0 - Phase A and phase B encoding mode.
4235 * - 1 - Count and direction encoding mode.
4238 #define BP_FTM_QDCTRL_QUADMODE (3U) /*!< Bit position for FTM_QDCTRL_QUADMODE. */
4239 #define BM_FTM_QDCTRL_QUADMODE (0x00000008U) /*!< Bit mask for FTM_QDCTRL_QUADMODE. */
4240 #define BS_FTM_QDCTRL_QUADMODE (1U) /*!< Bit field size in bits for FTM_QDCTRL_QUADMODE. */
4242 /*! @brief Read current value of the FTM_QDCTRL_QUADMODE field. */
4243 #define BR_FTM_QDCTRL_QUADMODE(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADMODE))
4245 /*! @brief Format value for bitfield FTM_QDCTRL_QUADMODE. */
4246 #define BF_FTM_QDCTRL_QUADMODE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_QUADMODE) & BM_FTM_QDCTRL_QUADMODE)
4248 /*! @brief Set the QUADMODE field to a new value. */
4249 #define BW_FTM_QDCTRL_QUADMODE(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADMODE) = (v))
4253 * @name Register FTM_QDCTRL, field PHBPOL[4] (RW)
4255 * Selects the polarity for the quadrature decoder phase B input.
4258 * - 0 - Normal polarity. Phase B input signal is not inverted before
4259 * identifying the rising and falling edges of this signal.
4260 * - 1 - Inverted polarity. Phase B input signal is inverted before identifying
4261 * the rising and falling edges of this signal.
4264 #define BP_FTM_QDCTRL_PHBPOL (4U) /*!< Bit position for FTM_QDCTRL_PHBPOL. */
4265 #define BM_FTM_QDCTRL_PHBPOL (0x00000010U) /*!< Bit mask for FTM_QDCTRL_PHBPOL. */
4266 #define BS_FTM_QDCTRL_PHBPOL (1U) /*!< Bit field size in bits for FTM_QDCTRL_PHBPOL. */
4268 /*! @brief Read current value of the FTM_QDCTRL_PHBPOL field. */
4269 #define BR_FTM_QDCTRL_PHBPOL(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBPOL))
4271 /*! @brief Format value for bitfield FTM_QDCTRL_PHBPOL. */
4272 #define BF_FTM_QDCTRL_PHBPOL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_PHBPOL) & BM_FTM_QDCTRL_PHBPOL)
4274 /*! @brief Set the PHBPOL field to a new value. */
4275 #define BW_FTM_QDCTRL_PHBPOL(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBPOL) = (v))
4279 * @name Register FTM_QDCTRL, field PHAPOL[5] (RW)
4281 * Selects the polarity for the quadrature decoder phase A input.
4284 * - 0 - Normal polarity. Phase A input signal is not inverted before
4285 * identifying the rising and falling edges of this signal.
4286 * - 1 - Inverted polarity. Phase A input signal is inverted before identifying
4287 * the rising and falling edges of this signal.
4290 #define BP_FTM_QDCTRL_PHAPOL (5U) /*!< Bit position for FTM_QDCTRL_PHAPOL. */
4291 #define BM_FTM_QDCTRL_PHAPOL (0x00000020U) /*!< Bit mask for FTM_QDCTRL_PHAPOL. */
4292 #define BS_FTM_QDCTRL_PHAPOL (1U) /*!< Bit field size in bits for FTM_QDCTRL_PHAPOL. */
4294 /*! @brief Read current value of the FTM_QDCTRL_PHAPOL field. */
4295 #define BR_FTM_QDCTRL_PHAPOL(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAPOL))
4297 /*! @brief Format value for bitfield FTM_QDCTRL_PHAPOL. */
4298 #define BF_FTM_QDCTRL_PHAPOL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_PHAPOL) & BM_FTM_QDCTRL_PHAPOL)
4300 /*! @brief Set the PHAPOL field to a new value. */
4301 #define BW_FTM_QDCTRL_PHAPOL(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAPOL) = (v))
4305 * @name Register FTM_QDCTRL, field PHBFLTREN[6] (RW)
4307 * Enables the filter for the quadrature decoder phase B input. The filter value
4308 * for the phase B input is defined by the CH1FVAL field of FILTER. The phase B
4309 * filter is also disabled when CH1FVAL is zero.
4312 * - 0 - Phase B input filter is disabled.
4313 * - 1 - Phase B input filter is enabled.
4316 #define BP_FTM_QDCTRL_PHBFLTREN (6U) /*!< Bit position for FTM_QDCTRL_PHBFLTREN. */
4317 #define BM_FTM_QDCTRL_PHBFLTREN (0x00000040U) /*!< Bit mask for FTM_QDCTRL_PHBFLTREN. */
4318 #define BS_FTM_QDCTRL_PHBFLTREN (1U) /*!< Bit field size in bits for FTM_QDCTRL_PHBFLTREN. */
4320 /*! @brief Read current value of the FTM_QDCTRL_PHBFLTREN field. */
4321 #define BR_FTM_QDCTRL_PHBFLTREN(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBFLTREN))
4323 /*! @brief Format value for bitfield FTM_QDCTRL_PHBFLTREN. */
4324 #define BF_FTM_QDCTRL_PHBFLTREN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_PHBFLTREN) & BM_FTM_QDCTRL_PHBFLTREN)
4326 /*! @brief Set the PHBFLTREN field to a new value. */
4327 #define BW_FTM_QDCTRL_PHBFLTREN(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBFLTREN) = (v))
4331 * @name Register FTM_QDCTRL, field PHAFLTREN[7] (RW)
4333 * Enables the filter for the quadrature decoder phase A input. The filter value
4334 * for the phase A input is defined by the CH0FVAL field of FILTER. The phase A
4335 * filter is also disabled when CH0FVAL is zero.
4338 * - 0 - Phase A input filter is disabled.
4339 * - 1 - Phase A input filter is enabled.
4342 #define BP_FTM_QDCTRL_PHAFLTREN (7U) /*!< Bit position for FTM_QDCTRL_PHAFLTREN. */
4343 #define BM_FTM_QDCTRL_PHAFLTREN (0x00000080U) /*!< Bit mask for FTM_QDCTRL_PHAFLTREN. */
4344 #define BS_FTM_QDCTRL_PHAFLTREN (1U) /*!< Bit field size in bits for FTM_QDCTRL_PHAFLTREN. */
4346 /*! @brief Read current value of the FTM_QDCTRL_PHAFLTREN field. */
4347 #define BR_FTM_QDCTRL_PHAFLTREN(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAFLTREN))
4349 /*! @brief Format value for bitfield FTM_QDCTRL_PHAFLTREN. */
4350 #define BF_FTM_QDCTRL_PHAFLTREN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_PHAFLTREN) & BM_FTM_QDCTRL_PHAFLTREN)
4352 /*! @brief Set the PHAFLTREN field to a new value. */
4353 #define BW_FTM_QDCTRL_PHAFLTREN(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAFLTREN) = (v))
4356 /*******************************************************************************
4357 * HW_FTM_CONF - Configuration
4358 ******************************************************************************/
4361 * @brief HW_FTM_CONF - Configuration (RW)
4363 * Reset value: 0x00000000U
4365 * This register selects the number of times that the FTM counter overflow
4366 * should occur before the TOF bit to be set, the FTM behavior in BDM modes, the use
4367 * of an external global time base, and the global time base signal generation.
4369 typedef union _hw_ftm_conf
4372 struct _hw_ftm_conf_bitfields
4374 uint32_t NUMTOF
: 5; /*!< [4:0] TOF Frequency */
4375 uint32_t RESERVED0
: 1; /*!< [5] */
4376 uint32_t BDMMODE
: 2; /*!< [7:6] BDM Mode */
4377 uint32_t RESERVED1
: 1; /*!< [8] */
4378 uint32_t GTBEEN
: 1; /*!< [9] Global Time Base Enable */
4379 uint32_t GTBEOUT
: 1; /*!< [10] Global Time Base Output */
4380 uint32_t RESERVED2
: 21; /*!< [31:11] */
4385 * @name Constants and macros for entire FTM_CONF register
4388 #define HW_FTM_CONF_ADDR(x) ((x) + 0x84U)
4390 #define HW_FTM_CONF(x) (*(__IO hw_ftm_conf_t *) HW_FTM_CONF_ADDR(x))
4391 #define HW_FTM_CONF_RD(x) (HW_FTM_CONF(x).U)
4392 #define HW_FTM_CONF_WR(x, v) (HW_FTM_CONF(x).U = (v))
4393 #define HW_FTM_CONF_SET(x, v) (HW_FTM_CONF_WR(x, HW_FTM_CONF_RD(x) | (v)))
4394 #define HW_FTM_CONF_CLR(x, v) (HW_FTM_CONF_WR(x, HW_FTM_CONF_RD(x) & ~(v)))
4395 #define HW_FTM_CONF_TOG(x, v) (HW_FTM_CONF_WR(x, HW_FTM_CONF_RD(x) ^ (v)))
4399 * Constants & macros for individual FTM_CONF bitfields
4403 * @name Register FTM_CONF, field NUMTOF[4:0] (RW)
4405 * Selects the ratio between the number of counter overflows to the number of
4406 * times the TOF bit is set. NUMTOF = 0: The TOF bit is set for each counter
4407 * overflow. NUMTOF = 1: The TOF bit is set for the first counter overflow but not for
4408 * the next overflow. NUMTOF = 2: The TOF bit is set for the first counter
4409 * overflow but not for the next 2 overflows. NUMTOF = 3: The TOF bit is set for the
4410 * first counter overflow but not for the next 3 overflows. This pattern continues
4411 * up to a maximum of 31.
4414 #define BP_FTM_CONF_NUMTOF (0U) /*!< Bit position for FTM_CONF_NUMTOF. */
4415 #define BM_FTM_CONF_NUMTOF (0x0000001FU) /*!< Bit mask for FTM_CONF_NUMTOF. */
4416 #define BS_FTM_CONF_NUMTOF (5U) /*!< Bit field size in bits for FTM_CONF_NUMTOF. */
4418 /*! @brief Read current value of the FTM_CONF_NUMTOF field. */
4419 #define BR_FTM_CONF_NUMTOF(x) (HW_FTM_CONF(x).B.NUMTOF)
4421 /*! @brief Format value for bitfield FTM_CONF_NUMTOF. */
4422 #define BF_FTM_CONF_NUMTOF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CONF_NUMTOF) & BM_FTM_CONF_NUMTOF)
4424 /*! @brief Set the NUMTOF field to a new value. */
4425 #define BW_FTM_CONF_NUMTOF(x, v) (HW_FTM_CONF_WR(x, (HW_FTM_CONF_RD(x) & ~BM_FTM_CONF_NUMTOF) | BF_FTM_CONF_NUMTOF(v)))
4429 * @name Register FTM_CONF, field BDMMODE[7:6] (RW)
4431 * Selects the FTM behavior in BDM mode. See BDM mode.
4434 #define BP_FTM_CONF_BDMMODE (6U) /*!< Bit position for FTM_CONF_BDMMODE. */
4435 #define BM_FTM_CONF_BDMMODE (0x000000C0U) /*!< Bit mask for FTM_CONF_BDMMODE. */
4436 #define BS_FTM_CONF_BDMMODE (2U) /*!< Bit field size in bits for FTM_CONF_BDMMODE. */
4438 /*! @brief Read current value of the FTM_CONF_BDMMODE field. */
4439 #define BR_FTM_CONF_BDMMODE(x) (HW_FTM_CONF(x).B.BDMMODE)
4441 /*! @brief Format value for bitfield FTM_CONF_BDMMODE. */
4442 #define BF_FTM_CONF_BDMMODE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CONF_BDMMODE) & BM_FTM_CONF_BDMMODE)
4444 /*! @brief Set the BDMMODE field to a new value. */
4445 #define BW_FTM_CONF_BDMMODE(x, v) (HW_FTM_CONF_WR(x, (HW_FTM_CONF_RD(x) & ~BM_FTM_CONF_BDMMODE) | BF_FTM_CONF_BDMMODE(v)))
4449 * @name Register FTM_CONF, field GTBEEN[9] (RW)
4451 * Configures the FTM to use an external global time base signal that is
4452 * generated by another FTM.
4455 * - 0 - Use of an external global time base is disabled.
4456 * - 1 - Use of an external global time base is enabled.
4459 #define BP_FTM_CONF_GTBEEN (9U) /*!< Bit position for FTM_CONF_GTBEEN. */
4460 #define BM_FTM_CONF_GTBEEN (0x00000200U) /*!< Bit mask for FTM_CONF_GTBEEN. */
4461 #define BS_FTM_CONF_GTBEEN (1U) /*!< Bit field size in bits for FTM_CONF_GTBEEN. */
4463 /*! @brief Read current value of the FTM_CONF_GTBEEN field. */
4464 #define BR_FTM_CONF_GTBEEN(x) (BITBAND_ACCESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEEN))
4466 /*! @brief Format value for bitfield FTM_CONF_GTBEEN. */
4467 #define BF_FTM_CONF_GTBEEN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CONF_GTBEEN) & BM_FTM_CONF_GTBEEN)
4469 /*! @brief Set the GTBEEN field to a new value. */
4470 #define BW_FTM_CONF_GTBEEN(x, v) (BITBAND_ACCESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEEN) = (v))
4474 * @name Register FTM_CONF, field GTBEOUT[10] (RW)
4476 * Enables the global time base signal generation to other FTMs.
4479 * - 0 - A global time base signal generation is disabled.
4480 * - 1 - A global time base signal generation is enabled.
4483 #define BP_FTM_CONF_GTBEOUT (10U) /*!< Bit position for FTM_CONF_GTBEOUT. */
4484 #define BM_FTM_CONF_GTBEOUT (0x00000400U) /*!< Bit mask for FTM_CONF_GTBEOUT. */
4485 #define BS_FTM_CONF_GTBEOUT (1U) /*!< Bit field size in bits for FTM_CONF_GTBEOUT. */
4487 /*! @brief Read current value of the FTM_CONF_GTBEOUT field. */
4488 #define BR_FTM_CONF_GTBEOUT(x) (BITBAND_ACCESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEOUT))
4490 /*! @brief Format value for bitfield FTM_CONF_GTBEOUT. */
4491 #define BF_FTM_CONF_GTBEOUT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CONF_GTBEOUT) & BM_FTM_CONF_GTBEOUT)
4493 /*! @brief Set the GTBEOUT field to a new value. */
4494 #define BW_FTM_CONF_GTBEOUT(x, v) (BITBAND_ACCESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEOUT) = (v))
4497 /*******************************************************************************
4498 * HW_FTM_FLTPOL - FTM Fault Input Polarity
4499 ******************************************************************************/
4502 * @brief HW_FTM_FLTPOL - FTM Fault Input Polarity (RW)
4504 * Reset value: 0x00000000U
4506 * This register defines the fault inputs polarity.
4508 typedef union _hw_ftm_fltpol
4511 struct _hw_ftm_fltpol_bitfields
4513 uint32_t FLT0POL
: 1; /*!< [0] Fault Input 0 Polarity */
4514 uint32_t FLT1POL
: 1; /*!< [1] Fault Input 1 Polarity */
4515 uint32_t FLT2POL
: 1; /*!< [2] Fault Input 2 Polarity */
4516 uint32_t FLT3POL
: 1; /*!< [3] Fault Input 3 Polarity */
4517 uint32_t RESERVED0
: 28; /*!< [31:4] */
4522 * @name Constants and macros for entire FTM_FLTPOL register
4525 #define HW_FTM_FLTPOL_ADDR(x) ((x) + 0x88U)
4527 #define HW_FTM_FLTPOL(x) (*(__IO hw_ftm_fltpol_t *) HW_FTM_FLTPOL_ADDR(x))
4528 #define HW_FTM_FLTPOL_RD(x) (HW_FTM_FLTPOL(x).U)
4529 #define HW_FTM_FLTPOL_WR(x, v) (HW_FTM_FLTPOL(x).U = (v))
4530 #define HW_FTM_FLTPOL_SET(x, v) (HW_FTM_FLTPOL_WR(x, HW_FTM_FLTPOL_RD(x) | (v)))
4531 #define HW_FTM_FLTPOL_CLR(x, v) (HW_FTM_FLTPOL_WR(x, HW_FTM_FLTPOL_RD(x) & ~(v)))
4532 #define HW_FTM_FLTPOL_TOG(x, v) (HW_FTM_FLTPOL_WR(x, HW_FTM_FLTPOL_RD(x) ^ (v)))
4536 * Constants & macros for individual FTM_FLTPOL bitfields
4540 * @name Register FTM_FLTPOL, field FLT0POL[0] (RW)
4542 * Defines the polarity of the fault input. This field is write protected. It
4543 * can be written only when MODE[WPDIS] = 1.
4546 * - 0 - The fault input polarity is active high. A 1 at the fault input
4547 * indicates a fault.
4548 * - 1 - The fault input polarity is active low. A 0 at the fault input
4549 * indicates a fault.
4552 #define BP_FTM_FLTPOL_FLT0POL (0U) /*!< Bit position for FTM_FLTPOL_FLT0POL. */
4553 #define BM_FTM_FLTPOL_FLT0POL (0x00000001U) /*!< Bit mask for FTM_FLTPOL_FLT0POL. */
4554 #define BS_FTM_FLTPOL_FLT0POL (1U) /*!< Bit field size in bits for FTM_FLTPOL_FLT0POL. */
4556 /*! @brief Read current value of the FTM_FLTPOL_FLT0POL field. */
4557 #define BR_FTM_FLTPOL_FLT0POL(x) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT0POL))
4559 /*! @brief Format value for bitfield FTM_FLTPOL_FLT0POL. */
4560 #define BF_FTM_FLTPOL_FLT0POL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTPOL_FLT0POL) & BM_FTM_FLTPOL_FLT0POL)
4562 /*! @brief Set the FLT0POL field to a new value. */
4563 #define BW_FTM_FLTPOL_FLT0POL(x, v) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT0POL) = (v))
4567 * @name Register FTM_FLTPOL, field FLT1POL[1] (RW)
4569 * Defines the polarity of the fault input. This field is write protected. It
4570 * can be written only when MODE[WPDIS] = 1.
4573 * - 0 - The fault input polarity is active high. A 1 at the fault input
4574 * indicates a fault.
4575 * - 1 - The fault input polarity is active low. A 0 at the fault input
4576 * indicates a fault.
4579 #define BP_FTM_FLTPOL_FLT1POL (1U) /*!< Bit position for FTM_FLTPOL_FLT1POL. */
4580 #define BM_FTM_FLTPOL_FLT1POL (0x00000002U) /*!< Bit mask for FTM_FLTPOL_FLT1POL. */
4581 #define BS_FTM_FLTPOL_FLT1POL (1U) /*!< Bit field size in bits for FTM_FLTPOL_FLT1POL. */
4583 /*! @brief Read current value of the FTM_FLTPOL_FLT1POL field. */
4584 #define BR_FTM_FLTPOL_FLT1POL(x) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT1POL))
4586 /*! @brief Format value for bitfield FTM_FLTPOL_FLT1POL. */
4587 #define BF_FTM_FLTPOL_FLT1POL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTPOL_FLT1POL) & BM_FTM_FLTPOL_FLT1POL)
4589 /*! @brief Set the FLT1POL field to a new value. */
4590 #define BW_FTM_FLTPOL_FLT1POL(x, v) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT1POL) = (v))
4594 * @name Register FTM_FLTPOL, field FLT2POL[2] (RW)
4596 * Defines the polarity of the fault input. This field is write protected. It
4597 * can be written only when MODE[WPDIS] = 1.
4600 * - 0 - The fault input polarity is active high. A 1 at the fault input
4601 * indicates a fault.
4602 * - 1 - The fault input polarity is active low. A 0 at the fault input
4603 * indicates a fault.
4606 #define BP_FTM_FLTPOL_FLT2POL (2U) /*!< Bit position for FTM_FLTPOL_FLT2POL. */
4607 #define BM_FTM_FLTPOL_FLT2POL (0x00000004U) /*!< Bit mask for FTM_FLTPOL_FLT2POL. */
4608 #define BS_FTM_FLTPOL_FLT2POL (1U) /*!< Bit field size in bits for FTM_FLTPOL_FLT2POL. */
4610 /*! @brief Read current value of the FTM_FLTPOL_FLT2POL field. */
4611 #define BR_FTM_FLTPOL_FLT2POL(x) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT2POL))
4613 /*! @brief Format value for bitfield FTM_FLTPOL_FLT2POL. */
4614 #define BF_FTM_FLTPOL_FLT2POL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTPOL_FLT2POL) & BM_FTM_FLTPOL_FLT2POL)
4616 /*! @brief Set the FLT2POL field to a new value. */
4617 #define BW_FTM_FLTPOL_FLT2POL(x, v) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT2POL) = (v))
4621 * @name Register FTM_FLTPOL, field FLT3POL[3] (RW)
4623 * Defines the polarity of the fault input. This field is write protected. It
4624 * can be written only when MODE[WPDIS] = 1.
4627 * - 0 - The fault input polarity is active high. A 1 at the fault input
4628 * indicates a fault.
4629 * - 1 - The fault input polarity is active low. A 0 at the fault input
4630 * indicates a fault.
4633 #define BP_FTM_FLTPOL_FLT3POL (3U) /*!< Bit position for FTM_FLTPOL_FLT3POL. */
4634 #define BM_FTM_FLTPOL_FLT3POL (0x00000008U) /*!< Bit mask for FTM_FLTPOL_FLT3POL. */
4635 #define BS_FTM_FLTPOL_FLT3POL (1U) /*!< Bit field size in bits for FTM_FLTPOL_FLT3POL. */
4637 /*! @brief Read current value of the FTM_FLTPOL_FLT3POL field. */
4638 #define BR_FTM_FLTPOL_FLT3POL(x) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT3POL))
4640 /*! @brief Format value for bitfield FTM_FLTPOL_FLT3POL. */
4641 #define BF_FTM_FLTPOL_FLT3POL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTPOL_FLT3POL) & BM_FTM_FLTPOL_FLT3POL)
4643 /*! @brief Set the FLT3POL field to a new value. */
4644 #define BW_FTM_FLTPOL_FLT3POL(x, v) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT3POL) = (v))
4647 /*******************************************************************************
4648 * HW_FTM_SYNCONF - Synchronization Configuration
4649 ******************************************************************************/
4652 * @brief HW_FTM_SYNCONF - Synchronization Configuration (RW)
4654 * Reset value: 0x00000000U
4656 * This register selects the PWM synchronization configuration, SWOCTRL, INVCTRL
4657 * and CNTIN registers synchronization, if FTM clears the TRIGj bit, where j =
4658 * 0, 1, 2, when the hardware trigger j is detected.
4660 typedef union _hw_ftm_synconf
4663 struct _hw_ftm_synconf_bitfields
4665 uint32_t HWTRIGMODE
: 1; /*!< [0] Hardware Trigger Mode */
4666 uint32_t RESERVED0
: 1; /*!< [1] */
4667 uint32_t CNTINC
: 1; /*!< [2] CNTIN Register Synchronization */
4668 uint32_t RESERVED1
: 1; /*!< [3] */
4669 uint32_t INVC
: 1; /*!< [4] INVCTRL Register Synchronization */
4670 uint32_t SWOC
: 1; /*!< [5] SWOCTRL Register Synchronization */
4671 uint32_t RESERVED2
: 1; /*!< [6] */
4672 uint32_t SYNCMODE
: 1; /*!< [7] Synchronization Mode */
4673 uint32_t SWRSTCNT
: 1; /*!< [8] */
4674 uint32_t SWWRBUF
: 1; /*!< [9] */
4675 uint32_t SWOM
: 1; /*!< [10] */
4676 uint32_t SWINVC
: 1; /*!< [11] */
4677 uint32_t SWSOC
: 1; /*!< [12] */
4678 uint32_t RESERVED3
: 3; /*!< [15:13] */
4679 uint32_t HWRSTCNT
: 1; /*!< [16] */
4680 uint32_t HWWRBUF
: 1; /*!< [17] */
4681 uint32_t HWOM
: 1; /*!< [18] */
4682 uint32_t HWINVC
: 1; /*!< [19] */
4683 uint32_t HWSOC
: 1; /*!< [20] */
4684 uint32_t RESERVED4
: 11; /*!< [31:21] */
4689 * @name Constants and macros for entire FTM_SYNCONF register
4692 #define HW_FTM_SYNCONF_ADDR(x) ((x) + 0x8CU)
4694 #define HW_FTM_SYNCONF(x) (*(__IO hw_ftm_synconf_t *) HW_FTM_SYNCONF_ADDR(x))
4695 #define HW_FTM_SYNCONF_RD(x) (HW_FTM_SYNCONF(x).U)
4696 #define HW_FTM_SYNCONF_WR(x, v) (HW_FTM_SYNCONF(x).U = (v))
4697 #define HW_FTM_SYNCONF_SET(x, v) (HW_FTM_SYNCONF_WR(x, HW_FTM_SYNCONF_RD(x) | (v)))
4698 #define HW_FTM_SYNCONF_CLR(x, v) (HW_FTM_SYNCONF_WR(x, HW_FTM_SYNCONF_RD(x) & ~(v)))
4699 #define HW_FTM_SYNCONF_TOG(x, v) (HW_FTM_SYNCONF_WR(x, HW_FTM_SYNCONF_RD(x) ^ (v)))
4703 * Constants & macros for individual FTM_SYNCONF bitfields
4707 * @name Register FTM_SYNCONF, field HWTRIGMODE[0] (RW)
4710 * - 0 - FTM clears the TRIGj bit when the hardware trigger j is detected, where
4712 * - 1 - FTM does not clear the TRIGj bit when the hardware trigger j is
4713 * detected, where j = 0, 1,2.
4716 #define BP_FTM_SYNCONF_HWTRIGMODE (0U) /*!< Bit position for FTM_SYNCONF_HWTRIGMODE. */
4717 #define BM_FTM_SYNCONF_HWTRIGMODE (0x00000001U) /*!< Bit mask for FTM_SYNCONF_HWTRIGMODE. */
4718 #define BS_FTM_SYNCONF_HWTRIGMODE (1U) /*!< Bit field size in bits for FTM_SYNCONF_HWTRIGMODE. */
4720 /*! @brief Read current value of the FTM_SYNCONF_HWTRIGMODE field. */
4721 #define BR_FTM_SYNCONF_HWTRIGMODE(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWTRIGMODE))
4723 /*! @brief Format value for bitfield FTM_SYNCONF_HWTRIGMODE. */
4724 #define BF_FTM_SYNCONF_HWTRIGMODE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWTRIGMODE) & BM_FTM_SYNCONF_HWTRIGMODE)
4726 /*! @brief Set the HWTRIGMODE field to a new value. */
4727 #define BW_FTM_SYNCONF_HWTRIGMODE(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWTRIGMODE) = (v))
4731 * @name Register FTM_SYNCONF, field CNTINC[2] (RW)
4734 * - 0 - CNTIN register is updated with its buffer value at all rising edges of
4736 * - 1 - CNTIN register is updated with its buffer value by the PWM
4740 #define BP_FTM_SYNCONF_CNTINC (2U) /*!< Bit position for FTM_SYNCONF_CNTINC. */
4741 #define BM_FTM_SYNCONF_CNTINC (0x00000004U) /*!< Bit mask for FTM_SYNCONF_CNTINC. */
4742 #define BS_FTM_SYNCONF_CNTINC (1U) /*!< Bit field size in bits for FTM_SYNCONF_CNTINC. */
4744 /*! @brief Read current value of the FTM_SYNCONF_CNTINC field. */
4745 #define BR_FTM_SYNCONF_CNTINC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_CNTINC))
4747 /*! @brief Format value for bitfield FTM_SYNCONF_CNTINC. */
4748 #define BF_FTM_SYNCONF_CNTINC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_CNTINC) & BM_FTM_SYNCONF_CNTINC)
4750 /*! @brief Set the CNTINC field to a new value. */
4751 #define BW_FTM_SYNCONF_CNTINC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_CNTINC) = (v))
4755 * @name Register FTM_SYNCONF, field INVC[4] (RW)
4758 * - 0 - INVCTRL register is updated with its buffer value at all rising edges
4760 * - 1 - INVCTRL register is updated with its buffer value by the PWM
4764 #define BP_FTM_SYNCONF_INVC (4U) /*!< Bit position for FTM_SYNCONF_INVC. */
4765 #define BM_FTM_SYNCONF_INVC (0x00000010U) /*!< Bit mask for FTM_SYNCONF_INVC. */
4766 #define BS_FTM_SYNCONF_INVC (1U) /*!< Bit field size in bits for FTM_SYNCONF_INVC. */
4768 /*! @brief Read current value of the FTM_SYNCONF_INVC field. */
4769 #define BR_FTM_SYNCONF_INVC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_INVC))
4771 /*! @brief Format value for bitfield FTM_SYNCONF_INVC. */
4772 #define BF_FTM_SYNCONF_INVC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_INVC) & BM_FTM_SYNCONF_INVC)
4774 /*! @brief Set the INVC field to a new value. */
4775 #define BW_FTM_SYNCONF_INVC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_INVC) = (v))
4779 * @name Register FTM_SYNCONF, field SWOC[5] (RW)
4782 * - 0 - SWOCTRL register is updated with its buffer value at all rising edges
4784 * - 1 - SWOCTRL register is updated with its buffer value by the PWM
4788 #define BP_FTM_SYNCONF_SWOC (5U) /*!< Bit position for FTM_SYNCONF_SWOC. */
4789 #define BM_FTM_SYNCONF_SWOC (0x00000020U) /*!< Bit mask for FTM_SYNCONF_SWOC. */
4790 #define BS_FTM_SYNCONF_SWOC (1U) /*!< Bit field size in bits for FTM_SYNCONF_SWOC. */
4792 /*! @brief Read current value of the FTM_SYNCONF_SWOC field. */
4793 #define BR_FTM_SYNCONF_SWOC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOC))
4795 /*! @brief Format value for bitfield FTM_SYNCONF_SWOC. */
4796 #define BF_FTM_SYNCONF_SWOC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWOC) & BM_FTM_SYNCONF_SWOC)
4798 /*! @brief Set the SWOC field to a new value. */
4799 #define BW_FTM_SYNCONF_SWOC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOC) = (v))
4803 * @name Register FTM_SYNCONF, field SYNCMODE[7] (RW)
4805 * Selects the PWM Synchronization mode.
4808 * - 0 - Legacy PWM synchronization is selected.
4809 * - 1 - Enhanced PWM synchronization is selected.
4812 #define BP_FTM_SYNCONF_SYNCMODE (7U) /*!< Bit position for FTM_SYNCONF_SYNCMODE. */
4813 #define BM_FTM_SYNCONF_SYNCMODE (0x00000080U) /*!< Bit mask for FTM_SYNCONF_SYNCMODE. */
4814 #define BS_FTM_SYNCONF_SYNCMODE (1U) /*!< Bit field size in bits for FTM_SYNCONF_SYNCMODE. */
4816 /*! @brief Read current value of the FTM_SYNCONF_SYNCMODE field. */
4817 #define BR_FTM_SYNCONF_SYNCMODE(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SYNCMODE))
4819 /*! @brief Format value for bitfield FTM_SYNCONF_SYNCMODE. */
4820 #define BF_FTM_SYNCONF_SYNCMODE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SYNCMODE) & BM_FTM_SYNCONF_SYNCMODE)
4822 /*! @brief Set the SYNCMODE field to a new value. */
4823 #define BW_FTM_SYNCONF_SYNCMODE(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SYNCMODE) = (v))
4827 * @name Register FTM_SYNCONF, field SWRSTCNT[8] (RW)
4829 * FTM counter synchronization is activated by the software trigger.
4832 * - 0 - The software trigger does not activate the FTM counter synchronization.
4833 * - 1 - The software trigger activates the FTM counter synchronization.
4836 #define BP_FTM_SYNCONF_SWRSTCNT (8U) /*!< Bit position for FTM_SYNCONF_SWRSTCNT. */
4837 #define BM_FTM_SYNCONF_SWRSTCNT (0x00000100U) /*!< Bit mask for FTM_SYNCONF_SWRSTCNT. */
4838 #define BS_FTM_SYNCONF_SWRSTCNT (1U) /*!< Bit field size in bits for FTM_SYNCONF_SWRSTCNT. */
4840 /*! @brief Read current value of the FTM_SYNCONF_SWRSTCNT field. */
4841 #define BR_FTM_SYNCONF_SWRSTCNT(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWRSTCNT))
4843 /*! @brief Format value for bitfield FTM_SYNCONF_SWRSTCNT. */
4844 #define BF_FTM_SYNCONF_SWRSTCNT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWRSTCNT) & BM_FTM_SYNCONF_SWRSTCNT)
4846 /*! @brief Set the SWRSTCNT field to a new value. */
4847 #define BW_FTM_SYNCONF_SWRSTCNT(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWRSTCNT) = (v))
4851 * @name Register FTM_SYNCONF, field SWWRBUF[9] (RW)
4853 * MOD, CNTIN, and CV registers synchronization is activated by the software
4857 * - 0 - The software trigger does not activate MOD, CNTIN, and CV registers
4859 * - 1 - The software trigger activates MOD, CNTIN, and CV registers
4863 #define BP_FTM_SYNCONF_SWWRBUF (9U) /*!< Bit position for FTM_SYNCONF_SWWRBUF. */
4864 #define BM_FTM_SYNCONF_SWWRBUF (0x00000200U) /*!< Bit mask for FTM_SYNCONF_SWWRBUF. */
4865 #define BS_FTM_SYNCONF_SWWRBUF (1U) /*!< Bit field size in bits for FTM_SYNCONF_SWWRBUF. */
4867 /*! @brief Read current value of the FTM_SYNCONF_SWWRBUF field. */
4868 #define BR_FTM_SYNCONF_SWWRBUF(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWWRBUF))
4870 /*! @brief Format value for bitfield FTM_SYNCONF_SWWRBUF. */
4871 #define BF_FTM_SYNCONF_SWWRBUF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWWRBUF) & BM_FTM_SYNCONF_SWWRBUF)
4873 /*! @brief Set the SWWRBUF field to a new value. */
4874 #define BW_FTM_SYNCONF_SWWRBUF(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWWRBUF) = (v))
4878 * @name Register FTM_SYNCONF, field SWOM[10] (RW)
4880 * Output mask synchronization is activated by the software trigger.
4883 * - 0 - The software trigger does not activate the OUTMASK register
4885 * - 1 - The software trigger activates the OUTMASK register synchronization.
4888 #define BP_FTM_SYNCONF_SWOM (10U) /*!< Bit position for FTM_SYNCONF_SWOM. */
4889 #define BM_FTM_SYNCONF_SWOM (0x00000400U) /*!< Bit mask for FTM_SYNCONF_SWOM. */
4890 #define BS_FTM_SYNCONF_SWOM (1U) /*!< Bit field size in bits for FTM_SYNCONF_SWOM. */
4892 /*! @brief Read current value of the FTM_SYNCONF_SWOM field. */
4893 #define BR_FTM_SYNCONF_SWOM(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOM))
4895 /*! @brief Format value for bitfield FTM_SYNCONF_SWOM. */
4896 #define BF_FTM_SYNCONF_SWOM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWOM) & BM_FTM_SYNCONF_SWOM)
4898 /*! @brief Set the SWOM field to a new value. */
4899 #define BW_FTM_SYNCONF_SWOM(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOM) = (v))
4903 * @name Register FTM_SYNCONF, field SWINVC[11] (RW)
4905 * Inverting control synchronization is activated by the software trigger.
4908 * - 0 - The software trigger does not activate the INVCTRL register
4910 * - 1 - The software trigger activates the INVCTRL register synchronization.
4913 #define BP_FTM_SYNCONF_SWINVC (11U) /*!< Bit position for FTM_SYNCONF_SWINVC. */
4914 #define BM_FTM_SYNCONF_SWINVC (0x00000800U) /*!< Bit mask for FTM_SYNCONF_SWINVC. */
4915 #define BS_FTM_SYNCONF_SWINVC (1U) /*!< Bit field size in bits for FTM_SYNCONF_SWINVC. */
4917 /*! @brief Read current value of the FTM_SYNCONF_SWINVC field. */
4918 #define BR_FTM_SYNCONF_SWINVC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWINVC))
4920 /*! @brief Format value for bitfield FTM_SYNCONF_SWINVC. */
4921 #define BF_FTM_SYNCONF_SWINVC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWINVC) & BM_FTM_SYNCONF_SWINVC)
4923 /*! @brief Set the SWINVC field to a new value. */
4924 #define BW_FTM_SYNCONF_SWINVC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWINVC) = (v))
4928 * @name Register FTM_SYNCONF, field SWSOC[12] (RW)
4930 * Software output control synchronization is activated by the software trigger.
4933 * - 0 - The software trigger does not activate the SWOCTRL register
4935 * - 1 - The software trigger activates the SWOCTRL register synchronization.
4938 #define BP_FTM_SYNCONF_SWSOC (12U) /*!< Bit position for FTM_SYNCONF_SWSOC. */
4939 #define BM_FTM_SYNCONF_SWSOC (0x00001000U) /*!< Bit mask for FTM_SYNCONF_SWSOC. */
4940 #define BS_FTM_SYNCONF_SWSOC (1U) /*!< Bit field size in bits for FTM_SYNCONF_SWSOC. */
4942 /*! @brief Read current value of the FTM_SYNCONF_SWSOC field. */
4943 #define BR_FTM_SYNCONF_SWSOC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWSOC))
4945 /*! @brief Format value for bitfield FTM_SYNCONF_SWSOC. */
4946 #define BF_FTM_SYNCONF_SWSOC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWSOC) & BM_FTM_SYNCONF_SWSOC)
4948 /*! @brief Set the SWSOC field to a new value. */
4949 #define BW_FTM_SYNCONF_SWSOC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWSOC) = (v))
4953 * @name Register FTM_SYNCONF, field HWRSTCNT[16] (RW)
4955 * FTM counter synchronization is activated by a hardware trigger.
4958 * - 0 - A hardware trigger does not activate the FTM counter synchronization.
4959 * - 1 - A hardware trigger activates the FTM counter synchronization.
4962 #define BP_FTM_SYNCONF_HWRSTCNT (16U) /*!< Bit position for FTM_SYNCONF_HWRSTCNT. */
4963 #define BM_FTM_SYNCONF_HWRSTCNT (0x00010000U) /*!< Bit mask for FTM_SYNCONF_HWRSTCNT. */
4964 #define BS_FTM_SYNCONF_HWRSTCNT (1U) /*!< Bit field size in bits for FTM_SYNCONF_HWRSTCNT. */
4966 /*! @brief Read current value of the FTM_SYNCONF_HWRSTCNT field. */
4967 #define BR_FTM_SYNCONF_HWRSTCNT(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWRSTCNT))
4969 /*! @brief Format value for bitfield FTM_SYNCONF_HWRSTCNT. */
4970 #define BF_FTM_SYNCONF_HWRSTCNT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWRSTCNT) & BM_FTM_SYNCONF_HWRSTCNT)
4972 /*! @brief Set the HWRSTCNT field to a new value. */
4973 #define BW_FTM_SYNCONF_HWRSTCNT(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWRSTCNT) = (v))
4977 * @name Register FTM_SYNCONF, field HWWRBUF[17] (RW)
4979 * MOD, CNTIN, and CV registers synchronization is activated by a hardware
4983 * - 0 - A hardware trigger does not activate MOD, CNTIN, and CV registers
4985 * - 1 - A hardware trigger activates MOD, CNTIN, and CV registers
4989 #define BP_FTM_SYNCONF_HWWRBUF (17U) /*!< Bit position for FTM_SYNCONF_HWWRBUF. */
4990 #define BM_FTM_SYNCONF_HWWRBUF (0x00020000U) /*!< Bit mask for FTM_SYNCONF_HWWRBUF. */
4991 #define BS_FTM_SYNCONF_HWWRBUF (1U) /*!< Bit field size in bits for FTM_SYNCONF_HWWRBUF. */
4993 /*! @brief Read current value of the FTM_SYNCONF_HWWRBUF field. */
4994 #define BR_FTM_SYNCONF_HWWRBUF(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWWRBUF))
4996 /*! @brief Format value for bitfield FTM_SYNCONF_HWWRBUF. */
4997 #define BF_FTM_SYNCONF_HWWRBUF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWWRBUF) & BM_FTM_SYNCONF_HWWRBUF)
4999 /*! @brief Set the HWWRBUF field to a new value. */
5000 #define BW_FTM_SYNCONF_HWWRBUF(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWWRBUF) = (v))
5004 * @name Register FTM_SYNCONF, field HWOM[18] (RW)
5006 * Output mask synchronization is activated by a hardware trigger.
5009 * - 0 - A hardware trigger does not activate the OUTMASK register
5011 * - 1 - A hardware trigger activates the OUTMASK register synchronization.
5014 #define BP_FTM_SYNCONF_HWOM (18U) /*!< Bit position for FTM_SYNCONF_HWOM. */
5015 #define BM_FTM_SYNCONF_HWOM (0x00040000U) /*!< Bit mask for FTM_SYNCONF_HWOM. */
5016 #define BS_FTM_SYNCONF_HWOM (1U) /*!< Bit field size in bits for FTM_SYNCONF_HWOM. */
5018 /*! @brief Read current value of the FTM_SYNCONF_HWOM field. */
5019 #define BR_FTM_SYNCONF_HWOM(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWOM))
5021 /*! @brief Format value for bitfield FTM_SYNCONF_HWOM. */
5022 #define BF_FTM_SYNCONF_HWOM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWOM) & BM_FTM_SYNCONF_HWOM)
5024 /*! @brief Set the HWOM field to a new value. */
5025 #define BW_FTM_SYNCONF_HWOM(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWOM) = (v))
5029 * @name Register FTM_SYNCONF, field HWINVC[19] (RW)
5031 * Inverting control synchronization is activated by a hardware trigger.
5034 * - 0 - A hardware trigger does not activate the INVCTRL register
5036 * - 1 - A hardware trigger activates the INVCTRL register synchronization.
5039 #define BP_FTM_SYNCONF_HWINVC (19U) /*!< Bit position for FTM_SYNCONF_HWINVC. */
5040 #define BM_FTM_SYNCONF_HWINVC (0x00080000U) /*!< Bit mask for FTM_SYNCONF_HWINVC. */
5041 #define BS_FTM_SYNCONF_HWINVC (1U) /*!< Bit field size in bits for FTM_SYNCONF_HWINVC. */
5043 /*! @brief Read current value of the FTM_SYNCONF_HWINVC field. */
5044 #define BR_FTM_SYNCONF_HWINVC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWINVC))
5046 /*! @brief Format value for bitfield FTM_SYNCONF_HWINVC. */
5047 #define BF_FTM_SYNCONF_HWINVC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWINVC) & BM_FTM_SYNCONF_HWINVC)
5049 /*! @brief Set the HWINVC field to a new value. */
5050 #define BW_FTM_SYNCONF_HWINVC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWINVC) = (v))
5054 * @name Register FTM_SYNCONF, field HWSOC[20] (RW)
5056 * Software output control synchronization is activated by a hardware trigger.
5059 * - 0 - A hardware trigger does not activate the SWOCTRL register
5061 * - 1 - A hardware trigger activates the SWOCTRL register synchronization.
5064 #define BP_FTM_SYNCONF_HWSOC (20U) /*!< Bit position for FTM_SYNCONF_HWSOC. */
5065 #define BM_FTM_SYNCONF_HWSOC (0x00100000U) /*!< Bit mask for FTM_SYNCONF_HWSOC. */
5066 #define BS_FTM_SYNCONF_HWSOC (1U) /*!< Bit field size in bits for FTM_SYNCONF_HWSOC. */
5068 /*! @brief Read current value of the FTM_SYNCONF_HWSOC field. */
5069 #define BR_FTM_SYNCONF_HWSOC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWSOC))
5071 /*! @brief Format value for bitfield FTM_SYNCONF_HWSOC. */
5072 #define BF_FTM_SYNCONF_HWSOC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWSOC) & BM_FTM_SYNCONF_HWSOC)
5074 /*! @brief Set the HWSOC field to a new value. */
5075 #define BW_FTM_SYNCONF_HWSOC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWSOC) = (v))
5078 /*******************************************************************************
5079 * HW_FTM_INVCTRL - FTM Inverting Control
5080 ******************************************************************************/
5083 * @brief HW_FTM_INVCTRL - FTM Inverting Control (RW)
5085 * Reset value: 0x00000000U
5087 * This register controls when the channel (n) output becomes the channel (n+1)
5088 * output, and channel (n+1) output becomes the channel (n) output. Each INVmEN
5089 * bit enables the inverting operation for the corresponding pair channels m. This
5090 * register has a write buffer. The INVmEN bit is updated by the INVCTRL
5091 * register synchronization.
5093 typedef union _hw_ftm_invctrl
5096 struct _hw_ftm_invctrl_bitfields
5098 uint32_t INV0EN
: 1; /*!< [0] Pair Channels 0 Inverting Enable */
5099 uint32_t INV1EN
: 1; /*!< [1] Pair Channels 1 Inverting Enable */
5100 uint32_t INV2EN
: 1; /*!< [2] Pair Channels 2 Inverting Enable */
5101 uint32_t INV3EN
: 1; /*!< [3] Pair Channels 3 Inverting Enable */
5102 uint32_t RESERVED0
: 28; /*!< [31:4] */
5107 * @name Constants and macros for entire FTM_INVCTRL register
5110 #define HW_FTM_INVCTRL_ADDR(x) ((x) + 0x90U)
5112 #define HW_FTM_INVCTRL(x) (*(__IO hw_ftm_invctrl_t *) HW_FTM_INVCTRL_ADDR(x))
5113 #define HW_FTM_INVCTRL_RD(x) (HW_FTM_INVCTRL(x).U)
5114 #define HW_FTM_INVCTRL_WR(x, v) (HW_FTM_INVCTRL(x).U = (v))
5115 #define HW_FTM_INVCTRL_SET(x, v) (HW_FTM_INVCTRL_WR(x, HW_FTM_INVCTRL_RD(x) | (v)))
5116 #define HW_FTM_INVCTRL_CLR(x, v) (HW_FTM_INVCTRL_WR(x, HW_FTM_INVCTRL_RD(x) & ~(v)))
5117 #define HW_FTM_INVCTRL_TOG(x, v) (HW_FTM_INVCTRL_WR(x, HW_FTM_INVCTRL_RD(x) ^ (v)))
5121 * Constants & macros for individual FTM_INVCTRL bitfields
5125 * @name Register FTM_INVCTRL, field INV0EN[0] (RW)
5128 * - 0 - Inverting is disabled.
5129 * - 1 - Inverting is enabled.
5132 #define BP_FTM_INVCTRL_INV0EN (0U) /*!< Bit position for FTM_INVCTRL_INV0EN. */
5133 #define BM_FTM_INVCTRL_INV0EN (0x00000001U) /*!< Bit mask for FTM_INVCTRL_INV0EN. */
5134 #define BS_FTM_INVCTRL_INV0EN (1U) /*!< Bit field size in bits for FTM_INVCTRL_INV0EN. */
5136 /*! @brief Read current value of the FTM_INVCTRL_INV0EN field. */
5137 #define BR_FTM_INVCTRL_INV0EN(x) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV0EN))
5139 /*! @brief Format value for bitfield FTM_INVCTRL_INV0EN. */
5140 #define BF_FTM_INVCTRL_INV0EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_INVCTRL_INV0EN) & BM_FTM_INVCTRL_INV0EN)
5142 /*! @brief Set the INV0EN field to a new value. */
5143 #define BW_FTM_INVCTRL_INV0EN(x, v) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV0EN) = (v))
5147 * @name Register FTM_INVCTRL, field INV1EN[1] (RW)
5150 * - 0 - Inverting is disabled.
5151 * - 1 - Inverting is enabled.
5154 #define BP_FTM_INVCTRL_INV1EN (1U) /*!< Bit position for FTM_INVCTRL_INV1EN. */
5155 #define BM_FTM_INVCTRL_INV1EN (0x00000002U) /*!< Bit mask for FTM_INVCTRL_INV1EN. */
5156 #define BS_FTM_INVCTRL_INV1EN (1U) /*!< Bit field size in bits for FTM_INVCTRL_INV1EN. */
5158 /*! @brief Read current value of the FTM_INVCTRL_INV1EN field. */
5159 #define BR_FTM_INVCTRL_INV1EN(x) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV1EN))
5161 /*! @brief Format value for bitfield FTM_INVCTRL_INV1EN. */
5162 #define BF_FTM_INVCTRL_INV1EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_INVCTRL_INV1EN) & BM_FTM_INVCTRL_INV1EN)
5164 /*! @brief Set the INV1EN field to a new value. */
5165 #define BW_FTM_INVCTRL_INV1EN(x, v) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV1EN) = (v))
5169 * @name Register FTM_INVCTRL, field INV2EN[2] (RW)
5172 * - 0 - Inverting is disabled.
5173 * - 1 - Inverting is enabled.
5176 #define BP_FTM_INVCTRL_INV2EN (2U) /*!< Bit position for FTM_INVCTRL_INV2EN. */
5177 #define BM_FTM_INVCTRL_INV2EN (0x00000004U) /*!< Bit mask for FTM_INVCTRL_INV2EN. */
5178 #define BS_FTM_INVCTRL_INV2EN (1U) /*!< Bit field size in bits for FTM_INVCTRL_INV2EN. */
5180 /*! @brief Read current value of the FTM_INVCTRL_INV2EN field. */
5181 #define BR_FTM_INVCTRL_INV2EN(x) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV2EN))
5183 /*! @brief Format value for bitfield FTM_INVCTRL_INV2EN. */
5184 #define BF_FTM_INVCTRL_INV2EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_INVCTRL_INV2EN) & BM_FTM_INVCTRL_INV2EN)
5186 /*! @brief Set the INV2EN field to a new value. */
5187 #define BW_FTM_INVCTRL_INV2EN(x, v) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV2EN) = (v))
5191 * @name Register FTM_INVCTRL, field INV3EN[3] (RW)
5194 * - 0 - Inverting is disabled.
5195 * - 1 - Inverting is enabled.
5198 #define BP_FTM_INVCTRL_INV3EN (3U) /*!< Bit position for FTM_INVCTRL_INV3EN. */
5199 #define BM_FTM_INVCTRL_INV3EN (0x00000008U) /*!< Bit mask for FTM_INVCTRL_INV3EN. */
5200 #define BS_FTM_INVCTRL_INV3EN (1U) /*!< Bit field size in bits for FTM_INVCTRL_INV3EN. */
5202 /*! @brief Read current value of the FTM_INVCTRL_INV3EN field. */
5203 #define BR_FTM_INVCTRL_INV3EN(x) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV3EN))
5205 /*! @brief Format value for bitfield FTM_INVCTRL_INV3EN. */
5206 #define BF_FTM_INVCTRL_INV3EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_INVCTRL_INV3EN) & BM_FTM_INVCTRL_INV3EN)
5208 /*! @brief Set the INV3EN field to a new value. */
5209 #define BW_FTM_INVCTRL_INV3EN(x, v) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV3EN) = (v))
5212 /*******************************************************************************
5213 * HW_FTM_SWOCTRL - FTM Software Output Control
5214 ******************************************************************************/
5217 * @brief HW_FTM_SWOCTRL - FTM Software Output Control (RW)
5219 * Reset value: 0x00000000U
5221 * This register enables software control of channel (n) output and defines the
5222 * value forced to the channel (n) output: The CHnOC bits enable the control of
5223 * the corresponding channel (n) output by software. The CHnOCV bits select the
5224 * value that is forced at the corresponding channel (n) output. This register has
5225 * a write buffer. The fields are updated by the SWOCTRL register synchronization.
5227 typedef union _hw_ftm_swoctrl
5230 struct _hw_ftm_swoctrl_bitfields
5232 uint32_t CH0OC
: 1; /*!< [0] Channel 0 Software Output Control Enable
5234 uint32_t CH1OC
: 1; /*!< [1] Channel 1 Software Output Control Enable
5236 uint32_t CH2OC
: 1; /*!< [2] Channel 2 Software Output Control Enable
5238 uint32_t CH3OC
: 1; /*!< [3] Channel 3 Software Output Control Enable
5240 uint32_t CH4OC
: 1; /*!< [4] Channel 4 Software Output Control Enable
5242 uint32_t CH5OC
: 1; /*!< [5] Channel 5 Software Output Control Enable
5244 uint32_t CH6OC
: 1; /*!< [6] Channel 6 Software Output Control Enable
5246 uint32_t CH7OC
: 1; /*!< [7] Channel 7 Software Output Control Enable
5248 uint32_t CH0OCV
: 1; /*!< [8] Channel 0 Software Output Control Value
5250 uint32_t CH1OCV
: 1; /*!< [9] Channel 1 Software Output Control Value
5252 uint32_t CH2OCV
: 1; /*!< [10] Channel 2 Software Output Control
5254 uint32_t CH3OCV
: 1; /*!< [11] Channel 3 Software Output Control
5256 uint32_t CH4OCV
: 1; /*!< [12] Channel 4 Software Output Control
5258 uint32_t CH5OCV
: 1; /*!< [13] Channel 5 Software Output Control
5260 uint32_t CH6OCV
: 1; /*!< [14] Channel 6 Software Output Control
5262 uint32_t CH7OCV
: 1; /*!< [15] Channel 7 Software Output Control
5264 uint32_t RESERVED0
: 16; /*!< [31:16] */
5269 * @name Constants and macros for entire FTM_SWOCTRL register
5272 #define HW_FTM_SWOCTRL_ADDR(x) ((x) + 0x94U)
5274 #define HW_FTM_SWOCTRL(x) (*(__IO hw_ftm_swoctrl_t *) HW_FTM_SWOCTRL_ADDR(x))
5275 #define HW_FTM_SWOCTRL_RD(x) (HW_FTM_SWOCTRL(x).U)
5276 #define HW_FTM_SWOCTRL_WR(x, v) (HW_FTM_SWOCTRL(x).U = (v))
5277 #define HW_FTM_SWOCTRL_SET(x, v) (HW_FTM_SWOCTRL_WR(x, HW_FTM_SWOCTRL_RD(x) | (v)))
5278 #define HW_FTM_SWOCTRL_CLR(x, v) (HW_FTM_SWOCTRL_WR(x, HW_FTM_SWOCTRL_RD(x) & ~(v)))
5279 #define HW_FTM_SWOCTRL_TOG(x, v) (HW_FTM_SWOCTRL_WR(x, HW_FTM_SWOCTRL_RD(x) ^ (v)))
5283 * Constants & macros for individual FTM_SWOCTRL bitfields
5287 * @name Register FTM_SWOCTRL, field CH0OC[0] (RW)
5290 * - 0 - The channel output is not affected by software output control.
5291 * - 1 - The channel output is affected by software output control.
5294 #define BP_FTM_SWOCTRL_CH0OC (0U) /*!< Bit position for FTM_SWOCTRL_CH0OC. */
5295 #define BM_FTM_SWOCTRL_CH0OC (0x00000001U) /*!< Bit mask for FTM_SWOCTRL_CH0OC. */
5296 #define BS_FTM_SWOCTRL_CH0OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH0OC. */
5298 /*! @brief Read current value of the FTM_SWOCTRL_CH0OC field. */
5299 #define BR_FTM_SWOCTRL_CH0OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OC))
5301 /*! @brief Format value for bitfield FTM_SWOCTRL_CH0OC. */
5302 #define BF_FTM_SWOCTRL_CH0OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH0OC) & BM_FTM_SWOCTRL_CH0OC)
5304 /*! @brief Set the CH0OC field to a new value. */
5305 #define BW_FTM_SWOCTRL_CH0OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OC) = (v))
5309 * @name Register FTM_SWOCTRL, field CH1OC[1] (RW)
5312 * - 0 - The channel output is not affected by software output control.
5313 * - 1 - The channel output is affected by software output control.
5316 #define BP_FTM_SWOCTRL_CH1OC (1U) /*!< Bit position for FTM_SWOCTRL_CH1OC. */
5317 #define BM_FTM_SWOCTRL_CH1OC (0x00000002U) /*!< Bit mask for FTM_SWOCTRL_CH1OC. */
5318 #define BS_FTM_SWOCTRL_CH1OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH1OC. */
5320 /*! @brief Read current value of the FTM_SWOCTRL_CH1OC field. */
5321 #define BR_FTM_SWOCTRL_CH1OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OC))
5323 /*! @brief Format value for bitfield FTM_SWOCTRL_CH1OC. */
5324 #define BF_FTM_SWOCTRL_CH1OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH1OC) & BM_FTM_SWOCTRL_CH1OC)
5326 /*! @brief Set the CH1OC field to a new value. */
5327 #define BW_FTM_SWOCTRL_CH1OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OC) = (v))
5331 * @name Register FTM_SWOCTRL, field CH2OC[2] (RW)
5334 * - 0 - The channel output is not affected by software output control.
5335 * - 1 - The channel output is affected by software output control.
5338 #define BP_FTM_SWOCTRL_CH2OC (2U) /*!< Bit position for FTM_SWOCTRL_CH2OC. */
5339 #define BM_FTM_SWOCTRL_CH2OC (0x00000004U) /*!< Bit mask for FTM_SWOCTRL_CH2OC. */
5340 #define BS_FTM_SWOCTRL_CH2OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH2OC. */
5342 /*! @brief Read current value of the FTM_SWOCTRL_CH2OC field. */
5343 #define BR_FTM_SWOCTRL_CH2OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OC))
5345 /*! @brief Format value for bitfield FTM_SWOCTRL_CH2OC. */
5346 #define BF_FTM_SWOCTRL_CH2OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH2OC) & BM_FTM_SWOCTRL_CH2OC)
5348 /*! @brief Set the CH2OC field to a new value. */
5349 #define BW_FTM_SWOCTRL_CH2OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OC) = (v))
5353 * @name Register FTM_SWOCTRL, field CH3OC[3] (RW)
5356 * - 0 - The channel output is not affected by software output control.
5357 * - 1 - The channel output is affected by software output control.
5360 #define BP_FTM_SWOCTRL_CH3OC (3U) /*!< Bit position for FTM_SWOCTRL_CH3OC. */
5361 #define BM_FTM_SWOCTRL_CH3OC (0x00000008U) /*!< Bit mask for FTM_SWOCTRL_CH3OC. */
5362 #define BS_FTM_SWOCTRL_CH3OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH3OC. */
5364 /*! @brief Read current value of the FTM_SWOCTRL_CH3OC field. */
5365 #define BR_FTM_SWOCTRL_CH3OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OC))
5367 /*! @brief Format value for bitfield FTM_SWOCTRL_CH3OC. */
5368 #define BF_FTM_SWOCTRL_CH3OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH3OC) & BM_FTM_SWOCTRL_CH3OC)
5370 /*! @brief Set the CH3OC field to a new value. */
5371 #define BW_FTM_SWOCTRL_CH3OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OC) = (v))
5375 * @name Register FTM_SWOCTRL, field CH4OC[4] (RW)
5378 * - 0 - The channel output is not affected by software output control.
5379 * - 1 - The channel output is affected by software output control.
5382 #define BP_FTM_SWOCTRL_CH4OC (4U) /*!< Bit position for FTM_SWOCTRL_CH4OC. */
5383 #define BM_FTM_SWOCTRL_CH4OC (0x00000010U) /*!< Bit mask for FTM_SWOCTRL_CH4OC. */
5384 #define BS_FTM_SWOCTRL_CH4OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH4OC. */
5386 /*! @brief Read current value of the FTM_SWOCTRL_CH4OC field. */
5387 #define BR_FTM_SWOCTRL_CH4OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OC))
5389 /*! @brief Format value for bitfield FTM_SWOCTRL_CH4OC. */
5390 #define BF_FTM_SWOCTRL_CH4OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH4OC) & BM_FTM_SWOCTRL_CH4OC)
5392 /*! @brief Set the CH4OC field to a new value. */
5393 #define BW_FTM_SWOCTRL_CH4OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OC) = (v))
5397 * @name Register FTM_SWOCTRL, field CH5OC[5] (RW)
5400 * - 0 - The channel output is not affected by software output control.
5401 * - 1 - The channel output is affected by software output control.
5404 #define BP_FTM_SWOCTRL_CH5OC (5U) /*!< Bit position for FTM_SWOCTRL_CH5OC. */
5405 #define BM_FTM_SWOCTRL_CH5OC (0x00000020U) /*!< Bit mask for FTM_SWOCTRL_CH5OC. */
5406 #define BS_FTM_SWOCTRL_CH5OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH5OC. */
5408 /*! @brief Read current value of the FTM_SWOCTRL_CH5OC field. */
5409 #define BR_FTM_SWOCTRL_CH5OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OC))
5411 /*! @brief Format value for bitfield FTM_SWOCTRL_CH5OC. */
5412 #define BF_FTM_SWOCTRL_CH5OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH5OC) & BM_FTM_SWOCTRL_CH5OC)
5414 /*! @brief Set the CH5OC field to a new value. */
5415 #define BW_FTM_SWOCTRL_CH5OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OC) = (v))
5419 * @name Register FTM_SWOCTRL, field CH6OC[6] (RW)
5422 * - 0 - The channel output is not affected by software output control.
5423 * - 1 - The channel output is affected by software output control.
5426 #define BP_FTM_SWOCTRL_CH6OC (6U) /*!< Bit position for FTM_SWOCTRL_CH6OC. */
5427 #define BM_FTM_SWOCTRL_CH6OC (0x00000040U) /*!< Bit mask for FTM_SWOCTRL_CH6OC. */
5428 #define BS_FTM_SWOCTRL_CH6OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH6OC. */
5430 /*! @brief Read current value of the FTM_SWOCTRL_CH6OC field. */
5431 #define BR_FTM_SWOCTRL_CH6OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OC))
5433 /*! @brief Format value for bitfield FTM_SWOCTRL_CH6OC. */
5434 #define BF_FTM_SWOCTRL_CH6OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH6OC) & BM_FTM_SWOCTRL_CH6OC)
5436 /*! @brief Set the CH6OC field to a new value. */
5437 #define BW_FTM_SWOCTRL_CH6OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OC) = (v))
5441 * @name Register FTM_SWOCTRL, field CH7OC[7] (RW)
5444 * - 0 - The channel output is not affected by software output control.
5445 * - 1 - The channel output is affected by software output control.
5448 #define BP_FTM_SWOCTRL_CH7OC (7U) /*!< Bit position for FTM_SWOCTRL_CH7OC. */
5449 #define BM_FTM_SWOCTRL_CH7OC (0x00000080U) /*!< Bit mask for FTM_SWOCTRL_CH7OC. */
5450 #define BS_FTM_SWOCTRL_CH7OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH7OC. */
5452 /*! @brief Read current value of the FTM_SWOCTRL_CH7OC field. */
5453 #define BR_FTM_SWOCTRL_CH7OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OC))
5455 /*! @brief Format value for bitfield FTM_SWOCTRL_CH7OC. */
5456 #define BF_FTM_SWOCTRL_CH7OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH7OC) & BM_FTM_SWOCTRL_CH7OC)
5458 /*! @brief Set the CH7OC field to a new value. */
5459 #define BW_FTM_SWOCTRL_CH7OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OC) = (v))
5463 * @name Register FTM_SWOCTRL, field CH0OCV[8] (RW)
5466 * - 0 - The software output control forces 0 to the channel output.
5467 * - 1 - The software output control forces 1 to the channel output.
5470 #define BP_FTM_SWOCTRL_CH0OCV (8U) /*!< Bit position for FTM_SWOCTRL_CH0OCV. */
5471 #define BM_FTM_SWOCTRL_CH0OCV (0x00000100U) /*!< Bit mask for FTM_SWOCTRL_CH0OCV. */
5472 #define BS_FTM_SWOCTRL_CH0OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH0OCV. */
5474 /*! @brief Read current value of the FTM_SWOCTRL_CH0OCV field. */
5475 #define BR_FTM_SWOCTRL_CH0OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OCV))
5477 /*! @brief Format value for bitfield FTM_SWOCTRL_CH0OCV. */
5478 #define BF_FTM_SWOCTRL_CH0OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH0OCV) & BM_FTM_SWOCTRL_CH0OCV)
5480 /*! @brief Set the CH0OCV field to a new value. */
5481 #define BW_FTM_SWOCTRL_CH0OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OCV) = (v))
5485 * @name Register FTM_SWOCTRL, field CH1OCV[9] (RW)
5488 * - 0 - The software output control forces 0 to the channel output.
5489 * - 1 - The software output control forces 1 to the channel output.
5492 #define BP_FTM_SWOCTRL_CH1OCV (9U) /*!< Bit position for FTM_SWOCTRL_CH1OCV. */
5493 #define BM_FTM_SWOCTRL_CH1OCV (0x00000200U) /*!< Bit mask for FTM_SWOCTRL_CH1OCV. */
5494 #define BS_FTM_SWOCTRL_CH1OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH1OCV. */
5496 /*! @brief Read current value of the FTM_SWOCTRL_CH1OCV field. */
5497 #define BR_FTM_SWOCTRL_CH1OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OCV))
5499 /*! @brief Format value for bitfield FTM_SWOCTRL_CH1OCV. */
5500 #define BF_FTM_SWOCTRL_CH1OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH1OCV) & BM_FTM_SWOCTRL_CH1OCV)
5502 /*! @brief Set the CH1OCV field to a new value. */
5503 #define BW_FTM_SWOCTRL_CH1OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OCV) = (v))
5507 * @name Register FTM_SWOCTRL, field CH2OCV[10] (RW)
5510 * - 0 - The software output control forces 0 to the channel output.
5511 * - 1 - The software output control forces 1 to the channel output.
5514 #define BP_FTM_SWOCTRL_CH2OCV (10U) /*!< Bit position for FTM_SWOCTRL_CH2OCV. */
5515 #define BM_FTM_SWOCTRL_CH2OCV (0x00000400U) /*!< Bit mask for FTM_SWOCTRL_CH2OCV. */
5516 #define BS_FTM_SWOCTRL_CH2OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH2OCV. */
5518 /*! @brief Read current value of the FTM_SWOCTRL_CH2OCV field. */
5519 #define BR_FTM_SWOCTRL_CH2OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OCV))
5521 /*! @brief Format value for bitfield FTM_SWOCTRL_CH2OCV. */
5522 #define BF_FTM_SWOCTRL_CH2OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH2OCV) & BM_FTM_SWOCTRL_CH2OCV)
5524 /*! @brief Set the CH2OCV field to a new value. */
5525 #define BW_FTM_SWOCTRL_CH2OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OCV) = (v))
5529 * @name Register FTM_SWOCTRL, field CH3OCV[11] (RW)
5532 * - 0 - The software output control forces 0 to the channel output.
5533 * - 1 - The software output control forces 1 to the channel output.
5536 #define BP_FTM_SWOCTRL_CH3OCV (11U) /*!< Bit position for FTM_SWOCTRL_CH3OCV. */
5537 #define BM_FTM_SWOCTRL_CH3OCV (0x00000800U) /*!< Bit mask for FTM_SWOCTRL_CH3OCV. */
5538 #define BS_FTM_SWOCTRL_CH3OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH3OCV. */
5540 /*! @brief Read current value of the FTM_SWOCTRL_CH3OCV field. */
5541 #define BR_FTM_SWOCTRL_CH3OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OCV))
5543 /*! @brief Format value for bitfield FTM_SWOCTRL_CH3OCV. */
5544 #define BF_FTM_SWOCTRL_CH3OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH3OCV) & BM_FTM_SWOCTRL_CH3OCV)
5546 /*! @brief Set the CH3OCV field to a new value. */
5547 #define BW_FTM_SWOCTRL_CH3OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OCV) = (v))
5551 * @name Register FTM_SWOCTRL, field CH4OCV[12] (RW)
5554 * - 0 - The software output control forces 0 to the channel output.
5555 * - 1 - The software output control forces 1 to the channel output.
5558 #define BP_FTM_SWOCTRL_CH4OCV (12U) /*!< Bit position for FTM_SWOCTRL_CH4OCV. */
5559 #define BM_FTM_SWOCTRL_CH4OCV (0x00001000U) /*!< Bit mask for FTM_SWOCTRL_CH4OCV. */
5560 #define BS_FTM_SWOCTRL_CH4OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH4OCV. */
5562 /*! @brief Read current value of the FTM_SWOCTRL_CH4OCV field. */
5563 #define BR_FTM_SWOCTRL_CH4OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OCV))
5565 /*! @brief Format value for bitfield FTM_SWOCTRL_CH4OCV. */
5566 #define BF_FTM_SWOCTRL_CH4OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH4OCV) & BM_FTM_SWOCTRL_CH4OCV)
5568 /*! @brief Set the CH4OCV field to a new value. */
5569 #define BW_FTM_SWOCTRL_CH4OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OCV) = (v))
5573 * @name Register FTM_SWOCTRL, field CH5OCV[13] (RW)
5576 * - 0 - The software output control forces 0 to the channel output.
5577 * - 1 - The software output control forces 1 to the channel output.
5580 #define BP_FTM_SWOCTRL_CH5OCV (13U) /*!< Bit position for FTM_SWOCTRL_CH5OCV. */
5581 #define BM_FTM_SWOCTRL_CH5OCV (0x00002000U) /*!< Bit mask for FTM_SWOCTRL_CH5OCV. */
5582 #define BS_FTM_SWOCTRL_CH5OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH5OCV. */
5584 /*! @brief Read current value of the FTM_SWOCTRL_CH5OCV field. */
5585 #define BR_FTM_SWOCTRL_CH5OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OCV))
5587 /*! @brief Format value for bitfield FTM_SWOCTRL_CH5OCV. */
5588 #define BF_FTM_SWOCTRL_CH5OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH5OCV) & BM_FTM_SWOCTRL_CH5OCV)
5590 /*! @brief Set the CH5OCV field to a new value. */
5591 #define BW_FTM_SWOCTRL_CH5OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OCV) = (v))
5595 * @name Register FTM_SWOCTRL, field CH6OCV[14] (RW)
5598 * - 0 - The software output control forces 0 to the channel output.
5599 * - 1 - The software output control forces 1 to the channel output.
5602 #define BP_FTM_SWOCTRL_CH6OCV (14U) /*!< Bit position for FTM_SWOCTRL_CH6OCV. */
5603 #define BM_FTM_SWOCTRL_CH6OCV (0x00004000U) /*!< Bit mask for FTM_SWOCTRL_CH6OCV. */
5604 #define BS_FTM_SWOCTRL_CH6OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH6OCV. */
5606 /*! @brief Read current value of the FTM_SWOCTRL_CH6OCV field. */
5607 #define BR_FTM_SWOCTRL_CH6OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OCV))
5609 /*! @brief Format value for bitfield FTM_SWOCTRL_CH6OCV. */
5610 #define BF_FTM_SWOCTRL_CH6OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH6OCV) & BM_FTM_SWOCTRL_CH6OCV)
5612 /*! @brief Set the CH6OCV field to a new value. */
5613 #define BW_FTM_SWOCTRL_CH6OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OCV) = (v))
5617 * @name Register FTM_SWOCTRL, field CH7OCV[15] (RW)
5620 * - 0 - The software output control forces 0 to the channel output.
5621 * - 1 - The software output control forces 1 to the channel output.
5624 #define BP_FTM_SWOCTRL_CH7OCV (15U) /*!< Bit position for FTM_SWOCTRL_CH7OCV. */
5625 #define BM_FTM_SWOCTRL_CH7OCV (0x00008000U) /*!< Bit mask for FTM_SWOCTRL_CH7OCV. */
5626 #define BS_FTM_SWOCTRL_CH7OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH7OCV. */
5628 /*! @brief Read current value of the FTM_SWOCTRL_CH7OCV field. */
5629 #define BR_FTM_SWOCTRL_CH7OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OCV))
5631 /*! @brief Format value for bitfield FTM_SWOCTRL_CH7OCV. */
5632 #define BF_FTM_SWOCTRL_CH7OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH7OCV) & BM_FTM_SWOCTRL_CH7OCV)
5634 /*! @brief Set the CH7OCV field to a new value. */
5635 #define BW_FTM_SWOCTRL_CH7OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OCV) = (v))
5638 /*******************************************************************************
5639 * HW_FTM_PWMLOAD - FTM PWM Load
5640 ******************************************************************************/
5643 * @brief HW_FTM_PWMLOAD - FTM PWM Load (RW)
5645 * Reset value: 0x00000000U
5647 * Enables the loading of the MOD, CNTIN, C(n)V, and C(n+1)V registers with the
5648 * values of their write buffers when the FTM counter changes from the MOD
5649 * register value to its next value or when a channel (j) match occurs. A match occurs
5650 * for the channel (j) when FTM counter = C(j)V.
5652 typedef union _hw_ftm_pwmload
5655 struct _hw_ftm_pwmload_bitfields
5657 uint32_t CH0SEL
: 1; /*!< [0] Channel 0 Select */
5658 uint32_t CH1SEL
: 1; /*!< [1] Channel 1 Select */
5659 uint32_t CH2SEL
: 1; /*!< [2] Channel 2 Select */
5660 uint32_t CH3SEL
: 1; /*!< [3] Channel 3 Select */
5661 uint32_t CH4SEL
: 1; /*!< [4] Channel 4 Select */
5662 uint32_t CH5SEL
: 1; /*!< [5] Channel 5 Select */
5663 uint32_t CH6SEL
: 1; /*!< [6] Channel 6 Select */
5664 uint32_t CH7SEL
: 1; /*!< [7] Channel 7 Select */
5665 uint32_t RESERVED0
: 1; /*!< [8] */
5666 uint32_t LDOK
: 1; /*!< [9] Load Enable */
5667 uint32_t RESERVED1
: 22; /*!< [31:10] */
5672 * @name Constants and macros for entire FTM_PWMLOAD register
5675 #define HW_FTM_PWMLOAD_ADDR(x) ((x) + 0x98U)
5677 #define HW_FTM_PWMLOAD(x) (*(__IO hw_ftm_pwmload_t *) HW_FTM_PWMLOAD_ADDR(x))
5678 #define HW_FTM_PWMLOAD_RD(x) (HW_FTM_PWMLOAD(x).U)
5679 #define HW_FTM_PWMLOAD_WR(x, v) (HW_FTM_PWMLOAD(x).U = (v))
5680 #define HW_FTM_PWMLOAD_SET(x, v) (HW_FTM_PWMLOAD_WR(x, HW_FTM_PWMLOAD_RD(x) | (v)))
5681 #define HW_FTM_PWMLOAD_CLR(x, v) (HW_FTM_PWMLOAD_WR(x, HW_FTM_PWMLOAD_RD(x) & ~(v)))
5682 #define HW_FTM_PWMLOAD_TOG(x, v) (HW_FTM_PWMLOAD_WR(x, HW_FTM_PWMLOAD_RD(x) ^ (v)))
5686 * Constants & macros for individual FTM_PWMLOAD bitfields
5690 * @name Register FTM_PWMLOAD, field CH0SEL[0] (RW)
5693 * - 0 - Do not include the channel in the matching process.
5694 * - 1 - Include the channel in the matching process.
5697 #define BP_FTM_PWMLOAD_CH0SEL (0U) /*!< Bit position for FTM_PWMLOAD_CH0SEL. */
5698 #define BM_FTM_PWMLOAD_CH0SEL (0x00000001U) /*!< Bit mask for FTM_PWMLOAD_CH0SEL. */
5699 #define BS_FTM_PWMLOAD_CH0SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH0SEL. */
5701 /*! @brief Read current value of the FTM_PWMLOAD_CH0SEL field. */
5702 #define BR_FTM_PWMLOAD_CH0SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH0SEL))
5704 /*! @brief Format value for bitfield FTM_PWMLOAD_CH0SEL. */
5705 #define BF_FTM_PWMLOAD_CH0SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH0SEL) & BM_FTM_PWMLOAD_CH0SEL)
5707 /*! @brief Set the CH0SEL field to a new value. */
5708 #define BW_FTM_PWMLOAD_CH0SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH0SEL) = (v))
5712 * @name Register FTM_PWMLOAD, field CH1SEL[1] (RW)
5715 * - 0 - Do not include the channel in the matching process.
5716 * - 1 - Include the channel in the matching process.
5719 #define BP_FTM_PWMLOAD_CH1SEL (1U) /*!< Bit position for FTM_PWMLOAD_CH1SEL. */
5720 #define BM_FTM_PWMLOAD_CH1SEL (0x00000002U) /*!< Bit mask for FTM_PWMLOAD_CH1SEL. */
5721 #define BS_FTM_PWMLOAD_CH1SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH1SEL. */
5723 /*! @brief Read current value of the FTM_PWMLOAD_CH1SEL field. */
5724 #define BR_FTM_PWMLOAD_CH1SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH1SEL))
5726 /*! @brief Format value for bitfield FTM_PWMLOAD_CH1SEL. */
5727 #define BF_FTM_PWMLOAD_CH1SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH1SEL) & BM_FTM_PWMLOAD_CH1SEL)
5729 /*! @brief Set the CH1SEL field to a new value. */
5730 #define BW_FTM_PWMLOAD_CH1SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH1SEL) = (v))
5734 * @name Register FTM_PWMLOAD, field CH2SEL[2] (RW)
5737 * - 0 - Do not include the channel in the matching process.
5738 * - 1 - Include the channel in the matching process.
5741 #define BP_FTM_PWMLOAD_CH2SEL (2U) /*!< Bit position for FTM_PWMLOAD_CH2SEL. */
5742 #define BM_FTM_PWMLOAD_CH2SEL (0x00000004U) /*!< Bit mask for FTM_PWMLOAD_CH2SEL. */
5743 #define BS_FTM_PWMLOAD_CH2SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH2SEL. */
5745 /*! @brief Read current value of the FTM_PWMLOAD_CH2SEL field. */
5746 #define BR_FTM_PWMLOAD_CH2SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH2SEL))
5748 /*! @brief Format value for bitfield FTM_PWMLOAD_CH2SEL. */
5749 #define BF_FTM_PWMLOAD_CH2SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH2SEL) & BM_FTM_PWMLOAD_CH2SEL)
5751 /*! @brief Set the CH2SEL field to a new value. */
5752 #define BW_FTM_PWMLOAD_CH2SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH2SEL) = (v))
5756 * @name Register FTM_PWMLOAD, field CH3SEL[3] (RW)
5759 * - 0 - Do not include the channel in the matching process.
5760 * - 1 - Include the channel in the matching process.
5763 #define BP_FTM_PWMLOAD_CH3SEL (3U) /*!< Bit position for FTM_PWMLOAD_CH3SEL. */
5764 #define BM_FTM_PWMLOAD_CH3SEL (0x00000008U) /*!< Bit mask for FTM_PWMLOAD_CH3SEL. */
5765 #define BS_FTM_PWMLOAD_CH3SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH3SEL. */
5767 /*! @brief Read current value of the FTM_PWMLOAD_CH3SEL field. */
5768 #define BR_FTM_PWMLOAD_CH3SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH3SEL))
5770 /*! @brief Format value for bitfield FTM_PWMLOAD_CH3SEL. */
5771 #define BF_FTM_PWMLOAD_CH3SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH3SEL) & BM_FTM_PWMLOAD_CH3SEL)
5773 /*! @brief Set the CH3SEL field to a new value. */
5774 #define BW_FTM_PWMLOAD_CH3SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH3SEL) = (v))
5778 * @name Register FTM_PWMLOAD, field CH4SEL[4] (RW)
5781 * - 0 - Do not include the channel in the matching process.
5782 * - 1 - Include the channel in the matching process.
5785 #define BP_FTM_PWMLOAD_CH4SEL (4U) /*!< Bit position for FTM_PWMLOAD_CH4SEL. */
5786 #define BM_FTM_PWMLOAD_CH4SEL (0x00000010U) /*!< Bit mask for FTM_PWMLOAD_CH4SEL. */
5787 #define BS_FTM_PWMLOAD_CH4SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH4SEL. */
5789 /*! @brief Read current value of the FTM_PWMLOAD_CH4SEL field. */
5790 #define BR_FTM_PWMLOAD_CH4SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH4SEL))
5792 /*! @brief Format value for bitfield FTM_PWMLOAD_CH4SEL. */
5793 #define BF_FTM_PWMLOAD_CH4SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH4SEL) & BM_FTM_PWMLOAD_CH4SEL)
5795 /*! @brief Set the CH4SEL field to a new value. */
5796 #define BW_FTM_PWMLOAD_CH4SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH4SEL) = (v))
5800 * @name Register FTM_PWMLOAD, field CH5SEL[5] (RW)
5803 * - 0 - Do not include the channel in the matching process.
5804 * - 1 - Include the channel in the matching process.
5807 #define BP_FTM_PWMLOAD_CH5SEL (5U) /*!< Bit position for FTM_PWMLOAD_CH5SEL. */
5808 #define BM_FTM_PWMLOAD_CH5SEL (0x00000020U) /*!< Bit mask for FTM_PWMLOAD_CH5SEL. */
5809 #define BS_FTM_PWMLOAD_CH5SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH5SEL. */
5811 /*! @brief Read current value of the FTM_PWMLOAD_CH5SEL field. */
5812 #define BR_FTM_PWMLOAD_CH5SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH5SEL))
5814 /*! @brief Format value for bitfield FTM_PWMLOAD_CH5SEL. */
5815 #define BF_FTM_PWMLOAD_CH5SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH5SEL) & BM_FTM_PWMLOAD_CH5SEL)
5817 /*! @brief Set the CH5SEL field to a new value. */
5818 #define BW_FTM_PWMLOAD_CH5SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH5SEL) = (v))
5822 * @name Register FTM_PWMLOAD, field CH6SEL[6] (RW)
5825 * - 0 - Do not include the channel in the matching process.
5826 * - 1 - Include the channel in the matching process.
5829 #define BP_FTM_PWMLOAD_CH6SEL (6U) /*!< Bit position for FTM_PWMLOAD_CH6SEL. */
5830 #define BM_FTM_PWMLOAD_CH6SEL (0x00000040U) /*!< Bit mask for FTM_PWMLOAD_CH6SEL. */
5831 #define BS_FTM_PWMLOAD_CH6SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH6SEL. */
5833 /*! @brief Read current value of the FTM_PWMLOAD_CH6SEL field. */
5834 #define BR_FTM_PWMLOAD_CH6SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH6SEL))
5836 /*! @brief Format value for bitfield FTM_PWMLOAD_CH6SEL. */
5837 #define BF_FTM_PWMLOAD_CH6SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH6SEL) & BM_FTM_PWMLOAD_CH6SEL)
5839 /*! @brief Set the CH6SEL field to a new value. */
5840 #define BW_FTM_PWMLOAD_CH6SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH6SEL) = (v))
5844 * @name Register FTM_PWMLOAD, field CH7SEL[7] (RW)
5847 * - 0 - Do not include the channel in the matching process.
5848 * - 1 - Include the channel in the matching process.
5851 #define BP_FTM_PWMLOAD_CH7SEL (7U) /*!< Bit position for FTM_PWMLOAD_CH7SEL. */
5852 #define BM_FTM_PWMLOAD_CH7SEL (0x00000080U) /*!< Bit mask for FTM_PWMLOAD_CH7SEL. */
5853 #define BS_FTM_PWMLOAD_CH7SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH7SEL. */
5855 /*! @brief Read current value of the FTM_PWMLOAD_CH7SEL field. */
5856 #define BR_FTM_PWMLOAD_CH7SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH7SEL))
5858 /*! @brief Format value for bitfield FTM_PWMLOAD_CH7SEL. */
5859 #define BF_FTM_PWMLOAD_CH7SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH7SEL) & BM_FTM_PWMLOAD_CH7SEL)
5861 /*! @brief Set the CH7SEL field to a new value. */
5862 #define BW_FTM_PWMLOAD_CH7SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH7SEL) = (v))
5866 * @name Register FTM_PWMLOAD, field LDOK[9] (RW)
5868 * Enables the loading of the MOD, CNTIN, and CV registers with the values of
5869 * their write buffers.
5872 * - 0 - Loading updated values is disabled.
5873 * - 1 - Loading updated values is enabled.
5876 #define BP_FTM_PWMLOAD_LDOK (9U) /*!< Bit position for FTM_PWMLOAD_LDOK. */
5877 #define BM_FTM_PWMLOAD_LDOK (0x00000200U) /*!< Bit mask for FTM_PWMLOAD_LDOK. */
5878 #define BS_FTM_PWMLOAD_LDOK (1U) /*!< Bit field size in bits for FTM_PWMLOAD_LDOK. */
5880 /*! @brief Read current value of the FTM_PWMLOAD_LDOK field. */
5881 #define BR_FTM_PWMLOAD_LDOK(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_LDOK))
5883 /*! @brief Format value for bitfield FTM_PWMLOAD_LDOK. */
5884 #define BF_FTM_PWMLOAD_LDOK(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_LDOK) & BM_FTM_PWMLOAD_LDOK)
5886 /*! @brief Set the LDOK field to a new value. */
5887 #define BW_FTM_PWMLOAD_LDOK(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_LDOK) = (v))
5890 /*******************************************************************************
5891 * hw_ftm_t - module struct
5892 ******************************************************************************/
5894 * @brief All FTM module registers.
5897 typedef struct _hw_ftm
5899 __IO hw_ftm_sc_t SC
; /*!< [0x0] Status And Control */
5900 __IO hw_ftm_cnt_t CNT
; /*!< [0x4] Counter */
5901 __IO hw_ftm_mod_t MOD
; /*!< [0x8] Modulo */
5903 __IO hw_ftm_cnsc_t CnSC
; /*!< [0xC] Channel (n) Status And Control */
5904 __IO hw_ftm_cnv_t CnV
; /*!< [0x10] Channel (n) Value */
5906 __IO hw_ftm_cntin_t CNTIN
; /*!< [0x4C] Counter Initial Value */
5907 __IO hw_ftm_status_t STATUS
; /*!< [0x50] Capture And Compare Status */
5908 __IO hw_ftm_mode_t MODE
; /*!< [0x54] Features Mode Selection */
5909 __IO hw_ftm_sync_t SYNC
; /*!< [0x58] Synchronization */
5910 __IO hw_ftm_outinit_t OUTINIT
; /*!< [0x5C] Initial State For Channels Output */
5911 __IO hw_ftm_outmask_t OUTMASK
; /*!< [0x60] Output Mask */
5912 __IO hw_ftm_combine_t COMBINE
; /*!< [0x64] Function For Linked Channels */
5913 __IO hw_ftm_deadtime_t DEADTIME
; /*!< [0x68] Deadtime Insertion Control */
5914 __IO hw_ftm_exttrig_t EXTTRIG
; /*!< [0x6C] FTM External Trigger */
5915 __IO hw_ftm_pol_t POL
; /*!< [0x70] Channels Polarity */
5916 __IO hw_ftm_fms_t FMS
; /*!< [0x74] Fault Mode Status */
5917 __IO hw_ftm_filter_t FILTER
; /*!< [0x78] Input Capture Filter Control */
5918 __IO hw_ftm_fltctrl_t FLTCTRL
; /*!< [0x7C] Fault Control */
5919 __IO hw_ftm_qdctrl_t QDCTRL
; /*!< [0x80] Quadrature Decoder Control And Status */
5920 __IO hw_ftm_conf_t CONF
; /*!< [0x84] Configuration */
5921 __IO hw_ftm_fltpol_t FLTPOL
; /*!< [0x88] FTM Fault Input Polarity */
5922 __IO hw_ftm_synconf_t SYNCONF
; /*!< [0x8C] Synchronization Configuration */
5923 __IO hw_ftm_invctrl_t INVCTRL
; /*!< [0x90] FTM Inverting Control */
5924 __IO hw_ftm_swoctrl_t SWOCTRL
; /*!< [0x94] FTM Software Output Control */
5925 __IO hw_ftm_pwmload_t PWMLOAD
; /*!< [0x98] FTM PWM Load */
5929 /*! @brief Macro to access all FTM registers. */
5930 /*! @param x FTM module instance base address. */
5931 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
5932 * use the '&' operator, like <code>&HW_FTM(FTM0_BASE)</code>. */
5933 #define HW_FTM(x) (*(hw_ftm_t *)(x))
5935 #endif /* __HW_FTM_REGISTERS_H__ */