tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_gpio.h

   1 /*
   2 ** ###################################################################
   3 **     Compilers:           Keil ARM C/C++ Compiler
   4 **                          Freescale C/C++ for Embedded ARM
   5 **                          GNU C Compiler
   6 **                          IAR ANSI C/C++ Compiler for ARM
   7 **
   8 **     Reference manual:    K22P121M120SF7RM, Rev. 1, March 24, 2014
   9 **     Version:             rev. 2.5, 2014-05-06
  10 **     Build:               b140604
  11 **
  12 **     Abstract:
  13 **         Extension to the CMSIS register access layer header.
  14 **
  15 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
  16 **     All rights reserved.
  17 **
  18 **     Redistribution and use in source and binary forms, with or without modification,
  19 **     are permitted provided that the following conditions are met:
  20 **
  21 **     o Redistributions of source code must retain the above copyright notice, this list
  22 **       of conditions and the following disclaimer.
  23 **
  24 **     o Redistributions in binary form must reproduce the above copyright notice, this
  25 **       list of conditions and the following disclaimer in the documentation and/or
  26 **       other materials provided with the distribution.
  27 **
  28 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  29 **       contributors may be used to endorse or promote products derived from this
  30 **       software without specific prior written permission.
  31 **
  32 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  33 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  34 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  35 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  36 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  37 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  38 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  39 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  41 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42 **
  43 **     http:                 www.freescale.com
  44 **     mail:                 support@freescale.com
  45 **
  46 **     Revisions:
  47 **     - rev. 1.0 (2013-07-23)
  48 **         Initial version.
  49 **     - rev. 1.1 (2013-09-17)
  50 **         RM rev. 0.4 update.
  51 **     - rev. 2.0 (2013-10-29)
  52 **         Register accessor macros added to the memory map.
  53 **         Symbols for Processor Expert memory map compatibility added to the memory map.
  54 **         Startup file for gcc has been updated according to CMSIS 3.2.
  55 **         System initialization updated.
  56 **     - rev. 2.1 (2013-10-30)
  57 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
  58 **     - rev. 2.2 (2013-12-20)
  59 **         Update according to reference manual rev. 0.6,
  60 **     - rev. 2.3 (2014-01-13)
  61 **         Update according to reference manual rev. 0.61,
  62 **     - rev. 2.4 (2014-02-10)
  63 **         The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
  64 **     - rev. 2.5 (2014-05-06)
  65 **         Update according to reference manual rev. 1.0,
  66 **         Update of system and startup files.
  67 **         Module access macro module_BASES replaced by module_BASE_PTRS.
  68 **
  69 ** ###################################################################
  70 */
  71
  72 /*
  73  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
  74  *
  75  * This file was generated automatically and any changes may be lost.
  76  */
  77 #ifndef __HW_GPIO_REGISTERS_H__
  78 #define __HW_GPIO_REGISTERS_H__
  79
  80 #include "MK22F51212.h"
  81 #include "fsl_bitaccess.h"
  82
  83 /*
  84  * MK22F51212 GPIO
  85  *
  86  * General Purpose Input/Output
  87  *
  88  * Registers defined in this header file:
  89  * - HW_GPIO_PDOR - Port Data Output Register
  90  * - HW_GPIO_PSOR - Port Set Output Register
  91  * - HW_GPIO_PCOR - Port Clear Output Register
  92  * - HW_GPIO_PTOR - Port Toggle Output Register
  93  * - HW_GPIO_PDIR - Port Data Input Register
  94  * - HW_GPIO_PDDR - Port Data Direction Register
  95  *
  96  * - hw_gpio_t - Struct containing all module registers.
  97  */
  98
  99 #define HW_GPIO_INSTANCE_COUNT (5U) /*!< Number of instances of the GPIO module. */
 100 #define HW_GPIOA (0U) /*!< Instance number for GPIOA. */
 101 #define HW_GPIOB (1U) /*!< Instance number for GPIOB. */
 102 #define HW_GPIOC (2U) /*!< Instance number for GPIOC. */
 103 #define HW_GPIOD (3U) /*!< Instance number for GPIOD. */
 104 #define HW_GPIOE (4U) /*!< Instance number for GPIOE. */
 105
 106 /*******************************************************************************
 107  * HW_GPIO_PDOR - Port Data Output Register
 108  ******************************************************************************/
 109
 110 /*!
 111  * @brief HW_GPIO_PDOR - Port Data Output Register (RW)
 112  *
 113  * Reset value: 0x00000000U
 114  *
 115  * This register configures the logic levels that are driven on each
 116  * general-purpose output pins. Do not modify pin configuration registers associated with
 117  * pins not available in your selected package. All unbonded pins not available in
 118  * your package will default to DISABLE state for lowest power consumption.
 119  */
 120 typedef union _hw_gpio_pdor
 121 {
 122     uint32_t U;
 123     struct _hw_gpio_pdor_bitfields
 124     {
 125         uint32_t PDO : 32;             /*!< [31:0] Port Data Output */
 126     } B;
 127 } hw_gpio_pdor_t;
 128
 129 /*!
 130  * @name Constants and macros for entire GPIO_PDOR register
 131  */
 132 /*@{*/
 133 #define HW_GPIO_PDOR_ADDR(x)     ((x) + 0x0U)
 134
 135 #define HW_GPIO_PDOR(x)          (*(__IO hw_gpio_pdor_t *) HW_GPIO_PDOR_ADDR(x))
 136 #define HW_GPIO_PDOR_RD(x)       (HW_GPIO_PDOR(x).U)
 137 #define HW_GPIO_PDOR_WR(x, v)    (HW_GPIO_PDOR(x).U = (v))
 138 #define HW_GPIO_PDOR_SET(x, v)   (HW_GPIO_PDOR_WR(x, HW_GPIO_PDOR_RD(x) |  (v)))
 139 #define HW_GPIO_PDOR_CLR(x, v)   (HW_GPIO_PDOR_WR(x, HW_GPIO_PDOR_RD(x) & ~(v)))
 140 #define HW_GPIO_PDOR_TOG(x, v)   (HW_GPIO_PDOR_WR(x, HW_GPIO_PDOR_RD(x) ^  (v)))
 141 /*@}*/
 142
 143 /*
 144  * Constants & macros for individual GPIO_PDOR bitfields
 145  */
 146
 147 /*!
 148  * @name Register GPIO_PDOR, field PDO[31:0] (RW)
 149  *
 150  * Register bits for unbonded pins return a undefined value when read.
 151  *
 152  * Values:
 153  * - 0 - Logic level 0 is driven on pin, provided pin is configured for
 154  *     general-purpose output.
 155  * - 1 - Logic level 1 is driven on pin, provided pin is configured for
 156  *     general-purpose output.
 157  */
 158 /*@{*/
 159 #define BP_GPIO_PDOR_PDO     (0U)          /*!< Bit position for GPIO_PDOR_PDO. */
 160 #define BM_GPIO_PDOR_PDO     (0xFFFFFFFFU) /*!< Bit mask for GPIO_PDOR_PDO. */
 161 #define BS_GPIO_PDOR_PDO     (32U)         /*!< Bit field size in bits for GPIO_PDOR_PDO. */
 162
 163 /*! @brief Read current value of the GPIO_PDOR_PDO field. */
 164 #define BR_GPIO_PDOR_PDO(x)  (HW_GPIO_PDOR(x).U)
 165
 166 /*! @brief Format value for bitfield GPIO_PDOR_PDO. */
 167 #define BF_GPIO_PDOR_PDO(v)  ((uint32_t)((uint32_t)(v) << BP_GPIO_PDOR_PDO) & BM_GPIO_PDOR_PDO)
 168
 169 /*! @brief Set the PDO field to a new value. */
 170 #define BW_GPIO_PDOR_PDO(x, v) (HW_GPIO_PDOR_WR(x, v))
 171 /*@}*/
 172
 173 /*******************************************************************************
 174  * HW_GPIO_PSOR - Port Set Output Register
 175  ******************************************************************************/
 176
 177 /*!
 178  * @brief HW_GPIO_PSOR - Port Set Output Register (WORZ)
 179  *
 180  * Reset value: 0x00000000U
 181  *
 182  * This register configures whether to set the fields of the PDOR.
 183  */
 184 typedef union _hw_gpio_psor
 185 {
 186     uint32_t U;
 187     struct _hw_gpio_psor_bitfields
 188     {
 189         uint32_t PTSO : 32;            /*!< [31:0] Port Set Output */
 190     } B;
 191 } hw_gpio_psor_t;
 192
 193 /*!
 194  * @name Constants and macros for entire GPIO_PSOR register
 195  */
 196 /*@{*/
 197 #define HW_GPIO_PSOR_ADDR(x)     ((x) + 0x4U)
 198
 199 #define HW_GPIO_PSOR(x)          (*(__O hw_gpio_psor_t *) HW_GPIO_PSOR_ADDR(x))
 200 #define HW_GPIO_PSOR_RD(x)       (HW_GPIO_PSOR(x).U)
 201 #define HW_GPIO_PSOR_WR(x, v)    (HW_GPIO_PSOR(x).U = (v))
 202 /*@}*/
 203
 204 /*
 205  * Constants & macros for individual GPIO_PSOR bitfields
 206  */
 207
 208 /*!
 209  * @name Register GPIO_PSOR, field PTSO[31:0] (WORZ)
 210  *
 211  * Writing to this register will update the contents of the corresponding bit in
 212  * the PDOR as follows:
 213  *
 214  * Values:
 215  * - 0 - Corresponding bit in PDORn does not change.
 216  * - 1 - Corresponding bit in PDORn is set to logic 1.
 217  */
 218 /*@{*/
 219 #define BP_GPIO_PSOR_PTSO    (0U)          /*!< Bit position for GPIO_PSOR_PTSO. */
 220 #define BM_GPIO_PSOR_PTSO    (0xFFFFFFFFU) /*!< Bit mask for GPIO_PSOR_PTSO. */
 221 #define BS_GPIO_PSOR_PTSO    (32U)         /*!< Bit field size in bits for GPIO_PSOR_PTSO. */
 222
 223 /*! @brief Format value for bitfield GPIO_PSOR_PTSO. */
 224 #define BF_GPIO_PSOR_PTSO(v) ((uint32_t)((uint32_t)(v) << BP_GPIO_PSOR_PTSO) & BM_GPIO_PSOR_PTSO)
 225
 226 /*! @brief Set the PTSO field to a new value. */
 227 #define BW_GPIO_PSOR_PTSO(x, v) (HW_GPIO_PSOR_WR(x, v))
 228 /*@}*/
 229
 230 /*******************************************************************************
 231  * HW_GPIO_PCOR - Port Clear Output Register
 232  ******************************************************************************/
 233
 234 /*!
 235  * @brief HW_GPIO_PCOR - Port Clear Output Register (WORZ)
 236  *
 237  * Reset value: 0x00000000U
 238  *
 239  * This register configures whether to clear the fields of PDOR.
 240  */
 241 typedef union _hw_gpio_pcor
 242 {
 243     uint32_t U;
 244     struct _hw_gpio_pcor_bitfields
 245     {
 246         uint32_t PTCO : 32;            /*!< [31:0] Port Clear Output */
 247     } B;
 248 } hw_gpio_pcor_t;
 249
 250 /*!
 251  * @name Constants and macros for entire GPIO_PCOR register
 252  */
 253 /*@{*/
 254 #define HW_GPIO_PCOR_ADDR(x)     ((x) + 0x8U)
 255
 256 #define HW_GPIO_PCOR(x)          (*(__O hw_gpio_pcor_t *) HW_GPIO_PCOR_ADDR(x))
 257 #define HW_GPIO_PCOR_RD(x)       (HW_GPIO_PCOR(x).U)
 258 #define HW_GPIO_PCOR_WR(x, v)    (HW_GPIO_PCOR(x).U = (v))
 259 /*@}*/
 260
 261 /*
 262  * Constants & macros for individual GPIO_PCOR bitfields
 263  */
 264
 265 /*!
 266  * @name Register GPIO_PCOR, field PTCO[31:0] (WORZ)
 267  *
 268  * Writing to this register will update the contents of the corresponding bit in
 269  * the Port Data Output Register (PDOR) as follows:
 270  *
 271  * Values:
 272  * - 0 - Corresponding bit in PDORn does not change.
 273  * - 1 - Corresponding bit in PDORn is cleared to logic 0.
 274  */
 275 /*@{*/
 276 #define BP_GPIO_PCOR_PTCO    (0U)          /*!< Bit position for GPIO_PCOR_PTCO. */
 277 #define BM_GPIO_PCOR_PTCO    (0xFFFFFFFFU) /*!< Bit mask for GPIO_PCOR_PTCO. */
 278 #define BS_GPIO_PCOR_PTCO    (32U)         /*!< Bit field size in bits for GPIO_PCOR_PTCO. */
 279
 280 /*! @brief Format value for bitfield GPIO_PCOR_PTCO. */
 281 #define BF_GPIO_PCOR_PTCO(v) ((uint32_t)((uint32_t)(v) << BP_GPIO_PCOR_PTCO) & BM_GPIO_PCOR_PTCO)
 282
 283 /*! @brief Set the PTCO field to a new value. */
 284 #define BW_GPIO_PCOR_PTCO(x, v) (HW_GPIO_PCOR_WR(x, v))
 285 /*@}*/
 286
 287 /*******************************************************************************
 288  * HW_GPIO_PTOR - Port Toggle Output Register
 289  ******************************************************************************/
 290
 291 /*!
 292  * @brief HW_GPIO_PTOR - Port Toggle Output Register (WORZ)
 293  *
 294  * Reset value: 0x00000000U
 295  */
 296 typedef union _hw_gpio_ptor
 297 {
 298     uint32_t U;
 299     struct _hw_gpio_ptor_bitfields
 300     {
 301         uint32_t PTTO : 32;            /*!< [31:0] Port Toggle Output */
 302     } B;
 303 } hw_gpio_ptor_t;
 304
 305 /*!
 306  * @name Constants and macros for entire GPIO_PTOR register
 307  */
 308 /*@{*/
 309 #define HW_GPIO_PTOR_ADDR(x)     ((x) + 0xCU)
 310
 311 #define HW_GPIO_PTOR(x)          (*(__O hw_gpio_ptor_t *) HW_GPIO_PTOR_ADDR(x))
 312 #define HW_GPIO_PTOR_RD(x)       (HW_GPIO_PTOR(x).U)
 313 #define HW_GPIO_PTOR_WR(x, v)    (HW_GPIO_PTOR(x).U = (v))
 314 /*@}*/
 315
 316 /*
 317  * Constants & macros for individual GPIO_PTOR bitfields
 318  */
 319
 320 /*!
 321  * @name Register GPIO_PTOR, field PTTO[31:0] (WORZ)
 322  *
 323  * Writing to this register will update the contents of the corresponding bit in
 324  * the PDOR as follows:
 325  *
 326  * Values:
 327  * - 0 - Corresponding bit in PDORn does not change.
 328  * - 1 - Corresponding bit in PDORn is set to the inverse of its existing logic
 329  *     state.
 330  */
 331 /*@{*/
 332 #define BP_GPIO_PTOR_PTTO    (0U)          /*!< Bit position for GPIO_PTOR_PTTO. */
 333 #define BM_GPIO_PTOR_PTTO    (0xFFFFFFFFU) /*!< Bit mask for GPIO_PTOR_PTTO. */
 334 #define BS_GPIO_PTOR_PTTO    (32U)         /*!< Bit field size in bits for GPIO_PTOR_PTTO. */
 335
 336 /*! @brief Format value for bitfield GPIO_PTOR_PTTO. */
 337 #define BF_GPIO_PTOR_PTTO(v) ((uint32_t)((uint32_t)(v) << BP_GPIO_PTOR_PTTO) & BM_GPIO_PTOR_PTTO)
 338
 339 /*! @brief Set the PTTO field to a new value. */
 340 #define BW_GPIO_PTOR_PTTO(x, v) (HW_GPIO_PTOR_WR(x, v))
 341 /*@}*/
 342
 343 /*******************************************************************************
 344  * HW_GPIO_PDIR - Port Data Input Register
 345  ******************************************************************************/
 346
 347 /*!
 348  * @brief HW_GPIO_PDIR - Port Data Input Register (RO)
 349  *
 350  * Reset value: 0x00000000U
 351  *
 352  * Do not modify pin configuration registers associated with pins not available
 353  * in your selected package. All unbonded pins not available in your package will
 354  * default to DISABLE state for lowest power consumption.
 355  */
 356 typedef union _hw_gpio_pdir
 357 {
 358     uint32_t U;
 359     struct _hw_gpio_pdir_bitfields
 360     {
 361         uint32_t PDI : 32;             /*!< [31:0] Port Data Input */
 362     } B;
 363 } hw_gpio_pdir_t;
 364
 365 /*!
 366  * @name Constants and macros for entire GPIO_PDIR register
 367  */
 368 /*@{*/
 369 #define HW_GPIO_PDIR_ADDR(x)     ((x) + 0x10U)
 370
 371 #define HW_GPIO_PDIR(x)          (*(__I hw_gpio_pdir_t *) HW_GPIO_PDIR_ADDR(x))
 372 #define HW_GPIO_PDIR_RD(x)       (HW_GPIO_PDIR(x).U)
 373 /*@}*/
 374
 375 /*
 376  * Constants & macros for individual GPIO_PDIR bitfields
 377  */
 378
 379 /*!
 380  * @name Register GPIO_PDIR, field PDI[31:0] (RO)
 381  *
 382  * Reads 0 at the unimplemented pins for a particular device. Pins that are not
 383  * configured for a digital function read 0. If the Port Control and Interrupt
 384  * module is disabled, then the corresponding bit in PDIR does not update.
 385  *
 386  * Values:
 387  * - 0 - Pin logic level is logic 0, or is not configured for use by digital
 388  *     function.
 389  * - 1 - Pin logic level is logic 1.
 390  */
 391 /*@{*/
 392 #define BP_GPIO_PDIR_PDI     (0U)          /*!< Bit position for GPIO_PDIR_PDI. */
 393 #define BM_GPIO_PDIR_PDI     (0xFFFFFFFFU) /*!< Bit mask for GPIO_PDIR_PDI. */
 394 #define BS_GPIO_PDIR_PDI     (32U)         /*!< Bit field size in bits for GPIO_PDIR_PDI. */
 395
 396 /*! @brief Read current value of the GPIO_PDIR_PDI field. */
 397 #define BR_GPIO_PDIR_PDI(x)  (HW_GPIO_PDIR(x).U)
 398 /*@}*/
 399
 400 /*******************************************************************************
 401  * HW_GPIO_PDDR - Port Data Direction Register
 402  ******************************************************************************/
 403
 404 /*!
 405  * @brief HW_GPIO_PDDR - Port Data Direction Register (RW)
 406  *
 407  * Reset value: 0x00000000U
 408  *
 409  * The PDDR configures the individual port pins for input or output.
 410  */
 411 typedef union _hw_gpio_pddr
 412 {
 413     uint32_t U;
 414     struct _hw_gpio_pddr_bitfields
 415     {
 416         uint32_t PDD : 32;             /*!< [31:0] Port Data Direction */
 417     } B;
 418 } hw_gpio_pddr_t;
 419
 420 /*!
 421  * @name Constants and macros for entire GPIO_PDDR register
 422  */
 423 /*@{*/
 424 #define HW_GPIO_PDDR_ADDR(x)     ((x) + 0x14U)
 425
 426 #define HW_GPIO_PDDR(x)          (*(__IO hw_gpio_pddr_t *) HW_GPIO_PDDR_ADDR(x))
 427 #define HW_GPIO_PDDR_RD(x)       (HW_GPIO_PDDR(x).U)
 428 #define HW_GPIO_PDDR_WR(x, v)    (HW_GPIO_PDDR(x).U = (v))
 429 #define HW_GPIO_PDDR_SET(x, v)   (HW_GPIO_PDDR_WR(x, HW_GPIO_PDDR_RD(x) |  (v)))
 430 #define HW_GPIO_PDDR_CLR(x, v)   (HW_GPIO_PDDR_WR(x, HW_GPIO_PDDR_RD(x) & ~(v)))
 431 #define HW_GPIO_PDDR_TOG(x, v)   (HW_GPIO_PDDR_WR(x, HW_GPIO_PDDR_RD(x) ^  (v)))
 432 /*@}*/
 433
 434 /*
 435  * Constants & macros for individual GPIO_PDDR bitfields
 436  */
 437
 438 /*!
 439  * @name Register GPIO_PDDR, field PDD[31:0] (RW)
 440  *
 441  * Configures individual port pins for input or output.
 442  *
 443  * Values:
 444  * - 0 - Pin is configured as general-purpose input, for the GPIO function.
 445  * - 1 - Pin is configured as general-purpose output, for the GPIO function.
 446  */
 447 /*@{*/
 448 #define BP_GPIO_PDDR_PDD     (0U)          /*!< Bit position for GPIO_PDDR_PDD. */
 449 #define BM_GPIO_PDDR_PDD     (0xFFFFFFFFU) /*!< Bit mask for GPIO_PDDR_PDD. */
 450 #define BS_GPIO_PDDR_PDD     (32U)         /*!< Bit field size in bits for GPIO_PDDR_PDD. */
 451
 452 /*! @brief Read current value of the GPIO_PDDR_PDD field. */
 453 #define BR_GPIO_PDDR_PDD(x)  (HW_GPIO_PDDR(x).U)
 454
 455 /*! @brief Format value for bitfield GPIO_PDDR_PDD. */
 456 #define BF_GPIO_PDDR_PDD(v)  ((uint32_t)((uint32_t)(v) << BP_GPIO_PDDR_PDD) & BM_GPIO_PDDR_PDD)
 457
 458 /*! @brief Set the PDD field to a new value. */
 459 #define BW_GPIO_PDDR_PDD(x, v) (HW_GPIO_PDDR_WR(x, v))
 460 /*@}*/
 461
 462 /*******************************************************************************
 463  * hw_gpio_t - module struct
 464  ******************************************************************************/
 465 /*!
 466  * @brief All GPIO module registers.
 467  */
 468 #pragma pack(1)
 469 typedef struct _hw_gpio
 470 {
 471     __IO hw_gpio_pdor_t PDOR;              /*!< [0x0] Port Data Output Register */
 472     __O hw_gpio_psor_t PSOR;               /*!< [0x4] Port Set Output Register */
 473     __O hw_gpio_pcor_t PCOR;               /*!< [0x8] Port Clear Output Register */
 474     __O hw_gpio_ptor_t PTOR;               /*!< [0xC] Port Toggle Output Register */
 475     __I hw_gpio_pdir_t PDIR;               /*!< [0x10] Port Data Input Register */
 476     __IO hw_gpio_pddr_t PDDR;              /*!< [0x14] Port Data Direction Register */
 477 } hw_gpio_t;
 478 #pragma pack()
 479
 480 /*! @brief Macro to access all GPIO registers. */
 481 /*! @param x GPIO module instance base address. */
 482 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
 483  *     use the '&' operator, like <code>&HW_GPIO(GPIOA_BASE)</code>. */
 484 #define HW_GPIO(x)     (*(hw_gpio_t *)(x))
 485
 486 #endif /* __HW_GPIO_REGISTERS_H__ */
 487 /* EOF */