tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_i2s.h

   1 /*
   2 ** ###################################################################
   3 **     Compilers:           Keil ARM C/C++ Compiler
   4 **                          Freescale C/C++ for Embedded ARM
   5 **                          GNU C Compiler
   6 **                          IAR ANSI C/C++ Compiler for ARM
   7 **
   8 **     Reference manual:    K22P121M120SF7RM, Rev. 1, March 24, 2014
   9 **     Version:             rev. 2.5, 2014-05-06
  10 **     Build:               b140604
  11 **
  12 **     Abstract:
  13 **         Extension to the CMSIS register access layer header.
  14 **
  15 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
  16 **     All rights reserved.
  17 **
  18 **     Redistribution and use in source and binary forms, with or without modification,
  19 **     are permitted provided that the following conditions are met:
  20 **
  21 **     o Redistributions of source code must retain the above copyright notice, this list
  22 **       of conditions and the following disclaimer.
  23 **
  24 **     o Redistributions in binary form must reproduce the above copyright notice, this
  25 **       list of conditions and the following disclaimer in the documentation and/or
  26 **       other materials provided with the distribution.
  27 **
  28 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  29 **       contributors may be used to endorse or promote products derived from this
  30 **       software without specific prior written permission.
  31 **
  32 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  33 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  34 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  35 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  36 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  37 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  38 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  39 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  41 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42 **
  43 **     http:                 www.freescale.com
  44 **     mail:                 support@freescale.com
  45 **
  46 **     Revisions:
  47 **     - rev. 1.0 (2013-07-23)
  48 **         Initial version.
  49 **     - rev. 1.1 (2013-09-17)
  50 **         RM rev. 0.4 update.
  51 **     - rev. 2.0 (2013-10-29)
  52 **         Register accessor macros added to the memory map.
  53 **         Symbols for Processor Expert memory map compatibility added to the memory map.
  54 **         Startup file for gcc has been updated according to CMSIS 3.2.
  55 **         System initialization updated.
  56 **     - rev. 2.1 (2013-10-30)
  57 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
  58 **     - rev. 2.2 (2013-12-20)
  59 **         Update according to reference manual rev. 0.6,
  60 **     - rev. 2.3 (2014-01-13)
  61 **         Update according to reference manual rev. 0.61,
  62 **     - rev. 2.4 (2014-02-10)
  63 **         The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
  64 **     - rev. 2.5 (2014-05-06)
  65 **         Update according to reference manual rev. 1.0,
  66 **         Update of system and startup files.
  67 **         Module access macro module_BASES replaced by module_BASE_PTRS.
  68 **
  69 ** ###################################################################
  70 */
  71
  72 /*
  73  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
  74  *
  75  * This file was generated automatically and any changes may be lost.
  76  */
  77 #ifndef __HW_I2S_REGISTERS_H__
  78 #define __HW_I2S_REGISTERS_H__
  79
  80 #include "MK22F51212.h"
  81 #include "fsl_bitaccess.h"
  82
  83 /*
  84  * MK22F51212 I2S
  85  *
  86  * Inter-IC Sound / Synchronous Audio Interface
  87  *
  88  * Registers defined in this header file:
  89  * - HW_I2S_TCSR - SAI Transmit Control Register
  90  * - HW_I2S_TCR1 - SAI Transmit Configuration 1 Register
  91  * - HW_I2S_TCR2 - SAI Transmit Configuration 2 Register
  92  * - HW_I2S_TCR3 - SAI Transmit Configuration 3 Register
  93  * - HW_I2S_TCR4 - SAI Transmit Configuration 4 Register
  94  * - HW_I2S_TCR5 - SAI Transmit Configuration 5 Register
  95  * - HW_I2S_TDRn - SAI Transmit Data Register
  96  * - HW_I2S_TFRn - SAI Transmit FIFO Register
  97  * - HW_I2S_TMR - SAI Transmit Mask Register
  98  * - HW_I2S_RCSR - SAI Receive Control Register
  99  * - HW_I2S_RCR1 - SAI Receive Configuration 1 Register
 100  * - HW_I2S_RCR2 - SAI Receive Configuration 2 Register
 101  * - HW_I2S_RCR3 - SAI Receive Configuration 3 Register
 102  * - HW_I2S_RCR4 - SAI Receive Configuration 4 Register
 103  * - HW_I2S_RCR5 - SAI Receive Configuration 5 Register
 104  * - HW_I2S_RDRn - SAI Receive Data Register
 105  * - HW_I2S_RFRn - SAI Receive FIFO Register
 106  * - HW_I2S_RMR - SAI Receive Mask Register
 107  * - HW_I2S_MCR - SAI MCLK Control Register
 108  * - HW_I2S_MDR - SAI MCLK Divide Register
 109  *
 110  * - hw_i2s_t - Struct containing all module registers.
 111  */
 112
 113 #define HW_I2S_INSTANCE_COUNT (1U) /*!< Number of instances of the I2S module. */
 114
 115 /*******************************************************************************
 116  * HW_I2S_TCSR - SAI Transmit Control Register
 117  ******************************************************************************/
 118
 119 /*!
 120  * @brief HW_I2S_TCSR - SAI Transmit Control Register (RW)
 121  *
 122  * Reset value: 0x00000000U
 123  */
 124 typedef union _hw_i2s_tcsr
 125 {
 126     uint32_t U;
 127     struct _hw_i2s_tcsr_bitfields
 128     {
 129         uint32_t FRDE : 1;             /*!< [0] FIFO Request DMA Enable */
 130         uint32_t FWDE : 1;             /*!< [1] FIFO Warning DMA Enable */
 131         uint32_t RESERVED0 : 6;        /*!< [7:2]  */
 132         uint32_t FRIE : 1;             /*!< [8] FIFO Request Interrupt Enable */
 133         uint32_t FWIE : 1;             /*!< [9] FIFO Warning Interrupt Enable */
 134         uint32_t FEIE : 1;             /*!< [10] FIFO Error Interrupt Enable */
 135         uint32_t SEIE : 1;             /*!< [11] Sync Error Interrupt Enable */
 136         uint32_t WSIE : 1;             /*!< [12] Word Start Interrupt Enable */
 137         uint32_t RESERVED1 : 3;        /*!< [15:13]  */
 138         uint32_t FRF : 1;              /*!< [16] FIFO Request Flag */
 139         uint32_t FWF : 1;              /*!< [17] FIFO Warning Flag */
 140         uint32_t FEF : 1;              /*!< [18] FIFO Error Flag */
 141         uint32_t SEF : 1;              /*!< [19] Sync Error Flag */
 142         uint32_t WSF : 1;              /*!< [20] Word Start Flag */
 143         uint32_t RESERVED2 : 3;        /*!< [23:21]  */
 144         uint32_t SR : 1;               /*!< [24] Software Reset */
 145         uint32_t FR : 1;               /*!< [25] FIFO Reset */
 146         uint32_t RESERVED3 : 2;        /*!< [27:26]  */
 147         uint32_t BCE : 1;              /*!< [28] Bit Clock Enable */
 148         uint32_t DBGE : 1;             /*!< [29] Debug Enable */
 149         uint32_t STOPE : 1;            /*!< [30] Stop Enable */
 150         uint32_t TE : 1;               /*!< [31] Transmitter Enable */
 151     } B;
 152 } hw_i2s_tcsr_t;
 153
 154 /*!
 155  * @name Constants and macros for entire I2S_TCSR register
 156  */
 157 /*@{*/
 158 #define HW_I2S_TCSR_ADDR(x)      ((x) + 0x0U)
 159
 160 #define HW_I2S_TCSR(x)           (*(__IO hw_i2s_tcsr_t *) HW_I2S_TCSR_ADDR(x))
 161 #define HW_I2S_TCSR_RD(x)        (HW_I2S_TCSR(x).U)
 162 #define HW_I2S_TCSR_WR(x, v)     (HW_I2S_TCSR(x).U = (v))
 163 #define HW_I2S_TCSR_SET(x, v)    (HW_I2S_TCSR_WR(x, HW_I2S_TCSR_RD(x) |  (v)))
 164 #define HW_I2S_TCSR_CLR(x, v)    (HW_I2S_TCSR_WR(x, HW_I2S_TCSR_RD(x) & ~(v)))
 165 #define HW_I2S_TCSR_TOG(x, v)    (HW_I2S_TCSR_WR(x, HW_I2S_TCSR_RD(x) ^  (v)))
 166 /*@}*/
 167
 168 /*
 169  * Constants & macros for individual I2S_TCSR bitfields
 170  */
 171
 172 /*!
 173  * @name Register I2S_TCSR, field FRDE[0] (RW)
 174  *
 175  * Enables/disables DMA requests.
 176  *
 177  * Values:
 178  * - 0 - Disables the DMA request.
 179  * - 1 - Enables the DMA request.
 180  */
 181 /*@{*/
 182 #define BP_I2S_TCSR_FRDE     (0U)          /*!< Bit position for I2S_TCSR_FRDE. */
 183 #define BM_I2S_TCSR_FRDE     (0x00000001U) /*!< Bit mask for I2S_TCSR_FRDE. */
 184 #define BS_I2S_TCSR_FRDE     (1U)          /*!< Bit field size in bits for I2S_TCSR_FRDE. */
 185
 186 /*! @brief Read current value of the I2S_TCSR_FRDE field. */
 187 #define BR_I2S_TCSR_FRDE(x)  (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRDE))
 188
 189 /*! @brief Format value for bitfield I2S_TCSR_FRDE. */
 190 #define BF_I2S_TCSR_FRDE(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FRDE) & BM_I2S_TCSR_FRDE)
 191
 192 /*! @brief Set the FRDE field to a new value. */
 193 #define BW_I2S_TCSR_FRDE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRDE) = (v))
 194 /*@}*/
 195
 196 /*!
 197  * @name Register I2S_TCSR, field FWDE[1] (RW)
 198  *
 199  * Enables/disables DMA requests.
 200  *
 201  * Values:
 202  * - 0 - Disables the DMA request.
 203  * - 1 - Enables the DMA request.
 204  */
 205 /*@{*/
 206 #define BP_I2S_TCSR_FWDE     (1U)          /*!< Bit position for I2S_TCSR_FWDE. */
 207 #define BM_I2S_TCSR_FWDE     (0x00000002U) /*!< Bit mask for I2S_TCSR_FWDE. */
 208 #define BS_I2S_TCSR_FWDE     (1U)          /*!< Bit field size in bits for I2S_TCSR_FWDE. */
 209
 210 /*! @brief Read current value of the I2S_TCSR_FWDE field. */
 211 #define BR_I2S_TCSR_FWDE(x)  (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWDE))
 212
 213 /*! @brief Format value for bitfield I2S_TCSR_FWDE. */
 214 #define BF_I2S_TCSR_FWDE(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FWDE) & BM_I2S_TCSR_FWDE)
 215
 216 /*! @brief Set the FWDE field to a new value. */
 217 #define BW_I2S_TCSR_FWDE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWDE) = (v))
 218 /*@}*/
 219
 220 /*!
 221  * @name Register I2S_TCSR, field FRIE[8] (RW)
 222  *
 223  * Enables/disables FIFO request interrupts.
 224  *
 225  * Values:
 226  * - 0 - Disables the interrupt.
 227  * - 1 - Enables the interrupt.
 228  */
 229 /*@{*/
 230 #define BP_I2S_TCSR_FRIE     (8U)          /*!< Bit position for I2S_TCSR_FRIE. */
 231 #define BM_I2S_TCSR_FRIE     (0x00000100U) /*!< Bit mask for I2S_TCSR_FRIE. */
 232 #define BS_I2S_TCSR_FRIE     (1U)          /*!< Bit field size in bits for I2S_TCSR_FRIE. */
 233
 234 /*! @brief Read current value of the I2S_TCSR_FRIE field. */
 235 #define BR_I2S_TCSR_FRIE(x)  (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRIE))
 236
 237 /*! @brief Format value for bitfield I2S_TCSR_FRIE. */
 238 #define BF_I2S_TCSR_FRIE(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FRIE) & BM_I2S_TCSR_FRIE)
 239
 240 /*! @brief Set the FRIE field to a new value. */
 241 #define BW_I2S_TCSR_FRIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRIE) = (v))
 242 /*@}*/
 243
 244 /*!
 245  * @name Register I2S_TCSR, field FWIE[9] (RW)
 246  *
 247  * Enables/disables FIFO warning interrupts.
 248  *
 249  * Values:
 250  * - 0 - Disables the interrupt.
 251  * - 1 - Enables the interrupt.
 252  */
 253 /*@{*/
 254 #define BP_I2S_TCSR_FWIE     (9U)          /*!< Bit position for I2S_TCSR_FWIE. */
 255 #define BM_I2S_TCSR_FWIE     (0x00000200U) /*!< Bit mask for I2S_TCSR_FWIE. */
 256 #define BS_I2S_TCSR_FWIE     (1U)          /*!< Bit field size in bits for I2S_TCSR_FWIE. */
 257
 258 /*! @brief Read current value of the I2S_TCSR_FWIE field. */
 259 #define BR_I2S_TCSR_FWIE(x)  (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWIE))
 260
 261 /*! @brief Format value for bitfield I2S_TCSR_FWIE. */
 262 #define BF_I2S_TCSR_FWIE(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FWIE) & BM_I2S_TCSR_FWIE)
 263
 264 /*! @brief Set the FWIE field to a new value. */
 265 #define BW_I2S_TCSR_FWIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWIE) = (v))
 266 /*@}*/
 267
 268 /*!
 269  * @name Register I2S_TCSR, field FEIE[10] (RW)
 270  *
 271  * Enables/disables FIFO error interrupts.
 272  *
 273  * Values:
 274  * - 0 - Disables the interrupt.
 275  * - 1 - Enables the interrupt.
 276  */
 277 /*@{*/
 278 #define BP_I2S_TCSR_FEIE     (10U)         /*!< Bit position for I2S_TCSR_FEIE. */
 279 #define BM_I2S_TCSR_FEIE     (0x00000400U) /*!< Bit mask for I2S_TCSR_FEIE. */
 280 #define BS_I2S_TCSR_FEIE     (1U)          /*!< Bit field size in bits for I2S_TCSR_FEIE. */
 281
 282 /*! @brief Read current value of the I2S_TCSR_FEIE field. */
 283 #define BR_I2S_TCSR_FEIE(x)  (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FEIE))
 284
 285 /*! @brief Format value for bitfield I2S_TCSR_FEIE. */
 286 #define BF_I2S_TCSR_FEIE(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FEIE) & BM_I2S_TCSR_FEIE)
 287
 288 /*! @brief Set the FEIE field to a new value. */
 289 #define BW_I2S_TCSR_FEIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FEIE) = (v))
 290 /*@}*/
 291
 292 /*!
 293  * @name Register I2S_TCSR, field SEIE[11] (RW)
 294  *
 295  * Enables/disables sync error interrupts.
 296  *
 297  * Values:
 298  * - 0 - Disables interrupt.
 299  * - 1 - Enables interrupt.
 300  */
 301 /*@{*/
 302 #define BP_I2S_TCSR_SEIE     (11U)         /*!< Bit position for I2S_TCSR_SEIE. */
 303 #define BM_I2S_TCSR_SEIE     (0x00000800U) /*!< Bit mask for I2S_TCSR_SEIE. */
 304 #define BS_I2S_TCSR_SEIE     (1U)          /*!< Bit field size in bits for I2S_TCSR_SEIE. */
 305
 306 /*! @brief Read current value of the I2S_TCSR_SEIE field. */
 307 #define BR_I2S_TCSR_SEIE(x)  (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SEIE))
 308
 309 /*! @brief Format value for bitfield I2S_TCSR_SEIE. */
 310 #define BF_I2S_TCSR_SEIE(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_SEIE) & BM_I2S_TCSR_SEIE)
 311
 312 /*! @brief Set the SEIE field to a new value. */
 313 #define BW_I2S_TCSR_SEIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SEIE) = (v))
 314 /*@}*/
 315
 316 /*!
 317  * @name Register I2S_TCSR, field WSIE[12] (RW)
 318  *
 319  * Enables/disables word start interrupts.
 320  *
 321  * Values:
 322  * - 0 - Disables interrupt.
 323  * - 1 - Enables interrupt.
 324  */
 325 /*@{*/
 326 #define BP_I2S_TCSR_WSIE     (12U)         /*!< Bit position for I2S_TCSR_WSIE. */
 327 #define BM_I2S_TCSR_WSIE     (0x00001000U) /*!< Bit mask for I2S_TCSR_WSIE. */
 328 #define BS_I2S_TCSR_WSIE     (1U)          /*!< Bit field size in bits for I2S_TCSR_WSIE. */
 329
 330 /*! @brief Read current value of the I2S_TCSR_WSIE field. */
 331 #define BR_I2S_TCSR_WSIE(x)  (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_WSIE))
 332
 333 /*! @brief Format value for bitfield I2S_TCSR_WSIE. */
 334 #define BF_I2S_TCSR_WSIE(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_WSIE) & BM_I2S_TCSR_WSIE)
 335
 336 /*! @brief Set the WSIE field to a new value. */
 337 #define BW_I2S_TCSR_WSIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_WSIE) = (v))
 338 /*@}*/
 339
 340 /*!
 341  * @name Register I2S_TCSR, field FRF[16] (RO)
 342  *
 343  * Indicates that the number of words in an enabled transmit channel FIFO is
 344  * less than or equal to the transmit FIFO watermark.
 345  *
 346  * Values:
 347  * - 0 - Transmit FIFO watermark has not been reached.
 348  * - 1 - Transmit FIFO watermark has been reached.
 349  */
 350 /*@{*/
 351 #define BP_I2S_TCSR_FRF      (16U)         /*!< Bit position for I2S_TCSR_FRF. */
 352 #define BM_I2S_TCSR_FRF      (0x00010000U) /*!< Bit mask for I2S_TCSR_FRF. */
 353 #define BS_I2S_TCSR_FRF      (1U)          /*!< Bit field size in bits for I2S_TCSR_FRF. */
 354
 355 /*! @brief Read current value of the I2S_TCSR_FRF field. */
 356 #define BR_I2S_TCSR_FRF(x)   (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRF))
 357 /*@}*/
 358
 359 /*!
 360  * @name Register I2S_TCSR, field FWF[17] (RO)
 361  *
 362  * Indicates that an enabled transmit FIFO is empty.
 363  *
 364  * Values:
 365  * - 0 - No enabled transmit FIFO is empty.
 366  * - 1 - Enabled transmit FIFO is empty.
 367  */
 368 /*@{*/
 369 #define BP_I2S_TCSR_FWF      (17U)         /*!< Bit position for I2S_TCSR_FWF. */
 370 #define BM_I2S_TCSR_FWF      (0x00020000U) /*!< Bit mask for I2S_TCSR_FWF. */
 371 #define BS_I2S_TCSR_FWF      (1U)          /*!< Bit field size in bits for I2S_TCSR_FWF. */
 372
 373 /*! @brief Read current value of the I2S_TCSR_FWF field. */
 374 #define BR_I2S_TCSR_FWF(x)   (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWF))
 375 /*@}*/
 376
 377 /*!
 378  * @name Register I2S_TCSR, field FEF[18] (W1C)
 379  *
 380  * Indicates that an enabled transmit FIFO has underrun. Write a logic 1 to this
 381  * field to clear this flag.
 382  *
 383  * Values:
 384  * - 0 - Transmit underrun not detected.
 385  * - 1 - Transmit underrun detected.
 386  */
 387 /*@{*/
 388 #define BP_I2S_TCSR_FEF      (18U)         /*!< Bit position for I2S_TCSR_FEF. */
 389 #define BM_I2S_TCSR_FEF      (0x00040000U) /*!< Bit mask for I2S_TCSR_FEF. */
 390 #define BS_I2S_TCSR_FEF      (1U)          /*!< Bit field size in bits for I2S_TCSR_FEF. */
 391
 392 /*! @brief Read current value of the I2S_TCSR_FEF field. */
 393 #define BR_I2S_TCSR_FEF(x)   (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FEF))
 394
 395 /*! @brief Format value for bitfield I2S_TCSR_FEF. */
 396 #define BF_I2S_TCSR_FEF(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FEF) & BM_I2S_TCSR_FEF)
 397
 398 /*! @brief Set the FEF field to a new value. */
 399 #define BW_I2S_TCSR_FEF(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FEF) = (v))
 400 /*@}*/
 401
 402 /*!
 403  * @name Register I2S_TCSR, field SEF[19] (W1C)
 404  *
 405  * Indicates that an error in the externally-generated frame sync has been
 406  * detected. Write a logic 1 to this field to clear this flag.
 407  *
 408  * Values:
 409  * - 0 - Sync error not detected.
 410  * - 1 - Frame sync error detected.
 411  */
 412 /*@{*/
 413 #define BP_I2S_TCSR_SEF      (19U)         /*!< Bit position for I2S_TCSR_SEF. */
 414 #define BM_I2S_TCSR_SEF      (0x00080000U) /*!< Bit mask for I2S_TCSR_SEF. */
 415 #define BS_I2S_TCSR_SEF      (1U)          /*!< Bit field size in bits for I2S_TCSR_SEF. */
 416
 417 /*! @brief Read current value of the I2S_TCSR_SEF field. */
 418 #define BR_I2S_TCSR_SEF(x)   (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SEF))
 419
 420 /*! @brief Format value for bitfield I2S_TCSR_SEF. */
 421 #define BF_I2S_TCSR_SEF(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_SEF) & BM_I2S_TCSR_SEF)
 422
 423 /*! @brief Set the SEF field to a new value. */
 424 #define BW_I2S_TCSR_SEF(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SEF) = (v))
 425 /*@}*/
 426
 427 /*!
 428  * @name Register I2S_TCSR, field WSF[20] (W1C)
 429  *
 430  * Indicates that the start of the configured word has been detected. Write a
 431  * logic 1 to this field to clear this flag.
 432  *
 433  * Values:
 434  * - 0 - Start of word not detected.
 435  * - 1 - Start of word detected.
 436  */
 437 /*@{*/
 438 #define BP_I2S_TCSR_WSF      (20U)         /*!< Bit position for I2S_TCSR_WSF. */
 439 #define BM_I2S_TCSR_WSF      (0x00100000U) /*!< Bit mask for I2S_TCSR_WSF. */
 440 #define BS_I2S_TCSR_WSF      (1U)          /*!< Bit field size in bits for I2S_TCSR_WSF. */
 441
 442 /*! @brief Read current value of the I2S_TCSR_WSF field. */
 443 #define BR_I2S_TCSR_WSF(x)   (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_WSF))
 444
 445 /*! @brief Format value for bitfield I2S_TCSR_WSF. */
 446 #define BF_I2S_TCSR_WSF(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_WSF) & BM_I2S_TCSR_WSF)
 447
 448 /*! @brief Set the WSF field to a new value. */
 449 #define BW_I2S_TCSR_WSF(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_WSF) = (v))
 450 /*@}*/
 451
 452 /*!
 453  * @name Register I2S_TCSR, field SR[24] (RW)
 454  *
 455  * When set, resets the internal transmitter logic including the FIFO pointers.
 456  * Software-visible registers are not affected, except for the status registers.
 457  *
 458  * Values:
 459  * - 0 - No effect.
 460  * - 1 - Software reset.
 461  */
 462 /*@{*/
 463 #define BP_I2S_TCSR_SR       (24U)         /*!< Bit position for I2S_TCSR_SR. */
 464 #define BM_I2S_TCSR_SR       (0x01000000U) /*!< Bit mask for I2S_TCSR_SR. */
 465 #define BS_I2S_TCSR_SR       (1U)          /*!< Bit field size in bits for I2S_TCSR_SR. */
 466
 467 /*! @brief Read current value of the I2S_TCSR_SR field. */
 468 #define BR_I2S_TCSR_SR(x)    (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SR))
 469
 470 /*! @brief Format value for bitfield I2S_TCSR_SR. */
 471 #define BF_I2S_TCSR_SR(v)    ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_SR) & BM_I2S_TCSR_SR)
 472
 473 /*! @brief Set the SR field to a new value. */
 474 #define BW_I2S_TCSR_SR(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SR) = (v))
 475 /*@}*/
 476
 477 /*!
 478  * @name Register I2S_TCSR, field FR[25] (WORZ)
 479  *
 480  * Resets the FIFO pointers. Reading this field will always return zero. FIFO
 481  * pointers should only be reset when the transmitter is disabled or the FIFO error
 482  * flag is set.
 483  *
 484  * Values:
 485  * - 0 - No effect.
 486  * - 1 - FIFO reset.
 487  */
 488 /*@{*/
 489 #define BP_I2S_TCSR_FR       (25U)         /*!< Bit position for I2S_TCSR_FR. */
 490 #define BM_I2S_TCSR_FR       (0x02000000U) /*!< Bit mask for I2S_TCSR_FR. */
 491 #define BS_I2S_TCSR_FR       (1U)          /*!< Bit field size in bits for I2S_TCSR_FR. */
 492
 493 /*! @brief Format value for bitfield I2S_TCSR_FR. */
 494 #define BF_I2S_TCSR_FR(v)    ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FR) & BM_I2S_TCSR_FR)
 495
 496 /*! @brief Set the FR field to a new value. */
 497 #define BW_I2S_TCSR_FR(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FR) = (v))
 498 /*@}*/
 499
 500 /*!
 501  * @name Register I2S_TCSR, field BCE[28] (RW)
 502  *
 503  * Enables the transmit bit clock, separately from the TE. This field is
 504  * automatically set whenever TE is set. When software clears this field, the transmit
 505  * bit clock remains enabled, and this bit remains set, until the end of the
 506  * current frame.
 507  *
 508  * Values:
 509  * - 0 - Transmit bit clock is disabled.
 510  * - 1 - Transmit bit clock is enabled.
 511  */
 512 /*@{*/
 513 #define BP_I2S_TCSR_BCE      (28U)         /*!< Bit position for I2S_TCSR_BCE. */
 514 #define BM_I2S_TCSR_BCE      (0x10000000U) /*!< Bit mask for I2S_TCSR_BCE. */
 515 #define BS_I2S_TCSR_BCE      (1U)          /*!< Bit field size in bits for I2S_TCSR_BCE. */
 516
 517 /*! @brief Read current value of the I2S_TCSR_BCE field. */
 518 #define BR_I2S_TCSR_BCE(x)   (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_BCE))
 519
 520 /*! @brief Format value for bitfield I2S_TCSR_BCE. */
 521 #define BF_I2S_TCSR_BCE(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_BCE) & BM_I2S_TCSR_BCE)
 522
 523 /*! @brief Set the BCE field to a new value. */
 524 #define BW_I2S_TCSR_BCE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_BCE) = (v))
 525 /*@}*/
 526
 527 /*!
 528  * @name Register I2S_TCSR, field DBGE[29] (RW)
 529  *
 530  * Enables/disables transmitter operation in Debug mode. The transmit bit clock
 531  * is not affected by debug mode.
 532  *
 533  * Values:
 534  * - 0 - Transmitter is disabled in Debug mode, after completing the current
 535  *     frame.
 536  * - 1 - Transmitter is enabled in Debug mode.
 537  */
 538 /*@{*/
 539 #define BP_I2S_TCSR_DBGE     (29U)         /*!< Bit position for I2S_TCSR_DBGE. */
 540 #define BM_I2S_TCSR_DBGE     (0x20000000U) /*!< Bit mask for I2S_TCSR_DBGE. */
 541 #define BS_I2S_TCSR_DBGE     (1U)          /*!< Bit field size in bits for I2S_TCSR_DBGE. */
 542
 543 /*! @brief Read current value of the I2S_TCSR_DBGE field. */
 544 #define BR_I2S_TCSR_DBGE(x)  (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_DBGE))
 545
 546 /*! @brief Format value for bitfield I2S_TCSR_DBGE. */
 547 #define BF_I2S_TCSR_DBGE(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_DBGE) & BM_I2S_TCSR_DBGE)
 548
 549 /*! @brief Set the DBGE field to a new value. */
 550 #define BW_I2S_TCSR_DBGE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_DBGE) = (v))
 551 /*@}*/
 552
 553 /*!
 554  * @name Register I2S_TCSR, field STOPE[30] (RW)
 555  *
 556  * Configures transmitter operation in Stop mode. This field is ignored and the
 557  * transmitter is disabled in all low-leakage stop modes.
 558  *
 559  * Values:
 560  * - 0 - Transmitter disabled in Stop mode.
 561  * - 1 - Transmitter enabled in Stop mode.
 562  */
 563 /*@{*/
 564 #define BP_I2S_TCSR_STOPE    (30U)         /*!< Bit position for I2S_TCSR_STOPE. */
 565 #define BM_I2S_TCSR_STOPE    (0x40000000U) /*!< Bit mask for I2S_TCSR_STOPE. */
 566 #define BS_I2S_TCSR_STOPE    (1U)          /*!< Bit field size in bits for I2S_TCSR_STOPE. */
 567
 568 /*! @brief Read current value of the I2S_TCSR_STOPE field. */
 569 #define BR_I2S_TCSR_STOPE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_STOPE))
 570
 571 /*! @brief Format value for bitfield I2S_TCSR_STOPE. */
 572 #define BF_I2S_TCSR_STOPE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_STOPE) & BM_I2S_TCSR_STOPE)
 573
 574 /*! @brief Set the STOPE field to a new value. */
 575 #define BW_I2S_TCSR_STOPE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_STOPE) = (v))
 576 /*@}*/
 577
 578 /*!
 579  * @name Register I2S_TCSR, field TE[31] (RW)
 580  *
 581  * Enables/disables the transmitter. When software clears this field, the
 582  * transmitter remains enabled, and this bit remains set, until the end of the current
 583  * frame.
 584  *
 585  * Values:
 586  * - 0 - Transmitter is disabled.
 587  * - 1 - Transmitter is enabled, or transmitter has been disabled and has not
 588  *     yet reached end of frame.
 589  */
 590 /*@{*/
 591 #define BP_I2S_TCSR_TE       (31U)         /*!< Bit position for I2S_TCSR_TE. */
 592 #define BM_I2S_TCSR_TE       (0x80000000U) /*!< Bit mask for I2S_TCSR_TE. */
 593 #define BS_I2S_TCSR_TE       (1U)          /*!< Bit field size in bits for I2S_TCSR_TE. */
 594
 595 /*! @brief Read current value of the I2S_TCSR_TE field. */
 596 #define BR_I2S_TCSR_TE(x)    (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_TE))
 597
 598 /*! @brief Format value for bitfield I2S_TCSR_TE. */
 599 #define BF_I2S_TCSR_TE(v)    ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_TE) & BM_I2S_TCSR_TE)
 600
 601 /*! @brief Set the TE field to a new value. */
 602 #define BW_I2S_TCSR_TE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_TE) = (v))
 603 /*@}*/
 604
 605 /*******************************************************************************
 606  * HW_I2S_TCR1 - SAI Transmit Configuration 1 Register
 607  ******************************************************************************/
 608
 609 /*!
 610  * @brief HW_I2S_TCR1 - SAI Transmit Configuration 1 Register (RW)
 611  *
 612  * Reset value: 0x00000000U
 613  */
 614 typedef union _hw_i2s_tcr1
 615 {
 616     uint32_t U;
 617     struct _hw_i2s_tcr1_bitfields
 618     {
 619         uint32_t TFW : 3;              /*!< [2:0] Transmit FIFO Watermark */
 620         uint32_t RESERVED0 : 29;       /*!< [31:3]  */
 621     } B;
 622 } hw_i2s_tcr1_t;
 623
 624 /*!
 625  * @name Constants and macros for entire I2S_TCR1 register
 626  */
 627 /*@{*/
 628 #define HW_I2S_TCR1_ADDR(x)      ((x) + 0x4U)
 629
 630 #define HW_I2S_TCR1(x)           (*(__IO hw_i2s_tcr1_t *) HW_I2S_TCR1_ADDR(x))
 631 #define HW_I2S_TCR1_RD(x)        (HW_I2S_TCR1(x).U)
 632 #define HW_I2S_TCR1_WR(x, v)     (HW_I2S_TCR1(x).U = (v))
 633 #define HW_I2S_TCR1_SET(x, v)    (HW_I2S_TCR1_WR(x, HW_I2S_TCR1_RD(x) |  (v)))
 634 #define HW_I2S_TCR1_CLR(x, v)    (HW_I2S_TCR1_WR(x, HW_I2S_TCR1_RD(x) & ~(v)))
 635 #define HW_I2S_TCR1_TOG(x, v)    (HW_I2S_TCR1_WR(x, HW_I2S_TCR1_RD(x) ^  (v)))
 636 /*@}*/
 637
 638 /*
 639  * Constants & macros for individual I2S_TCR1 bitfields
 640  */
 641
 642 /*!
 643  * @name Register I2S_TCR1, field TFW[2:0] (RW)
 644  *
 645  * Configures the watermark level for all enabled transmit channels.
 646  */
 647 /*@{*/
 648 #define BP_I2S_TCR1_TFW      (0U)          /*!< Bit position for I2S_TCR1_TFW. */
 649 #define BM_I2S_TCR1_TFW      (0x00000007U) /*!< Bit mask for I2S_TCR1_TFW. */
 650 #define BS_I2S_TCR1_TFW      (3U)          /*!< Bit field size in bits for I2S_TCR1_TFW. */
 651
 652 /*! @brief Read current value of the I2S_TCR1_TFW field. */
 653 #define BR_I2S_TCR1_TFW(x)   (HW_I2S_TCR1(x).B.TFW)
 654
 655 /*! @brief Format value for bitfield I2S_TCR1_TFW. */
 656 #define BF_I2S_TCR1_TFW(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TCR1_TFW) & BM_I2S_TCR1_TFW)
 657
 658 /*! @brief Set the TFW field to a new value. */
 659 #define BW_I2S_TCR1_TFW(x, v) (HW_I2S_TCR1_WR(x, (HW_I2S_TCR1_RD(x) & ~BM_I2S_TCR1_TFW) | BF_I2S_TCR1_TFW(v)))
 660 /*@}*/
 661
 662 /*******************************************************************************
 663  * HW_I2S_TCR2 - SAI Transmit Configuration 2 Register
 664  ******************************************************************************/
 665
 666 /*!
 667  * @brief HW_I2S_TCR2 - SAI Transmit Configuration 2 Register (RW)
 668  *
 669  * Reset value: 0x00000000U
 670  *
 671  * This register must not be altered when TCSR[TE] is set.
 672  */
 673 typedef union _hw_i2s_tcr2
 674 {
 675     uint32_t U;
 676     struct _hw_i2s_tcr2_bitfields
 677     {
 678         uint32_t DIV : 8;              /*!< [7:0] Bit Clock Divide */
 679         uint32_t RESERVED0 : 16;       /*!< [23:8]  */
 680         uint32_t BCD : 1;              /*!< [24] Bit Clock Direction */
 681         uint32_t BCP : 1;              /*!< [25] Bit Clock Polarity */
 682         uint32_t MSEL : 2;             /*!< [27:26] MCLK Select */
 683         uint32_t BCI : 1;              /*!< [28] Bit Clock Input */
 684         uint32_t BCS : 1;              /*!< [29] Bit Clock Swap */
 685         uint32_t SYNC : 2;             /*!< [31:30] Synchronous Mode */
 686     } B;
 687 } hw_i2s_tcr2_t;
 688
 689 /*!
 690  * @name Constants and macros for entire I2S_TCR2 register
 691  */
 692 /*@{*/
 693 #define HW_I2S_TCR2_ADDR(x)      ((x) + 0x8U)
 694
 695 #define HW_I2S_TCR2(x)           (*(__IO hw_i2s_tcr2_t *) HW_I2S_TCR2_ADDR(x))
 696 #define HW_I2S_TCR2_RD(x)        (HW_I2S_TCR2(x).U)
 697 #define HW_I2S_TCR2_WR(x, v)     (HW_I2S_TCR2(x).U = (v))
 698 #define HW_I2S_TCR2_SET(x, v)    (HW_I2S_TCR2_WR(x, HW_I2S_TCR2_RD(x) |  (v)))
 699 #define HW_I2S_TCR2_CLR(x, v)    (HW_I2S_TCR2_WR(x, HW_I2S_TCR2_RD(x) & ~(v)))
 700 #define HW_I2S_TCR2_TOG(x, v)    (HW_I2S_TCR2_WR(x, HW_I2S_TCR2_RD(x) ^  (v)))
 701 /*@}*/
 702
 703 /*
 704  * Constants & macros for individual I2S_TCR2 bitfields
 705  */
 706
 707 /*!
 708  * @name Register I2S_TCR2, field DIV[7:0] (RW)
 709  *
 710  * Divides down the audio master clock to generate the bit clock when configured
 711  * for an internal bit clock. The division value is (DIV + 1) * 2.
 712  */
 713 /*@{*/
 714 #define BP_I2S_TCR2_DIV      (0U)          /*!< Bit position for I2S_TCR2_DIV. */
 715 #define BM_I2S_TCR2_DIV      (0x000000FFU) /*!< Bit mask for I2S_TCR2_DIV. */
 716 #define BS_I2S_TCR2_DIV      (8U)          /*!< Bit field size in bits for I2S_TCR2_DIV. */
 717
 718 /*! @brief Read current value of the I2S_TCR2_DIV field. */
 719 #define BR_I2S_TCR2_DIV(x)   (HW_I2S_TCR2(x).B.DIV)
 720
 721 /*! @brief Format value for bitfield I2S_TCR2_DIV. */
 722 #define BF_I2S_TCR2_DIV(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_DIV) & BM_I2S_TCR2_DIV)
 723
 724 /*! @brief Set the DIV field to a new value. */
 725 #define BW_I2S_TCR2_DIV(x, v) (HW_I2S_TCR2_WR(x, (HW_I2S_TCR2_RD(x) & ~BM_I2S_TCR2_DIV) | BF_I2S_TCR2_DIV(v)))
 726 /*@}*/
 727
 728 /*!
 729  * @name Register I2S_TCR2, field BCD[24] (RW)
 730  *
 731  * Configures the direction of the bit clock.
 732  *
 733  * Values:
 734  * - 0 - Bit clock is generated externally in Slave mode.
 735  * - 1 - Bit clock is generated internally in Master mode.
 736  */
 737 /*@{*/
 738 #define BP_I2S_TCR2_BCD      (24U)         /*!< Bit position for I2S_TCR2_BCD. */
 739 #define BM_I2S_TCR2_BCD      (0x01000000U) /*!< Bit mask for I2S_TCR2_BCD. */
 740 #define BS_I2S_TCR2_BCD      (1U)          /*!< Bit field size in bits for I2S_TCR2_BCD. */
 741
 742 /*! @brief Read current value of the I2S_TCR2_BCD field. */
 743 #define BR_I2S_TCR2_BCD(x)   (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCD))
 744
 745 /*! @brief Format value for bitfield I2S_TCR2_BCD. */
 746 #define BF_I2S_TCR2_BCD(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_BCD) & BM_I2S_TCR2_BCD)
 747
 748 /*! @brief Set the BCD field to a new value. */
 749 #define BW_I2S_TCR2_BCD(x, v) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCD) = (v))
 750 /*@}*/
 751
 752 /*!
 753  * @name Register I2S_TCR2, field BCP[25] (RW)
 754  *
 755  * Configures the polarity of the bit clock.
 756  *
 757  * Values:
 758  * - 0 - Bit clock is active high with drive outputs on rising edge and sample
 759  *     inputs on falling edge.
 760  * - 1 - Bit clock is active low with drive outputs on falling edge and sample
 761  *     inputs on rising edge.
 762  */
 763 /*@{*/
 764 #define BP_I2S_TCR2_BCP      (25U)         /*!< Bit position for I2S_TCR2_BCP. */
 765 #define BM_I2S_TCR2_BCP      (0x02000000U) /*!< Bit mask for I2S_TCR2_BCP. */
 766 #define BS_I2S_TCR2_BCP      (1U)          /*!< Bit field size in bits for I2S_TCR2_BCP. */
 767
 768 /*! @brief Read current value of the I2S_TCR2_BCP field. */
 769 #define BR_I2S_TCR2_BCP(x)   (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCP))
 770
 771 /*! @brief Format value for bitfield I2S_TCR2_BCP. */
 772 #define BF_I2S_TCR2_BCP(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_BCP) & BM_I2S_TCR2_BCP)
 773
 774 /*! @brief Set the BCP field to a new value. */
 775 #define BW_I2S_TCR2_BCP(x, v) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCP) = (v))
 776 /*@}*/
 777
 778 /*!
 779  * @name Register I2S_TCR2, field MSEL[27:26] (RW)
 780  *
 781  * Selects the audio Master Clock option used to generate an internally
 782  * generated bit clock. This field has no effect when configured for an externally
 783  * generated bit clock. Depending on the device, some Master Clock options might not be
 784  * available. See the chip configuration details for the availability and
 785  * chip-specific meaning of each option.
 786  *
 787  * Values:
 788  * - 00 - Bus Clock selected.
 789  * - 01 - Master Clock (MCLK) 1 option selected.
 790  * - 10 - Master Clock (MCLK) 2 option selected.
 791  * - 11 - Master Clock (MCLK) 3 option selected.
 792  */
 793 /*@{*/
 794 #define BP_I2S_TCR2_MSEL     (26U)         /*!< Bit position for I2S_TCR2_MSEL. */
 795 #define BM_I2S_TCR2_MSEL     (0x0C000000U) /*!< Bit mask for I2S_TCR2_MSEL. */
 796 #define BS_I2S_TCR2_MSEL     (2U)          /*!< Bit field size in bits for I2S_TCR2_MSEL. */
 797
 798 /*! @brief Read current value of the I2S_TCR2_MSEL field. */
 799 #define BR_I2S_TCR2_MSEL(x)  (HW_I2S_TCR2(x).B.MSEL)
 800
 801 /*! @brief Format value for bitfield I2S_TCR2_MSEL. */
 802 #define BF_I2S_TCR2_MSEL(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_MSEL) & BM_I2S_TCR2_MSEL)
 803
 804 /*! @brief Set the MSEL field to a new value. */
 805 #define BW_I2S_TCR2_MSEL(x, v) (HW_I2S_TCR2_WR(x, (HW_I2S_TCR2_RD(x) & ~BM_I2S_TCR2_MSEL) | BF_I2S_TCR2_MSEL(v)))
 806 /*@}*/
 807
 808 /*!
 809  * @name Register I2S_TCR2, field BCI[28] (RW)
 810  *
 811  * When this field is set and using an internally generated bit clock in either
 812  * synchronous or asynchronous mode, the bit clock actually used by the
 813  * transmitter is delayed by the pad output delay (the transmitter is clocked by the pad
 814  * input as if the clock was externally generated). This has the effect of
 815  * decreasing the data input setup time, but increasing the data output valid time. The
 816  * slave mode timing from the datasheet should be used for the transmitter when
 817  * this bit is set. In synchronous mode, this bit allows the transmitter to use
 818  * the slave mode timing from the datasheet, while the receiver uses the master
 819  * mode timing. This field has no effect when configured for an externally generated
 820  * bit clock .
 821  *
 822  * Values:
 823  * - 0 - No effect.
 824  * - 1 - Internal logic is clocked as if bit clock was externally generated.
 825  */
 826 /*@{*/
 827 #define BP_I2S_TCR2_BCI      (28U)         /*!< Bit position for I2S_TCR2_BCI. */
 828 #define BM_I2S_TCR2_BCI      (0x10000000U) /*!< Bit mask for I2S_TCR2_BCI. */
 829 #define BS_I2S_TCR2_BCI      (1U)          /*!< Bit field size in bits for I2S_TCR2_BCI. */
 830
 831 /*! @brief Read current value of the I2S_TCR2_BCI field. */
 832 #define BR_I2S_TCR2_BCI(x)   (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCI))
 833
 834 /*! @brief Format value for bitfield I2S_TCR2_BCI. */
 835 #define BF_I2S_TCR2_BCI(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_BCI) & BM_I2S_TCR2_BCI)
 836
 837 /*! @brief Set the BCI field to a new value. */
 838 #define BW_I2S_TCR2_BCI(x, v) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCI) = (v))
 839 /*@}*/
 840
 841 /*!
 842  * @name Register I2S_TCR2, field BCS[29] (RW)
 843  *
 844  * This field swaps the bit clock used by the transmitter. When the transmitter
 845  * is configured in asynchronous mode and this bit is set, the transmitter is
 846  * clocked by the receiver bit clock (SAI_RX_BCLK). This allows the transmitter and
 847  * receiver to share the same bit clock, but the transmitter continues to use the
 848  * transmit frame sync (SAI_TX_SYNC). When the transmitter is configured in
 849  * synchronous mode, the transmitter BCS field and receiver BCS field must be set to
 850  * the same value. When both are set, the transmitter and receiver are both
 851  * clocked by the transmitter bit clock (SAI_TX_BCLK) but use the receiver frame sync
 852  * (SAI_RX_SYNC).
 853  *
 854  * Values:
 855  * - 0 - Use the normal bit clock source.
 856  * - 1 - Swap the bit clock source.
 857  */
 858 /*@{*/
 859 #define BP_I2S_TCR2_BCS      (29U)         /*!< Bit position for I2S_TCR2_BCS. */
 860 #define BM_I2S_TCR2_BCS      (0x20000000U) /*!< Bit mask for I2S_TCR2_BCS. */
 861 #define BS_I2S_TCR2_BCS      (1U)          /*!< Bit field size in bits for I2S_TCR2_BCS. */
 862
 863 /*! @brief Read current value of the I2S_TCR2_BCS field. */
 864 #define BR_I2S_TCR2_BCS(x)   (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCS))
 865
 866 /*! @brief Format value for bitfield I2S_TCR2_BCS. */
 867 #define BF_I2S_TCR2_BCS(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_BCS) & BM_I2S_TCR2_BCS)
 868
 869 /*! @brief Set the BCS field to a new value. */
 870 #define BW_I2S_TCR2_BCS(x, v) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCS) = (v))
 871 /*@}*/
 872
 873 /*!
 874  * @name Register I2S_TCR2, field SYNC[31:30] (RW)
 875  *
 876  * Configures between asynchronous and synchronous modes of operation. When
 877  * configured for a synchronous mode of operation, the receiver must be configured
 878  * for asynchronous operation.
 879  *
 880  * Values:
 881  * - 00 - Asynchronous mode.
 882  * - 01 - Synchronous with receiver.
 883  * - 10 - Synchronous with another SAI transmitter.
 884  * - 11 - Synchronous with another SAI receiver.
 885  */
 886 /*@{*/
 887 #define BP_I2S_TCR2_SYNC     (30U)         /*!< Bit position for I2S_TCR2_SYNC. */
 888 #define BM_I2S_TCR2_SYNC     (0xC0000000U) /*!< Bit mask for I2S_TCR2_SYNC. */
 889 #define BS_I2S_TCR2_SYNC     (2U)          /*!< Bit field size in bits for I2S_TCR2_SYNC. */
 890
 891 /*! @brief Read current value of the I2S_TCR2_SYNC field. */
 892 #define BR_I2S_TCR2_SYNC(x)  (HW_I2S_TCR2(x).B.SYNC)
 893
 894 /*! @brief Format value for bitfield I2S_TCR2_SYNC. */
 895 #define BF_I2S_TCR2_SYNC(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_SYNC) & BM_I2S_TCR2_SYNC)
 896
 897 /*! @brief Set the SYNC field to a new value. */
 898 #define BW_I2S_TCR2_SYNC(x, v) (HW_I2S_TCR2_WR(x, (HW_I2S_TCR2_RD(x) & ~BM_I2S_TCR2_SYNC) | BF_I2S_TCR2_SYNC(v)))
 899 /*@}*/
 900
 901 /*******************************************************************************
 902  * HW_I2S_TCR3 - SAI Transmit Configuration 3 Register
 903  ******************************************************************************/
 904
 905 /*!
 906  * @brief HW_I2S_TCR3 - SAI Transmit Configuration 3 Register (RW)
 907  *
 908  * Reset value: 0x00000000U
 909  */
 910 typedef union _hw_i2s_tcr3
 911 {
 912     uint32_t U;
 913     struct _hw_i2s_tcr3_bitfields
 914     {
 915         uint32_t WDFL : 4;             /*!< [3:0] Word Flag Configuration */
 916         uint32_t RESERVED0 : 12;       /*!< [15:4]  */
 917         uint32_t TCE : 1;              /*!< [16] Transmit Channel Enable */
 918         uint32_t RESERVED1 : 15;       /*!< [31:17]  */
 919     } B;
 920 } hw_i2s_tcr3_t;
 921
 922 /*!
 923  * @name Constants and macros for entire I2S_TCR3 register
 924  */
 925 /*@{*/
 926 #define HW_I2S_TCR3_ADDR(x)      ((x) + 0xCU)
 927
 928 #define HW_I2S_TCR3(x)           (*(__IO hw_i2s_tcr3_t *) HW_I2S_TCR3_ADDR(x))
 929 #define HW_I2S_TCR3_RD(x)        (HW_I2S_TCR3(x).U)
 930 #define HW_I2S_TCR3_WR(x, v)     (HW_I2S_TCR3(x).U = (v))
 931 #define HW_I2S_TCR3_SET(x, v)    (HW_I2S_TCR3_WR(x, HW_I2S_TCR3_RD(x) |  (v)))
 932 #define HW_I2S_TCR3_CLR(x, v)    (HW_I2S_TCR3_WR(x, HW_I2S_TCR3_RD(x) & ~(v)))
 933 #define HW_I2S_TCR3_TOG(x, v)    (HW_I2S_TCR3_WR(x, HW_I2S_TCR3_RD(x) ^  (v)))
 934 /*@}*/
 935
 936 /*
 937  * Constants & macros for individual I2S_TCR3 bitfields
 938  */
 939
 940 /*!
 941  * @name Register I2S_TCR3, field WDFL[3:0] (RW)
 942  *
 943  * Configures which word sets the start of word flag. The value written must be
 944  * one less than the word number. For example, writing 0 configures the first
 945  * word in the frame. When configured to a value greater than TCR4[FRSZ], then the
 946  * start of word flag is never set.
 947  */
 948 /*@{*/
 949 #define BP_I2S_TCR3_WDFL     (0U)          /*!< Bit position for I2S_TCR3_WDFL. */
 950 #define BM_I2S_TCR3_WDFL     (0x0000000FU) /*!< Bit mask for I2S_TCR3_WDFL. */
 951 #define BS_I2S_TCR3_WDFL     (4U)          /*!< Bit field size in bits for I2S_TCR3_WDFL. */
 952
 953 /*! @brief Read current value of the I2S_TCR3_WDFL field. */
 954 #define BR_I2S_TCR3_WDFL(x)  (HW_I2S_TCR3(x).B.WDFL)
 955
 956 /*! @brief Format value for bitfield I2S_TCR3_WDFL. */
 957 #define BF_I2S_TCR3_WDFL(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_TCR3_WDFL) & BM_I2S_TCR3_WDFL)
 958
 959 /*! @brief Set the WDFL field to a new value. */
 960 #define BW_I2S_TCR3_WDFL(x, v) (HW_I2S_TCR3_WR(x, (HW_I2S_TCR3_RD(x) & ~BM_I2S_TCR3_WDFL) | BF_I2S_TCR3_WDFL(v)))
 961 /*@}*/
 962
 963 /*!
 964  * @name Register I2S_TCR3, field TCE[16] (RW)
 965  *
 966  * Enables the corresponding data channel for transmit operation. A channel must
 967  * be enabled before its FIFO is accessed. Changing this field will take effect
 968  * immediately for generating the FIFO request and warning flags, but at the end
 969  * of each frame for transmit operation.
 970  *
 971  * Values:
 972  * - 0 - Transmit data channel N is disabled.
 973  * - 1 - Transmit data channel N is enabled.
 974  */
 975 /*@{*/
 976 #define BP_I2S_TCR3_TCE      (16U)         /*!< Bit position for I2S_TCR3_TCE. */
 977 #define BM_I2S_TCR3_TCE      (0x00010000U) /*!< Bit mask for I2S_TCR3_TCE. */
 978 #define BS_I2S_TCR3_TCE      (1U)          /*!< Bit field size in bits for I2S_TCR3_TCE. */
 979
 980 /*! @brief Read current value of the I2S_TCR3_TCE field. */
 981 #define BR_I2S_TCR3_TCE(x)   (BITBAND_ACCESS32(HW_I2S_TCR3_ADDR(x), BP_I2S_TCR3_TCE))
 982
 983 /*! @brief Format value for bitfield I2S_TCR3_TCE. */
 984 #define BF_I2S_TCR3_TCE(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TCR3_TCE) & BM_I2S_TCR3_TCE)
 985
 986 /*! @brief Set the TCE field to a new value. */
 987 #define BW_I2S_TCR3_TCE(x, v) (BITBAND_ACCESS32(HW_I2S_TCR3_ADDR(x), BP_I2S_TCR3_TCE) = (v))
 988 /*@}*/
 989
 990 /*******************************************************************************
 991  * HW_I2S_TCR4 - SAI Transmit Configuration 4 Register
 992  ******************************************************************************/
 993
 994 /*!
 995  * @brief HW_I2S_TCR4 - SAI Transmit Configuration 4 Register (RW)
 996  *
 997  * Reset value: 0x00000000U
 998  *
 999  * This register must not be altered when TCSR[TE] is set.
1000  */
1001 typedef union _hw_i2s_tcr4
1002 {
1003     uint32_t U;
1004     struct _hw_i2s_tcr4_bitfields
1005     {
1006         uint32_t FSD : 1;              /*!< [0] Frame Sync Direction */
1007         uint32_t FSP : 1;              /*!< [1] Frame Sync Polarity */
1008         uint32_t ONDEM : 1;            /*!< [2] On Demand Mode */
1009         uint32_t FSE : 1;              /*!< [3] Frame Sync Early */
1010         uint32_t MF : 1;               /*!< [4] MSB First */
1011         uint32_t RESERVED0 : 3;        /*!< [7:5]  */
1012         uint32_t SYWD : 5;             /*!< [12:8] Sync Width */
1013         uint32_t RESERVED1 : 3;        /*!< [15:13]  */
1014         uint32_t FRSZ : 4;             /*!< [19:16] Frame size */
1015         uint32_t RESERVED2 : 4;        /*!< [23:20]  */
1016         uint32_t FPACK : 2;            /*!< [25:24] FIFO Packing Mode */
1017         uint32_t RESERVED3 : 2;        /*!< [27:26]  */
1018         uint32_t FCONT : 1;            /*!< [28] FIFO Continue on Error */
1019         uint32_t RESERVED4 : 3;        /*!< [31:29]  */
1020     } B;
1021 } hw_i2s_tcr4_t;
1022
1023 /*!
1024  * @name Constants and macros for entire I2S_TCR4 register
1025  */
1026 /*@{*/
1027 #define HW_I2S_TCR4_ADDR(x)      ((x) + 0x10U)
1028
1029 #define HW_I2S_TCR4(x)           (*(__IO hw_i2s_tcr4_t *) HW_I2S_TCR4_ADDR(x))
1030 #define HW_I2S_TCR4_RD(x)        (HW_I2S_TCR4(x).U)
1031 #define HW_I2S_TCR4_WR(x, v)     (HW_I2S_TCR4(x).U = (v))
1032 #define HW_I2S_TCR4_SET(x, v)    (HW_I2S_TCR4_WR(x, HW_I2S_TCR4_RD(x) |  (v)))
1033 #define HW_I2S_TCR4_CLR(x, v)    (HW_I2S_TCR4_WR(x, HW_I2S_TCR4_RD(x) & ~(v)))
1034 #define HW_I2S_TCR4_TOG(x, v)    (HW_I2S_TCR4_WR(x, HW_I2S_TCR4_RD(x) ^  (v)))
1035 /*@}*/
1036
1037 /*
1038  * Constants & macros for individual I2S_TCR4 bitfields
1039  */
1040
1041 /*!
1042  * @name Register I2S_TCR4, field FSD[0] (RW)
1043  *
1044  * Configures the direction of the frame sync.
1045  *
1046  * Values:
1047  * - 0 - Frame sync is generated externally in Slave mode.
1048  * - 1 - Frame sync is generated internally in Master mode.
1049  */
1050 /*@{*/
1051 #define BP_I2S_TCR4_FSD      (0U)          /*!< Bit position for I2S_TCR4_FSD. */
1052 #define BM_I2S_TCR4_FSD      (0x00000001U) /*!< Bit mask for I2S_TCR4_FSD. */
1053 #define BS_I2S_TCR4_FSD      (1U)          /*!< Bit field size in bits for I2S_TCR4_FSD. */
1054
1055 /*! @brief Read current value of the I2S_TCR4_FSD field. */
1056 #define BR_I2S_TCR4_FSD(x)   (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSD))
1057
1058 /*! @brief Format value for bitfield I2S_TCR4_FSD. */
1059 #define BF_I2S_TCR4_FSD(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_FSD) & BM_I2S_TCR4_FSD)
1060
1061 /*! @brief Set the FSD field to a new value. */
1062 #define BW_I2S_TCR4_FSD(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSD) = (v))
1063 /*@}*/
1064
1065 /*!
1066  * @name Register I2S_TCR4, field FSP[1] (RW)
1067  *
1068  * Configures the polarity of the frame sync.
1069  *
1070  * Values:
1071  * - 0 - Frame sync is active high.
1072  * - 1 - Frame sync is active low.
1073  */
1074 /*@{*/
1075 #define BP_I2S_TCR4_FSP      (1U)          /*!< Bit position for I2S_TCR4_FSP. */
1076 #define BM_I2S_TCR4_FSP      (0x00000002U) /*!< Bit mask for I2S_TCR4_FSP. */
1077 #define BS_I2S_TCR4_FSP      (1U)          /*!< Bit field size in bits for I2S_TCR4_FSP. */
1078
1079 /*! @brief Read current value of the I2S_TCR4_FSP field. */
1080 #define BR_I2S_TCR4_FSP(x)   (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSP))
1081
1082 /*! @brief Format value for bitfield I2S_TCR4_FSP. */
1083 #define BF_I2S_TCR4_FSP(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_FSP) & BM_I2S_TCR4_FSP)
1084
1085 /*! @brief Set the FSP field to a new value. */
1086 #define BW_I2S_TCR4_FSP(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSP) = (v))
1087 /*@}*/
1088
1089 /*!
1090  * @name Register I2S_TCR4, field ONDEM[2] (RW)
1091  *
1092  * When set, and the frame sync is generated internally, a frame sync is only
1093  * generated when the FIFO warning flag is clear.
1094  *
1095  * Values:
1096  * - 0 - Internal frame sync is generated continuously.
1097  * - 1 - Internal frame sync is generated when the FIFO warning flag is clear.
1098  */
1099 /*@{*/
1100 #define BP_I2S_TCR4_ONDEM    (2U)          /*!< Bit position for I2S_TCR4_ONDEM. */
1101 #define BM_I2S_TCR4_ONDEM    (0x00000004U) /*!< Bit mask for I2S_TCR4_ONDEM. */
1102 #define BS_I2S_TCR4_ONDEM    (1U)          /*!< Bit field size in bits for I2S_TCR4_ONDEM. */
1103
1104 /*! @brief Read current value of the I2S_TCR4_ONDEM field. */
1105 #define BR_I2S_TCR4_ONDEM(x) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_ONDEM))
1106
1107 /*! @brief Format value for bitfield I2S_TCR4_ONDEM. */
1108 #define BF_I2S_TCR4_ONDEM(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_ONDEM) & BM_I2S_TCR4_ONDEM)
1109
1110 /*! @brief Set the ONDEM field to a new value. */
1111 #define BW_I2S_TCR4_ONDEM(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_ONDEM) = (v))
1112 /*@}*/
1113
1114 /*!
1115  * @name Register I2S_TCR4, field FSE[3] (RW)
1116  *
1117  * Values:
1118  * - 0 - Frame sync asserts with the first bit of the frame.
1119  * - 1 - Frame sync asserts one bit before the first bit of the frame.
1120  */
1121 /*@{*/
1122 #define BP_I2S_TCR4_FSE      (3U)          /*!< Bit position for I2S_TCR4_FSE. */
1123 #define BM_I2S_TCR4_FSE      (0x00000008U) /*!< Bit mask for I2S_TCR4_FSE. */
1124 #define BS_I2S_TCR4_FSE      (1U)          /*!< Bit field size in bits for I2S_TCR4_FSE. */
1125
1126 /*! @brief Read current value of the I2S_TCR4_FSE field. */
1127 #define BR_I2S_TCR4_FSE(x)   (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSE))
1128
1129 /*! @brief Format value for bitfield I2S_TCR4_FSE. */
1130 #define BF_I2S_TCR4_FSE(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_FSE) & BM_I2S_TCR4_FSE)
1131
1132 /*! @brief Set the FSE field to a new value. */
1133 #define BW_I2S_TCR4_FSE(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSE) = (v))
1134 /*@}*/
1135
1136 /*!
1137  * @name Register I2S_TCR4, field MF[4] (RW)
1138  *
1139  * Configures whether the LSB or the MSB is transmitted first.
1140  *
1141  * Values:
1142  * - 0 - LSB is transmitted first.
1143  * - 1 - MSB is transmitted first.
1144  */
1145 /*@{*/
1146 #define BP_I2S_TCR4_MF       (4U)          /*!< Bit position for I2S_TCR4_MF. */
1147 #define BM_I2S_TCR4_MF       (0x00000010U) /*!< Bit mask for I2S_TCR4_MF. */
1148 #define BS_I2S_TCR4_MF       (1U)          /*!< Bit field size in bits for I2S_TCR4_MF. */
1149
1150 /*! @brief Read current value of the I2S_TCR4_MF field. */
1151 #define BR_I2S_TCR4_MF(x)    (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_MF))
1152
1153 /*! @brief Format value for bitfield I2S_TCR4_MF. */
1154 #define BF_I2S_TCR4_MF(v)    ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_MF) & BM_I2S_TCR4_MF)
1155
1156 /*! @brief Set the MF field to a new value. */
1157 #define BW_I2S_TCR4_MF(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_MF) = (v))
1158 /*@}*/
1159
1160 /*!
1161  * @name Register I2S_TCR4, field SYWD[12:8] (RW)
1162  *
1163  * Configures the length of the frame sync in number of bit clocks. The value
1164  * written must be one less than the number of bit clocks. For example, write 0 for
1165  * the frame sync to assert for one bit clock only. The sync width cannot be
1166  * configured longer than the first word of the frame.
1167  */
1168 /*@{*/
1169 #define BP_I2S_TCR4_SYWD     (8U)          /*!< Bit position for I2S_TCR4_SYWD. */
1170 #define BM_I2S_TCR4_SYWD     (0x00001F00U) /*!< Bit mask for I2S_TCR4_SYWD. */
1171 #define BS_I2S_TCR4_SYWD     (5U)          /*!< Bit field size in bits for I2S_TCR4_SYWD. */
1172
1173 /*! @brief Read current value of the I2S_TCR4_SYWD field. */
1174 #define BR_I2S_TCR4_SYWD(x)  (HW_I2S_TCR4(x).B.SYWD)
1175
1176 /*! @brief Format value for bitfield I2S_TCR4_SYWD. */
1177 #define BF_I2S_TCR4_SYWD(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_SYWD) & BM_I2S_TCR4_SYWD)
1178
1179 /*! @brief Set the SYWD field to a new value. */
1180 #define BW_I2S_TCR4_SYWD(x, v) (HW_I2S_TCR4_WR(x, (HW_I2S_TCR4_RD(x) & ~BM_I2S_TCR4_SYWD) | BF_I2S_TCR4_SYWD(v)))
1181 /*@}*/
1182
1183 /*!
1184  * @name Register I2S_TCR4, field FRSZ[19:16] (RW)
1185  *
1186  * Configures the number of words in each frame. The value written must be one
1187  * less than the number of words in the frame. For example, write 0 for one word
1188  * per frame. The maximum supported frame size is 16 words.
1189  */
1190 /*@{*/
1191 #define BP_I2S_TCR4_FRSZ     (16U)         /*!< Bit position for I2S_TCR4_FRSZ. */
1192 #define BM_I2S_TCR4_FRSZ     (0x000F0000U) /*!< Bit mask for I2S_TCR4_FRSZ. */
1193 #define BS_I2S_TCR4_FRSZ     (4U)          /*!< Bit field size in bits for I2S_TCR4_FRSZ. */
1194
1195 /*! @brief Read current value of the I2S_TCR4_FRSZ field. */
1196 #define BR_I2S_TCR4_FRSZ(x)  (HW_I2S_TCR4(x).B.FRSZ)
1197
1198 /*! @brief Format value for bitfield I2S_TCR4_FRSZ. */
1199 #define BF_I2S_TCR4_FRSZ(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_FRSZ) & BM_I2S_TCR4_FRSZ)
1200
1201 /*! @brief Set the FRSZ field to a new value. */
1202 #define BW_I2S_TCR4_FRSZ(x, v) (HW_I2S_TCR4_WR(x, (HW_I2S_TCR4_RD(x) & ~BM_I2S_TCR4_FRSZ) | BF_I2S_TCR4_FRSZ(v)))
1203 /*@}*/
1204
1205 /*!
1206  * @name Register I2S_TCR4, field FPACK[25:24] (RW)
1207  *
1208  * Enables packing of 8-bit data or 16-bit data into each 32-bit FIFO word. If
1209  * the word size is greater than 8-bit or 16-bit then only the first 8-bit or
1210  * 16-bits are loaded from the FIFO. The first word in each frame always starts with
1211  * a new 32-bit FIFO word and the first bit shifted must be configured within the
1212  * first packed word. When FIFO packing is enabled, the FIFO write pointer will
1213  * only increment when the full 32-bit FIFO word has been written by software.
1214  *
1215  * Values:
1216  * - 00 - FIFO packing is disabled
1217  * - 01 - Reserved
1218  * - 10 - 8-bit FIFO packing is enabled
1219  * - 11 - 16-bit FIFO packing is enabled
1220  */
1221 /*@{*/
1222 #define BP_I2S_TCR4_FPACK    (24U)         /*!< Bit position for I2S_TCR4_FPACK. */
1223 #define BM_I2S_TCR4_FPACK    (0x03000000U) /*!< Bit mask for I2S_TCR4_FPACK. */
1224 #define BS_I2S_TCR4_FPACK    (2U)          /*!< Bit field size in bits for I2S_TCR4_FPACK. */
1225
1226 /*! @brief Read current value of the I2S_TCR4_FPACK field. */
1227 #define BR_I2S_TCR4_FPACK(x) (HW_I2S_TCR4(x).B.FPACK)
1228
1229 /*! @brief Format value for bitfield I2S_TCR4_FPACK. */
1230 #define BF_I2S_TCR4_FPACK(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_FPACK) & BM_I2S_TCR4_FPACK)
1231
1232 /*! @brief Set the FPACK field to a new value. */
1233 #define BW_I2S_TCR4_FPACK(x, v) (HW_I2S_TCR4_WR(x, (HW_I2S_TCR4_RD(x) & ~BM_I2S_TCR4_FPACK) | BF_I2S_TCR4_FPACK(v)))
1234 /*@}*/
1235
1236 /*!
1237  * @name Register I2S_TCR4, field FCONT[28] (RW)
1238  *
1239  * Configures when the SAI will continue transmitting after a FIFO error has
1240  * been detected.
1241  *
1242  * Values:
1243  * - 0 - On FIFO error, the SAI will continue from the start of the next frame
1244  *     after the FIFO error flag has been cleared.
1245  * - 1 - On FIFO error, the SAI will continue from the same word that caused the
1246  *     FIFO error to set after the FIFO warning flag has been cleared.
1247  */
1248 /*@{*/
1249 #define BP_I2S_TCR4_FCONT    (28U)         /*!< Bit position for I2S_TCR4_FCONT. */
1250 #define BM_I2S_TCR4_FCONT    (0x10000000U) /*!< Bit mask for I2S_TCR4_FCONT. */
1251 #define BS_I2S_TCR4_FCONT    (1U)          /*!< Bit field size in bits for I2S_TCR4_FCONT. */
1252
1253 /*! @brief Read current value of the I2S_TCR4_FCONT field. */
1254 #define BR_I2S_TCR4_FCONT(x) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FCONT))
1255
1256 /*! @brief Format value for bitfield I2S_TCR4_FCONT. */
1257 #define BF_I2S_TCR4_FCONT(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_FCONT) & BM_I2S_TCR4_FCONT)
1258
1259 /*! @brief Set the FCONT field to a new value. */
1260 #define BW_I2S_TCR4_FCONT(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FCONT) = (v))
1261 /*@}*/
1262
1263 /*******************************************************************************
1264  * HW_I2S_TCR5 - SAI Transmit Configuration 5 Register
1265  ******************************************************************************/
1266
1267 /*!
1268  * @brief HW_I2S_TCR5 - SAI Transmit Configuration 5 Register (RW)
1269  *
1270  * Reset value: 0x00000000U
1271  *
1272  * This register must not be altered when TCSR[TE] is set.
1273  */
1274 typedef union _hw_i2s_tcr5
1275 {
1276     uint32_t U;
1277     struct _hw_i2s_tcr5_bitfields
1278     {
1279         uint32_t RESERVED0 : 8;        /*!< [7:0]  */
1280         uint32_t FBT : 5;              /*!< [12:8] First Bit Shifted */
1281         uint32_t RESERVED1 : 3;        /*!< [15:13]  */
1282         uint32_t W0W : 5;              /*!< [20:16] Word 0 Width */
1283         uint32_t RESERVED2 : 3;        /*!< [23:21]  */
1284         uint32_t WNW : 5;              /*!< [28:24] Word N Width */
1285         uint32_t RESERVED3 : 3;        /*!< [31:29]  */
1286     } B;
1287 } hw_i2s_tcr5_t;
1288
1289 /*!
1290  * @name Constants and macros for entire I2S_TCR5 register
1291  */
1292 /*@{*/
1293 #define HW_I2S_TCR5_ADDR(x)      ((x) + 0x14U)
1294
1295 #define HW_I2S_TCR5(x)           (*(__IO hw_i2s_tcr5_t *) HW_I2S_TCR5_ADDR(x))
1296 #define HW_I2S_TCR5_RD(x)        (HW_I2S_TCR5(x).U)
1297 #define HW_I2S_TCR5_WR(x, v)     (HW_I2S_TCR5(x).U = (v))
1298 #define HW_I2S_TCR5_SET(x, v)    (HW_I2S_TCR5_WR(x, HW_I2S_TCR5_RD(x) |  (v)))
1299 #define HW_I2S_TCR5_CLR(x, v)    (HW_I2S_TCR5_WR(x, HW_I2S_TCR5_RD(x) & ~(v)))
1300 #define HW_I2S_TCR5_TOG(x, v)    (HW_I2S_TCR5_WR(x, HW_I2S_TCR5_RD(x) ^  (v)))
1301 /*@}*/
1302
1303 /*
1304  * Constants & macros for individual I2S_TCR5 bitfields
1305  */
1306
1307 /*!
1308  * @name Register I2S_TCR5, field FBT[12:8] (RW)
1309  *
1310  * Configures the bit index for the first bit transmitted for each word in the
1311  * frame. If configured for MSB First, the index of the next bit transmitted is
1312  * one less than the current bit transmitted. If configured for LSB First, the
1313  * index of the next bit transmitted is one more than the current bit transmitted.
1314  * The value written must be greater than or equal to the word width when
1315  * configured for MSB First. The value written must be less than or equal to 31-word width
1316  * when configured for LSB First.
1317  */
1318 /*@{*/
1319 #define BP_I2S_TCR5_FBT      (8U)          /*!< Bit position for I2S_TCR5_FBT. */
1320 #define BM_I2S_TCR5_FBT      (0x00001F00U) /*!< Bit mask for I2S_TCR5_FBT. */
1321 #define BS_I2S_TCR5_FBT      (5U)          /*!< Bit field size in bits for I2S_TCR5_FBT. */
1322
1323 /*! @brief Read current value of the I2S_TCR5_FBT field. */
1324 #define BR_I2S_TCR5_FBT(x)   (HW_I2S_TCR5(x).B.FBT)
1325
1326 /*! @brief Format value for bitfield I2S_TCR5_FBT. */
1327 #define BF_I2S_TCR5_FBT(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TCR5_FBT) & BM_I2S_TCR5_FBT)
1328
1329 /*! @brief Set the FBT field to a new value. */
1330 #define BW_I2S_TCR5_FBT(x, v) (HW_I2S_TCR5_WR(x, (HW_I2S_TCR5_RD(x) & ~BM_I2S_TCR5_FBT) | BF_I2S_TCR5_FBT(v)))
1331 /*@}*/
1332
1333 /*!
1334  * @name Register I2S_TCR5, field W0W[20:16] (RW)
1335  *
1336  * Configures the number of bits in the first word in each frame. The value
1337  * written must be one less than the number of bits in the first word. Word width of
1338  * less than 8 bits is not supported if there is only one word per frame.
1339  */
1340 /*@{*/
1341 #define BP_I2S_TCR5_W0W      (16U)         /*!< Bit position for I2S_TCR5_W0W. */
1342 #define BM_I2S_TCR5_W0W      (0x001F0000U) /*!< Bit mask for I2S_TCR5_W0W. */
1343 #define BS_I2S_TCR5_W0W      (5U)          /*!< Bit field size in bits for I2S_TCR5_W0W. */
1344
1345 /*! @brief Read current value of the I2S_TCR5_W0W field. */
1346 #define BR_I2S_TCR5_W0W(x)   (HW_I2S_TCR5(x).B.W0W)
1347
1348 /*! @brief Format value for bitfield I2S_TCR5_W0W. */
1349 #define BF_I2S_TCR5_W0W(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TCR5_W0W) & BM_I2S_TCR5_W0W)
1350
1351 /*! @brief Set the W0W field to a new value. */
1352 #define BW_I2S_TCR5_W0W(x, v) (HW_I2S_TCR5_WR(x, (HW_I2S_TCR5_RD(x) & ~BM_I2S_TCR5_W0W) | BF_I2S_TCR5_W0W(v)))
1353 /*@}*/
1354
1355 /*!
1356  * @name Register I2S_TCR5, field WNW[28:24] (RW)
1357  *
1358  * Configures the number of bits in each word, for each word except the first in
1359  * the frame. The value written must be one less than the number of bits per
1360  * word. Word width of less than 8 bits is not supported.
1361  */
1362 /*@{*/
1363 #define BP_I2S_TCR5_WNW      (24U)         /*!< Bit position for I2S_TCR5_WNW. */
1364 #define BM_I2S_TCR5_WNW      (0x1F000000U) /*!< Bit mask for I2S_TCR5_WNW. */
1365 #define BS_I2S_TCR5_WNW      (5U)          /*!< Bit field size in bits for I2S_TCR5_WNW. */
1366
1367 /*! @brief Read current value of the I2S_TCR5_WNW field. */
1368 #define BR_I2S_TCR5_WNW(x)   (HW_I2S_TCR5(x).B.WNW)
1369
1370 /*! @brief Format value for bitfield I2S_TCR5_WNW. */
1371 #define BF_I2S_TCR5_WNW(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TCR5_WNW) & BM_I2S_TCR5_WNW)
1372
1373 /*! @brief Set the WNW field to a new value. */
1374 #define BW_I2S_TCR5_WNW(x, v) (HW_I2S_TCR5_WR(x, (HW_I2S_TCR5_RD(x) & ~BM_I2S_TCR5_WNW) | BF_I2S_TCR5_WNW(v)))
1375 /*@}*/
1376
1377 /*******************************************************************************
1378  * HW_I2S_TDRn - SAI Transmit Data Register
1379  ******************************************************************************/
1380
1381 /*!
1382  * @brief HW_I2S_TDRn - SAI Transmit Data Register (WORZ)
1383  *
1384  * Reset value: 0x00000000U
1385  */
1386 typedef union _hw_i2s_tdrn
1387 {
1388     uint32_t U;
1389     struct _hw_i2s_tdrn_bitfields
1390     {
1391         uint32_t TDR : 32;             /*!< [31:0] Transmit Data Register */
1392     } B;
1393 } hw_i2s_tdrn_t;
1394
1395 /*!
1396  * @name Constants and macros for entire I2S_TDRn register
1397  */
1398 /*@{*/
1399 #define HW_I2S_TDRn_COUNT (1U)
1400
1401 #define HW_I2S_TDRn_ADDR(x, n)   ((x) + 0x20U + (0x4U * (n)))
1402
1403 #define HW_I2S_TDRn(x, n)        (*(__O hw_i2s_tdrn_t *) HW_I2S_TDRn_ADDR(x, n))
1404 #define HW_I2S_TDRn_RD(x, n)     (HW_I2S_TDRn(x, n).U)
1405 #define HW_I2S_TDRn_WR(x, n, v)  (HW_I2S_TDRn(x, n).U = (v))
1406 /*@}*/
1407
1408 /*
1409  * Constants & macros for individual I2S_TDRn bitfields
1410  */
1411
1412 /*!
1413  * @name Register I2S_TDRn, field TDR[31:0] (WORZ)
1414  *
1415  * The corresponding TCR3[TCE] bit must be set before accessing the channel's
1416  * transmit data register. Writes to this register when the transmit FIFO is not
1417  * full will push the data written into the transmit data FIFO. Writes to this
1418  * register when the transmit FIFO is full are ignored.
1419  */
1420 /*@{*/
1421 #define BP_I2S_TDRn_TDR      (0U)          /*!< Bit position for I2S_TDRn_TDR. */
1422 #define BM_I2S_TDRn_TDR      (0xFFFFFFFFU) /*!< Bit mask for I2S_TDRn_TDR. */
1423 #define BS_I2S_TDRn_TDR      (32U)         /*!< Bit field size in bits for I2S_TDRn_TDR. */
1424
1425 /*! @brief Format value for bitfield I2S_TDRn_TDR. */
1426 #define BF_I2S_TDRn_TDR(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TDRn_TDR) & BM_I2S_TDRn_TDR)
1427
1428 /*! @brief Set the TDR field to a new value. */
1429 #define BW_I2S_TDRn_TDR(x, n, v) (HW_I2S_TDRn_WR(x, n, v))
1430 /*@}*/
1431
1432 /*******************************************************************************
1433  * HW_I2S_TFRn - SAI Transmit FIFO Register
1434  ******************************************************************************/
1435
1436 /*!
1437  * @brief HW_I2S_TFRn - SAI Transmit FIFO Register (RO)
1438  *
1439  * Reset value: 0x00000000U
1440  *
1441  * The MSB of the read and write pointers is used to distinguish between FIFO
1442  * full and empty conditions. If the read and write pointers are identical, then
1443  * the FIFO is empty. If the read and write pointers are identical except for the
1444  * MSB, then the FIFO is full.
1445  */
1446 typedef union _hw_i2s_tfrn
1447 {
1448     uint32_t U;
1449     struct _hw_i2s_tfrn_bitfields
1450     {
1451         uint32_t RFP : 4;              /*!< [3:0] Read FIFO Pointer */
1452         uint32_t RESERVED0 : 12;       /*!< [15:4]  */
1453         uint32_t WFP : 4;              /*!< [19:16] Write FIFO Pointer */
1454         uint32_t RESERVED1 : 12;       /*!< [31:20]  */
1455     } B;
1456 } hw_i2s_tfrn_t;
1457
1458 /*!
1459  * @name Constants and macros for entire I2S_TFRn register
1460  */
1461 /*@{*/
1462 #define HW_I2S_TFRn_COUNT (1U)
1463
1464 #define HW_I2S_TFRn_ADDR(x, n)   ((x) + 0x40U + (0x4U * (n)))
1465
1466 #define HW_I2S_TFRn(x, n)        (*(__I hw_i2s_tfrn_t *) HW_I2S_TFRn_ADDR(x, n))
1467 #define HW_I2S_TFRn_RD(x, n)     (HW_I2S_TFRn(x, n).U)
1468 /*@}*/
1469
1470 /*
1471  * Constants & macros for individual I2S_TFRn bitfields
1472  */
1473
1474 /*!
1475  * @name Register I2S_TFRn, field RFP[3:0] (RO)
1476  *
1477  * FIFO read pointer for transmit data channel.
1478  */
1479 /*@{*/
1480 #define BP_I2S_TFRn_RFP      (0U)          /*!< Bit position for I2S_TFRn_RFP. */
1481 #define BM_I2S_TFRn_RFP      (0x0000000FU) /*!< Bit mask for I2S_TFRn_RFP. */
1482 #define BS_I2S_TFRn_RFP      (4U)          /*!< Bit field size in bits for I2S_TFRn_RFP. */
1483
1484 /*! @brief Read current value of the I2S_TFRn_RFP field. */
1485 #define BR_I2S_TFRn_RFP(x, n) (HW_I2S_TFRn(x, n).B.RFP)
1486 /*@}*/
1487
1488 /*!
1489  * @name Register I2S_TFRn, field WFP[19:16] (RO)
1490  *
1491  * FIFO write pointer for transmit data channel.
1492  */
1493 /*@{*/
1494 #define BP_I2S_TFRn_WFP      (16U)         /*!< Bit position for I2S_TFRn_WFP. */
1495 #define BM_I2S_TFRn_WFP      (0x000F0000U) /*!< Bit mask for I2S_TFRn_WFP. */
1496 #define BS_I2S_TFRn_WFP      (4U)          /*!< Bit field size in bits for I2S_TFRn_WFP. */
1497
1498 /*! @brief Read current value of the I2S_TFRn_WFP field. */
1499 #define BR_I2S_TFRn_WFP(x, n) (HW_I2S_TFRn(x, n).B.WFP)
1500 /*@}*/
1501
1502 /*******************************************************************************
1503  * HW_I2S_TMR - SAI Transmit Mask Register
1504  ******************************************************************************/
1505
1506 /*!
1507  * @brief HW_I2S_TMR - SAI Transmit Mask Register (RW)
1508  *
1509  * Reset value: 0x00000000U
1510  *
1511  * This register is double-buffered and updates: When TCSR[TE] is first set At
1512  * the end of each frame. This allows the masked words in each frame to change
1513  * from frame to frame.
1514  */
1515 typedef union _hw_i2s_tmr
1516 {
1517     uint32_t U;
1518     struct _hw_i2s_tmr_bitfields
1519     {
1520         uint32_t TWM : 16;             /*!< [15:0] Transmit Word Mask */
1521         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
1522     } B;
1523 } hw_i2s_tmr_t;
1524
1525 /*!
1526  * @name Constants and macros for entire I2S_TMR register
1527  */
1528 /*@{*/
1529 #define HW_I2S_TMR_ADDR(x)       ((x) + 0x60U)
1530
1531 #define HW_I2S_TMR(x)            (*(__IO hw_i2s_tmr_t *) HW_I2S_TMR_ADDR(x))
1532 #define HW_I2S_TMR_RD(x)         (HW_I2S_TMR(x).U)
1533 #define HW_I2S_TMR_WR(x, v)      (HW_I2S_TMR(x).U = (v))
1534 #define HW_I2S_TMR_SET(x, v)     (HW_I2S_TMR_WR(x, HW_I2S_TMR_RD(x) |  (v)))
1535 #define HW_I2S_TMR_CLR(x, v)     (HW_I2S_TMR_WR(x, HW_I2S_TMR_RD(x) & ~(v)))
1536 #define HW_I2S_TMR_TOG(x, v)     (HW_I2S_TMR_WR(x, HW_I2S_TMR_RD(x) ^  (v)))
1537 /*@}*/
1538
1539 /*
1540  * Constants & macros for individual I2S_TMR bitfields
1541  */
1542
1543 /*!
1544  * @name Register I2S_TMR, field TWM[15:0] (RW)
1545  *
1546  * Configures whether the transmit word is masked (transmit data pin tristated
1547  * and transmit data not read from FIFO) for the corresponding word in the frame.
1548  *
1549  * Values:
1550  * - 0 - Word N is enabled.
1551  * - 1 - Word N is masked. The transmit data pins are tri-stated when masked.
1552  */
1553 /*@{*/
1554 #define BP_I2S_TMR_TWM       (0U)          /*!< Bit position for I2S_TMR_TWM. */
1555 #define BM_I2S_TMR_TWM       (0x0000FFFFU) /*!< Bit mask for I2S_TMR_TWM. */
1556 #define BS_I2S_TMR_TWM       (16U)         /*!< Bit field size in bits for I2S_TMR_TWM. */
1557
1558 /*! @brief Read current value of the I2S_TMR_TWM field. */
1559 #define BR_I2S_TMR_TWM(x)    (HW_I2S_TMR(x).B.TWM)
1560
1561 /*! @brief Format value for bitfield I2S_TMR_TWM. */
1562 #define BF_I2S_TMR_TWM(v)    ((uint32_t)((uint32_t)(v) << BP_I2S_TMR_TWM) & BM_I2S_TMR_TWM)
1563
1564 /*! @brief Set the TWM field to a new value. */
1565 #define BW_I2S_TMR_TWM(x, v) (HW_I2S_TMR_WR(x, (HW_I2S_TMR_RD(x) & ~BM_I2S_TMR_TWM) | BF_I2S_TMR_TWM(v)))
1566 /*@}*/
1567
1568 /*******************************************************************************
1569  * HW_I2S_RCSR - SAI Receive Control Register
1570  ******************************************************************************/
1571
1572 /*!
1573  * @brief HW_I2S_RCSR - SAI Receive Control Register (RW)
1574  *
1575  * Reset value: 0x00000000U
1576  */
1577 typedef union _hw_i2s_rcsr
1578 {
1579     uint32_t U;
1580     struct _hw_i2s_rcsr_bitfields
1581     {
1582         uint32_t FRDE : 1;             /*!< [0] FIFO Request DMA Enable */
1583         uint32_t FWDE : 1;             /*!< [1] FIFO Warning DMA Enable */
1584         uint32_t RESERVED0 : 6;        /*!< [7:2]  */
1585         uint32_t FRIE : 1;             /*!< [8] FIFO Request Interrupt Enable */
1586         uint32_t FWIE : 1;             /*!< [9] FIFO Warning Interrupt Enable */
1587         uint32_t FEIE : 1;             /*!< [10] FIFO Error Interrupt Enable */
1588         uint32_t SEIE : 1;             /*!< [11] Sync Error Interrupt Enable */
1589         uint32_t WSIE : 1;             /*!< [12] Word Start Interrupt Enable */
1590         uint32_t RESERVED1 : 3;        /*!< [15:13]  */
1591         uint32_t FRF : 1;              /*!< [16] FIFO Request Flag */
1592         uint32_t FWF : 1;              /*!< [17] FIFO Warning Flag */
1593         uint32_t FEF : 1;              /*!< [18] FIFO Error Flag */
1594         uint32_t SEF : 1;              /*!< [19] Sync Error Flag */
1595         uint32_t WSF : 1;              /*!< [20] Word Start Flag */
1596         uint32_t RESERVED2 : 3;        /*!< [23:21]  */
1597         uint32_t SR : 1;               /*!< [24] Software Reset */
1598         uint32_t FR : 1;               /*!< [25] FIFO Reset */
1599         uint32_t RESERVED3 : 2;        /*!< [27:26]  */
1600         uint32_t BCE : 1;              /*!< [28] Bit Clock Enable */
1601         uint32_t DBGE : 1;             /*!< [29] Debug Enable */
1602         uint32_t STOPE : 1;            /*!< [30] Stop Enable */
1603         uint32_t RE : 1;               /*!< [31] Receiver Enable */
1604     } B;
1605 } hw_i2s_rcsr_t;
1606
1607 /*!
1608  * @name Constants and macros for entire I2S_RCSR register
1609  */
1610 /*@{*/
1611 #define HW_I2S_RCSR_ADDR(x)      ((x) + 0x80U)
1612
1613 #define HW_I2S_RCSR(x)           (*(__IO hw_i2s_rcsr_t *) HW_I2S_RCSR_ADDR(x))
1614 #define HW_I2S_RCSR_RD(x)        (HW_I2S_RCSR(x).U)
1615 #define HW_I2S_RCSR_WR(x, v)     (HW_I2S_RCSR(x).U = (v))
1616 #define HW_I2S_RCSR_SET(x, v)    (HW_I2S_RCSR_WR(x, HW_I2S_RCSR_RD(x) |  (v)))
1617 #define HW_I2S_RCSR_CLR(x, v)    (HW_I2S_RCSR_WR(x, HW_I2S_RCSR_RD(x) & ~(v)))
1618 #define HW_I2S_RCSR_TOG(x, v)    (HW_I2S_RCSR_WR(x, HW_I2S_RCSR_RD(x) ^  (v)))
1619 /*@}*/
1620
1621 /*
1622  * Constants & macros for individual I2S_RCSR bitfields
1623  */
1624
1625 /*!
1626  * @name Register I2S_RCSR, field FRDE[0] (RW)
1627  *
1628  * Enables/disables DMA requests.
1629  *
1630  * Values:
1631  * - 0 - Disables the DMA request.
1632  * - 1 - Enables the DMA request.
1633  */
1634 /*@{*/
1635 #define BP_I2S_RCSR_FRDE     (0U)          /*!< Bit position for I2S_RCSR_FRDE. */
1636 #define BM_I2S_RCSR_FRDE     (0x00000001U) /*!< Bit mask for I2S_RCSR_FRDE. */
1637 #define BS_I2S_RCSR_FRDE     (1U)          /*!< Bit field size in bits for I2S_RCSR_FRDE. */
1638
1639 /*! @brief Read current value of the I2S_RCSR_FRDE field. */
1640 #define BR_I2S_RCSR_FRDE(x)  (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRDE))
1641
1642 /*! @brief Format value for bitfield I2S_RCSR_FRDE. */
1643 #define BF_I2S_RCSR_FRDE(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FRDE) & BM_I2S_RCSR_FRDE)
1644
1645 /*! @brief Set the FRDE field to a new value. */
1646 #define BW_I2S_RCSR_FRDE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRDE) = (v))
1647 /*@}*/
1648
1649 /*!
1650  * @name Register I2S_RCSR, field FWDE[1] (RW)
1651  *
1652  * Enables/disables DMA requests.
1653  *
1654  * Values:
1655  * - 0 - Disables the DMA request.
1656  * - 1 - Enables the DMA request.
1657  */
1658 /*@{*/
1659 #define BP_I2S_RCSR_FWDE     (1U)          /*!< Bit position for I2S_RCSR_FWDE. */
1660 #define BM_I2S_RCSR_FWDE     (0x00000002U) /*!< Bit mask for I2S_RCSR_FWDE. */
1661 #define BS_I2S_RCSR_FWDE     (1U)          /*!< Bit field size in bits for I2S_RCSR_FWDE. */
1662
1663 /*! @brief Read current value of the I2S_RCSR_FWDE field. */
1664 #define BR_I2S_RCSR_FWDE(x)  (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWDE))
1665
1666 /*! @brief Format value for bitfield I2S_RCSR_FWDE. */
1667 #define BF_I2S_RCSR_FWDE(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FWDE) & BM_I2S_RCSR_FWDE)
1668
1669 /*! @brief Set the FWDE field to a new value. */
1670 #define BW_I2S_RCSR_FWDE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWDE) = (v))
1671 /*@}*/
1672
1673 /*!
1674  * @name Register I2S_RCSR, field FRIE[8] (RW)
1675  *
1676  * Enables/disables FIFO request interrupts.
1677  *
1678  * Values:
1679  * - 0 - Disables the interrupt.
1680  * - 1 - Enables the interrupt.
1681  */
1682 /*@{*/
1683 #define BP_I2S_RCSR_FRIE     (8U)          /*!< Bit position for I2S_RCSR_FRIE. */
1684 #define BM_I2S_RCSR_FRIE     (0x00000100U) /*!< Bit mask for I2S_RCSR_FRIE. */
1685 #define BS_I2S_RCSR_FRIE     (1U)          /*!< Bit field size in bits for I2S_RCSR_FRIE. */
1686
1687 /*! @brief Read current value of the I2S_RCSR_FRIE field. */
1688 #define BR_I2S_RCSR_FRIE(x)  (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRIE))
1689
1690 /*! @brief Format value for bitfield I2S_RCSR_FRIE. */
1691 #define BF_I2S_RCSR_FRIE(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FRIE) & BM_I2S_RCSR_FRIE)
1692
1693 /*! @brief Set the FRIE field to a new value. */
1694 #define BW_I2S_RCSR_FRIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRIE) = (v))
1695 /*@}*/
1696
1697 /*!
1698  * @name Register I2S_RCSR, field FWIE[9] (RW)
1699  *
1700  * Enables/disables FIFO warning interrupts.
1701  *
1702  * Values:
1703  * - 0 - Disables the interrupt.
1704  * - 1 - Enables the interrupt.
1705  */
1706 /*@{*/
1707 #define BP_I2S_RCSR_FWIE     (9U)          /*!< Bit position for I2S_RCSR_FWIE. */
1708 #define BM_I2S_RCSR_FWIE     (0x00000200U) /*!< Bit mask for I2S_RCSR_FWIE. */
1709 #define BS_I2S_RCSR_FWIE     (1U)          /*!< Bit field size in bits for I2S_RCSR_FWIE. */
1710
1711 /*! @brief Read current value of the I2S_RCSR_FWIE field. */
1712 #define BR_I2S_RCSR_FWIE(x)  (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWIE))
1713
1714 /*! @brief Format value for bitfield I2S_RCSR_FWIE. */
1715 #define BF_I2S_RCSR_FWIE(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FWIE) & BM_I2S_RCSR_FWIE)
1716
1717 /*! @brief Set the FWIE field to a new value. */
1718 #define BW_I2S_RCSR_FWIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWIE) = (v))
1719 /*@}*/
1720
1721 /*!
1722  * @name Register I2S_RCSR, field FEIE[10] (RW)
1723  *
1724  * Enables/disables FIFO error interrupts.
1725  *
1726  * Values:
1727  * - 0 - Disables the interrupt.
1728  * - 1 - Enables the interrupt.
1729  */
1730 /*@{*/
1731 #define BP_I2S_RCSR_FEIE     (10U)         /*!< Bit position for I2S_RCSR_FEIE. */
1732 #define BM_I2S_RCSR_FEIE     (0x00000400U) /*!< Bit mask for I2S_RCSR_FEIE. */
1733 #define BS_I2S_RCSR_FEIE     (1U)          /*!< Bit field size in bits for I2S_RCSR_FEIE. */
1734
1735 /*! @brief Read current value of the I2S_RCSR_FEIE field. */
1736 #define BR_I2S_RCSR_FEIE(x)  (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FEIE))
1737
1738 /*! @brief Format value for bitfield I2S_RCSR_FEIE. */
1739 #define BF_I2S_RCSR_FEIE(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FEIE) & BM_I2S_RCSR_FEIE)
1740
1741 /*! @brief Set the FEIE field to a new value. */
1742 #define BW_I2S_RCSR_FEIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FEIE) = (v))
1743 /*@}*/
1744
1745 /*!
1746  * @name Register I2S_RCSR, field SEIE[11] (RW)
1747  *
1748  * Enables/disables sync error interrupts.
1749  *
1750  * Values:
1751  * - 0 - Disables interrupt.
1752  * - 1 - Enables interrupt.
1753  */
1754 /*@{*/
1755 #define BP_I2S_RCSR_SEIE     (11U)         /*!< Bit position for I2S_RCSR_SEIE. */
1756 #define BM_I2S_RCSR_SEIE     (0x00000800U) /*!< Bit mask for I2S_RCSR_SEIE. */
1757 #define BS_I2S_RCSR_SEIE     (1U)          /*!< Bit field size in bits for I2S_RCSR_SEIE. */
1758
1759 /*! @brief Read current value of the I2S_RCSR_SEIE field. */
1760 #define BR_I2S_RCSR_SEIE(x)  (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SEIE))
1761
1762 /*! @brief Format value for bitfield I2S_RCSR_SEIE. */
1763 #define BF_I2S_RCSR_SEIE(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_SEIE) & BM_I2S_RCSR_SEIE)
1764
1765 /*! @brief Set the SEIE field to a new value. */
1766 #define BW_I2S_RCSR_SEIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SEIE) = (v))
1767 /*@}*/
1768
1769 /*!
1770  * @name Register I2S_RCSR, field WSIE[12] (RW)
1771  *
1772  * Enables/disables word start interrupts.
1773  *
1774  * Values:
1775  * - 0 - Disables interrupt.
1776  * - 1 - Enables interrupt.
1777  */
1778 /*@{*/
1779 #define BP_I2S_RCSR_WSIE     (12U)         /*!< Bit position for I2S_RCSR_WSIE. */
1780 #define BM_I2S_RCSR_WSIE     (0x00001000U) /*!< Bit mask for I2S_RCSR_WSIE. */
1781 #define BS_I2S_RCSR_WSIE     (1U)          /*!< Bit field size in bits for I2S_RCSR_WSIE. */
1782
1783 /*! @brief Read current value of the I2S_RCSR_WSIE field. */
1784 #define BR_I2S_RCSR_WSIE(x)  (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_WSIE))
1785
1786 /*! @brief Format value for bitfield I2S_RCSR_WSIE. */
1787 #define BF_I2S_RCSR_WSIE(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_WSIE) & BM_I2S_RCSR_WSIE)
1788
1789 /*! @brief Set the WSIE field to a new value. */
1790 #define BW_I2S_RCSR_WSIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_WSIE) = (v))
1791 /*@}*/
1792
1793 /*!
1794  * @name Register I2S_RCSR, field FRF[16] (RO)
1795  *
1796  * Indicates that the number of words in an enabled receive channel FIFO is
1797  * greater than the receive FIFO watermark.
1798  *
1799  * Values:
1800  * - 0 - Receive FIFO watermark not reached.
1801  * - 1 - Receive FIFO watermark has been reached.
1802  */
1803 /*@{*/
1804 #define BP_I2S_RCSR_FRF      (16U)         /*!< Bit position for I2S_RCSR_FRF. */
1805 #define BM_I2S_RCSR_FRF      (0x00010000U) /*!< Bit mask for I2S_RCSR_FRF. */
1806 #define BS_I2S_RCSR_FRF      (1U)          /*!< Bit field size in bits for I2S_RCSR_FRF. */
1807
1808 /*! @brief Read current value of the I2S_RCSR_FRF field. */
1809 #define BR_I2S_RCSR_FRF(x)   (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRF))
1810 /*@}*/
1811
1812 /*!
1813  * @name Register I2S_RCSR, field FWF[17] (RO)
1814  *
1815  * Indicates that an enabled receive FIFO is full.
1816  *
1817  * Values:
1818  * - 0 - No enabled receive FIFO is full.
1819  * - 1 - Enabled receive FIFO is full.
1820  */
1821 /*@{*/
1822 #define BP_I2S_RCSR_FWF      (17U)         /*!< Bit position for I2S_RCSR_FWF. */
1823 #define BM_I2S_RCSR_FWF      (0x00020000U) /*!< Bit mask for I2S_RCSR_FWF. */
1824 #define BS_I2S_RCSR_FWF      (1U)          /*!< Bit field size in bits for I2S_RCSR_FWF. */
1825
1826 /*! @brief Read current value of the I2S_RCSR_FWF field. */
1827 #define BR_I2S_RCSR_FWF(x)   (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWF))
1828 /*@}*/
1829
1830 /*!
1831  * @name Register I2S_RCSR, field FEF[18] (W1C)
1832  *
1833  * Indicates that an enabled receive FIFO has overflowed. Write a logic 1 to
1834  * this field to clear this flag.
1835  *
1836  * Values:
1837  * - 0 - Receive overflow not detected.
1838  * - 1 - Receive overflow detected.
1839  */
1840 /*@{*/
1841 #define BP_I2S_RCSR_FEF      (18U)         /*!< Bit position for I2S_RCSR_FEF. */
1842 #define BM_I2S_RCSR_FEF      (0x00040000U) /*!< Bit mask for I2S_RCSR_FEF. */
1843 #define BS_I2S_RCSR_FEF      (1U)          /*!< Bit field size in bits for I2S_RCSR_FEF. */
1844
1845 /*! @brief Read current value of the I2S_RCSR_FEF field. */
1846 #define BR_I2S_RCSR_FEF(x)   (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FEF))
1847
1848 /*! @brief Format value for bitfield I2S_RCSR_FEF. */
1849 #define BF_I2S_RCSR_FEF(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FEF) & BM_I2S_RCSR_FEF)
1850
1851 /*! @brief Set the FEF field to a new value. */
1852 #define BW_I2S_RCSR_FEF(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FEF) = (v))
1853 /*@}*/
1854
1855 /*!
1856  * @name Register I2S_RCSR, field SEF[19] (W1C)
1857  *
1858  * Indicates that an error in the externally-generated frame sync has been
1859  * detected. Write a logic 1 to this field to clear this flag.
1860  *
1861  * Values:
1862  * - 0 - Sync error not detected.
1863  * - 1 - Frame sync error detected.
1864  */
1865 /*@{*/
1866 #define BP_I2S_RCSR_SEF      (19U)         /*!< Bit position for I2S_RCSR_SEF. */
1867 #define BM_I2S_RCSR_SEF      (0x00080000U) /*!< Bit mask for I2S_RCSR_SEF. */
1868 #define BS_I2S_RCSR_SEF      (1U)          /*!< Bit field size in bits for I2S_RCSR_SEF. */
1869
1870 /*! @brief Read current value of the I2S_RCSR_SEF field. */
1871 #define BR_I2S_RCSR_SEF(x)   (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SEF))
1872
1873 /*! @brief Format value for bitfield I2S_RCSR_SEF. */
1874 #define BF_I2S_RCSR_SEF(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_SEF) & BM_I2S_RCSR_SEF)
1875
1876 /*! @brief Set the SEF field to a new value. */
1877 #define BW_I2S_RCSR_SEF(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SEF) = (v))
1878 /*@}*/
1879
1880 /*!
1881  * @name Register I2S_RCSR, field WSF[20] (W1C)
1882  *
1883  * Indicates that the start of the configured word has been detected. Write a
1884  * logic 1 to this field to clear this flag.
1885  *
1886  * Values:
1887  * - 0 - Start of word not detected.
1888  * - 1 - Start of word detected.
1889  */
1890 /*@{*/
1891 #define BP_I2S_RCSR_WSF      (20U)         /*!< Bit position for I2S_RCSR_WSF. */
1892 #define BM_I2S_RCSR_WSF      (0x00100000U) /*!< Bit mask for I2S_RCSR_WSF. */
1893 #define BS_I2S_RCSR_WSF      (1U)          /*!< Bit field size in bits for I2S_RCSR_WSF. */
1894
1895 /*! @brief Read current value of the I2S_RCSR_WSF field. */
1896 #define BR_I2S_RCSR_WSF(x)   (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_WSF))
1897
1898 /*! @brief Format value for bitfield I2S_RCSR_WSF. */
1899 #define BF_I2S_RCSR_WSF(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_WSF) & BM_I2S_RCSR_WSF)
1900
1901 /*! @brief Set the WSF field to a new value. */
1902 #define BW_I2S_RCSR_WSF(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_WSF) = (v))
1903 /*@}*/
1904
1905 /*!
1906  * @name Register I2S_RCSR, field SR[24] (RW)
1907  *
1908  * Resets the internal receiver logic including the FIFO pointers.
1909  * Software-visible registers are not affected, except for the status registers.
1910  *
1911  * Values:
1912  * - 0 - No effect.
1913  * - 1 - Software reset.
1914  */
1915 /*@{*/
1916 #define BP_I2S_RCSR_SR       (24U)         /*!< Bit position for I2S_RCSR_SR. */
1917 #define BM_I2S_RCSR_SR       (0x01000000U) /*!< Bit mask for I2S_RCSR_SR. */
1918 #define BS_I2S_RCSR_SR       (1U)          /*!< Bit field size in bits for I2S_RCSR_SR. */
1919
1920 /*! @brief Read current value of the I2S_RCSR_SR field. */
1921 #define BR_I2S_RCSR_SR(x)    (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SR))
1922
1923 /*! @brief Format value for bitfield I2S_RCSR_SR. */
1924 #define BF_I2S_RCSR_SR(v)    ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_SR) & BM_I2S_RCSR_SR)
1925
1926 /*! @brief Set the SR field to a new value. */
1927 #define BW_I2S_RCSR_SR(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SR) = (v))
1928 /*@}*/
1929
1930 /*!
1931  * @name Register I2S_RCSR, field FR[25] (WORZ)
1932  *
1933  * Resets the FIFO pointers. Reading this field will always return zero. FIFO
1934  * pointers should only be reset when the receiver is disabled or the FIFO error
1935  * flag is set.
1936  *
1937  * Values:
1938  * - 0 - No effect.
1939  * - 1 - FIFO reset.
1940  */
1941 /*@{*/
1942 #define BP_I2S_RCSR_FR       (25U)         /*!< Bit position for I2S_RCSR_FR. */
1943 #define BM_I2S_RCSR_FR       (0x02000000U) /*!< Bit mask for I2S_RCSR_FR. */
1944 #define BS_I2S_RCSR_FR       (1U)          /*!< Bit field size in bits for I2S_RCSR_FR. */
1945
1946 /*! @brief Format value for bitfield I2S_RCSR_FR. */
1947 #define BF_I2S_RCSR_FR(v)    ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FR) & BM_I2S_RCSR_FR)
1948
1949 /*! @brief Set the FR field to a new value. */
1950 #define BW_I2S_RCSR_FR(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FR) = (v))
1951 /*@}*/
1952
1953 /*!
1954  * @name Register I2S_RCSR, field BCE[28] (RW)
1955  *
1956  * Enables the receive bit clock, separately from RE. This field is
1957  * automatically set whenever RE is set. When software clears this field, the receive bit
1958  * clock remains enabled, and this field remains set, until the end of the current
1959  * frame.
1960  *
1961  * Values:
1962  * - 0 - Receive bit clock is disabled.
1963  * - 1 - Receive bit clock is enabled.
1964  */
1965 /*@{*/
1966 #define BP_I2S_RCSR_BCE      (28U)         /*!< Bit position for I2S_RCSR_BCE. */
1967 #define BM_I2S_RCSR_BCE      (0x10000000U) /*!< Bit mask for I2S_RCSR_BCE. */
1968 #define BS_I2S_RCSR_BCE      (1U)          /*!< Bit field size in bits for I2S_RCSR_BCE. */
1969
1970 /*! @brief Read current value of the I2S_RCSR_BCE field. */
1971 #define BR_I2S_RCSR_BCE(x)   (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_BCE))
1972
1973 /*! @brief Format value for bitfield I2S_RCSR_BCE. */
1974 #define BF_I2S_RCSR_BCE(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_BCE) & BM_I2S_RCSR_BCE)
1975
1976 /*! @brief Set the BCE field to a new value. */
1977 #define BW_I2S_RCSR_BCE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_BCE) = (v))
1978 /*@}*/
1979
1980 /*!
1981  * @name Register I2S_RCSR, field DBGE[29] (RW)
1982  *
1983  * Enables/disables receiver operation in Debug mode. The receive bit clock is
1984  * not affected by Debug mode.
1985  *
1986  * Values:
1987  * - 0 - Receiver is disabled in Debug mode, after completing the current frame.
1988  * - 1 - Receiver is enabled in Debug mode.
1989  */
1990 /*@{*/
1991 #define BP_I2S_RCSR_DBGE     (29U)         /*!< Bit position for I2S_RCSR_DBGE. */
1992 #define BM_I2S_RCSR_DBGE     (0x20000000U) /*!< Bit mask for I2S_RCSR_DBGE. */
1993 #define BS_I2S_RCSR_DBGE     (1U)          /*!< Bit field size in bits for I2S_RCSR_DBGE. */
1994
1995 /*! @brief Read current value of the I2S_RCSR_DBGE field. */
1996 #define BR_I2S_RCSR_DBGE(x)  (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_DBGE))
1997
1998 /*! @brief Format value for bitfield I2S_RCSR_DBGE. */
1999 #define BF_I2S_RCSR_DBGE(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_DBGE) & BM_I2S_RCSR_DBGE)
2000
2001 /*! @brief Set the DBGE field to a new value. */
2002 #define BW_I2S_RCSR_DBGE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_DBGE) = (v))
2003 /*@}*/
2004
2005 /*!
2006  * @name Register I2S_RCSR, field STOPE[30] (RW)
2007  *
2008  * Configures receiver operation in Stop mode. This bit is ignored and the
2009  * receiver is disabled in all low-leakage stop modes.
2010  *
2011  * Values:
2012  * - 0 - Receiver disabled in Stop mode.
2013  * - 1 - Receiver enabled in Stop mode.
2014  */
2015 /*@{*/
2016 #define BP_I2S_RCSR_STOPE    (30U)         /*!< Bit position for I2S_RCSR_STOPE. */
2017 #define BM_I2S_RCSR_STOPE    (0x40000000U) /*!< Bit mask for I2S_RCSR_STOPE. */
2018 #define BS_I2S_RCSR_STOPE    (1U)          /*!< Bit field size in bits for I2S_RCSR_STOPE. */
2019
2020 /*! @brief Read current value of the I2S_RCSR_STOPE field. */
2021 #define BR_I2S_RCSR_STOPE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_STOPE))
2022
2023 /*! @brief Format value for bitfield I2S_RCSR_STOPE. */
2024 #define BF_I2S_RCSR_STOPE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_STOPE) & BM_I2S_RCSR_STOPE)
2025
2026 /*! @brief Set the STOPE field to a new value. */
2027 #define BW_I2S_RCSR_STOPE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_STOPE) = (v))
2028 /*@}*/
2029
2030 /*!
2031  * @name Register I2S_RCSR, field RE[31] (RW)
2032  *
2033  * Enables/disables the receiver. When software clears this field, the receiver
2034  * remains enabled, and this bit remains set, until the end of the current frame.
2035  *
2036  * Values:
2037  * - 0 - Receiver is disabled.
2038  * - 1 - Receiver is enabled, or receiver has been disabled and has not yet
2039  *     reached end of frame.
2040  */
2041 /*@{*/
2042 #define BP_I2S_RCSR_RE       (31U)         /*!< Bit position for I2S_RCSR_RE. */
2043 #define BM_I2S_RCSR_RE       (0x80000000U) /*!< Bit mask for I2S_RCSR_RE. */
2044 #define BS_I2S_RCSR_RE       (1U)          /*!< Bit field size in bits for I2S_RCSR_RE. */
2045
2046 /*! @brief Read current value of the I2S_RCSR_RE field. */
2047 #define BR_I2S_RCSR_RE(x)    (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_RE))
2048
2049 /*! @brief Format value for bitfield I2S_RCSR_RE. */
2050 #define BF_I2S_RCSR_RE(v)    ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_RE) & BM_I2S_RCSR_RE)
2051
2052 /*! @brief Set the RE field to a new value. */
2053 #define BW_I2S_RCSR_RE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_RE) = (v))
2054 /*@}*/
2055
2056 /*******************************************************************************
2057  * HW_I2S_RCR1 - SAI Receive Configuration 1 Register
2058  ******************************************************************************/
2059
2060 /*!
2061  * @brief HW_I2S_RCR1 - SAI Receive Configuration 1 Register (RW)
2062  *
2063  * Reset value: 0x00000000U
2064  */
2065 typedef union _hw_i2s_rcr1
2066 {
2067     uint32_t U;
2068     struct _hw_i2s_rcr1_bitfields
2069     {
2070         uint32_t RFW : 3;              /*!< [2:0] Receive FIFO Watermark */
2071         uint32_t RESERVED0 : 29;       /*!< [31:3]  */
2072     } B;
2073 } hw_i2s_rcr1_t;
2074
2075 /*!
2076  * @name Constants and macros for entire I2S_RCR1 register
2077  */
2078 /*@{*/
2079 #define HW_I2S_RCR1_ADDR(x)      ((x) + 0x84U)
2080
2081 #define HW_I2S_RCR1(x)           (*(__IO hw_i2s_rcr1_t *) HW_I2S_RCR1_ADDR(x))
2082 #define HW_I2S_RCR1_RD(x)        (HW_I2S_RCR1(x).U)
2083 #define HW_I2S_RCR1_WR(x, v)     (HW_I2S_RCR1(x).U = (v))
2084 #define HW_I2S_RCR1_SET(x, v)    (HW_I2S_RCR1_WR(x, HW_I2S_RCR1_RD(x) |  (v)))
2085 #define HW_I2S_RCR1_CLR(x, v)    (HW_I2S_RCR1_WR(x, HW_I2S_RCR1_RD(x) & ~(v)))
2086 #define HW_I2S_RCR1_TOG(x, v)    (HW_I2S_RCR1_WR(x, HW_I2S_RCR1_RD(x) ^  (v)))
2087 /*@}*/
2088
2089 /*
2090  * Constants & macros for individual I2S_RCR1 bitfields
2091  */
2092
2093 /*!
2094  * @name Register I2S_RCR1, field RFW[2:0] (RW)
2095  *
2096  * Configures the watermark level for all enabled receiver channels.
2097  */
2098 /*@{*/
2099 #define BP_I2S_RCR1_RFW      (0U)          /*!< Bit position for I2S_RCR1_RFW. */
2100 #define BM_I2S_RCR1_RFW      (0x00000007U) /*!< Bit mask for I2S_RCR1_RFW. */
2101 #define BS_I2S_RCR1_RFW      (3U)          /*!< Bit field size in bits for I2S_RCR1_RFW. */
2102
2103 /*! @brief Read current value of the I2S_RCR1_RFW field. */
2104 #define BR_I2S_RCR1_RFW(x)   (HW_I2S_RCR1(x).B.RFW)
2105
2106 /*! @brief Format value for bitfield I2S_RCR1_RFW. */
2107 #define BF_I2S_RCR1_RFW(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_RCR1_RFW) & BM_I2S_RCR1_RFW)
2108
2109 /*! @brief Set the RFW field to a new value. */
2110 #define BW_I2S_RCR1_RFW(x, v) (HW_I2S_RCR1_WR(x, (HW_I2S_RCR1_RD(x) & ~BM_I2S_RCR1_RFW) | BF_I2S_RCR1_RFW(v)))
2111 /*@}*/
2112
2113 /*******************************************************************************
2114  * HW_I2S_RCR2 - SAI Receive Configuration 2 Register
2115  ******************************************************************************/
2116
2117 /*!
2118  * @brief HW_I2S_RCR2 - SAI Receive Configuration 2 Register (RW)
2119  *
2120  * Reset value: 0x00000000U
2121  *
2122  * This register must not be altered when RCSR[RE] is set.
2123  */
2124 typedef union _hw_i2s_rcr2
2125 {
2126     uint32_t U;
2127     struct _hw_i2s_rcr2_bitfields
2128     {
2129         uint32_t DIV : 8;              /*!< [7:0] Bit Clock Divide */
2130         uint32_t RESERVED0 : 16;       /*!< [23:8]  */
2131         uint32_t BCD : 1;              /*!< [24] Bit Clock Direction */
2132         uint32_t BCP : 1;              /*!< [25] Bit Clock Polarity */
2133         uint32_t MSEL : 2;             /*!< [27:26] MCLK Select */
2134         uint32_t BCI : 1;              /*!< [28] Bit Clock Input */
2135         uint32_t BCS : 1;              /*!< [29] Bit Clock Swap */
2136         uint32_t SYNC : 2;             /*!< [31:30] Synchronous Mode */
2137     } B;
2138 } hw_i2s_rcr2_t;
2139
2140 /*!
2141  * @name Constants and macros for entire I2S_RCR2 register
2142  */
2143 /*@{*/
2144 #define HW_I2S_RCR2_ADDR(x)      ((x) + 0x88U)
2145
2146 #define HW_I2S_RCR2(x)           (*(__IO hw_i2s_rcr2_t *) HW_I2S_RCR2_ADDR(x))
2147 #define HW_I2S_RCR2_RD(x)        (HW_I2S_RCR2(x).U)
2148 #define HW_I2S_RCR2_WR(x, v)     (HW_I2S_RCR2(x).U = (v))
2149 #define HW_I2S_RCR2_SET(x, v)    (HW_I2S_RCR2_WR(x, HW_I2S_RCR2_RD(x) |  (v)))
2150 #define HW_I2S_RCR2_CLR(x, v)    (HW_I2S_RCR2_WR(x, HW_I2S_RCR2_RD(x) & ~(v)))
2151 #define HW_I2S_RCR2_TOG(x, v)    (HW_I2S_RCR2_WR(x, HW_I2S_RCR2_RD(x) ^  (v)))
2152 /*@}*/
2153
2154 /*
2155  * Constants & macros for individual I2S_RCR2 bitfields
2156  */
2157
2158 /*!
2159  * @name Register I2S_RCR2, field DIV[7:0] (RW)
2160  *
2161  * Divides down the audio master clock to generate the bit clock when configured
2162  * for an internal bit clock. The division value is (DIV + 1) * 2.
2163  */
2164 /*@{*/
2165 #define BP_I2S_RCR2_DIV      (0U)          /*!< Bit position for I2S_RCR2_DIV. */
2166 #define BM_I2S_RCR2_DIV      (0x000000FFU) /*!< Bit mask for I2S_RCR2_DIV. */
2167 #define BS_I2S_RCR2_DIV      (8U)          /*!< Bit field size in bits for I2S_RCR2_DIV. */
2168
2169 /*! @brief Read current value of the I2S_RCR2_DIV field. */
2170 #define BR_I2S_RCR2_DIV(x)   (HW_I2S_RCR2(x).B.DIV)
2171
2172 /*! @brief Format value for bitfield I2S_RCR2_DIV. */
2173 #define BF_I2S_RCR2_DIV(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_DIV) & BM_I2S_RCR2_DIV)
2174
2175 /*! @brief Set the DIV field to a new value. */
2176 #define BW_I2S_RCR2_DIV(x, v) (HW_I2S_RCR2_WR(x, (HW_I2S_RCR2_RD(x) & ~BM_I2S_RCR2_DIV) | BF_I2S_RCR2_DIV(v)))
2177 /*@}*/
2178
2179 /*!
2180  * @name Register I2S_RCR2, field BCD[24] (RW)
2181  *
2182  * Configures the direction of the bit clock.
2183  *
2184  * Values:
2185  * - 0 - Bit clock is generated externally in Slave mode.
2186  * - 1 - Bit clock is generated internally in Master mode.
2187  */
2188 /*@{*/
2189 #define BP_I2S_RCR2_BCD      (24U)         /*!< Bit position for I2S_RCR2_BCD. */
2190 #define BM_I2S_RCR2_BCD      (0x01000000U) /*!< Bit mask for I2S_RCR2_BCD. */
2191 #define BS_I2S_RCR2_BCD      (1U)          /*!< Bit field size in bits for I2S_RCR2_BCD. */
2192
2193 /*! @brief Read current value of the I2S_RCR2_BCD field. */
2194 #define BR_I2S_RCR2_BCD(x)   (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCD))
2195
2196 /*! @brief Format value for bitfield I2S_RCR2_BCD. */
2197 #define BF_I2S_RCR2_BCD(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_BCD) & BM_I2S_RCR2_BCD)
2198
2199 /*! @brief Set the BCD field to a new value. */
2200 #define BW_I2S_RCR2_BCD(x, v) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCD) = (v))
2201 /*@}*/
2202
2203 /*!
2204  * @name Register I2S_RCR2, field BCP[25] (RW)
2205  *
2206  * Configures the polarity of the bit clock.
2207  *
2208  * Values:
2209  * - 0 - Bit Clock is active high with drive outputs on rising edge and sample
2210  *     inputs on falling edge.
2211  * - 1 - Bit Clock is active low with drive outputs on falling edge and sample
2212  *     inputs on rising edge.
2213  */
2214 /*@{*/
2215 #define BP_I2S_RCR2_BCP      (25U)         /*!< Bit position for I2S_RCR2_BCP. */
2216 #define BM_I2S_RCR2_BCP      (0x02000000U) /*!< Bit mask for I2S_RCR2_BCP. */
2217 #define BS_I2S_RCR2_BCP      (1U)          /*!< Bit field size in bits for I2S_RCR2_BCP. */
2218
2219 /*! @brief Read current value of the I2S_RCR2_BCP field. */
2220 #define BR_I2S_RCR2_BCP(x)   (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCP))
2221
2222 /*! @brief Format value for bitfield I2S_RCR2_BCP. */
2223 #define BF_I2S_RCR2_BCP(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_BCP) & BM_I2S_RCR2_BCP)
2224
2225 /*! @brief Set the BCP field to a new value. */
2226 #define BW_I2S_RCR2_BCP(x, v) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCP) = (v))
2227 /*@}*/
2228
2229 /*!
2230  * @name Register I2S_RCR2, field MSEL[27:26] (RW)
2231  *
2232  * Selects the audio Master Clock option used to generate an internally
2233  * generated bit clock. This field has no effect when configured for an externally
2234  * generated bit clock. Depending on the device, some Master Clock options might not be
2235  * available. See the chip configuration details for the availability and
2236  * chip-specific meaning of each option.
2237  *
2238  * Values:
2239  * - 00 - Bus Clock selected.
2240  * - 01 - Master Clock (MCLK) 1 option selected.
2241  * - 10 - Master Clock (MCLK) 2 option selected.
2242  * - 11 - Master Clock (MCLK) 3 option selected.
2243  */
2244 /*@{*/
2245 #define BP_I2S_RCR2_MSEL     (26U)         /*!< Bit position for I2S_RCR2_MSEL. */
2246 #define BM_I2S_RCR2_MSEL     (0x0C000000U) /*!< Bit mask for I2S_RCR2_MSEL. */
2247 #define BS_I2S_RCR2_MSEL     (2U)          /*!< Bit field size in bits for I2S_RCR2_MSEL. */
2248
2249 /*! @brief Read current value of the I2S_RCR2_MSEL field. */
2250 #define BR_I2S_RCR2_MSEL(x)  (HW_I2S_RCR2(x).B.MSEL)
2251
2252 /*! @brief Format value for bitfield I2S_RCR2_MSEL. */
2253 #define BF_I2S_RCR2_MSEL(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_MSEL) & BM_I2S_RCR2_MSEL)
2254
2255 /*! @brief Set the MSEL field to a new value. */
2256 #define BW_I2S_RCR2_MSEL(x, v) (HW_I2S_RCR2_WR(x, (HW_I2S_RCR2_RD(x) & ~BM_I2S_RCR2_MSEL) | BF_I2S_RCR2_MSEL(v)))
2257 /*@}*/
2258
2259 /*!
2260  * @name Register I2S_RCR2, field BCI[28] (RW)
2261  *
2262  * When this field is set and using an internally generated bit clock in either
2263  * synchronous or asynchronous mode, the bit clock actually used by the receiver
2264  * is delayed by the pad output delay (the receiver is clocked by the pad input
2265  * as if the clock was externally generated). This has the effect of decreasing
2266  * the data input setup time, but increasing the data output valid time. The slave
2267  * mode timing from the datasheet should be used for the receiver when this bit
2268  * is set. In synchronous mode, this bit allows the receiver to use the slave mode
2269  * timing from the datasheet, while the transmitter uses the master mode timing.
2270  * This field has no effect when configured for an externally generated bit
2271  * clock .
2272  *
2273  * Values:
2274  * - 0 - No effect.
2275  * - 1 - Internal logic is clocked as if bit clock was externally generated.
2276  */
2277 /*@{*/
2278 #define BP_I2S_RCR2_BCI      (28U)         /*!< Bit position for I2S_RCR2_BCI. */
2279 #define BM_I2S_RCR2_BCI      (0x10000000U) /*!< Bit mask for I2S_RCR2_BCI. */
2280 #define BS_I2S_RCR2_BCI      (1U)          /*!< Bit field size in bits for I2S_RCR2_BCI. */
2281
2282 /*! @brief Read current value of the I2S_RCR2_BCI field. */
2283 #define BR_I2S_RCR2_BCI(x)   (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCI))
2284
2285 /*! @brief Format value for bitfield I2S_RCR2_BCI. */
2286 #define BF_I2S_RCR2_BCI(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_BCI) & BM_I2S_RCR2_BCI)
2287
2288 /*! @brief Set the BCI field to a new value. */
2289 #define BW_I2S_RCR2_BCI(x, v) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCI) = (v))
2290 /*@}*/
2291
2292 /*!
2293  * @name Register I2S_RCR2, field BCS[29] (RW)
2294  *
2295  * This field swaps the bit clock used by the receiver. When the receiver is
2296  * configured in asynchronous mode and this bit is set, the receiver is clocked by
2297  * the transmitter bit clock (SAI_TX_BCLK). This allows the transmitter and
2298  * receiver to share the same bit clock, but the receiver continues to use the receiver
2299  * frame sync (SAI_RX_SYNC). When the receiver is configured in synchronous
2300  * mode, the transmitter BCS field and receiver BCS field must be set to the same
2301  * value. When both are set, the transmitter and receiver are both clocked by the
2302  * receiver bit clock (SAI_RX_BCLK) but use the transmitter frame sync
2303  * (SAI_TX_SYNC).
2304  *
2305  * Values:
2306  * - 0 - Use the normal bit clock source.
2307  * - 1 - Swap the bit clock source.
2308  */
2309 /*@{*/
2310 #define BP_I2S_RCR2_BCS      (29U)         /*!< Bit position for I2S_RCR2_BCS. */
2311 #define BM_I2S_RCR2_BCS      (0x20000000U) /*!< Bit mask for I2S_RCR2_BCS. */
2312 #define BS_I2S_RCR2_BCS      (1U)          /*!< Bit field size in bits for I2S_RCR2_BCS. */
2313
2314 /*! @brief Read current value of the I2S_RCR2_BCS field. */
2315 #define BR_I2S_RCR2_BCS(x)   (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCS))
2316
2317 /*! @brief Format value for bitfield I2S_RCR2_BCS. */
2318 #define BF_I2S_RCR2_BCS(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_BCS) & BM_I2S_RCR2_BCS)
2319
2320 /*! @brief Set the BCS field to a new value. */
2321 #define BW_I2S_RCR2_BCS(x, v) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCS) = (v))
2322 /*@}*/
2323
2324 /*!
2325  * @name Register I2S_RCR2, field SYNC[31:30] (RW)
2326  *
2327  * Configures between asynchronous and synchronous modes of operation. When
2328  * configured for a synchronous mode of operation, the transmitter must be configured
2329  * for asynchronous operation.
2330  *
2331  * Values:
2332  * - 00 - Asynchronous mode.
2333  * - 01 - Synchronous with transmitter.
2334  * - 10 - Synchronous with another SAI receiver.
2335  * - 11 - Synchronous with another SAI transmitter.
2336  */
2337 /*@{*/
2338 #define BP_I2S_RCR2_SYNC     (30U)         /*!< Bit position for I2S_RCR2_SYNC. */
2339 #define BM_I2S_RCR2_SYNC     (0xC0000000U) /*!< Bit mask for I2S_RCR2_SYNC. */
2340 #define BS_I2S_RCR2_SYNC     (2U)          /*!< Bit field size in bits for I2S_RCR2_SYNC. */
2341
2342 /*! @brief Read current value of the I2S_RCR2_SYNC field. */
2343 #define BR_I2S_RCR2_SYNC(x)  (HW_I2S_RCR2(x).B.SYNC)
2344
2345 /*! @brief Format value for bitfield I2S_RCR2_SYNC. */
2346 #define BF_I2S_RCR2_SYNC(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_SYNC) & BM_I2S_RCR2_SYNC)
2347
2348 /*! @brief Set the SYNC field to a new value. */
2349 #define BW_I2S_RCR2_SYNC(x, v) (HW_I2S_RCR2_WR(x, (HW_I2S_RCR2_RD(x) & ~BM_I2S_RCR2_SYNC) | BF_I2S_RCR2_SYNC(v)))
2350 /*@}*/
2351
2352 /*******************************************************************************
2353  * HW_I2S_RCR3 - SAI Receive Configuration 3 Register
2354  ******************************************************************************/
2355
2356 /*!
2357  * @brief HW_I2S_RCR3 - SAI Receive Configuration 3 Register (RW)
2358  *
2359  * Reset value: 0x00000000U
2360  */
2361 typedef union _hw_i2s_rcr3
2362 {
2363     uint32_t U;
2364     struct _hw_i2s_rcr3_bitfields
2365     {
2366         uint32_t WDFL : 4;             /*!< [3:0] Word Flag Configuration */
2367         uint32_t RESERVED0 : 12;       /*!< [15:4]  */
2368         uint32_t RCE : 1;              /*!< [16] Receive Channel Enable */
2369         uint32_t RESERVED1 : 15;       /*!< [31:17]  */
2370     } B;
2371 } hw_i2s_rcr3_t;
2372
2373 /*!
2374  * @name Constants and macros for entire I2S_RCR3 register
2375  */
2376 /*@{*/
2377 #define HW_I2S_RCR3_ADDR(x)      ((x) + 0x8CU)
2378
2379 #define HW_I2S_RCR3(x)           (*(__IO hw_i2s_rcr3_t *) HW_I2S_RCR3_ADDR(x))
2380 #define HW_I2S_RCR3_RD(x)        (HW_I2S_RCR3(x).U)
2381 #define HW_I2S_RCR3_WR(x, v)     (HW_I2S_RCR3(x).U = (v))
2382 #define HW_I2S_RCR3_SET(x, v)    (HW_I2S_RCR3_WR(x, HW_I2S_RCR3_RD(x) |  (v)))
2383 #define HW_I2S_RCR3_CLR(x, v)    (HW_I2S_RCR3_WR(x, HW_I2S_RCR3_RD(x) & ~(v)))
2384 #define HW_I2S_RCR3_TOG(x, v)    (HW_I2S_RCR3_WR(x, HW_I2S_RCR3_RD(x) ^  (v)))
2385 /*@}*/
2386
2387 /*
2388  * Constants & macros for individual I2S_RCR3 bitfields
2389  */
2390
2391 /*!
2392  * @name Register I2S_RCR3, field WDFL[3:0] (RW)
2393  *
2394  * Configures which word the start of word flag is set. The value written should
2395  * be one less than the word number (for example, write zero to configure for
2396  * the first word in the frame). When configured to a value greater than the Frame
2397  * Size field, then the start of word flag is never set.
2398  */
2399 /*@{*/
2400 #define BP_I2S_RCR3_WDFL     (0U)          /*!< Bit position for I2S_RCR3_WDFL. */
2401 #define BM_I2S_RCR3_WDFL     (0x0000000FU) /*!< Bit mask for I2S_RCR3_WDFL. */
2402 #define BS_I2S_RCR3_WDFL     (4U)          /*!< Bit field size in bits for I2S_RCR3_WDFL. */
2403
2404 /*! @brief Read current value of the I2S_RCR3_WDFL field. */
2405 #define BR_I2S_RCR3_WDFL(x)  (HW_I2S_RCR3(x).B.WDFL)
2406
2407 /*! @brief Format value for bitfield I2S_RCR3_WDFL. */
2408 #define BF_I2S_RCR3_WDFL(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_RCR3_WDFL) & BM_I2S_RCR3_WDFL)
2409
2410 /*! @brief Set the WDFL field to a new value. */
2411 #define BW_I2S_RCR3_WDFL(x, v) (HW_I2S_RCR3_WR(x, (HW_I2S_RCR3_RD(x) & ~BM_I2S_RCR3_WDFL) | BF_I2S_RCR3_WDFL(v)))
2412 /*@}*/
2413
2414 /*!
2415  * @name Register I2S_RCR3, field RCE[16] (RW)
2416  *
2417  * Enables the corresponding data channel for receive operation. A channel must
2418  * be enabled before its FIFO is accessed. Changing this field will take effect
2419  * immediately for generating the FIFO request and warning flags, but at the end
2420  * of each frame for receive operation.
2421  *
2422  * Values:
2423  * - 0 - Receive data channel N is disabled.
2424  * - 1 - Receive data channel N is enabled.
2425  */
2426 /*@{*/
2427 #define BP_I2S_RCR3_RCE      (16U)         /*!< Bit position for I2S_RCR3_RCE. */
2428 #define BM_I2S_RCR3_RCE      (0x00010000U) /*!< Bit mask for I2S_RCR3_RCE. */
2429 #define BS_I2S_RCR3_RCE      (1U)          /*!< Bit field size in bits for I2S_RCR3_RCE. */
2430
2431 /*! @brief Read current value of the I2S_RCR3_RCE field. */
2432 #define BR_I2S_RCR3_RCE(x)   (BITBAND_ACCESS32(HW_I2S_RCR3_ADDR(x), BP_I2S_RCR3_RCE))
2433
2434 /*! @brief Format value for bitfield I2S_RCR3_RCE. */
2435 #define BF_I2S_RCR3_RCE(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_RCR3_RCE) & BM_I2S_RCR3_RCE)
2436
2437 /*! @brief Set the RCE field to a new value. */
2438 #define BW_I2S_RCR3_RCE(x, v) (BITBAND_ACCESS32(HW_I2S_RCR3_ADDR(x), BP_I2S_RCR3_RCE) = (v))
2439 /*@}*/
2440
2441 /*******************************************************************************
2442  * HW_I2S_RCR4 - SAI Receive Configuration 4 Register
2443  ******************************************************************************/
2444
2445 /*!
2446  * @brief HW_I2S_RCR4 - SAI Receive Configuration 4 Register (RW)
2447  *
2448  * Reset value: 0x00000000U
2449  *
2450  * This register must not be altered when RCSR[RE] is set.
2451  */
2452 typedef union _hw_i2s_rcr4
2453 {
2454     uint32_t U;
2455     struct _hw_i2s_rcr4_bitfields
2456     {
2457         uint32_t FSD : 1;              /*!< [0] Frame Sync Direction */
2458         uint32_t FSP : 1;              /*!< [1] Frame Sync Polarity */
2459         uint32_t ONDEM : 1;            /*!< [2] On Demand Mode */
2460         uint32_t FSE : 1;              /*!< [3] Frame Sync Early */
2461         uint32_t MF : 1;               /*!< [4] MSB First */
2462         uint32_t RESERVED0 : 3;        /*!< [7:5]  */
2463         uint32_t SYWD : 5;             /*!< [12:8] Sync Width */
2464         uint32_t RESERVED1 : 3;        /*!< [15:13]  */
2465         uint32_t FRSZ : 4;             /*!< [19:16] Frame Size */
2466         uint32_t RESERVED2 : 4;        /*!< [23:20]  */
2467         uint32_t FPACK : 2;            /*!< [25:24] FIFO Packing Mode */
2468         uint32_t RESERVED3 : 2;        /*!< [27:26]  */
2469         uint32_t FCONT : 1;            /*!< [28] FIFO Continue on Error */
2470         uint32_t RESERVED4 : 3;        /*!< [31:29]  */
2471     } B;
2472 } hw_i2s_rcr4_t;
2473
2474 /*!
2475  * @name Constants and macros for entire I2S_RCR4 register
2476  */
2477 /*@{*/
2478 #define HW_I2S_RCR4_ADDR(x)      ((x) + 0x90U)
2479
2480 #define HW_I2S_RCR4(x)           (*(__IO hw_i2s_rcr4_t *) HW_I2S_RCR4_ADDR(x))
2481 #define HW_I2S_RCR4_RD(x)        (HW_I2S_RCR4(x).U)
2482 #define HW_I2S_RCR4_WR(x, v)     (HW_I2S_RCR4(x).U = (v))
2483 #define HW_I2S_RCR4_SET(x, v)    (HW_I2S_RCR4_WR(x, HW_I2S_RCR4_RD(x) |  (v)))
2484 #define HW_I2S_RCR4_CLR(x, v)    (HW_I2S_RCR4_WR(x, HW_I2S_RCR4_RD(x) & ~(v)))
2485 #define HW_I2S_RCR4_TOG(x, v)    (HW_I2S_RCR4_WR(x, HW_I2S_RCR4_RD(x) ^  (v)))
2486 /*@}*/
2487
2488 /*
2489  * Constants & macros for individual I2S_RCR4 bitfields
2490  */
2491
2492 /*!
2493  * @name Register I2S_RCR4, field FSD[0] (RW)
2494  *
2495  * Configures the direction of the frame sync.
2496  *
2497  * Values:
2498  * - 0 - Frame Sync is generated externally in Slave mode.
2499  * - 1 - Frame Sync is generated internally in Master mode.
2500  */
2501 /*@{*/
2502 #define BP_I2S_RCR4_FSD      (0U)          /*!< Bit position for I2S_RCR4_FSD. */
2503 #define BM_I2S_RCR4_FSD      (0x00000001U) /*!< Bit mask for I2S_RCR4_FSD. */
2504 #define BS_I2S_RCR4_FSD      (1U)          /*!< Bit field size in bits for I2S_RCR4_FSD. */
2505
2506 /*! @brief Read current value of the I2S_RCR4_FSD field. */
2507 #define BR_I2S_RCR4_FSD(x)   (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSD))
2508
2509 /*! @brief Format value for bitfield I2S_RCR4_FSD. */
2510 #define BF_I2S_RCR4_FSD(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_FSD) & BM_I2S_RCR4_FSD)
2511
2512 /*! @brief Set the FSD field to a new value. */
2513 #define BW_I2S_RCR4_FSD(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSD) = (v))
2514 /*@}*/
2515
2516 /*!
2517  * @name Register I2S_RCR4, field FSP[1] (RW)
2518  *
2519  * Configures the polarity of the frame sync.
2520  *
2521  * Values:
2522  * - 0 - Frame sync is active high.
2523  * - 1 - Frame sync is active low.
2524  */
2525 /*@{*/
2526 #define BP_I2S_RCR4_FSP      (1U)          /*!< Bit position for I2S_RCR4_FSP. */
2527 #define BM_I2S_RCR4_FSP      (0x00000002U) /*!< Bit mask for I2S_RCR4_FSP. */
2528 #define BS_I2S_RCR4_FSP      (1U)          /*!< Bit field size in bits for I2S_RCR4_FSP. */
2529
2530 /*! @brief Read current value of the I2S_RCR4_FSP field. */
2531 #define BR_I2S_RCR4_FSP(x)   (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSP))
2532
2533 /*! @brief Format value for bitfield I2S_RCR4_FSP. */
2534 #define BF_I2S_RCR4_FSP(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_FSP) & BM_I2S_RCR4_FSP)
2535
2536 /*! @brief Set the FSP field to a new value. */
2537 #define BW_I2S_RCR4_FSP(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSP) = (v))
2538 /*@}*/
2539
2540 /*!
2541  * @name Register I2S_RCR4, field ONDEM[2] (RW)
2542  *
2543  * When set, and the frame sync is generated internally, a frame sync is only
2544  * generated when the FIFO warning flag is clear.
2545  *
2546  * Values:
2547  * - 0 - Internal frame sync is generated continuously.
2548  * - 1 - Internal frame sync is generated when the FIFO warning flag is clear.
2549  */
2550 /*@{*/
2551 #define BP_I2S_RCR4_ONDEM    (2U)          /*!< Bit position for I2S_RCR4_ONDEM. */
2552 #define BM_I2S_RCR4_ONDEM    (0x00000004U) /*!< Bit mask for I2S_RCR4_ONDEM. */
2553 #define BS_I2S_RCR4_ONDEM    (1U)          /*!< Bit field size in bits for I2S_RCR4_ONDEM. */
2554
2555 /*! @brief Read current value of the I2S_RCR4_ONDEM field. */
2556 #define BR_I2S_RCR4_ONDEM(x) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_ONDEM))
2557
2558 /*! @brief Format value for bitfield I2S_RCR4_ONDEM. */
2559 #define BF_I2S_RCR4_ONDEM(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_ONDEM) & BM_I2S_RCR4_ONDEM)
2560
2561 /*! @brief Set the ONDEM field to a new value. */
2562 #define BW_I2S_RCR4_ONDEM(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_ONDEM) = (v))
2563 /*@}*/
2564
2565 /*!
2566  * @name Register I2S_RCR4, field FSE[3] (RW)
2567  *
2568  * Values:
2569  * - 0 - Frame sync asserts with the first bit of the frame.
2570  * - 1 - Frame sync asserts one bit before the first bit of the frame.
2571  */
2572 /*@{*/
2573 #define BP_I2S_RCR4_FSE      (3U)          /*!< Bit position for I2S_RCR4_FSE. */
2574 #define BM_I2S_RCR4_FSE      (0x00000008U) /*!< Bit mask for I2S_RCR4_FSE. */
2575 #define BS_I2S_RCR4_FSE      (1U)          /*!< Bit field size in bits for I2S_RCR4_FSE. */
2576
2577 /*! @brief Read current value of the I2S_RCR4_FSE field. */
2578 #define BR_I2S_RCR4_FSE(x)   (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSE))
2579
2580 /*! @brief Format value for bitfield I2S_RCR4_FSE. */
2581 #define BF_I2S_RCR4_FSE(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_FSE) & BM_I2S_RCR4_FSE)
2582
2583 /*! @brief Set the FSE field to a new value. */
2584 #define BW_I2S_RCR4_FSE(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSE) = (v))
2585 /*@}*/
2586
2587 /*!
2588  * @name Register I2S_RCR4, field MF[4] (RW)
2589  *
2590  * Configures whether the LSB or the MSB is received first.
2591  *
2592  * Values:
2593  * - 0 - LSB is received first.
2594  * - 1 - MSB is received first.
2595  */
2596 /*@{*/
2597 #define BP_I2S_RCR4_MF       (4U)          /*!< Bit position for I2S_RCR4_MF. */
2598 #define BM_I2S_RCR4_MF       (0x00000010U) /*!< Bit mask for I2S_RCR4_MF. */
2599 #define BS_I2S_RCR4_MF       (1U)          /*!< Bit field size in bits for I2S_RCR4_MF. */
2600
2601 /*! @brief Read current value of the I2S_RCR4_MF field. */
2602 #define BR_I2S_RCR4_MF(x)    (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_MF))
2603
2604 /*! @brief Format value for bitfield I2S_RCR4_MF. */
2605 #define BF_I2S_RCR4_MF(v)    ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_MF) & BM_I2S_RCR4_MF)
2606
2607 /*! @brief Set the MF field to a new value. */
2608 #define BW_I2S_RCR4_MF(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_MF) = (v))
2609 /*@}*/
2610
2611 /*!
2612  * @name Register I2S_RCR4, field SYWD[12:8] (RW)
2613  *
2614  * Configures the length of the frame sync in number of bit clocks. The value
2615  * written must be one less than the number of bit clocks. For example, write 0 for
2616  * the frame sync to assert for one bit clock only. The sync width cannot be
2617  * configured longer than the first word of the frame.
2618  */
2619 /*@{*/
2620 #define BP_I2S_RCR4_SYWD     (8U)          /*!< Bit position for I2S_RCR4_SYWD. */
2621 #define BM_I2S_RCR4_SYWD     (0x00001F00U) /*!< Bit mask for I2S_RCR4_SYWD. */
2622 #define BS_I2S_RCR4_SYWD     (5U)          /*!< Bit field size in bits for I2S_RCR4_SYWD. */
2623
2624 /*! @brief Read current value of the I2S_RCR4_SYWD field. */
2625 #define BR_I2S_RCR4_SYWD(x)  (HW_I2S_RCR4(x).B.SYWD)
2626
2627 /*! @brief Format value for bitfield I2S_RCR4_SYWD. */
2628 #define BF_I2S_RCR4_SYWD(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_SYWD) & BM_I2S_RCR4_SYWD)
2629
2630 /*! @brief Set the SYWD field to a new value. */
2631 #define BW_I2S_RCR4_SYWD(x, v) (HW_I2S_RCR4_WR(x, (HW_I2S_RCR4_RD(x) & ~BM_I2S_RCR4_SYWD) | BF_I2S_RCR4_SYWD(v)))
2632 /*@}*/
2633
2634 /*!
2635  * @name Register I2S_RCR4, field FRSZ[19:16] (RW)
2636  *
2637  * Configures the number of words in each frame. The value written must be one
2638  * less than the number of words in the frame. For example, write 0 for one word
2639  * per frame. The maximum supported frame size is 16 words.
2640  */
2641 /*@{*/
2642 #define BP_I2S_RCR4_FRSZ     (16U)         /*!< Bit position for I2S_RCR4_FRSZ. */
2643 #define BM_I2S_RCR4_FRSZ     (0x000F0000U) /*!< Bit mask for I2S_RCR4_FRSZ. */
2644 #define BS_I2S_RCR4_FRSZ     (4U)          /*!< Bit field size in bits for I2S_RCR4_FRSZ. */
2645
2646 /*! @brief Read current value of the I2S_RCR4_FRSZ field. */
2647 #define BR_I2S_RCR4_FRSZ(x)  (HW_I2S_RCR4(x).B.FRSZ)
2648
2649 /*! @brief Format value for bitfield I2S_RCR4_FRSZ. */
2650 #define BF_I2S_RCR4_FRSZ(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_FRSZ) & BM_I2S_RCR4_FRSZ)
2651
2652 /*! @brief Set the FRSZ field to a new value. */
2653 #define BW_I2S_RCR4_FRSZ(x, v) (HW_I2S_RCR4_WR(x, (HW_I2S_RCR4_RD(x) & ~BM_I2S_RCR4_FRSZ) | BF_I2S_RCR4_FRSZ(v)))
2654 /*@}*/
2655
2656 /*!
2657  * @name Register I2S_RCR4, field FPACK[25:24] (RW)
2658  *
2659  * Enables packing of 8-bit data or 16-bit data into each 32-bit FIFO word. If
2660  * the word size is greater than 8-bit or 16-bit then only the first 8-bit or
2661  * 16-bits are stored to the FIFO. The first word in each frame always starts with a
2662  * new 32-bit FIFO word and the first bit shifted must be configured within the
2663  * first packed word. When FIFO packing is enabled, the FIFO read pointer will
2664  * only increment when the full 32-bit FIFO word has been read by software.
2665  *
2666  * Values:
2667  * - 00 - FIFO packing is disabled
2668  * - 01 - Reserved.
2669  * - 10 - 8-bit FIFO packing is enabled
2670  * - 11 - 16-bit FIFO packing is enabled
2671  */
2672 /*@{*/
2673 #define BP_I2S_RCR4_FPACK    (24U)         /*!< Bit position for I2S_RCR4_FPACK. */
2674 #define BM_I2S_RCR4_FPACK    (0x03000000U) /*!< Bit mask for I2S_RCR4_FPACK. */
2675 #define BS_I2S_RCR4_FPACK    (2U)          /*!< Bit field size in bits for I2S_RCR4_FPACK. */
2676
2677 /*! @brief Read current value of the I2S_RCR4_FPACK field. */
2678 #define BR_I2S_RCR4_FPACK(x) (HW_I2S_RCR4(x).B.FPACK)
2679
2680 /*! @brief Format value for bitfield I2S_RCR4_FPACK. */
2681 #define BF_I2S_RCR4_FPACK(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_FPACK) & BM_I2S_RCR4_FPACK)
2682
2683 /*! @brief Set the FPACK field to a new value. */
2684 #define BW_I2S_RCR4_FPACK(x, v) (HW_I2S_RCR4_WR(x, (HW_I2S_RCR4_RD(x) & ~BM_I2S_RCR4_FPACK) | BF_I2S_RCR4_FPACK(v)))
2685 /*@}*/
2686
2687 /*!
2688  * @name Register I2S_RCR4, field FCONT[28] (RW)
2689  *
2690  * Configures when the SAI will continue receiving after a FIFO error has been
2691  * detected.
2692  *
2693  * Values:
2694  * - 0 - On FIFO error, the SAI will continue from the start of the next frame
2695  *     after the FIFO error flag has been cleared.
2696  * - 1 - On FIFO error, the SAI will continue from the same word that caused the
2697  *     FIFO error to set after the FIFO warning flag has been cleared.
2698  */
2699 /*@{*/
2700 #define BP_I2S_RCR4_FCONT    (28U)         /*!< Bit position for I2S_RCR4_FCONT. */
2701 #define BM_I2S_RCR4_FCONT    (0x10000000U) /*!< Bit mask for I2S_RCR4_FCONT. */
2702 #define BS_I2S_RCR4_FCONT    (1U)          /*!< Bit field size in bits for I2S_RCR4_FCONT. */
2703
2704 /*! @brief Read current value of the I2S_RCR4_FCONT field. */
2705 #define BR_I2S_RCR4_FCONT(x) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FCONT))
2706
2707 /*! @brief Format value for bitfield I2S_RCR4_FCONT. */
2708 #define BF_I2S_RCR4_FCONT(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_FCONT) & BM_I2S_RCR4_FCONT)
2709
2710 /*! @brief Set the FCONT field to a new value. */
2711 #define BW_I2S_RCR4_FCONT(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FCONT) = (v))
2712 /*@}*/
2713
2714 /*******************************************************************************
2715  * HW_I2S_RCR5 - SAI Receive Configuration 5 Register
2716  ******************************************************************************/
2717
2718 /*!
2719  * @brief HW_I2S_RCR5 - SAI Receive Configuration 5 Register (RW)
2720  *
2721  * Reset value: 0x00000000U
2722  *
2723  * This register must not be altered when RCSR[RE] is set.
2724  */
2725 typedef union _hw_i2s_rcr5
2726 {
2727     uint32_t U;
2728     struct _hw_i2s_rcr5_bitfields
2729     {
2730         uint32_t RESERVED0 : 8;        /*!< [7:0]  */
2731         uint32_t FBT : 5;              /*!< [12:8] First Bit Shifted */
2732         uint32_t RESERVED1 : 3;        /*!< [15:13]  */
2733         uint32_t W0W : 5;              /*!< [20:16] Word 0 Width */
2734         uint32_t RESERVED2 : 3;        /*!< [23:21]  */
2735         uint32_t WNW : 5;              /*!< [28:24] Word N Width */
2736         uint32_t RESERVED3 : 3;        /*!< [31:29]  */
2737     } B;
2738 } hw_i2s_rcr5_t;
2739
2740 /*!
2741  * @name Constants and macros for entire I2S_RCR5 register
2742  */
2743 /*@{*/
2744 #define HW_I2S_RCR5_ADDR(x)      ((x) + 0x94U)
2745
2746 #define HW_I2S_RCR5(x)           (*(__IO hw_i2s_rcr5_t *) HW_I2S_RCR5_ADDR(x))
2747 #define HW_I2S_RCR5_RD(x)        (HW_I2S_RCR5(x).U)
2748 #define HW_I2S_RCR5_WR(x, v)     (HW_I2S_RCR5(x).U = (v))
2749 #define HW_I2S_RCR5_SET(x, v)    (HW_I2S_RCR5_WR(x, HW_I2S_RCR5_RD(x) |  (v)))
2750 #define HW_I2S_RCR5_CLR(x, v)    (HW_I2S_RCR5_WR(x, HW_I2S_RCR5_RD(x) & ~(v)))
2751 #define HW_I2S_RCR5_TOG(x, v)    (HW_I2S_RCR5_WR(x, HW_I2S_RCR5_RD(x) ^  (v)))
2752 /*@}*/
2753
2754 /*
2755  * Constants & macros for individual I2S_RCR5 bitfields
2756  */
2757
2758 /*!
2759  * @name Register I2S_RCR5, field FBT[12:8] (RW)
2760  *
2761  * Configures the bit index for the first bit received for each word in the
2762  * frame. If configured for MSB First, the index of the next bit received is one less
2763  * than the current bit received. If configured for LSB First, the index of the
2764  * next bit received is one more than the current bit received. The value written
2765  * must be greater than or equal to the word width when configured for MSB
2766  * First. The value written must be less than or equal to 31-word width when
2767  * configured for LSB First.
2768  */
2769 /*@{*/
2770 #define BP_I2S_RCR5_FBT      (8U)          /*!< Bit position for I2S_RCR5_FBT. */
2771 #define BM_I2S_RCR5_FBT      (0x00001F00U) /*!< Bit mask for I2S_RCR5_FBT. */
2772 #define BS_I2S_RCR5_FBT      (5U)          /*!< Bit field size in bits for I2S_RCR5_FBT. */
2773
2774 /*! @brief Read current value of the I2S_RCR5_FBT field. */
2775 #define BR_I2S_RCR5_FBT(x)   (HW_I2S_RCR5(x).B.FBT)
2776
2777 /*! @brief Format value for bitfield I2S_RCR5_FBT. */
2778 #define BF_I2S_RCR5_FBT(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_RCR5_FBT) & BM_I2S_RCR5_FBT)
2779
2780 /*! @brief Set the FBT field to a new value. */
2781 #define BW_I2S_RCR5_FBT(x, v) (HW_I2S_RCR5_WR(x, (HW_I2S_RCR5_RD(x) & ~BM_I2S_RCR5_FBT) | BF_I2S_RCR5_FBT(v)))
2782 /*@}*/
2783
2784 /*!
2785  * @name Register I2S_RCR5, field W0W[20:16] (RW)
2786  *
2787  * Configures the number of bits in the first word in each frame. The value
2788  * written must be one less than the number of bits in the first word. Word width of
2789  * less than 8 bits is not supported if there is only one word per frame.
2790  */
2791 /*@{*/
2792 #define BP_I2S_RCR5_W0W      (16U)         /*!< Bit position for I2S_RCR5_W0W. */
2793 #define BM_I2S_RCR5_W0W      (0x001F0000U) /*!< Bit mask for I2S_RCR5_W0W. */
2794 #define BS_I2S_RCR5_W0W      (5U)          /*!< Bit field size in bits for I2S_RCR5_W0W. */
2795
2796 /*! @brief Read current value of the I2S_RCR5_W0W field. */
2797 #define BR_I2S_RCR5_W0W(x)   (HW_I2S_RCR5(x).B.W0W)
2798
2799 /*! @brief Format value for bitfield I2S_RCR5_W0W. */
2800 #define BF_I2S_RCR5_W0W(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_RCR5_W0W) & BM_I2S_RCR5_W0W)
2801
2802 /*! @brief Set the W0W field to a new value. */
2803 #define BW_I2S_RCR5_W0W(x, v) (HW_I2S_RCR5_WR(x, (HW_I2S_RCR5_RD(x) & ~BM_I2S_RCR5_W0W) | BF_I2S_RCR5_W0W(v)))
2804 /*@}*/
2805
2806 /*!
2807  * @name Register I2S_RCR5, field WNW[28:24] (RW)
2808  *
2809  * Configures the number of bits in each word, for each word except the first in
2810  * the frame. The value written must be one less than the number of bits per
2811  * word. Word width of less than 8 bits is not supported.
2812  */
2813 /*@{*/
2814 #define BP_I2S_RCR5_WNW      (24U)         /*!< Bit position for I2S_RCR5_WNW. */
2815 #define BM_I2S_RCR5_WNW      (0x1F000000U) /*!< Bit mask for I2S_RCR5_WNW. */
2816 #define BS_I2S_RCR5_WNW      (5U)          /*!< Bit field size in bits for I2S_RCR5_WNW. */
2817
2818 /*! @brief Read current value of the I2S_RCR5_WNW field. */
2819 #define BR_I2S_RCR5_WNW(x)   (HW_I2S_RCR5(x).B.WNW)
2820
2821 /*! @brief Format value for bitfield I2S_RCR5_WNW. */
2822 #define BF_I2S_RCR5_WNW(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_RCR5_WNW) & BM_I2S_RCR5_WNW)
2823
2824 /*! @brief Set the WNW field to a new value. */
2825 #define BW_I2S_RCR5_WNW(x, v) (HW_I2S_RCR5_WR(x, (HW_I2S_RCR5_RD(x) & ~BM_I2S_RCR5_WNW) | BF_I2S_RCR5_WNW(v)))
2826 /*@}*/
2827
2828 /*******************************************************************************
2829  * HW_I2S_RDRn - SAI Receive Data Register
2830  ******************************************************************************/
2831
2832 /*!
2833  * @brief HW_I2S_RDRn - SAI Receive Data Register (RO)
2834  *
2835  * Reset value: 0x00000000U
2836  *
2837  * Reading this register introduces one additional peripheral clock wait state
2838  * on each read.
2839  */
2840 typedef union _hw_i2s_rdrn
2841 {
2842     uint32_t U;
2843     struct _hw_i2s_rdrn_bitfields
2844     {
2845         uint32_t RDR : 32;             /*!< [31:0] Receive Data Register */
2846     } B;
2847 } hw_i2s_rdrn_t;
2848
2849 /*!
2850  * @name Constants and macros for entire I2S_RDRn register
2851  */
2852 /*@{*/
2853 #define HW_I2S_RDRn_COUNT (1U)
2854
2855 #define HW_I2S_RDRn_ADDR(x, n)   ((x) + 0xA0U + (0x4U * (n)))
2856
2857 #define HW_I2S_RDRn(x, n)        (*(__I hw_i2s_rdrn_t *) HW_I2S_RDRn_ADDR(x, n))
2858 #define HW_I2S_RDRn_RD(x, n)     (HW_I2S_RDRn(x, n).U)
2859 /*@}*/
2860
2861 /*
2862  * Constants & macros for individual I2S_RDRn bitfields
2863  */
2864
2865 /*!
2866  * @name Register I2S_RDRn, field RDR[31:0] (RO)
2867  *
2868  * The corresponding RCR3[RCE] bit must be set before accessing the channel's
2869  * receive data register. Reads from this register when the receive FIFO is not
2870  * empty will return the data from the top of the receive FIFO. Reads from this
2871  * register when the receive FIFO is empty are ignored.
2872  */
2873 /*@{*/
2874 #define BP_I2S_RDRn_RDR      (0U)          /*!< Bit position for I2S_RDRn_RDR. */
2875 #define BM_I2S_RDRn_RDR      (0xFFFFFFFFU) /*!< Bit mask for I2S_RDRn_RDR. */
2876 #define BS_I2S_RDRn_RDR      (32U)         /*!< Bit field size in bits for I2S_RDRn_RDR. */
2877
2878 /*! @brief Read current value of the I2S_RDRn_RDR field. */
2879 #define BR_I2S_RDRn_RDR(x, n) (HW_I2S_RDRn(x, n).U)
2880 /*@}*/
2881
2882 /*******************************************************************************
2883  * HW_I2S_RFRn - SAI Receive FIFO Register
2884  ******************************************************************************/
2885
2886 /*!
2887  * @brief HW_I2S_RFRn - SAI Receive FIFO Register (RO)
2888  *
2889  * Reset value: 0x00000000U
2890  *
2891  * The MSB of the read and write pointers is used to distinguish between FIFO
2892  * full and empty conditions. If the read and write pointers are identical, then
2893  * the FIFO is empty. If the read and write pointers are identical except for the
2894  * MSB, then the FIFO is full.
2895  */
2896 typedef union _hw_i2s_rfrn
2897 {
2898     uint32_t U;
2899     struct _hw_i2s_rfrn_bitfields
2900     {
2901         uint32_t RFP : 4;              /*!< [3:0] Read FIFO Pointer */
2902         uint32_t RESERVED0 : 12;       /*!< [15:4]  */
2903         uint32_t WFP : 4;              /*!< [19:16] Write FIFO Pointer */
2904         uint32_t RESERVED1 : 12;       /*!< [31:20]  */
2905     } B;
2906 } hw_i2s_rfrn_t;
2907
2908 /*!
2909  * @name Constants and macros for entire I2S_RFRn register
2910  */
2911 /*@{*/
2912 #define HW_I2S_RFRn_COUNT (1U)
2913
2914 #define HW_I2S_RFRn_ADDR(x, n)   ((x) + 0xC0U + (0x4U * (n)))
2915
2916 #define HW_I2S_RFRn(x, n)        (*(__I hw_i2s_rfrn_t *) HW_I2S_RFRn_ADDR(x, n))
2917 #define HW_I2S_RFRn_RD(x, n)     (HW_I2S_RFRn(x, n).U)
2918 /*@}*/
2919
2920 /*
2921  * Constants & macros for individual I2S_RFRn bitfields
2922  */
2923
2924 /*!
2925  * @name Register I2S_RFRn, field RFP[3:0] (RO)
2926  *
2927  * FIFO read pointer for receive data channel.
2928  */
2929 /*@{*/
2930 #define BP_I2S_RFRn_RFP      (0U)          /*!< Bit position for I2S_RFRn_RFP. */
2931 #define BM_I2S_RFRn_RFP      (0x0000000FU) /*!< Bit mask for I2S_RFRn_RFP. */
2932 #define BS_I2S_RFRn_RFP      (4U)          /*!< Bit field size in bits for I2S_RFRn_RFP. */
2933
2934 /*! @brief Read current value of the I2S_RFRn_RFP field. */
2935 #define BR_I2S_RFRn_RFP(x, n) (HW_I2S_RFRn(x, n).B.RFP)
2936 /*@}*/
2937
2938 /*!
2939  * @name Register I2S_RFRn, field WFP[19:16] (RO)
2940  *
2941  * FIFO write pointer for receive data channel.
2942  */
2943 /*@{*/
2944 #define BP_I2S_RFRn_WFP      (16U)         /*!< Bit position for I2S_RFRn_WFP. */
2945 #define BM_I2S_RFRn_WFP      (0x000F0000U) /*!< Bit mask for I2S_RFRn_WFP. */
2946 #define BS_I2S_RFRn_WFP      (4U)          /*!< Bit field size in bits for I2S_RFRn_WFP. */
2947
2948 /*! @brief Read current value of the I2S_RFRn_WFP field. */
2949 #define BR_I2S_RFRn_WFP(x, n) (HW_I2S_RFRn(x, n).B.WFP)
2950 /*@}*/
2951
2952 /*******************************************************************************
2953  * HW_I2S_RMR - SAI Receive Mask Register
2954  ******************************************************************************/
2955
2956 /*!
2957  * @brief HW_I2S_RMR - SAI Receive Mask Register (RW)
2958  *
2959  * Reset value: 0x00000000U
2960  *
2961  * This register is double-buffered and updates: When RCSR[RE] is first set At
2962  * the end of each frame This allows the masked words in each frame to change from
2963  * frame to frame.
2964  */
2965 typedef union _hw_i2s_rmr
2966 {
2967     uint32_t U;
2968     struct _hw_i2s_rmr_bitfields
2969     {
2970         uint32_t RWM : 16;             /*!< [15:0] Receive Word Mask */
2971         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
2972     } B;
2973 } hw_i2s_rmr_t;
2974
2975 /*!
2976  * @name Constants and macros for entire I2S_RMR register
2977  */
2978 /*@{*/
2979 #define HW_I2S_RMR_ADDR(x)       ((x) + 0xE0U)
2980
2981 #define HW_I2S_RMR(x)            (*(__IO hw_i2s_rmr_t *) HW_I2S_RMR_ADDR(x))
2982 #define HW_I2S_RMR_RD(x)         (HW_I2S_RMR(x).U)
2983 #define HW_I2S_RMR_WR(x, v)      (HW_I2S_RMR(x).U = (v))
2984 #define HW_I2S_RMR_SET(x, v)     (HW_I2S_RMR_WR(x, HW_I2S_RMR_RD(x) |  (v)))
2985 #define HW_I2S_RMR_CLR(x, v)     (HW_I2S_RMR_WR(x, HW_I2S_RMR_RD(x) & ~(v)))
2986 #define HW_I2S_RMR_TOG(x, v)     (HW_I2S_RMR_WR(x, HW_I2S_RMR_RD(x) ^  (v)))
2987 /*@}*/
2988
2989 /*
2990  * Constants & macros for individual I2S_RMR bitfields
2991  */
2992
2993 /*!
2994  * @name Register I2S_RMR, field RWM[15:0] (RW)
2995  *
2996  * Configures whether the receive word is masked (received data ignored and not
2997  * written to receive FIFO) for the corresponding word in the frame.
2998  *
2999  * Values:
3000  * - 0 - Word N is enabled.
3001  * - 1 - Word N is masked.
3002  */
3003 /*@{*/
3004 #define BP_I2S_RMR_RWM       (0U)          /*!< Bit position for I2S_RMR_RWM. */
3005 #define BM_I2S_RMR_RWM       (0x0000FFFFU) /*!< Bit mask for I2S_RMR_RWM. */
3006 #define BS_I2S_RMR_RWM       (16U)         /*!< Bit field size in bits for I2S_RMR_RWM. */
3007
3008 /*! @brief Read current value of the I2S_RMR_RWM field. */
3009 #define BR_I2S_RMR_RWM(x)    (HW_I2S_RMR(x).B.RWM)
3010
3011 /*! @brief Format value for bitfield I2S_RMR_RWM. */
3012 #define BF_I2S_RMR_RWM(v)    ((uint32_t)((uint32_t)(v) << BP_I2S_RMR_RWM) & BM_I2S_RMR_RWM)
3013
3014 /*! @brief Set the RWM field to a new value. */
3015 #define BW_I2S_RMR_RWM(x, v) (HW_I2S_RMR_WR(x, (HW_I2S_RMR_RD(x) & ~BM_I2S_RMR_RWM) | BF_I2S_RMR_RWM(v)))
3016 /*@}*/
3017
3018 /*******************************************************************************
3019  * HW_I2S_MCR - SAI MCLK Control Register
3020  ******************************************************************************/
3021
3022 /*!
3023  * @brief HW_I2S_MCR - SAI MCLK Control Register (RW)
3024  *
3025  * Reset value: 0x00000000U
3026  *
3027  * The MCLK Control Register (MCR) controls the clock source and direction of
3028  * the audio master clock.
3029  */
3030 typedef union _hw_i2s_mcr
3031 {
3032     uint32_t U;
3033     struct _hw_i2s_mcr_bitfields
3034     {
3035         uint32_t RESERVED0 : 24;       /*!< [23:0]  */
3036         uint32_t MICS : 2;             /*!< [25:24] MCLK Input Clock Select */
3037         uint32_t RESERVED1 : 4;        /*!< [29:26]  */
3038         uint32_t MOE : 1;              /*!< [30] MCLK Output Enable */
3039         uint32_t DUF : 1;              /*!< [31] Divider Update Flag */
3040     } B;
3041 } hw_i2s_mcr_t;
3042
3043 /*!
3044  * @name Constants and macros for entire I2S_MCR register
3045  */
3046 /*@{*/
3047 #define HW_I2S_MCR_ADDR(x)       ((x) + 0x100U)
3048
3049 #define HW_I2S_MCR(x)            (*(__IO hw_i2s_mcr_t *) HW_I2S_MCR_ADDR(x))
3050 #define HW_I2S_MCR_RD(x)         (HW_I2S_MCR(x).U)
3051 #define HW_I2S_MCR_WR(x, v)      (HW_I2S_MCR(x).U = (v))
3052 #define HW_I2S_MCR_SET(x, v)     (HW_I2S_MCR_WR(x, HW_I2S_MCR_RD(x) |  (v)))
3053 #define HW_I2S_MCR_CLR(x, v)     (HW_I2S_MCR_WR(x, HW_I2S_MCR_RD(x) & ~(v)))
3054 #define HW_I2S_MCR_TOG(x, v)     (HW_I2S_MCR_WR(x, HW_I2S_MCR_RD(x) ^  (v)))
3055 /*@}*/
3056
3057 /*
3058  * Constants & macros for individual I2S_MCR bitfields
3059  */
3060
3061 /*!
3062  * @name Register I2S_MCR, field MICS[25:24] (RW)
3063  *
3064  * Selects the clock input to the MCLK divider. This field cannot be changed
3065  * while the MCLK divider is enabled. See the chip configuration details for
3066  * information about the connections to these inputs.
3067  *
3068  * Values:
3069  * - 00 - MCLK divider input clock 0 selected.
3070  * - 01 - MCLK divider input clock 1 selected.
3071  * - 10 - MCLK divider input clock 2 selected.
3072  * - 11 - MCLK divider input clock 3 selected.
3073  */
3074 /*@{*/
3075 #define BP_I2S_MCR_MICS      (24U)         /*!< Bit position for I2S_MCR_MICS. */
3076 #define BM_I2S_MCR_MICS      (0x03000000U) /*!< Bit mask for I2S_MCR_MICS. */
3077 #define BS_I2S_MCR_MICS      (2U)          /*!< Bit field size in bits for I2S_MCR_MICS. */
3078
3079 /*! @brief Read current value of the I2S_MCR_MICS field. */
3080 #define BR_I2S_MCR_MICS(x)   (HW_I2S_MCR(x).B.MICS)
3081
3082 /*! @brief Format value for bitfield I2S_MCR_MICS. */
3083 #define BF_I2S_MCR_MICS(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_MCR_MICS) & BM_I2S_MCR_MICS)
3084
3085 /*! @brief Set the MICS field to a new value. */
3086 #define BW_I2S_MCR_MICS(x, v) (HW_I2S_MCR_WR(x, (HW_I2S_MCR_RD(x) & ~BM_I2S_MCR_MICS) | BF_I2S_MCR_MICS(v)))
3087 /*@}*/
3088
3089 /*!
3090  * @name Register I2S_MCR, field MOE[30] (RW)
3091  *
3092  * Enables the MCLK divider and configures the MCLK signal pin as an output.
3093  * When software clears this field, it remains set until the MCLK divider is fully
3094  * disabled.
3095  *
3096  * Values:
3097  * - 0 - MCLK signal pin is configured as an input that bypasses the MCLK
3098  *     divider.
3099  * - 1 - MCLK signal pin is configured as an output from the MCLK divider and
3100  *     the MCLK divider is enabled.
3101  */
3102 /*@{*/
3103 #define BP_I2S_MCR_MOE       (30U)         /*!< Bit position for I2S_MCR_MOE. */
3104 #define BM_I2S_MCR_MOE       (0x40000000U) /*!< Bit mask for I2S_MCR_MOE. */
3105 #define BS_I2S_MCR_MOE       (1U)          /*!< Bit field size in bits for I2S_MCR_MOE. */
3106
3107 /*! @brief Read current value of the I2S_MCR_MOE field. */
3108 #define BR_I2S_MCR_MOE(x)    (BITBAND_ACCESS32(HW_I2S_MCR_ADDR(x), BP_I2S_MCR_MOE))
3109
3110 /*! @brief Format value for bitfield I2S_MCR_MOE. */
3111 #define BF_I2S_MCR_MOE(v)    ((uint32_t)((uint32_t)(v) << BP_I2S_MCR_MOE) & BM_I2S_MCR_MOE)
3112
3113 /*! @brief Set the MOE field to a new value. */
3114 #define BW_I2S_MCR_MOE(x, v) (BITBAND_ACCESS32(HW_I2S_MCR_ADDR(x), BP_I2S_MCR_MOE) = (v))
3115 /*@}*/
3116
3117 /*!
3118  * @name Register I2S_MCR, field DUF[31] (RO)
3119  *
3120  * Provides the status of on-the-fly updates to the MCLK divider ratio.
3121  *
3122  * Values:
3123  * - 0 - MCLK divider ratio is not being updated currently.
3124  * - 1 - MCLK divider ratio is updating on-the-fly. Further updates to the MCLK
3125  *     divider ratio are blocked while this flag remains set.
3126  */
3127 /*@{*/
3128 #define BP_I2S_MCR_DUF       (31U)         /*!< Bit position for I2S_MCR_DUF. */
3129 #define BM_I2S_MCR_DUF       (0x80000000U) /*!< Bit mask for I2S_MCR_DUF. */
3130 #define BS_I2S_MCR_DUF       (1U)          /*!< Bit field size in bits for I2S_MCR_DUF. */
3131
3132 /*! @brief Read current value of the I2S_MCR_DUF field. */
3133 #define BR_I2S_MCR_DUF(x)    (BITBAND_ACCESS32(HW_I2S_MCR_ADDR(x), BP_I2S_MCR_DUF))
3134 /*@}*/
3135
3136 /*******************************************************************************
3137  * HW_I2S_MDR - SAI MCLK Divide Register
3138  ******************************************************************************/
3139
3140 /*!
3141  * @brief HW_I2S_MDR - SAI MCLK Divide Register (RW)
3142  *
3143  * Reset value: 0x00000000U
3144  *
3145  * The MCLK Divide Register (MDR) configures the MCLK divide ratio. Although the
3146  * MDR can be changed when the MCLK divider clock is enabled, additional writes
3147  * to the MDR are blocked while MCR[DUF] is set. Writes to the MDR when the MCLK
3148  * divided clock is disabled do not set MCR[DUF].
3149  */
3150 typedef union _hw_i2s_mdr
3151 {
3152     uint32_t U;
3153     struct _hw_i2s_mdr_bitfields
3154     {
3155         uint32_t DIVIDE : 12;          /*!< [11:0] MCLK Divide */
3156         uint32_t FRACT : 8;            /*!< [19:12] MCLK Fraction */
3157         uint32_t RESERVED0 : 12;       /*!< [31:20]  */
3158     } B;
3159 } hw_i2s_mdr_t;
3160
3161 /*!
3162  * @name Constants and macros for entire I2S_MDR register
3163  */
3164 /*@{*/
3165 #define HW_I2S_MDR_ADDR(x)       ((x) + 0x104U)
3166
3167 #define HW_I2S_MDR(x)            (*(__IO hw_i2s_mdr_t *) HW_I2S_MDR_ADDR(x))
3168 #define HW_I2S_MDR_RD(x)         (HW_I2S_MDR(x).U)
3169 #define HW_I2S_MDR_WR(x, v)      (HW_I2S_MDR(x).U = (v))
3170 #define HW_I2S_MDR_SET(x, v)     (HW_I2S_MDR_WR(x, HW_I2S_MDR_RD(x) |  (v)))
3171 #define HW_I2S_MDR_CLR(x, v)     (HW_I2S_MDR_WR(x, HW_I2S_MDR_RD(x) & ~(v)))
3172 #define HW_I2S_MDR_TOG(x, v)     (HW_I2S_MDR_WR(x, HW_I2S_MDR_RD(x) ^  (v)))
3173 /*@}*/
3174
3175 /*
3176  * Constants & macros for individual I2S_MDR bitfields
3177  */
3178
3179 /*!
3180  * @name Register I2S_MDR, field DIVIDE[11:0] (RW)
3181  *
3182  * Sets the MCLK divide ratio such that: MCLK output = MCLK input * ( (FRACT +
3183  * 1) / (DIVIDE + 1) ). FRACT must be set equal or less than the value in the
3184  * DIVIDE field.
3185  */
3186 /*@{*/
3187 #define BP_I2S_MDR_DIVIDE    (0U)          /*!< Bit position for I2S_MDR_DIVIDE. */
3188 #define BM_I2S_MDR_DIVIDE    (0x00000FFFU) /*!< Bit mask for I2S_MDR_DIVIDE. */
3189 #define BS_I2S_MDR_DIVIDE    (12U)         /*!< Bit field size in bits for I2S_MDR_DIVIDE. */
3190
3191 /*! @brief Read current value of the I2S_MDR_DIVIDE field. */
3192 #define BR_I2S_MDR_DIVIDE(x) (HW_I2S_MDR(x).B.DIVIDE)
3193
3194 /*! @brief Format value for bitfield I2S_MDR_DIVIDE. */
3195 #define BF_I2S_MDR_DIVIDE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_MDR_DIVIDE) & BM_I2S_MDR_DIVIDE)
3196
3197 /*! @brief Set the DIVIDE field to a new value. */
3198 #define BW_I2S_MDR_DIVIDE(x, v) (HW_I2S_MDR_WR(x, (HW_I2S_MDR_RD(x) & ~BM_I2S_MDR_DIVIDE) | BF_I2S_MDR_DIVIDE(v)))
3199 /*@}*/
3200
3201 /*!
3202  * @name Register I2S_MDR, field FRACT[19:12] (RW)
3203  *
3204  * Sets the MCLK divide ratio such that: MCLK output = MCLK input * ( (FRACT +
3205  * 1) / (DIVIDE + 1) ). FRACT must be set equal or less than the value in the
3206  * DIVIDE field.
3207  */
3208 /*@{*/
3209 #define BP_I2S_MDR_FRACT     (12U)         /*!< Bit position for I2S_MDR_FRACT. */
3210 #define BM_I2S_MDR_FRACT     (0x000FF000U) /*!< Bit mask for I2S_MDR_FRACT. */
3211 #define BS_I2S_MDR_FRACT     (8U)          /*!< Bit field size in bits for I2S_MDR_FRACT. */
3212
3213 /*! @brief Read current value of the I2S_MDR_FRACT field. */
3214 #define BR_I2S_MDR_FRACT(x)  (HW_I2S_MDR(x).B.FRACT)
3215
3216 /*! @brief Format value for bitfield I2S_MDR_FRACT. */
3217 #define BF_I2S_MDR_FRACT(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_MDR_FRACT) & BM_I2S_MDR_FRACT)
3218
3219 /*! @brief Set the FRACT field to a new value. */
3220 #define BW_I2S_MDR_FRACT(x, v) (HW_I2S_MDR_WR(x, (HW_I2S_MDR_RD(x) & ~BM_I2S_MDR_FRACT) | BF_I2S_MDR_FRACT(v)))
3221 /*@}*/
3222
3223 /*******************************************************************************
3224  * hw_i2s_t - module struct
3225  ******************************************************************************/
3226 /*!
3227  * @brief All I2S module registers.
3228  */
3229 #pragma pack(1)
3230 typedef struct _hw_i2s
3231 {
3232     __IO hw_i2s_tcsr_t TCSR;               /*!< [0x0] SAI Transmit Control Register */
3233     __IO hw_i2s_tcr1_t TCR1;               /*!< [0x4] SAI Transmit Configuration 1 Register */
3234     __IO hw_i2s_tcr2_t TCR2;               /*!< [0x8] SAI Transmit Configuration 2 Register */
3235     __IO hw_i2s_tcr3_t TCR3;               /*!< [0xC] SAI Transmit Configuration 3 Register */
3236     __IO hw_i2s_tcr4_t TCR4;               /*!< [0x10] SAI Transmit Configuration 4 Register */
3237     __IO hw_i2s_tcr5_t TCR5;               /*!< [0x14] SAI Transmit Configuration 5 Register */
3238     uint8_t _reserved0[8];
3239     __O hw_i2s_tdrn_t TDRn[1];             /*!< [0x20] SAI Transmit Data Register */
3240     uint8_t _reserved1[28];
3241     __I hw_i2s_tfrn_t TFRn[1];             /*!< [0x40] SAI Transmit FIFO Register */
3242     uint8_t _reserved2[28];
3243     __IO hw_i2s_tmr_t TMR;                 /*!< [0x60] SAI Transmit Mask Register */
3244     uint8_t _reserved3[28];
3245     __IO hw_i2s_rcsr_t RCSR;               /*!< [0x80] SAI Receive Control Register */
3246     __IO hw_i2s_rcr1_t RCR1;               /*!< [0x84] SAI Receive Configuration 1 Register */
3247     __IO hw_i2s_rcr2_t RCR2;               /*!< [0x88] SAI Receive Configuration 2 Register */
3248     __IO hw_i2s_rcr3_t RCR3;               /*!< [0x8C] SAI Receive Configuration 3 Register */
3249     __IO hw_i2s_rcr4_t RCR4;               /*!< [0x90] SAI Receive Configuration 4 Register */
3250     __IO hw_i2s_rcr5_t RCR5;               /*!< [0x94] SAI Receive Configuration 5 Register */
3251     uint8_t _reserved4[8];
3252     __I hw_i2s_rdrn_t RDRn[1];             /*!< [0xA0] SAI Receive Data Register */
3253     uint8_t _reserved5[28];
3254     __I hw_i2s_rfrn_t RFRn[1];             /*!< [0xC0] SAI Receive FIFO Register */
3255     uint8_t _reserved6[28];
3256     __IO hw_i2s_rmr_t RMR;                 /*!< [0xE0] SAI Receive Mask Register */
3257     uint8_t _reserved7[28];
3258     __IO hw_i2s_mcr_t MCR;                 /*!< [0x100] SAI MCLK Control Register */
3259     __IO hw_i2s_mdr_t MDR;                 /*!< [0x104] SAI MCLK Divide Register */
3260 } hw_i2s_t;
3261 #pragma pack()
3262
3263 /*! @brief Macro to access all I2S registers. */
3264 /*! @param x I2S module instance base address. */
3265 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
3266  *     use the '&' operator, like <code>&HW_I2S(I2S0_BASE)</code>. */
3267 #define HW_I2S(x)      (*(hw_i2s_t *)(x))
3268
3269 #endif /* __HW_I2S_REGISTERS_H__ */
3270 /* EOF */