2 ** ###################################################################
3 ** Compilers: Keil ARM C/C++ Compiler
4 ** Freescale C/C++ for Embedded ARM
6 ** IAR ANSI C/C++ Compiler for ARM
8 ** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
9 ** Version: rev. 2.5, 2014-05-06
13 ** Extension to the CMSIS register access layer header.
15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
16 ** All rights reserved.
18 ** Redistribution and use in source and binary forms, with or without modification,
19 ** are permitted provided that the following conditions are met:
21 ** o Redistributions of source code must retain the above copyright notice, this list
22 ** of conditions and the following disclaimer.
24 ** o Redistributions in binary form must reproduce the above copyright notice, this
25 ** list of conditions and the following disclaimer in the documentation and/or
26 ** other materials provided with the distribution.
28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
29 ** contributors may be used to endorse or promote products derived from this
30 ** software without specific prior written permission.
32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 ** http: www.freescale.com
44 ** mail: support@freescale.com
47 ** - rev. 1.0 (2013-07-23)
49 ** - rev. 1.1 (2013-09-17)
50 ** RM rev. 0.4 update.
51 ** - rev. 2.0 (2013-10-29)
52 ** Register accessor macros added to the memory map.
53 ** Symbols for Processor Expert memory map compatibility added to the memory map.
54 ** Startup file for gcc has been updated according to CMSIS 3.2.
55 ** System initialization updated.
56 ** - rev. 2.1 (2013-10-30)
57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
58 ** - rev. 2.2 (2013-12-20)
59 ** Update according to reference manual rev. 0.6,
60 ** - rev. 2.3 (2014-01-13)
61 ** Update according to reference manual rev. 0.61,
62 ** - rev. 2.4 (2014-02-10)
63 ** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
64 ** - rev. 2.5 (2014-05-06)
65 ** Update according to reference manual rev. 1.0,
66 ** Update of system and startup files.
67 ** Module access macro module_BASES replaced by module_BASE_PTRS.
69 ** ###################################################################
73 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
75 * This file was generated automatically and any changes may be lost.
77 #ifndef __HW_LLWU_REGISTERS_H__
78 #define __HW_LLWU_REGISTERS_H__
80 #include "MK22F51212.h"
81 #include "fsl_bitaccess.h"
86 * Low leakage wakeup unit
88 * Registers defined in this header file:
89 * - HW_LLWU_PE1 - LLWU Pin Enable 1 register
90 * - HW_LLWU_PE2 - LLWU Pin Enable 2 register
91 * - HW_LLWU_PE3 - LLWU Pin Enable 3 register
92 * - HW_LLWU_PE4 - LLWU Pin Enable 4 register
93 * - HW_LLWU_ME - LLWU Module Enable register
94 * - HW_LLWU_F1 - LLWU Flag 1 register
95 * - HW_LLWU_F2 - LLWU Flag 2 register
96 * - HW_LLWU_F3 - LLWU Flag 3 register
97 * - HW_LLWU_FILT1 - LLWU Pin Filter 1 register
98 * - HW_LLWU_FILT2 - LLWU Pin Filter 2 register
100 * - hw_llwu_t - Struct containing all module registers.
103 #define HW_LLWU_INSTANCE_COUNT (1U) /*!< Number of instances of the LLWU module. */
105 /*******************************************************************************
106 * HW_LLWU_PE1 - LLWU Pin Enable 1 register
107 ******************************************************************************/
110 * @brief HW_LLWU_PE1 - LLWU Pin Enable 1 register (RW)
114 * LLWU_PE1 contains the field to enable and select the edge detect type for the
115 * external wakeup input pins LLWU_P3-LLWU_P0. This register is reset on Chip
116 * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
117 * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
118 * IntroductionInformation found here describes the registers of the Reset Control Module
119 * (RCM). The RCM implements many of the reset functions for the chip. See the
120 * chip's reset chapter for more information. details for more information.
122 typedef union _hw_llwu_pe1
125 struct _hw_llwu_pe1_bitfields
127 uint8_t WUPE0
: 2; /*!< [1:0] Wakeup Pin Enable For LLWU_P0 */
128 uint8_t WUPE1
: 2; /*!< [3:2] Wakeup Pin Enable For LLWU_P1 */
129 uint8_t WUPE2
: 2; /*!< [5:4] Wakeup Pin Enable For LLWU_P2 */
130 uint8_t WUPE3
: 2; /*!< [7:6] Wakeup Pin Enable For LLWU_P3 */
135 * @name Constants and macros for entire LLWU_PE1 register
138 #define HW_LLWU_PE1_ADDR(x) ((x) + 0x0U)
140 #define HW_LLWU_PE1(x) (*(__IO hw_llwu_pe1_t *) HW_LLWU_PE1_ADDR(x))
141 #define HW_LLWU_PE1_RD(x) (HW_LLWU_PE1(x).U)
142 #define HW_LLWU_PE1_WR(x, v) (HW_LLWU_PE1(x).U = (v))
143 #define HW_LLWU_PE1_SET(x, v) (HW_LLWU_PE1_WR(x, HW_LLWU_PE1_RD(x) | (v)))
144 #define HW_LLWU_PE1_CLR(x, v) (HW_LLWU_PE1_WR(x, HW_LLWU_PE1_RD(x) & ~(v)))
145 #define HW_LLWU_PE1_TOG(x, v) (HW_LLWU_PE1_WR(x, HW_LLWU_PE1_RD(x) ^ (v)))
149 * Constants & macros for individual LLWU_PE1 bitfields
153 * @name Register LLWU_PE1, field WUPE0[1:0] (RW)
155 * Enables and configures the edge detection for the wakeup pin.
158 * - 00 - External input pin disabled as wakeup input
159 * - 01 - External input pin enabled with rising edge detection
160 * - 10 - External input pin enabled with falling edge detection
161 * - 11 - External input pin enabled with any change detection
164 #define BP_LLWU_PE1_WUPE0 (0U) /*!< Bit position for LLWU_PE1_WUPE0. */
165 #define BM_LLWU_PE1_WUPE0 (0x03U) /*!< Bit mask for LLWU_PE1_WUPE0. */
166 #define BS_LLWU_PE1_WUPE0 (2U) /*!< Bit field size in bits for LLWU_PE1_WUPE0. */
168 /*! @brief Read current value of the LLWU_PE1_WUPE0 field. */
169 #define BR_LLWU_PE1_WUPE0(x) (HW_LLWU_PE1(x).B.WUPE0)
171 /*! @brief Format value for bitfield LLWU_PE1_WUPE0. */
172 #define BF_LLWU_PE1_WUPE0(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE1_WUPE0) & BM_LLWU_PE1_WUPE0)
174 /*! @brief Set the WUPE0 field to a new value. */
175 #define BW_LLWU_PE1_WUPE0(x, v) (HW_LLWU_PE1_WR(x, (HW_LLWU_PE1_RD(x) & ~BM_LLWU_PE1_WUPE0) | BF_LLWU_PE1_WUPE0(v)))
179 * @name Register LLWU_PE1, field WUPE1[3:2] (RW)
181 * Enables and configures the edge detection for the wakeup pin.
184 * - 00 - External input pin disabled as wakeup input
185 * - 01 - External input pin enabled with rising edge detection
186 * - 10 - External input pin enabled with falling edge detection
187 * - 11 - External input pin enabled with any change detection
190 #define BP_LLWU_PE1_WUPE1 (2U) /*!< Bit position for LLWU_PE1_WUPE1. */
191 #define BM_LLWU_PE1_WUPE1 (0x0CU) /*!< Bit mask for LLWU_PE1_WUPE1. */
192 #define BS_LLWU_PE1_WUPE1 (2U) /*!< Bit field size in bits for LLWU_PE1_WUPE1. */
194 /*! @brief Read current value of the LLWU_PE1_WUPE1 field. */
195 #define BR_LLWU_PE1_WUPE1(x) (HW_LLWU_PE1(x).B.WUPE1)
197 /*! @brief Format value for bitfield LLWU_PE1_WUPE1. */
198 #define BF_LLWU_PE1_WUPE1(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE1_WUPE1) & BM_LLWU_PE1_WUPE1)
200 /*! @brief Set the WUPE1 field to a new value. */
201 #define BW_LLWU_PE1_WUPE1(x, v) (HW_LLWU_PE1_WR(x, (HW_LLWU_PE1_RD(x) & ~BM_LLWU_PE1_WUPE1) | BF_LLWU_PE1_WUPE1(v)))
205 * @name Register LLWU_PE1, field WUPE2[5:4] (RW)
207 * Enables and configures the edge detection for the wakeup pin.
210 * - 00 - External input pin disabled as wakeup input
211 * - 01 - External input pin enabled with rising edge detection
212 * - 10 - External input pin enabled with falling edge detection
213 * - 11 - External input pin enabled with any change detection
216 #define BP_LLWU_PE1_WUPE2 (4U) /*!< Bit position for LLWU_PE1_WUPE2. */
217 #define BM_LLWU_PE1_WUPE2 (0x30U) /*!< Bit mask for LLWU_PE1_WUPE2. */
218 #define BS_LLWU_PE1_WUPE2 (2U) /*!< Bit field size in bits for LLWU_PE1_WUPE2. */
220 /*! @brief Read current value of the LLWU_PE1_WUPE2 field. */
221 #define BR_LLWU_PE1_WUPE2(x) (HW_LLWU_PE1(x).B.WUPE2)
223 /*! @brief Format value for bitfield LLWU_PE1_WUPE2. */
224 #define BF_LLWU_PE1_WUPE2(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE1_WUPE2) & BM_LLWU_PE1_WUPE2)
226 /*! @brief Set the WUPE2 field to a new value. */
227 #define BW_LLWU_PE1_WUPE2(x, v) (HW_LLWU_PE1_WR(x, (HW_LLWU_PE1_RD(x) & ~BM_LLWU_PE1_WUPE2) | BF_LLWU_PE1_WUPE2(v)))
231 * @name Register LLWU_PE1, field WUPE3[7:6] (RW)
233 * Enables and configures the edge detection for the wakeup pin.
236 * - 00 - External input pin disabled as wakeup input
237 * - 01 - External input pin enabled with rising edge detection
238 * - 10 - External input pin enabled with falling edge detection
239 * - 11 - External input pin enabled with any change detection
242 #define BP_LLWU_PE1_WUPE3 (6U) /*!< Bit position for LLWU_PE1_WUPE3. */
243 #define BM_LLWU_PE1_WUPE3 (0xC0U) /*!< Bit mask for LLWU_PE1_WUPE3. */
244 #define BS_LLWU_PE1_WUPE3 (2U) /*!< Bit field size in bits for LLWU_PE1_WUPE3. */
246 /*! @brief Read current value of the LLWU_PE1_WUPE3 field. */
247 #define BR_LLWU_PE1_WUPE3(x) (HW_LLWU_PE1(x).B.WUPE3)
249 /*! @brief Format value for bitfield LLWU_PE1_WUPE3. */
250 #define BF_LLWU_PE1_WUPE3(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE1_WUPE3) & BM_LLWU_PE1_WUPE3)
252 /*! @brief Set the WUPE3 field to a new value. */
253 #define BW_LLWU_PE1_WUPE3(x, v) (HW_LLWU_PE1_WR(x, (HW_LLWU_PE1_RD(x) & ~BM_LLWU_PE1_WUPE3) | BF_LLWU_PE1_WUPE3(v)))
256 /*******************************************************************************
257 * HW_LLWU_PE2 - LLWU Pin Enable 2 register
258 ******************************************************************************/
261 * @brief HW_LLWU_PE2 - LLWU Pin Enable 2 register (RW)
265 * LLWU_PE2 contains the field to enable and select the edge detect type for the
266 * external wakeup input pins LLWU_P7-LLWU_P4. This register is reset on Chip
267 * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
268 * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
269 * IntroductionInformation found here describes the registers of the Reset Control Module
270 * (RCM). The RCM implements many of the reset functions for the chip. See the
271 * chip's reset chapter for more information. details for more information.
273 typedef union _hw_llwu_pe2
276 struct _hw_llwu_pe2_bitfields
278 uint8_t WUPE4
: 2; /*!< [1:0] Wakeup Pin Enable For LLWU_P4 */
279 uint8_t WUPE5
: 2; /*!< [3:2] Wakeup Pin Enable For LLWU_P5 */
280 uint8_t WUPE6
: 2; /*!< [5:4] Wakeup Pin Enable For LLWU_P6 */
281 uint8_t WUPE7
: 2; /*!< [7:6] Wakeup Pin Enable For LLWU_P7 */
286 * @name Constants and macros for entire LLWU_PE2 register
289 #define HW_LLWU_PE2_ADDR(x) ((x) + 0x1U)
291 #define HW_LLWU_PE2(x) (*(__IO hw_llwu_pe2_t *) HW_LLWU_PE2_ADDR(x))
292 #define HW_LLWU_PE2_RD(x) (HW_LLWU_PE2(x).U)
293 #define HW_LLWU_PE2_WR(x, v) (HW_LLWU_PE2(x).U = (v))
294 #define HW_LLWU_PE2_SET(x, v) (HW_LLWU_PE2_WR(x, HW_LLWU_PE2_RD(x) | (v)))
295 #define HW_LLWU_PE2_CLR(x, v) (HW_LLWU_PE2_WR(x, HW_LLWU_PE2_RD(x) & ~(v)))
296 #define HW_LLWU_PE2_TOG(x, v) (HW_LLWU_PE2_WR(x, HW_LLWU_PE2_RD(x) ^ (v)))
300 * Constants & macros for individual LLWU_PE2 bitfields
304 * @name Register LLWU_PE2, field WUPE4[1:0] (RW)
306 * Enables and configures the edge detection for the wakeup pin.
309 * - 00 - External input pin disabled as wakeup input
310 * - 01 - External input pin enabled with rising edge detection
311 * - 10 - External input pin enabled with falling edge detection
312 * - 11 - External input pin enabled with any change detection
315 #define BP_LLWU_PE2_WUPE4 (0U) /*!< Bit position for LLWU_PE2_WUPE4. */
316 #define BM_LLWU_PE2_WUPE4 (0x03U) /*!< Bit mask for LLWU_PE2_WUPE4. */
317 #define BS_LLWU_PE2_WUPE4 (2U) /*!< Bit field size in bits for LLWU_PE2_WUPE4. */
319 /*! @brief Read current value of the LLWU_PE2_WUPE4 field. */
320 #define BR_LLWU_PE2_WUPE4(x) (HW_LLWU_PE2(x).B.WUPE4)
322 /*! @brief Format value for bitfield LLWU_PE2_WUPE4. */
323 #define BF_LLWU_PE2_WUPE4(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE2_WUPE4) & BM_LLWU_PE2_WUPE4)
325 /*! @brief Set the WUPE4 field to a new value. */
326 #define BW_LLWU_PE2_WUPE4(x, v) (HW_LLWU_PE2_WR(x, (HW_LLWU_PE2_RD(x) & ~BM_LLWU_PE2_WUPE4) | BF_LLWU_PE2_WUPE4(v)))
330 * @name Register LLWU_PE2, field WUPE5[3:2] (RW)
332 * Enables and configures the edge detection for the wakeup pin.
335 * - 00 - External input pin disabled as wakeup input
336 * - 01 - External input pin enabled with rising edge detection
337 * - 10 - External input pin enabled with falling edge detection
338 * - 11 - External input pin enabled with any change detection
341 #define BP_LLWU_PE2_WUPE5 (2U) /*!< Bit position for LLWU_PE2_WUPE5. */
342 #define BM_LLWU_PE2_WUPE5 (0x0CU) /*!< Bit mask for LLWU_PE2_WUPE5. */
343 #define BS_LLWU_PE2_WUPE5 (2U) /*!< Bit field size in bits for LLWU_PE2_WUPE5. */
345 /*! @brief Read current value of the LLWU_PE2_WUPE5 field. */
346 #define BR_LLWU_PE2_WUPE5(x) (HW_LLWU_PE2(x).B.WUPE5)
348 /*! @brief Format value for bitfield LLWU_PE2_WUPE5. */
349 #define BF_LLWU_PE2_WUPE5(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE2_WUPE5) & BM_LLWU_PE2_WUPE5)
351 /*! @brief Set the WUPE5 field to a new value. */
352 #define BW_LLWU_PE2_WUPE5(x, v) (HW_LLWU_PE2_WR(x, (HW_LLWU_PE2_RD(x) & ~BM_LLWU_PE2_WUPE5) | BF_LLWU_PE2_WUPE5(v)))
356 * @name Register LLWU_PE2, field WUPE6[5:4] (RW)
358 * Enables and configures the edge detection for the wakeup pin.
361 * - 00 - External input pin disabled as wakeup input
362 * - 01 - External input pin enabled with rising edge detection
363 * - 10 - External input pin enabled with falling edge detection
364 * - 11 - External input pin enabled with any change detection
367 #define BP_LLWU_PE2_WUPE6 (4U) /*!< Bit position for LLWU_PE2_WUPE6. */
368 #define BM_LLWU_PE2_WUPE6 (0x30U) /*!< Bit mask for LLWU_PE2_WUPE6. */
369 #define BS_LLWU_PE2_WUPE6 (2U) /*!< Bit field size in bits for LLWU_PE2_WUPE6. */
371 /*! @brief Read current value of the LLWU_PE2_WUPE6 field. */
372 #define BR_LLWU_PE2_WUPE6(x) (HW_LLWU_PE2(x).B.WUPE6)
374 /*! @brief Format value for bitfield LLWU_PE2_WUPE6. */
375 #define BF_LLWU_PE2_WUPE6(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE2_WUPE6) & BM_LLWU_PE2_WUPE6)
377 /*! @brief Set the WUPE6 field to a new value. */
378 #define BW_LLWU_PE2_WUPE6(x, v) (HW_LLWU_PE2_WR(x, (HW_LLWU_PE2_RD(x) & ~BM_LLWU_PE2_WUPE6) | BF_LLWU_PE2_WUPE6(v)))
382 * @name Register LLWU_PE2, field WUPE7[7:6] (RW)
384 * Enables and configures the edge detection for the wakeup pin.
387 * - 00 - External input pin disabled as wakeup input
388 * - 01 - External input pin enabled with rising edge detection
389 * - 10 - External input pin enabled with falling edge detection
390 * - 11 - External input pin enabled with any change detection
393 #define BP_LLWU_PE2_WUPE7 (6U) /*!< Bit position for LLWU_PE2_WUPE7. */
394 #define BM_LLWU_PE2_WUPE7 (0xC0U) /*!< Bit mask for LLWU_PE2_WUPE7. */
395 #define BS_LLWU_PE2_WUPE7 (2U) /*!< Bit field size in bits for LLWU_PE2_WUPE7. */
397 /*! @brief Read current value of the LLWU_PE2_WUPE7 field. */
398 #define BR_LLWU_PE2_WUPE7(x) (HW_LLWU_PE2(x).B.WUPE7)
400 /*! @brief Format value for bitfield LLWU_PE2_WUPE7. */
401 #define BF_LLWU_PE2_WUPE7(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE2_WUPE7) & BM_LLWU_PE2_WUPE7)
403 /*! @brief Set the WUPE7 field to a new value. */
404 #define BW_LLWU_PE2_WUPE7(x, v) (HW_LLWU_PE2_WR(x, (HW_LLWU_PE2_RD(x) & ~BM_LLWU_PE2_WUPE7) | BF_LLWU_PE2_WUPE7(v)))
407 /*******************************************************************************
408 * HW_LLWU_PE3 - LLWU Pin Enable 3 register
409 ******************************************************************************/
412 * @brief HW_LLWU_PE3 - LLWU Pin Enable 3 register (RW)
416 * LLWU_PE3 contains the field to enable and select the edge detect type for the
417 * external wakeup input pins LLWU_P11-LLWU_P8. This register is reset on Chip
418 * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
419 * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
420 * IntroductionInformation found here describes the registers of the Reset Control Module
421 * (RCM). The RCM implements many of the reset functions for the chip. See the
422 * chip's reset chapter for more information. details for more information.
424 typedef union _hw_llwu_pe3
427 struct _hw_llwu_pe3_bitfields
429 uint8_t WUPE8
: 2; /*!< [1:0] Wakeup Pin Enable For LLWU_P8 */
430 uint8_t WUPE9
: 2; /*!< [3:2] Wakeup Pin Enable For LLWU_P9 */
431 uint8_t WUPE10
: 2; /*!< [5:4] Wakeup Pin Enable For LLWU_P10 */
432 uint8_t WUPE11
: 2; /*!< [7:6] Wakeup Pin Enable For LLWU_P11 */
437 * @name Constants and macros for entire LLWU_PE3 register
440 #define HW_LLWU_PE3_ADDR(x) ((x) + 0x2U)
442 #define HW_LLWU_PE3(x) (*(__IO hw_llwu_pe3_t *) HW_LLWU_PE3_ADDR(x))
443 #define HW_LLWU_PE3_RD(x) (HW_LLWU_PE3(x).U)
444 #define HW_LLWU_PE3_WR(x, v) (HW_LLWU_PE3(x).U = (v))
445 #define HW_LLWU_PE3_SET(x, v) (HW_LLWU_PE3_WR(x, HW_LLWU_PE3_RD(x) | (v)))
446 #define HW_LLWU_PE3_CLR(x, v) (HW_LLWU_PE3_WR(x, HW_LLWU_PE3_RD(x) & ~(v)))
447 #define HW_LLWU_PE3_TOG(x, v) (HW_LLWU_PE3_WR(x, HW_LLWU_PE3_RD(x) ^ (v)))
451 * Constants & macros for individual LLWU_PE3 bitfields
455 * @name Register LLWU_PE3, field WUPE8[1:0] (RW)
457 * Enables and configures the edge detection for the wakeup pin.
460 * - 00 - External input pin disabled as wakeup input
461 * - 01 - External input pin enabled with rising edge detection
462 * - 10 - External input pin enabled with falling edge detection
463 * - 11 - External input pin enabled with any change detection
466 #define BP_LLWU_PE3_WUPE8 (0U) /*!< Bit position for LLWU_PE3_WUPE8. */
467 #define BM_LLWU_PE3_WUPE8 (0x03U) /*!< Bit mask for LLWU_PE3_WUPE8. */
468 #define BS_LLWU_PE3_WUPE8 (2U) /*!< Bit field size in bits for LLWU_PE3_WUPE8. */
470 /*! @brief Read current value of the LLWU_PE3_WUPE8 field. */
471 #define BR_LLWU_PE3_WUPE8(x) (HW_LLWU_PE3(x).B.WUPE8)
473 /*! @brief Format value for bitfield LLWU_PE3_WUPE8. */
474 #define BF_LLWU_PE3_WUPE8(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE3_WUPE8) & BM_LLWU_PE3_WUPE8)
476 /*! @brief Set the WUPE8 field to a new value. */
477 #define BW_LLWU_PE3_WUPE8(x, v) (HW_LLWU_PE3_WR(x, (HW_LLWU_PE3_RD(x) & ~BM_LLWU_PE3_WUPE8) | BF_LLWU_PE3_WUPE8(v)))
481 * @name Register LLWU_PE3, field WUPE9[3:2] (RW)
483 * Enables and configures the edge detection for the wakeup pin.
486 * - 00 - External input pin disabled as wakeup input
487 * - 01 - External input pin enabled with rising edge detection
488 * - 10 - External input pin enabled with falling edge detection
489 * - 11 - External input pin enabled with any change detection
492 #define BP_LLWU_PE3_WUPE9 (2U) /*!< Bit position for LLWU_PE3_WUPE9. */
493 #define BM_LLWU_PE3_WUPE9 (0x0CU) /*!< Bit mask for LLWU_PE3_WUPE9. */
494 #define BS_LLWU_PE3_WUPE9 (2U) /*!< Bit field size in bits for LLWU_PE3_WUPE9. */
496 /*! @brief Read current value of the LLWU_PE3_WUPE9 field. */
497 #define BR_LLWU_PE3_WUPE9(x) (HW_LLWU_PE3(x).B.WUPE9)
499 /*! @brief Format value for bitfield LLWU_PE3_WUPE9. */
500 #define BF_LLWU_PE3_WUPE9(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE3_WUPE9) & BM_LLWU_PE3_WUPE9)
502 /*! @brief Set the WUPE9 field to a new value. */
503 #define BW_LLWU_PE3_WUPE9(x, v) (HW_LLWU_PE3_WR(x, (HW_LLWU_PE3_RD(x) & ~BM_LLWU_PE3_WUPE9) | BF_LLWU_PE3_WUPE9(v)))
507 * @name Register LLWU_PE3, field WUPE10[5:4] (RW)
509 * Enables and configures the edge detection for the wakeup pin.
512 * - 00 - External input pin disabled as wakeup input
513 * - 01 - External input pin enabled with rising edge detection
514 * - 10 - External input pin enabled with falling edge detection
515 * - 11 - External input pin enabled with any change detection
518 #define BP_LLWU_PE3_WUPE10 (4U) /*!< Bit position for LLWU_PE3_WUPE10. */
519 #define BM_LLWU_PE3_WUPE10 (0x30U) /*!< Bit mask for LLWU_PE3_WUPE10. */
520 #define BS_LLWU_PE3_WUPE10 (2U) /*!< Bit field size in bits for LLWU_PE3_WUPE10. */
522 /*! @brief Read current value of the LLWU_PE3_WUPE10 field. */
523 #define BR_LLWU_PE3_WUPE10(x) (HW_LLWU_PE3(x).B.WUPE10)
525 /*! @brief Format value for bitfield LLWU_PE3_WUPE10. */
526 #define BF_LLWU_PE3_WUPE10(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE3_WUPE10) & BM_LLWU_PE3_WUPE10)
528 /*! @brief Set the WUPE10 field to a new value. */
529 #define BW_LLWU_PE3_WUPE10(x, v) (HW_LLWU_PE3_WR(x, (HW_LLWU_PE3_RD(x) & ~BM_LLWU_PE3_WUPE10) | BF_LLWU_PE3_WUPE10(v)))
533 * @name Register LLWU_PE3, field WUPE11[7:6] (RW)
535 * Enables and configures the edge detection for the wakeup pin.
538 * - 00 - External input pin disabled as wakeup input
539 * - 01 - External input pin enabled with rising edge detection
540 * - 10 - External input pin enabled with falling edge detection
541 * - 11 - External input pin enabled with any change detection
544 #define BP_LLWU_PE3_WUPE11 (6U) /*!< Bit position for LLWU_PE3_WUPE11. */
545 #define BM_LLWU_PE3_WUPE11 (0xC0U) /*!< Bit mask for LLWU_PE3_WUPE11. */
546 #define BS_LLWU_PE3_WUPE11 (2U) /*!< Bit field size in bits for LLWU_PE3_WUPE11. */
548 /*! @brief Read current value of the LLWU_PE3_WUPE11 field. */
549 #define BR_LLWU_PE3_WUPE11(x) (HW_LLWU_PE3(x).B.WUPE11)
551 /*! @brief Format value for bitfield LLWU_PE3_WUPE11. */
552 #define BF_LLWU_PE3_WUPE11(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE3_WUPE11) & BM_LLWU_PE3_WUPE11)
554 /*! @brief Set the WUPE11 field to a new value. */
555 #define BW_LLWU_PE3_WUPE11(x, v) (HW_LLWU_PE3_WR(x, (HW_LLWU_PE3_RD(x) & ~BM_LLWU_PE3_WUPE11) | BF_LLWU_PE3_WUPE11(v)))
558 /*******************************************************************************
559 * HW_LLWU_PE4 - LLWU Pin Enable 4 register
560 ******************************************************************************/
563 * @brief HW_LLWU_PE4 - LLWU Pin Enable 4 register (RW)
567 * LLWU_PE4 contains the field to enable and select the edge detect type for the
568 * external wakeup input pins LLWU_P15-LLWU_P12. This register is reset on Chip
569 * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
570 * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
571 * IntroductionInformation found here describes the registers of the Reset Control
572 * Module (RCM). The RCM implements many of the reset functions for the chip. See the
573 * chip's reset chapter for more information. details for more information.
575 typedef union _hw_llwu_pe4
578 struct _hw_llwu_pe4_bitfields
580 uint8_t WUPE12
: 2; /*!< [1:0] Wakeup Pin Enable For LLWU_P12 */
581 uint8_t WUPE13
: 2; /*!< [3:2] Wakeup Pin Enable For LLWU_P13 */
582 uint8_t WUPE14
: 2; /*!< [5:4] Wakeup Pin Enable For LLWU_P14 */
583 uint8_t WUPE15
: 2; /*!< [7:6] Wakeup Pin Enable For LLWU_P15 */
588 * @name Constants and macros for entire LLWU_PE4 register
591 #define HW_LLWU_PE4_ADDR(x) ((x) + 0x3U)
593 #define HW_LLWU_PE4(x) (*(__IO hw_llwu_pe4_t *) HW_LLWU_PE4_ADDR(x))
594 #define HW_LLWU_PE4_RD(x) (HW_LLWU_PE4(x).U)
595 #define HW_LLWU_PE4_WR(x, v) (HW_LLWU_PE4(x).U = (v))
596 #define HW_LLWU_PE4_SET(x, v) (HW_LLWU_PE4_WR(x, HW_LLWU_PE4_RD(x) | (v)))
597 #define HW_LLWU_PE4_CLR(x, v) (HW_LLWU_PE4_WR(x, HW_LLWU_PE4_RD(x) & ~(v)))
598 #define HW_LLWU_PE4_TOG(x, v) (HW_LLWU_PE4_WR(x, HW_LLWU_PE4_RD(x) ^ (v)))
602 * Constants & macros for individual LLWU_PE4 bitfields
606 * @name Register LLWU_PE4, field WUPE12[1:0] (RW)
608 * Enables and configures the edge detection for the wakeup pin.
611 * - 00 - External input pin disabled as wakeup input
612 * - 01 - External input pin enabled with rising edge detection
613 * - 10 - External input pin enabled with falling edge detection
614 * - 11 - External input pin enabled with any change detection
617 #define BP_LLWU_PE4_WUPE12 (0U) /*!< Bit position for LLWU_PE4_WUPE12. */
618 #define BM_LLWU_PE4_WUPE12 (0x03U) /*!< Bit mask for LLWU_PE4_WUPE12. */
619 #define BS_LLWU_PE4_WUPE12 (2U) /*!< Bit field size in bits for LLWU_PE4_WUPE12. */
621 /*! @brief Read current value of the LLWU_PE4_WUPE12 field. */
622 #define BR_LLWU_PE4_WUPE12(x) (HW_LLWU_PE4(x).B.WUPE12)
624 /*! @brief Format value for bitfield LLWU_PE4_WUPE12. */
625 #define BF_LLWU_PE4_WUPE12(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE4_WUPE12) & BM_LLWU_PE4_WUPE12)
627 /*! @brief Set the WUPE12 field to a new value. */
628 #define BW_LLWU_PE4_WUPE12(x, v) (HW_LLWU_PE4_WR(x, (HW_LLWU_PE4_RD(x) & ~BM_LLWU_PE4_WUPE12) | BF_LLWU_PE4_WUPE12(v)))
632 * @name Register LLWU_PE4, field WUPE13[3:2] (RW)
634 * Enables and configures the edge detection for the wakeup pin.
637 * - 00 - External input pin disabled as wakeup input
638 * - 01 - External input pin enabled with rising edge detection
639 * - 10 - External input pin enabled with falling edge detection
640 * - 11 - External input pin enabled with any change detection
643 #define BP_LLWU_PE4_WUPE13 (2U) /*!< Bit position for LLWU_PE4_WUPE13. */
644 #define BM_LLWU_PE4_WUPE13 (0x0CU) /*!< Bit mask for LLWU_PE4_WUPE13. */
645 #define BS_LLWU_PE4_WUPE13 (2U) /*!< Bit field size in bits for LLWU_PE4_WUPE13. */
647 /*! @brief Read current value of the LLWU_PE4_WUPE13 field. */
648 #define BR_LLWU_PE4_WUPE13(x) (HW_LLWU_PE4(x).B.WUPE13)
650 /*! @brief Format value for bitfield LLWU_PE4_WUPE13. */
651 #define BF_LLWU_PE4_WUPE13(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE4_WUPE13) & BM_LLWU_PE4_WUPE13)
653 /*! @brief Set the WUPE13 field to a new value. */
654 #define BW_LLWU_PE4_WUPE13(x, v) (HW_LLWU_PE4_WR(x, (HW_LLWU_PE4_RD(x) & ~BM_LLWU_PE4_WUPE13) | BF_LLWU_PE4_WUPE13(v)))
658 * @name Register LLWU_PE4, field WUPE14[5:4] (RW)
660 * Enables and configures the edge detection for the wakeup pin.
663 * - 00 - External input pin disabled as wakeup input
664 * - 01 - External input pin enabled with rising edge detection
665 * - 10 - External input pin enabled with falling edge detection
666 * - 11 - External input pin enabled with any change detection
669 #define BP_LLWU_PE4_WUPE14 (4U) /*!< Bit position for LLWU_PE4_WUPE14. */
670 #define BM_LLWU_PE4_WUPE14 (0x30U) /*!< Bit mask for LLWU_PE4_WUPE14. */
671 #define BS_LLWU_PE4_WUPE14 (2U) /*!< Bit field size in bits for LLWU_PE4_WUPE14. */
673 /*! @brief Read current value of the LLWU_PE4_WUPE14 field. */
674 #define BR_LLWU_PE4_WUPE14(x) (HW_LLWU_PE4(x).B.WUPE14)
676 /*! @brief Format value for bitfield LLWU_PE4_WUPE14. */
677 #define BF_LLWU_PE4_WUPE14(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE4_WUPE14) & BM_LLWU_PE4_WUPE14)
679 /*! @brief Set the WUPE14 field to a new value. */
680 #define BW_LLWU_PE4_WUPE14(x, v) (HW_LLWU_PE4_WR(x, (HW_LLWU_PE4_RD(x) & ~BM_LLWU_PE4_WUPE14) | BF_LLWU_PE4_WUPE14(v)))
684 * @name Register LLWU_PE4, field WUPE15[7:6] (RW)
686 * Enables and configures the edge detection for the wakeup pin.
689 * - 00 - External input pin disabled as wakeup input
690 * - 01 - External input pin enabled with rising edge detection
691 * - 10 - External input pin enabled with falling edge detection
692 * - 11 - External input pin enabled with any change detection
695 #define BP_LLWU_PE4_WUPE15 (6U) /*!< Bit position for LLWU_PE4_WUPE15. */
696 #define BM_LLWU_PE4_WUPE15 (0xC0U) /*!< Bit mask for LLWU_PE4_WUPE15. */
697 #define BS_LLWU_PE4_WUPE15 (2U) /*!< Bit field size in bits for LLWU_PE4_WUPE15. */
699 /*! @brief Read current value of the LLWU_PE4_WUPE15 field. */
700 #define BR_LLWU_PE4_WUPE15(x) (HW_LLWU_PE4(x).B.WUPE15)
702 /*! @brief Format value for bitfield LLWU_PE4_WUPE15. */
703 #define BF_LLWU_PE4_WUPE15(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE4_WUPE15) & BM_LLWU_PE4_WUPE15)
705 /*! @brief Set the WUPE15 field to a new value. */
706 #define BW_LLWU_PE4_WUPE15(x, v) (HW_LLWU_PE4_WR(x, (HW_LLWU_PE4_RD(x) & ~BM_LLWU_PE4_WUPE15) | BF_LLWU_PE4_WUPE15(v)))
709 /*******************************************************************************
710 * HW_LLWU_ME - LLWU Module Enable register
711 ******************************************************************************/
714 * @brief HW_LLWU_ME - LLWU Module Enable register (RW)
718 * LLWU_ME contains the bits to enable the internal module flag as a wakeup
719 * input source for inputs MWUF7-MWUF0. This register is reset on Chip Reset not VLLS
720 * and by reset types that trigger Chip Reset not VLLS. It is unaffected by
721 * reset types that do not trigger Chip Reset not VLLS. See the
722 * IntroductionInformation found here describes the registers of the Reset Control Module (RCM). The
723 * RCM implements many of the reset functions for the chip. See the chip's reset
724 * chapter for more information. details for more information.
726 typedef union _hw_llwu_me
729 struct _hw_llwu_me_bitfields
731 uint8_t WUME0
: 1; /*!< [0] Wakeup Module Enable For Module 0 */
732 uint8_t WUME1
: 1; /*!< [1] Wakeup Module Enable for Module 1 */
733 uint8_t WUME2
: 1; /*!< [2] Wakeup Module Enable For Module 2 */
734 uint8_t WUME3
: 1; /*!< [3] Wakeup Module Enable For Module 3 */
735 uint8_t WUME4
: 1; /*!< [4] Wakeup Module Enable For Module 4 */
736 uint8_t WUME5
: 1; /*!< [5] Wakeup Module Enable For Module 5 */
737 uint8_t WUME6
: 1; /*!< [6] Wakeup Module Enable For Module 6 */
738 uint8_t WUME7
: 1; /*!< [7] Wakeup Module Enable For Module 7 */
743 * @name Constants and macros for entire LLWU_ME register
746 #define HW_LLWU_ME_ADDR(x) ((x) + 0x4U)
748 #define HW_LLWU_ME(x) (*(__IO hw_llwu_me_t *) HW_LLWU_ME_ADDR(x))
749 #define HW_LLWU_ME_RD(x) (HW_LLWU_ME(x).U)
750 #define HW_LLWU_ME_WR(x, v) (HW_LLWU_ME(x).U = (v))
751 #define HW_LLWU_ME_SET(x, v) (HW_LLWU_ME_WR(x, HW_LLWU_ME_RD(x) | (v)))
752 #define HW_LLWU_ME_CLR(x, v) (HW_LLWU_ME_WR(x, HW_LLWU_ME_RD(x) & ~(v)))
753 #define HW_LLWU_ME_TOG(x, v) (HW_LLWU_ME_WR(x, HW_LLWU_ME_RD(x) ^ (v)))
757 * Constants & macros for individual LLWU_ME bitfields
761 * @name Register LLWU_ME, field WUME0[0] (RW)
763 * Enables an internal module as a wakeup source input.
766 * - 0 - Internal module flag not used as wakeup source
767 * - 1 - Internal module flag used as wakeup source
770 #define BP_LLWU_ME_WUME0 (0U) /*!< Bit position for LLWU_ME_WUME0. */
771 #define BM_LLWU_ME_WUME0 (0x01U) /*!< Bit mask for LLWU_ME_WUME0. */
772 #define BS_LLWU_ME_WUME0 (1U) /*!< Bit field size in bits for LLWU_ME_WUME0. */
774 /*! @brief Read current value of the LLWU_ME_WUME0 field. */
775 #define BR_LLWU_ME_WUME0(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME0))
777 /*! @brief Format value for bitfield LLWU_ME_WUME0. */
778 #define BF_LLWU_ME_WUME0(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME0) & BM_LLWU_ME_WUME0)
780 /*! @brief Set the WUME0 field to a new value. */
781 #define BW_LLWU_ME_WUME0(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME0) = (v))
785 * @name Register LLWU_ME, field WUME1[1] (RW)
787 * Enables an internal module as a wakeup source input.
790 * - 0 - Internal module flag not used as wakeup source
791 * - 1 - Internal module flag used as wakeup source
794 #define BP_LLWU_ME_WUME1 (1U) /*!< Bit position for LLWU_ME_WUME1. */
795 #define BM_LLWU_ME_WUME1 (0x02U) /*!< Bit mask for LLWU_ME_WUME1. */
796 #define BS_LLWU_ME_WUME1 (1U) /*!< Bit field size in bits for LLWU_ME_WUME1. */
798 /*! @brief Read current value of the LLWU_ME_WUME1 field. */
799 #define BR_LLWU_ME_WUME1(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME1))
801 /*! @brief Format value for bitfield LLWU_ME_WUME1. */
802 #define BF_LLWU_ME_WUME1(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME1) & BM_LLWU_ME_WUME1)
804 /*! @brief Set the WUME1 field to a new value. */
805 #define BW_LLWU_ME_WUME1(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME1) = (v))
809 * @name Register LLWU_ME, field WUME2[2] (RW)
811 * Enables an internal module as a wakeup source input.
814 * - 0 - Internal module flag not used as wakeup source
815 * - 1 - Internal module flag used as wakeup source
818 #define BP_LLWU_ME_WUME2 (2U) /*!< Bit position for LLWU_ME_WUME2. */
819 #define BM_LLWU_ME_WUME2 (0x04U) /*!< Bit mask for LLWU_ME_WUME2. */
820 #define BS_LLWU_ME_WUME2 (1U) /*!< Bit field size in bits for LLWU_ME_WUME2. */
822 /*! @brief Read current value of the LLWU_ME_WUME2 field. */
823 #define BR_LLWU_ME_WUME2(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME2))
825 /*! @brief Format value for bitfield LLWU_ME_WUME2. */
826 #define BF_LLWU_ME_WUME2(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME2) & BM_LLWU_ME_WUME2)
828 /*! @brief Set the WUME2 field to a new value. */
829 #define BW_LLWU_ME_WUME2(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME2) = (v))
833 * @name Register LLWU_ME, field WUME3[3] (RW)
835 * Enables an internal module as a wakeup source input.
838 * - 0 - Internal module flag not used as wakeup source
839 * - 1 - Internal module flag used as wakeup source
842 #define BP_LLWU_ME_WUME3 (3U) /*!< Bit position for LLWU_ME_WUME3. */
843 #define BM_LLWU_ME_WUME3 (0x08U) /*!< Bit mask for LLWU_ME_WUME3. */
844 #define BS_LLWU_ME_WUME3 (1U) /*!< Bit field size in bits for LLWU_ME_WUME3. */
846 /*! @brief Read current value of the LLWU_ME_WUME3 field. */
847 #define BR_LLWU_ME_WUME3(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME3))
849 /*! @brief Format value for bitfield LLWU_ME_WUME3. */
850 #define BF_LLWU_ME_WUME3(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME3) & BM_LLWU_ME_WUME3)
852 /*! @brief Set the WUME3 field to a new value. */
853 #define BW_LLWU_ME_WUME3(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME3) = (v))
857 * @name Register LLWU_ME, field WUME4[4] (RW)
859 * Enables an internal module as a wakeup source input.
862 * - 0 - Internal module flag not used as wakeup source
863 * - 1 - Internal module flag used as wakeup source
866 #define BP_LLWU_ME_WUME4 (4U) /*!< Bit position for LLWU_ME_WUME4. */
867 #define BM_LLWU_ME_WUME4 (0x10U) /*!< Bit mask for LLWU_ME_WUME4. */
868 #define BS_LLWU_ME_WUME4 (1U) /*!< Bit field size in bits for LLWU_ME_WUME4. */
870 /*! @brief Read current value of the LLWU_ME_WUME4 field. */
871 #define BR_LLWU_ME_WUME4(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME4))
873 /*! @brief Format value for bitfield LLWU_ME_WUME4. */
874 #define BF_LLWU_ME_WUME4(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME4) & BM_LLWU_ME_WUME4)
876 /*! @brief Set the WUME4 field to a new value. */
877 #define BW_LLWU_ME_WUME4(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME4) = (v))
881 * @name Register LLWU_ME, field WUME5[5] (RW)
883 * Enables an internal module as a wakeup source input.
886 * - 0 - Internal module flag not used as wakeup source
887 * - 1 - Internal module flag used as wakeup source
890 #define BP_LLWU_ME_WUME5 (5U) /*!< Bit position for LLWU_ME_WUME5. */
891 #define BM_LLWU_ME_WUME5 (0x20U) /*!< Bit mask for LLWU_ME_WUME5. */
892 #define BS_LLWU_ME_WUME5 (1U) /*!< Bit field size in bits for LLWU_ME_WUME5. */
894 /*! @brief Read current value of the LLWU_ME_WUME5 field. */
895 #define BR_LLWU_ME_WUME5(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME5))
897 /*! @brief Format value for bitfield LLWU_ME_WUME5. */
898 #define BF_LLWU_ME_WUME5(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME5) & BM_LLWU_ME_WUME5)
900 /*! @brief Set the WUME5 field to a new value. */
901 #define BW_LLWU_ME_WUME5(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME5) = (v))
905 * @name Register LLWU_ME, field WUME6[6] (RW)
907 * Enables an internal module as a wakeup source input.
910 * - 0 - Internal module flag not used as wakeup source
911 * - 1 - Internal module flag used as wakeup source
914 #define BP_LLWU_ME_WUME6 (6U) /*!< Bit position for LLWU_ME_WUME6. */
915 #define BM_LLWU_ME_WUME6 (0x40U) /*!< Bit mask for LLWU_ME_WUME6. */
916 #define BS_LLWU_ME_WUME6 (1U) /*!< Bit field size in bits for LLWU_ME_WUME6. */
918 /*! @brief Read current value of the LLWU_ME_WUME6 field. */
919 #define BR_LLWU_ME_WUME6(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME6))
921 /*! @brief Format value for bitfield LLWU_ME_WUME6. */
922 #define BF_LLWU_ME_WUME6(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME6) & BM_LLWU_ME_WUME6)
924 /*! @brief Set the WUME6 field to a new value. */
925 #define BW_LLWU_ME_WUME6(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME6) = (v))
929 * @name Register LLWU_ME, field WUME7[7] (RW)
931 * Enables an internal module as a wakeup source input.
934 * - 0 - Internal module flag not used as wakeup source
935 * - 1 - Internal module flag used as wakeup source
938 #define BP_LLWU_ME_WUME7 (7U) /*!< Bit position for LLWU_ME_WUME7. */
939 #define BM_LLWU_ME_WUME7 (0x80U) /*!< Bit mask for LLWU_ME_WUME7. */
940 #define BS_LLWU_ME_WUME7 (1U) /*!< Bit field size in bits for LLWU_ME_WUME7. */
942 /*! @brief Read current value of the LLWU_ME_WUME7 field. */
943 #define BR_LLWU_ME_WUME7(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME7))
945 /*! @brief Format value for bitfield LLWU_ME_WUME7. */
946 #define BF_LLWU_ME_WUME7(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME7) & BM_LLWU_ME_WUME7)
948 /*! @brief Set the WUME7 field to a new value. */
949 #define BW_LLWU_ME_WUME7(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME7) = (v))
952 /*******************************************************************************
953 * HW_LLWU_F1 - LLWU Flag 1 register
954 ******************************************************************************/
957 * @brief HW_LLWU_F1 - LLWU Flag 1 register (W1C)
961 * LLWU_F1 contains the wakeup flags indicating which wakeup source caused the
962 * MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU
963 * interrupt flow. For VLLS, this is the source causing the MCU reset flow. The
964 * external wakeup flags are read-only and clearing a flag is accomplished by a write
965 * of a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will
966 * remain set if the associated WUPEx bit is cleared. This register is reset on Chip
967 * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
968 * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
969 * IntroductionInformation found here describes the registers of the Reset Control
970 * Module (RCM). The RCM implements many of the reset functions for the chip. See the
971 * chip's reset chapter for more information. details for more information.
973 typedef union _hw_llwu_f1
976 struct _hw_llwu_f1_bitfields
978 uint8_t WUF0
: 1; /*!< [0] Wakeup Flag For LLWU_P0 */
979 uint8_t WUF1
: 1; /*!< [1] Wakeup Flag For LLWU_P1 */
980 uint8_t WUF2
: 1; /*!< [2] Wakeup Flag For LLWU_P2 */
981 uint8_t WUF3
: 1; /*!< [3] Wakeup Flag For LLWU_P3 */
982 uint8_t WUF4
: 1; /*!< [4] Wakeup Flag For LLWU_P4 */
983 uint8_t WUF5
: 1; /*!< [5] Wakeup Flag For LLWU_P5 */
984 uint8_t WUF6
: 1; /*!< [6] Wakeup Flag For LLWU_P6 */
985 uint8_t WUF7
: 1; /*!< [7] Wakeup Flag For LLWU_P7 */
990 * @name Constants and macros for entire LLWU_F1 register
993 #define HW_LLWU_F1_ADDR(x) ((x) + 0x5U)
995 #define HW_LLWU_F1(x) (*(__IO hw_llwu_f1_t *) HW_LLWU_F1_ADDR(x))
996 #define HW_LLWU_F1_RD(x) (HW_LLWU_F1(x).U)
997 #define HW_LLWU_F1_WR(x, v) (HW_LLWU_F1(x).U = (v))
998 #define HW_LLWU_F1_SET(x, v) (HW_LLWU_F1_WR(x, HW_LLWU_F1_RD(x) | (v)))
999 #define HW_LLWU_F1_CLR(x, v) (HW_LLWU_F1_WR(x, HW_LLWU_F1_RD(x) & ~(v)))
1000 #define HW_LLWU_F1_TOG(x, v) (HW_LLWU_F1_WR(x, HW_LLWU_F1_RD(x) ^ (v)))
1004 * Constants & macros for individual LLWU_F1 bitfields
1008 * @name Register LLWU_F1, field WUF0[0] (W1C)
1010 * Indicates that an enabled external wake-up pin was a source of exiting a
1011 * low-leakage power mode. To clear the flag, write a 1 to WUF0.
1014 * - 0 - LLWU_P0 input was not a wakeup source
1015 * - 1 - LLWU_P0 input was a wakeup source
1018 #define BP_LLWU_F1_WUF0 (0U) /*!< Bit position for LLWU_F1_WUF0. */
1019 #define BM_LLWU_F1_WUF0 (0x01U) /*!< Bit mask for LLWU_F1_WUF0. */
1020 #define BS_LLWU_F1_WUF0 (1U) /*!< Bit field size in bits for LLWU_F1_WUF0. */
1022 /*! @brief Read current value of the LLWU_F1_WUF0 field. */
1023 #define BR_LLWU_F1_WUF0(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF0))
1025 /*! @brief Format value for bitfield LLWU_F1_WUF0. */
1026 #define BF_LLWU_F1_WUF0(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF0) & BM_LLWU_F1_WUF0)
1028 /*! @brief Set the WUF0 field to a new value. */
1029 #define BW_LLWU_F1_WUF0(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF0) = (v))
1033 * @name Register LLWU_F1, field WUF1[1] (W1C)
1035 * Indicates that an enabled external wakeup pin was a source of exiting a
1036 * low-leakage power mode. To clear the flag, write a 1 to WUF1.
1039 * - 0 - LLWU_P1 input was not a wakeup source
1040 * - 1 - LLWU_P1 input was a wakeup source
1043 #define BP_LLWU_F1_WUF1 (1U) /*!< Bit position for LLWU_F1_WUF1. */
1044 #define BM_LLWU_F1_WUF1 (0x02U) /*!< Bit mask for LLWU_F1_WUF1. */
1045 #define BS_LLWU_F1_WUF1 (1U) /*!< Bit field size in bits for LLWU_F1_WUF1. */
1047 /*! @brief Read current value of the LLWU_F1_WUF1 field. */
1048 #define BR_LLWU_F1_WUF1(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF1))
1050 /*! @brief Format value for bitfield LLWU_F1_WUF1. */
1051 #define BF_LLWU_F1_WUF1(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF1) & BM_LLWU_F1_WUF1)
1053 /*! @brief Set the WUF1 field to a new value. */
1054 #define BW_LLWU_F1_WUF1(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF1) = (v))
1058 * @name Register LLWU_F1, field WUF2[2] (W1C)
1060 * Indicates that an enabled external wakeup pin was a source of exiting a
1061 * low-leakage power mode. To clear the flag, write a 1 to WUF2.
1064 * - 0 - LLWU_P2 input was not a wakeup source
1065 * - 1 - LLWU_P2 input was a wakeup source
1068 #define BP_LLWU_F1_WUF2 (2U) /*!< Bit position for LLWU_F1_WUF2. */
1069 #define BM_LLWU_F1_WUF2 (0x04U) /*!< Bit mask for LLWU_F1_WUF2. */
1070 #define BS_LLWU_F1_WUF2 (1U) /*!< Bit field size in bits for LLWU_F1_WUF2. */
1072 /*! @brief Read current value of the LLWU_F1_WUF2 field. */
1073 #define BR_LLWU_F1_WUF2(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF2))
1075 /*! @brief Format value for bitfield LLWU_F1_WUF2. */
1076 #define BF_LLWU_F1_WUF2(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF2) & BM_LLWU_F1_WUF2)
1078 /*! @brief Set the WUF2 field to a new value. */
1079 #define BW_LLWU_F1_WUF2(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF2) = (v))
1083 * @name Register LLWU_F1, field WUF3[3] (W1C)
1085 * Indicates that an enabled external wakeup pin was a source of exiting a
1086 * low-leakage power mode. To clear the flag, write a 1 to WUF3.
1089 * - 0 - LLWU_P3 input was not a wake-up source
1090 * - 1 - LLWU_P3 input was a wake-up source
1093 #define BP_LLWU_F1_WUF3 (3U) /*!< Bit position for LLWU_F1_WUF3. */
1094 #define BM_LLWU_F1_WUF3 (0x08U) /*!< Bit mask for LLWU_F1_WUF3. */
1095 #define BS_LLWU_F1_WUF3 (1U) /*!< Bit field size in bits for LLWU_F1_WUF3. */
1097 /*! @brief Read current value of the LLWU_F1_WUF3 field. */
1098 #define BR_LLWU_F1_WUF3(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF3))
1100 /*! @brief Format value for bitfield LLWU_F1_WUF3. */
1101 #define BF_LLWU_F1_WUF3(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF3) & BM_LLWU_F1_WUF3)
1103 /*! @brief Set the WUF3 field to a new value. */
1104 #define BW_LLWU_F1_WUF3(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF3) = (v))
1108 * @name Register LLWU_F1, field WUF4[4] (W1C)
1110 * Indicates that an enabled external wake-up pin was a source of exiting a
1111 * low-leakage power mode. To clear the flag, write a 1 to WUF4.
1114 * - 0 - LLWU_P4 input was not a wakeup source
1115 * - 1 - LLWU_P4 input was a wakeup source
1118 #define BP_LLWU_F1_WUF4 (4U) /*!< Bit position for LLWU_F1_WUF4. */
1119 #define BM_LLWU_F1_WUF4 (0x10U) /*!< Bit mask for LLWU_F1_WUF4. */
1120 #define BS_LLWU_F1_WUF4 (1U) /*!< Bit field size in bits for LLWU_F1_WUF4. */
1122 /*! @brief Read current value of the LLWU_F1_WUF4 field. */
1123 #define BR_LLWU_F1_WUF4(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF4))
1125 /*! @brief Format value for bitfield LLWU_F1_WUF4. */
1126 #define BF_LLWU_F1_WUF4(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF4) & BM_LLWU_F1_WUF4)
1128 /*! @brief Set the WUF4 field to a new value. */
1129 #define BW_LLWU_F1_WUF4(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF4) = (v))
1133 * @name Register LLWU_F1, field WUF5[5] (W1C)
1135 * Indicates that an enabled external wakeup pin was a source of exiting a
1136 * low-leakage power mode. To clear the flag, write a 1 to WUF5.
1139 * - 0 - LLWU_P5 input was not a wakeup source
1140 * - 1 - LLWU_P5 input was a wakeup source
1143 #define BP_LLWU_F1_WUF5 (5U) /*!< Bit position for LLWU_F1_WUF5. */
1144 #define BM_LLWU_F1_WUF5 (0x20U) /*!< Bit mask for LLWU_F1_WUF5. */
1145 #define BS_LLWU_F1_WUF5 (1U) /*!< Bit field size in bits for LLWU_F1_WUF5. */
1147 /*! @brief Read current value of the LLWU_F1_WUF5 field. */
1148 #define BR_LLWU_F1_WUF5(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF5))
1150 /*! @brief Format value for bitfield LLWU_F1_WUF5. */
1151 #define BF_LLWU_F1_WUF5(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF5) & BM_LLWU_F1_WUF5)
1153 /*! @brief Set the WUF5 field to a new value. */
1154 #define BW_LLWU_F1_WUF5(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF5) = (v))
1158 * @name Register LLWU_F1, field WUF6[6] (W1C)
1160 * Indicates that an enabled external wakeup pin was a source of exiting a
1161 * low-leakage power mode. To clear the flag, write a 1 to WUF6.
1164 * - 0 - LLWU_P6 input was not a wakeup source
1165 * - 1 - LLWU_P6 input was a wakeup source
1168 #define BP_LLWU_F1_WUF6 (6U) /*!< Bit position for LLWU_F1_WUF6. */
1169 #define BM_LLWU_F1_WUF6 (0x40U) /*!< Bit mask for LLWU_F1_WUF6. */
1170 #define BS_LLWU_F1_WUF6 (1U) /*!< Bit field size in bits for LLWU_F1_WUF6. */
1172 /*! @brief Read current value of the LLWU_F1_WUF6 field. */
1173 #define BR_LLWU_F1_WUF6(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF6))
1175 /*! @brief Format value for bitfield LLWU_F1_WUF6. */
1176 #define BF_LLWU_F1_WUF6(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF6) & BM_LLWU_F1_WUF6)
1178 /*! @brief Set the WUF6 field to a new value. */
1179 #define BW_LLWU_F1_WUF6(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF6) = (v))
1183 * @name Register LLWU_F1, field WUF7[7] (W1C)
1185 * Indicates that an enabled external wakeup pin was a source of exiting a
1186 * low-leakage power mode. To clear the flag, write a 1 to WUF7.
1189 * - 0 - LLWU_P7 input was not a wakeup source
1190 * - 1 - LLWU_P7 input was a wakeup source
1193 #define BP_LLWU_F1_WUF7 (7U) /*!< Bit position for LLWU_F1_WUF7. */
1194 #define BM_LLWU_F1_WUF7 (0x80U) /*!< Bit mask for LLWU_F1_WUF7. */
1195 #define BS_LLWU_F1_WUF7 (1U) /*!< Bit field size in bits for LLWU_F1_WUF7. */
1197 /*! @brief Read current value of the LLWU_F1_WUF7 field. */
1198 #define BR_LLWU_F1_WUF7(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF7))
1200 /*! @brief Format value for bitfield LLWU_F1_WUF7. */
1201 #define BF_LLWU_F1_WUF7(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF7) & BM_LLWU_F1_WUF7)
1203 /*! @brief Set the WUF7 field to a new value. */
1204 #define BW_LLWU_F1_WUF7(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF7) = (v))
1207 /*******************************************************************************
1208 * HW_LLWU_F2 - LLWU Flag 2 register
1209 ******************************************************************************/
1212 * @brief HW_LLWU_F2 - LLWU Flag 2 register (W1C)
1214 * Reset value: 0x00U
1216 * LLWU_F2 contains the wakeup flags indicating which wakeup source caused the
1217 * MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU
1218 * interrupt flow. For VLLS, this is the source causing the MCU reset flow. The
1219 * external wakeup flags are read-only and clearing a flag is accomplished by a write
1220 * of a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will
1221 * remain set if the associated WUPEx bit is cleared. This register is reset on Chip
1222 * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
1223 * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
1224 * IntroductionInformation found here describes the registers of the Reset Control
1225 * Module (RCM). The RCM implements many of the reset functions for the chip. See the
1226 * chip's reset chapter for more information. details for more information.
1228 typedef union _hw_llwu_f2
1231 struct _hw_llwu_f2_bitfields
1233 uint8_t WUF8
: 1; /*!< [0] Wakeup Flag For LLWU_P8 */
1234 uint8_t WUF9
: 1; /*!< [1] Wakeup Flag For LLWU_P9 */
1235 uint8_t WUF10
: 1; /*!< [2] Wakeup Flag For LLWU_P10 */
1236 uint8_t WUF11
: 1; /*!< [3] Wakeup Flag For LLWU_P11 */
1237 uint8_t WUF12
: 1; /*!< [4] Wakeup Flag For LLWU_P12 */
1238 uint8_t WUF13
: 1; /*!< [5] Wakeup Flag For LLWU_P13 */
1239 uint8_t WUF14
: 1; /*!< [6] Wakeup Flag For LLWU_P14 */
1240 uint8_t WUF15
: 1; /*!< [7] Wakeup Flag For LLWU_P15 */
1245 * @name Constants and macros for entire LLWU_F2 register
1248 #define HW_LLWU_F2_ADDR(x) ((x) + 0x6U)
1250 #define HW_LLWU_F2(x) (*(__IO hw_llwu_f2_t *) HW_LLWU_F2_ADDR(x))
1251 #define HW_LLWU_F2_RD(x) (HW_LLWU_F2(x).U)
1252 #define HW_LLWU_F2_WR(x, v) (HW_LLWU_F2(x).U = (v))
1253 #define HW_LLWU_F2_SET(x, v) (HW_LLWU_F2_WR(x, HW_LLWU_F2_RD(x) | (v)))
1254 #define HW_LLWU_F2_CLR(x, v) (HW_LLWU_F2_WR(x, HW_LLWU_F2_RD(x) & ~(v)))
1255 #define HW_LLWU_F2_TOG(x, v) (HW_LLWU_F2_WR(x, HW_LLWU_F2_RD(x) ^ (v)))
1259 * Constants & macros for individual LLWU_F2 bitfields
1263 * @name Register LLWU_F2, field WUF8[0] (W1C)
1265 * Indicates that an enabled external wakeup pin was a source of exiting a
1266 * low-leakage power mode. To clear the flag, write a 1 to WUF8.
1269 * - 0 - LLWU_P8 input was not a wakeup source
1270 * - 1 - LLWU_P8 input was a wakeup source
1273 #define BP_LLWU_F2_WUF8 (0U) /*!< Bit position for LLWU_F2_WUF8. */
1274 #define BM_LLWU_F2_WUF8 (0x01U) /*!< Bit mask for LLWU_F2_WUF8. */
1275 #define BS_LLWU_F2_WUF8 (1U) /*!< Bit field size in bits for LLWU_F2_WUF8. */
1277 /*! @brief Read current value of the LLWU_F2_WUF8 field. */
1278 #define BR_LLWU_F2_WUF8(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF8))
1280 /*! @brief Format value for bitfield LLWU_F2_WUF8. */
1281 #define BF_LLWU_F2_WUF8(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF8) & BM_LLWU_F2_WUF8)
1283 /*! @brief Set the WUF8 field to a new value. */
1284 #define BW_LLWU_F2_WUF8(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF8) = (v))
1288 * @name Register LLWU_F2, field WUF9[1] (W1C)
1290 * Indicates that an enabled external wakeup pin was a source of exiting a
1291 * low-leakage power mode. To clear the flag, write a 1 to WUF9.
1294 * - 0 - LLWU_P9 input was not a wakeup source
1295 * - 1 - LLWU_P9 input was a wakeup source
1298 #define BP_LLWU_F2_WUF9 (1U) /*!< Bit position for LLWU_F2_WUF9. */
1299 #define BM_LLWU_F2_WUF9 (0x02U) /*!< Bit mask for LLWU_F2_WUF9. */
1300 #define BS_LLWU_F2_WUF9 (1U) /*!< Bit field size in bits for LLWU_F2_WUF9. */
1302 /*! @brief Read current value of the LLWU_F2_WUF9 field. */
1303 #define BR_LLWU_F2_WUF9(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF9))
1305 /*! @brief Format value for bitfield LLWU_F2_WUF9. */
1306 #define BF_LLWU_F2_WUF9(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF9) & BM_LLWU_F2_WUF9)
1308 /*! @brief Set the WUF9 field to a new value. */
1309 #define BW_LLWU_F2_WUF9(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF9) = (v))
1313 * @name Register LLWU_F2, field WUF10[2] (W1C)
1315 * Indicates that an enabled external wakeup pin was a source of exiting a
1316 * low-leakage power mode. To clear the flag, write a 1 to WUF10.
1319 * - 0 - LLWU_P10 input was not a wakeup source
1320 * - 1 - LLWU_P10 input was a wakeup source
1323 #define BP_LLWU_F2_WUF10 (2U) /*!< Bit position for LLWU_F2_WUF10. */
1324 #define BM_LLWU_F2_WUF10 (0x04U) /*!< Bit mask for LLWU_F2_WUF10. */
1325 #define BS_LLWU_F2_WUF10 (1U) /*!< Bit field size in bits for LLWU_F2_WUF10. */
1327 /*! @brief Read current value of the LLWU_F2_WUF10 field. */
1328 #define BR_LLWU_F2_WUF10(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF10))
1330 /*! @brief Format value for bitfield LLWU_F2_WUF10. */
1331 #define BF_LLWU_F2_WUF10(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF10) & BM_LLWU_F2_WUF10)
1333 /*! @brief Set the WUF10 field to a new value. */
1334 #define BW_LLWU_F2_WUF10(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF10) = (v))
1338 * @name Register LLWU_F2, field WUF11[3] (W1C)
1340 * Indicates that an enabled external wakeup pin was a source of exiting a
1341 * low-leakage power mode. To clear the flag, write a 1 to WUF11.
1344 * - 0 - LLWU_P11 input was not a wakeup source
1345 * - 1 - LLWU_P11 input was a wakeup source
1348 #define BP_LLWU_F2_WUF11 (3U) /*!< Bit position for LLWU_F2_WUF11. */
1349 #define BM_LLWU_F2_WUF11 (0x08U) /*!< Bit mask for LLWU_F2_WUF11. */
1350 #define BS_LLWU_F2_WUF11 (1U) /*!< Bit field size in bits for LLWU_F2_WUF11. */
1352 /*! @brief Read current value of the LLWU_F2_WUF11 field. */
1353 #define BR_LLWU_F2_WUF11(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF11))
1355 /*! @brief Format value for bitfield LLWU_F2_WUF11. */
1356 #define BF_LLWU_F2_WUF11(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF11) & BM_LLWU_F2_WUF11)
1358 /*! @brief Set the WUF11 field to a new value. */
1359 #define BW_LLWU_F2_WUF11(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF11) = (v))
1363 * @name Register LLWU_F2, field WUF12[4] (W1C)
1365 * Indicates that an enabled external wakeup pin was a source of exiting a
1366 * low-leakage power mode. To clear the flag, write a 1 to WUF12.
1369 * - 0 - LLWU_P12 input was not a wakeup source
1370 * - 1 - LLWU_P12 input was a wakeup source
1373 #define BP_LLWU_F2_WUF12 (4U) /*!< Bit position for LLWU_F2_WUF12. */
1374 #define BM_LLWU_F2_WUF12 (0x10U) /*!< Bit mask for LLWU_F2_WUF12. */
1375 #define BS_LLWU_F2_WUF12 (1U) /*!< Bit field size in bits for LLWU_F2_WUF12. */
1377 /*! @brief Read current value of the LLWU_F2_WUF12 field. */
1378 #define BR_LLWU_F2_WUF12(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF12))
1380 /*! @brief Format value for bitfield LLWU_F2_WUF12. */
1381 #define BF_LLWU_F2_WUF12(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF12) & BM_LLWU_F2_WUF12)
1383 /*! @brief Set the WUF12 field to a new value. */
1384 #define BW_LLWU_F2_WUF12(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF12) = (v))
1388 * @name Register LLWU_F2, field WUF13[5] (W1C)
1390 * Indicates that an enabled external wakeup pin was a source of exiting a
1391 * low-leakage power mode. To clear the flag, write a 1 to WUF13.
1394 * - 0 - LLWU_P13 input was not a wakeup source
1395 * - 1 - LLWU_P13 input was a wakeup source
1398 #define BP_LLWU_F2_WUF13 (5U) /*!< Bit position for LLWU_F2_WUF13. */
1399 #define BM_LLWU_F2_WUF13 (0x20U) /*!< Bit mask for LLWU_F2_WUF13. */
1400 #define BS_LLWU_F2_WUF13 (1U) /*!< Bit field size in bits for LLWU_F2_WUF13. */
1402 /*! @brief Read current value of the LLWU_F2_WUF13 field. */
1403 #define BR_LLWU_F2_WUF13(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF13))
1405 /*! @brief Format value for bitfield LLWU_F2_WUF13. */
1406 #define BF_LLWU_F2_WUF13(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF13) & BM_LLWU_F2_WUF13)
1408 /*! @brief Set the WUF13 field to a new value. */
1409 #define BW_LLWU_F2_WUF13(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF13) = (v))
1413 * @name Register LLWU_F2, field WUF14[6] (W1C)
1415 * Indicates that an enabled external wakeup pin was a source of exiting a
1416 * low-leakage power mode. To clear the flag, write a 1 to WUF14.
1419 * - 0 - LLWU_P14 input was not a wakeup source
1420 * - 1 - LLWU_P14 input was a wakeup source
1423 #define BP_LLWU_F2_WUF14 (6U) /*!< Bit position for LLWU_F2_WUF14. */
1424 #define BM_LLWU_F2_WUF14 (0x40U) /*!< Bit mask for LLWU_F2_WUF14. */
1425 #define BS_LLWU_F2_WUF14 (1U) /*!< Bit field size in bits for LLWU_F2_WUF14. */
1427 /*! @brief Read current value of the LLWU_F2_WUF14 field. */
1428 #define BR_LLWU_F2_WUF14(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF14))
1430 /*! @brief Format value for bitfield LLWU_F2_WUF14. */
1431 #define BF_LLWU_F2_WUF14(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF14) & BM_LLWU_F2_WUF14)
1433 /*! @brief Set the WUF14 field to a new value. */
1434 #define BW_LLWU_F2_WUF14(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF14) = (v))
1438 * @name Register LLWU_F2, field WUF15[7] (W1C)
1440 * Indicates that an enabled external wakeup pin was a source of exiting a
1441 * low-leakage power mode. To clear the flag, write a 1 to WUF15.
1444 * - 0 - LLWU_P15 input was not a wakeup source
1445 * - 1 - LLWU_P15 input was a wakeup source
1448 #define BP_LLWU_F2_WUF15 (7U) /*!< Bit position for LLWU_F2_WUF15. */
1449 #define BM_LLWU_F2_WUF15 (0x80U) /*!< Bit mask for LLWU_F2_WUF15. */
1450 #define BS_LLWU_F2_WUF15 (1U) /*!< Bit field size in bits for LLWU_F2_WUF15. */
1452 /*! @brief Read current value of the LLWU_F2_WUF15 field. */
1453 #define BR_LLWU_F2_WUF15(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF15))
1455 /*! @brief Format value for bitfield LLWU_F2_WUF15. */
1456 #define BF_LLWU_F2_WUF15(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF15) & BM_LLWU_F2_WUF15)
1458 /*! @brief Set the WUF15 field to a new value. */
1459 #define BW_LLWU_F2_WUF15(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF15) = (v))
1462 /*******************************************************************************
1463 * HW_LLWU_F3 - LLWU Flag 3 register
1464 ******************************************************************************/
1467 * @brief HW_LLWU_F3 - LLWU Flag 3 register (RO)
1469 * Reset value: 0x00U
1471 * LLWU_F3 contains the wakeup flags indicating which internal wakeup source
1472 * caused the MCU to exit LLS or VLLS mode. For LLS, this is the source causing the
1473 * CPU interrupt flow. For VLLS, this is the source causing the MCU reset flow.
1474 * For internal peripherals that are capable of running in a low-leakage power
1475 * mode, such as a real time clock module or CMP module, the flag from the
1476 * associated peripheral is accessible as the MWUFx bit. The flag will need to be cleared
1477 * in the peripheral instead of writing a 1 to the MWUFx bit. This register is
1478 * reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not
1479 * VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See
1480 * the IntroductionInformation found here describes the registers of the Reset
1481 * Control Module (RCM). The RCM implements many of the reset functions for the
1482 * chip. See the chip's reset chapter for more information. details for more
1485 typedef union _hw_llwu_f3
1488 struct _hw_llwu_f3_bitfields
1490 uint8_t MWUF0
: 1; /*!< [0] Wakeup flag For module 0 */
1491 uint8_t MWUF1
: 1; /*!< [1] Wakeup flag For module 1 */
1492 uint8_t MWUF2
: 1; /*!< [2] Wakeup flag For module 2 */
1493 uint8_t MWUF3
: 1; /*!< [3] Wakeup flag For module 3 */
1494 uint8_t MWUF4
: 1; /*!< [4] Wakeup flag For module 4 */
1495 uint8_t MWUF5
: 1; /*!< [5] Wakeup flag For module 5 */
1496 uint8_t MWUF6
: 1; /*!< [6] Wakeup flag For module 6 */
1497 uint8_t MWUF7
: 1; /*!< [7] Wakeup flag For module 7 */
1502 * @name Constants and macros for entire LLWU_F3 register
1505 #define HW_LLWU_F3_ADDR(x) ((x) + 0x7U)
1507 #define HW_LLWU_F3(x) (*(__I hw_llwu_f3_t *) HW_LLWU_F3_ADDR(x))
1508 #define HW_LLWU_F3_RD(x) (HW_LLWU_F3(x).U)
1512 * Constants & macros for individual LLWU_F3 bitfields
1516 * @name Register LLWU_F3, field MWUF0[0] (RO)
1518 * Indicates that an enabled internal peripheral was a source of exiting a
1519 * low-leakage power mode. To clear the flag, follow the internal peripheral flag
1520 * clearing mechanism.
1523 * - 0 - Module 0 input was not a wakeup source
1524 * - 1 - Module 0 input was a wakeup source
1527 #define BP_LLWU_F3_MWUF0 (0U) /*!< Bit position for LLWU_F3_MWUF0. */
1528 #define BM_LLWU_F3_MWUF0 (0x01U) /*!< Bit mask for LLWU_F3_MWUF0. */
1529 #define BS_LLWU_F3_MWUF0 (1U) /*!< Bit field size in bits for LLWU_F3_MWUF0. */
1531 /*! @brief Read current value of the LLWU_F3_MWUF0 field. */
1532 #define BR_LLWU_F3_MWUF0(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF0))
1536 * @name Register LLWU_F3, field MWUF1[1] (RO)
1538 * Indicates that an enabled internal peripheral was a source of exiting a
1539 * low-leakage power mode. To clear the flag, follow the internal peripheral flag
1540 * clearing mechanism.
1543 * - 0 - Module 1 input was not a wakeup source
1544 * - 1 - Module 1 input was a wakeup source
1547 #define BP_LLWU_F3_MWUF1 (1U) /*!< Bit position for LLWU_F3_MWUF1. */
1548 #define BM_LLWU_F3_MWUF1 (0x02U) /*!< Bit mask for LLWU_F3_MWUF1. */
1549 #define BS_LLWU_F3_MWUF1 (1U) /*!< Bit field size in bits for LLWU_F3_MWUF1. */
1551 /*! @brief Read current value of the LLWU_F3_MWUF1 field. */
1552 #define BR_LLWU_F3_MWUF1(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF1))
1556 * @name Register LLWU_F3, field MWUF2[2] (RO)
1558 * Indicates that an enabled internal peripheral was a source of exiting a
1559 * low-leakage power mode. To clear the flag, follow the internal peripheral flag
1560 * clearing mechanism.
1563 * - 0 - Module 2 input was not a wakeup source
1564 * - 1 - Module 2 input was a wakeup source
1567 #define BP_LLWU_F3_MWUF2 (2U) /*!< Bit position for LLWU_F3_MWUF2. */
1568 #define BM_LLWU_F3_MWUF2 (0x04U) /*!< Bit mask for LLWU_F3_MWUF2. */
1569 #define BS_LLWU_F3_MWUF2 (1U) /*!< Bit field size in bits for LLWU_F3_MWUF2. */
1571 /*! @brief Read current value of the LLWU_F3_MWUF2 field. */
1572 #define BR_LLWU_F3_MWUF2(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF2))
1576 * @name Register LLWU_F3, field MWUF3[3] (RO)
1578 * Indicates that an enabled internal peripheral was a source of exiting a
1579 * low-leakage power mode. To clear the flag, follow the internal peripheral flag
1580 * clearing mechanism.
1583 * - 0 - Module 3 input was not a wakeup source
1584 * - 1 - Module 3 input was a wakeup source
1587 #define BP_LLWU_F3_MWUF3 (3U) /*!< Bit position for LLWU_F3_MWUF3. */
1588 #define BM_LLWU_F3_MWUF3 (0x08U) /*!< Bit mask for LLWU_F3_MWUF3. */
1589 #define BS_LLWU_F3_MWUF3 (1U) /*!< Bit field size in bits for LLWU_F3_MWUF3. */
1591 /*! @brief Read current value of the LLWU_F3_MWUF3 field. */
1592 #define BR_LLWU_F3_MWUF3(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF3))
1596 * @name Register LLWU_F3, field MWUF4[4] (RO)
1598 * Indicates that an enabled internal peripheral was a source of exiting a
1599 * low-leakage power mode. To clear the flag, follow the internal peripheral flag
1600 * clearing mechanism.
1603 * - 0 - Module 4 input was not a wakeup source
1604 * - 1 - Module 4 input was a wakeup source
1607 #define BP_LLWU_F3_MWUF4 (4U) /*!< Bit position for LLWU_F3_MWUF4. */
1608 #define BM_LLWU_F3_MWUF4 (0x10U) /*!< Bit mask for LLWU_F3_MWUF4. */
1609 #define BS_LLWU_F3_MWUF4 (1U) /*!< Bit field size in bits for LLWU_F3_MWUF4. */
1611 /*! @brief Read current value of the LLWU_F3_MWUF4 field. */
1612 #define BR_LLWU_F3_MWUF4(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF4))
1616 * @name Register LLWU_F3, field MWUF5[5] (RO)
1618 * Indicates that an enabled internal peripheral was a source of exiting a
1619 * low-leakage power mode. To clear the flag, follow the internal peripheral flag
1620 * clearing mechanism.
1623 * - 0 - Module 5 input was not a wakeup source
1624 * - 1 - Module 5 input was a wakeup source
1627 #define BP_LLWU_F3_MWUF5 (5U) /*!< Bit position for LLWU_F3_MWUF5. */
1628 #define BM_LLWU_F3_MWUF5 (0x20U) /*!< Bit mask for LLWU_F3_MWUF5. */
1629 #define BS_LLWU_F3_MWUF5 (1U) /*!< Bit field size in bits for LLWU_F3_MWUF5. */
1631 /*! @brief Read current value of the LLWU_F3_MWUF5 field. */
1632 #define BR_LLWU_F3_MWUF5(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF5))
1636 * @name Register LLWU_F3, field MWUF6[6] (RO)
1638 * Indicates that an enabled internal peripheral was a source of exiting a
1639 * low-leakage power mode. To clear the flag, follow the internal peripheral flag
1640 * clearing mechanism.
1643 * - 0 - Module 6 input was not a wakeup source
1644 * - 1 - Module 6 input was a wakeup source
1647 #define BP_LLWU_F3_MWUF6 (6U) /*!< Bit position for LLWU_F3_MWUF6. */
1648 #define BM_LLWU_F3_MWUF6 (0x40U) /*!< Bit mask for LLWU_F3_MWUF6. */
1649 #define BS_LLWU_F3_MWUF6 (1U) /*!< Bit field size in bits for LLWU_F3_MWUF6. */
1651 /*! @brief Read current value of the LLWU_F3_MWUF6 field. */
1652 #define BR_LLWU_F3_MWUF6(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF6))
1656 * @name Register LLWU_F3, field MWUF7[7] (RO)
1658 * Indicates that an enabled internal peripheral was a source of exiting a
1659 * low-leakage power mode. To clear the flag, follow the internal peripheral flag
1660 * clearing mechanism.
1663 * - 0 - Module 7 input was not a wakeup source
1664 * - 1 - Module 7 input was a wakeup source
1667 #define BP_LLWU_F3_MWUF7 (7U) /*!< Bit position for LLWU_F3_MWUF7. */
1668 #define BM_LLWU_F3_MWUF7 (0x80U) /*!< Bit mask for LLWU_F3_MWUF7. */
1669 #define BS_LLWU_F3_MWUF7 (1U) /*!< Bit field size in bits for LLWU_F3_MWUF7. */
1671 /*! @brief Read current value of the LLWU_F3_MWUF7 field. */
1672 #define BR_LLWU_F3_MWUF7(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF7))
1675 /*******************************************************************************
1676 * HW_LLWU_FILT1 - LLWU Pin Filter 1 register
1677 ******************************************************************************/
1680 * @brief HW_LLWU_FILT1 - LLWU Pin Filter 1 register (RW)
1682 * Reset value: 0x00U
1684 * LLWU_FILT1 is a control and status register that is used to enable/disable
1685 * the digital filter 1 features for an external pin. This register is reset on
1686 * Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
1687 * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
1688 * IntroductionInformation found here describes the registers of the Reset Control
1689 * Module (RCM). The RCM implements many of the reset functions for the chip. See
1690 * the chip's reset chapter for more information. details for more information.
1692 typedef union _hw_llwu_filt1
1695 struct _hw_llwu_filt1_bitfields
1697 uint8_t FILTSEL
: 4; /*!< [3:0] Filter Pin Select */
1698 uint8_t RESERVED0
: 1; /*!< [4] */
1699 uint8_t FILTE
: 2; /*!< [6:5] Digital Filter On External Pin */
1700 uint8_t FILTF
: 1; /*!< [7] Filter Detect Flag */
1705 * @name Constants and macros for entire LLWU_FILT1 register
1708 #define HW_LLWU_FILT1_ADDR(x) ((x) + 0x8U)
1710 #define HW_LLWU_FILT1(x) (*(__IO hw_llwu_filt1_t *) HW_LLWU_FILT1_ADDR(x))
1711 #define HW_LLWU_FILT1_RD(x) (HW_LLWU_FILT1(x).U)
1712 #define HW_LLWU_FILT1_WR(x, v) (HW_LLWU_FILT1(x).U = (v))
1713 #define HW_LLWU_FILT1_SET(x, v) (HW_LLWU_FILT1_WR(x, HW_LLWU_FILT1_RD(x) | (v)))
1714 #define HW_LLWU_FILT1_CLR(x, v) (HW_LLWU_FILT1_WR(x, HW_LLWU_FILT1_RD(x) & ~(v)))
1715 #define HW_LLWU_FILT1_TOG(x, v) (HW_LLWU_FILT1_WR(x, HW_LLWU_FILT1_RD(x) ^ (v)))
1719 * Constants & macros for individual LLWU_FILT1 bitfields
1723 * @name Register LLWU_FILT1, field FILTSEL[3:0] (RW)
1725 * Selects 1 out of the 16 wakeup pins to be muxed into the filter.
1728 * - 0000 - Select LLWU_P0 for filter
1729 * - 1111 - Select LLWU_P15 for filter
1732 #define BP_LLWU_FILT1_FILTSEL (0U) /*!< Bit position for LLWU_FILT1_FILTSEL. */
1733 #define BM_LLWU_FILT1_FILTSEL (0x0FU) /*!< Bit mask for LLWU_FILT1_FILTSEL. */
1734 #define BS_LLWU_FILT1_FILTSEL (4U) /*!< Bit field size in bits for LLWU_FILT1_FILTSEL. */
1736 /*! @brief Read current value of the LLWU_FILT1_FILTSEL field. */
1737 #define BR_LLWU_FILT1_FILTSEL(x) (HW_LLWU_FILT1(x).B.FILTSEL)
1739 /*! @brief Format value for bitfield LLWU_FILT1_FILTSEL. */
1740 #define BF_LLWU_FILT1_FILTSEL(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_FILT1_FILTSEL) & BM_LLWU_FILT1_FILTSEL)
1742 /*! @brief Set the FILTSEL field to a new value. */
1743 #define BW_LLWU_FILT1_FILTSEL(x, v) (HW_LLWU_FILT1_WR(x, (HW_LLWU_FILT1_RD(x) & ~BM_LLWU_FILT1_FILTSEL) | BF_LLWU_FILT1_FILTSEL(v)))
1747 * @name Register LLWU_FILT1, field FILTE[6:5] (RW)
1749 * Controls the digital filter options for the external pin detect.
1752 * - 00 - Filter disabled
1753 * - 01 - Filter posedge detect enabled
1754 * - 10 - Filter negedge detect enabled
1755 * - 11 - Filter any edge detect enabled
1758 #define BP_LLWU_FILT1_FILTE (5U) /*!< Bit position for LLWU_FILT1_FILTE. */
1759 #define BM_LLWU_FILT1_FILTE (0x60U) /*!< Bit mask for LLWU_FILT1_FILTE. */
1760 #define BS_LLWU_FILT1_FILTE (2U) /*!< Bit field size in bits for LLWU_FILT1_FILTE. */
1762 /*! @brief Read current value of the LLWU_FILT1_FILTE field. */
1763 #define BR_LLWU_FILT1_FILTE(x) (HW_LLWU_FILT1(x).B.FILTE)
1765 /*! @brief Format value for bitfield LLWU_FILT1_FILTE. */
1766 #define BF_LLWU_FILT1_FILTE(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_FILT1_FILTE) & BM_LLWU_FILT1_FILTE)
1768 /*! @brief Set the FILTE field to a new value. */
1769 #define BW_LLWU_FILT1_FILTE(x, v) (HW_LLWU_FILT1_WR(x, (HW_LLWU_FILT1_RD(x) & ~BM_LLWU_FILT1_FILTE) | BF_LLWU_FILT1_FILTE(v)))
1773 * @name Register LLWU_FILT1, field FILTF[7] (W1C)
1775 * Indicates that the filtered external wakeup pin, selected by FILTSEL, was a
1776 * source of exiting a low-leakage power mode. To clear the flag write a one to
1780 * - 0 - Pin Filter 1 was not a wakeup source
1781 * - 1 - Pin Filter 1 was a wakeup source
1784 #define BP_LLWU_FILT1_FILTF (7U) /*!< Bit position for LLWU_FILT1_FILTF. */
1785 #define BM_LLWU_FILT1_FILTF (0x80U) /*!< Bit mask for LLWU_FILT1_FILTF. */
1786 #define BS_LLWU_FILT1_FILTF (1U) /*!< Bit field size in bits for LLWU_FILT1_FILTF. */
1788 /*! @brief Read current value of the LLWU_FILT1_FILTF field. */
1789 #define BR_LLWU_FILT1_FILTF(x) (BITBAND_ACCESS8(HW_LLWU_FILT1_ADDR(x), BP_LLWU_FILT1_FILTF))
1791 /*! @brief Format value for bitfield LLWU_FILT1_FILTF. */
1792 #define BF_LLWU_FILT1_FILTF(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_FILT1_FILTF) & BM_LLWU_FILT1_FILTF)
1794 /*! @brief Set the FILTF field to a new value. */
1795 #define BW_LLWU_FILT1_FILTF(x, v) (BITBAND_ACCESS8(HW_LLWU_FILT1_ADDR(x), BP_LLWU_FILT1_FILTF) = (v))
1798 /*******************************************************************************
1799 * HW_LLWU_FILT2 - LLWU Pin Filter 2 register
1800 ******************************************************************************/
1803 * @brief HW_LLWU_FILT2 - LLWU Pin Filter 2 register (RW)
1805 * Reset value: 0x00U
1807 * LLWU_FILT2 is a control and status register that is used to enable/disable
1808 * the digital filter 2 features for an external pin. This register is reset on
1809 * Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
1810 * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
1811 * IntroductionInformation found here describes the registers of the Reset Control
1812 * Module (RCM). The RCM implements many of the reset functions for the chip. See
1813 * the chip's reset chapter for more information. details for more information.
1815 typedef union _hw_llwu_filt2
1818 struct _hw_llwu_filt2_bitfields
1820 uint8_t FILTSEL
: 4; /*!< [3:0] Filter Pin Select */
1821 uint8_t RESERVED0
: 1; /*!< [4] */
1822 uint8_t FILTE
: 2; /*!< [6:5] Digital Filter On External Pin */
1823 uint8_t FILTF
: 1; /*!< [7] Filter Detect Flag */
1828 * @name Constants and macros for entire LLWU_FILT2 register
1831 #define HW_LLWU_FILT2_ADDR(x) ((x) + 0x9U)
1833 #define HW_LLWU_FILT2(x) (*(__IO hw_llwu_filt2_t *) HW_LLWU_FILT2_ADDR(x))
1834 #define HW_LLWU_FILT2_RD(x) (HW_LLWU_FILT2(x).U)
1835 #define HW_LLWU_FILT2_WR(x, v) (HW_LLWU_FILT2(x).U = (v))
1836 #define HW_LLWU_FILT2_SET(x, v) (HW_LLWU_FILT2_WR(x, HW_LLWU_FILT2_RD(x) | (v)))
1837 #define HW_LLWU_FILT2_CLR(x, v) (HW_LLWU_FILT2_WR(x, HW_LLWU_FILT2_RD(x) & ~(v)))
1838 #define HW_LLWU_FILT2_TOG(x, v) (HW_LLWU_FILT2_WR(x, HW_LLWU_FILT2_RD(x) ^ (v)))
1842 * Constants & macros for individual LLWU_FILT2 bitfields
1846 * @name Register LLWU_FILT2, field FILTSEL[3:0] (RW)
1848 * Selects 1 out of the 16 wakeup pins to be muxed into the filter.
1851 * - 0000 - Select LLWU_P0 for filter
1852 * - 1111 - Select LLWU_P15 for filter
1855 #define BP_LLWU_FILT2_FILTSEL (0U) /*!< Bit position for LLWU_FILT2_FILTSEL. */
1856 #define BM_LLWU_FILT2_FILTSEL (0x0FU) /*!< Bit mask for LLWU_FILT2_FILTSEL. */
1857 #define BS_LLWU_FILT2_FILTSEL (4U) /*!< Bit field size in bits for LLWU_FILT2_FILTSEL. */
1859 /*! @brief Read current value of the LLWU_FILT2_FILTSEL field. */
1860 #define BR_LLWU_FILT2_FILTSEL(x) (HW_LLWU_FILT2(x).B.FILTSEL)
1862 /*! @brief Format value for bitfield LLWU_FILT2_FILTSEL. */
1863 #define BF_LLWU_FILT2_FILTSEL(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_FILT2_FILTSEL) & BM_LLWU_FILT2_FILTSEL)
1865 /*! @brief Set the FILTSEL field to a new value. */
1866 #define BW_LLWU_FILT2_FILTSEL(x, v) (HW_LLWU_FILT2_WR(x, (HW_LLWU_FILT2_RD(x) & ~BM_LLWU_FILT2_FILTSEL) | BF_LLWU_FILT2_FILTSEL(v)))
1870 * @name Register LLWU_FILT2, field FILTE[6:5] (RW)
1872 * Controls the digital filter options for the external pin detect.
1875 * - 00 - Filter disabled
1876 * - 01 - Filter posedge detect enabled
1877 * - 10 - Filter negedge detect enabled
1878 * - 11 - Filter any edge detect enabled
1881 #define BP_LLWU_FILT2_FILTE (5U) /*!< Bit position for LLWU_FILT2_FILTE. */
1882 #define BM_LLWU_FILT2_FILTE (0x60U) /*!< Bit mask for LLWU_FILT2_FILTE. */
1883 #define BS_LLWU_FILT2_FILTE (2U) /*!< Bit field size in bits for LLWU_FILT2_FILTE. */
1885 /*! @brief Read current value of the LLWU_FILT2_FILTE field. */
1886 #define BR_LLWU_FILT2_FILTE(x) (HW_LLWU_FILT2(x).B.FILTE)
1888 /*! @brief Format value for bitfield LLWU_FILT2_FILTE. */
1889 #define BF_LLWU_FILT2_FILTE(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_FILT2_FILTE) & BM_LLWU_FILT2_FILTE)
1891 /*! @brief Set the FILTE field to a new value. */
1892 #define BW_LLWU_FILT2_FILTE(x, v) (HW_LLWU_FILT2_WR(x, (HW_LLWU_FILT2_RD(x) & ~BM_LLWU_FILT2_FILTE) | BF_LLWU_FILT2_FILTE(v)))
1896 * @name Register LLWU_FILT2, field FILTF[7] (W1C)
1898 * Indicates that the filtered external wakeup pin, selected by FILTSEL, was a
1899 * source of exiting a low-leakage power mode. To clear the flag write a one to
1903 * - 0 - Pin Filter 2 was not a wakeup source
1904 * - 1 - Pin Filter 2 was a wakeup source
1907 #define BP_LLWU_FILT2_FILTF (7U) /*!< Bit position for LLWU_FILT2_FILTF. */
1908 #define BM_LLWU_FILT2_FILTF (0x80U) /*!< Bit mask for LLWU_FILT2_FILTF. */
1909 #define BS_LLWU_FILT2_FILTF (1U) /*!< Bit field size in bits for LLWU_FILT2_FILTF. */
1911 /*! @brief Read current value of the LLWU_FILT2_FILTF field. */
1912 #define BR_LLWU_FILT2_FILTF(x) (BITBAND_ACCESS8(HW_LLWU_FILT2_ADDR(x), BP_LLWU_FILT2_FILTF))
1914 /*! @brief Format value for bitfield LLWU_FILT2_FILTF. */
1915 #define BF_LLWU_FILT2_FILTF(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_FILT2_FILTF) & BM_LLWU_FILT2_FILTF)
1917 /*! @brief Set the FILTF field to a new value. */
1918 #define BW_LLWU_FILT2_FILTF(x, v) (BITBAND_ACCESS8(HW_LLWU_FILT2_ADDR(x), BP_LLWU_FILT2_FILTF) = (v))
1921 /*******************************************************************************
1922 * hw_llwu_t - module struct
1923 ******************************************************************************/
1925 * @brief All LLWU module registers.
1928 typedef struct _hw_llwu
1930 __IO hw_llwu_pe1_t PE1
; /*!< [0x0] LLWU Pin Enable 1 register */
1931 __IO hw_llwu_pe2_t PE2
; /*!< [0x1] LLWU Pin Enable 2 register */
1932 __IO hw_llwu_pe3_t PE3
; /*!< [0x2] LLWU Pin Enable 3 register */
1933 __IO hw_llwu_pe4_t PE4
; /*!< [0x3] LLWU Pin Enable 4 register */
1934 __IO hw_llwu_me_t ME
; /*!< [0x4] LLWU Module Enable register */
1935 __IO hw_llwu_f1_t F1
; /*!< [0x5] LLWU Flag 1 register */
1936 __IO hw_llwu_f2_t F2
; /*!< [0x6] LLWU Flag 2 register */
1937 __I hw_llwu_f3_t F3
; /*!< [0x7] LLWU Flag 3 register */
1938 __IO hw_llwu_filt1_t FILT1
; /*!< [0x8] LLWU Pin Filter 1 register */
1939 __IO hw_llwu_filt2_t FILT2
; /*!< [0x9] LLWU Pin Filter 2 register */
1943 /*! @brief Macro to access all LLWU registers. */
1944 /*! @param x LLWU module instance base address. */
1945 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
1946 * use the '&' operator, like <code>&HW_LLWU(LLWU_BASE)</code>. */
1947 #define HW_LLWU(x) (*(hw_llwu_t *)(x))
1949 #endif /* __HW_LLWU_REGISTERS_H__ */