tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_lptmr.h

   1 /*
   2 ** ###################################################################
   3 **     Compilers:           Keil ARM C/C++ Compiler
   4 **                          Freescale C/C++ for Embedded ARM
   5 **                          GNU C Compiler
   6 **                          IAR ANSI C/C++ Compiler for ARM
   7 **
   8 **     Reference manual:    K22P121M120SF7RM, Rev. 1, March 24, 2014
   9 **     Version:             rev. 2.5, 2014-05-06
  10 **     Build:               b140604
  11 **
  12 **     Abstract:
  13 **         Extension to the CMSIS register access layer header.
  14 **
  15 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
  16 **     All rights reserved.
  17 **
  18 **     Redistribution and use in source and binary forms, with or without modification,
  19 **     are permitted provided that the following conditions are met:
  20 **
  21 **     o Redistributions of source code must retain the above copyright notice, this list
  22 **       of conditions and the following disclaimer.
  23 **
  24 **     o Redistributions in binary form must reproduce the above copyright notice, this
  25 **       list of conditions and the following disclaimer in the documentation and/or
  26 **       other materials provided with the distribution.
  27 **
  28 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  29 **       contributors may be used to endorse or promote products derived from this
  30 **       software without specific prior written permission.
  31 **
  32 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  33 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  34 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  35 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  36 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  37 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  38 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  39 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  41 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42 **
  43 **     http:                 www.freescale.com
  44 **     mail:                 support@freescale.com
  45 **
  46 **     Revisions:
  47 **     - rev. 1.0 (2013-07-23)
  48 **         Initial version.
  49 **     - rev. 1.1 (2013-09-17)
  50 **         RM rev. 0.4 update.
  51 **     - rev. 2.0 (2013-10-29)
  52 **         Register accessor macros added to the memory map.
  53 **         Symbols for Processor Expert memory map compatibility added to the memory map.
  54 **         Startup file for gcc has been updated according to CMSIS 3.2.
  55 **         System initialization updated.
  56 **     - rev. 2.1 (2013-10-30)
  57 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
  58 **     - rev. 2.2 (2013-12-20)
  59 **         Update according to reference manual rev. 0.6,
  60 **     - rev. 2.3 (2014-01-13)
  61 **         Update according to reference manual rev. 0.61,
  62 **     - rev. 2.4 (2014-02-10)
  63 **         The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
  64 **     - rev. 2.5 (2014-05-06)
  65 **         Update according to reference manual rev. 1.0,
  66 **         Update of system and startup files.
  67 **         Module access macro module_BASES replaced by module_BASE_PTRS.
  68 **
  69 ** ###################################################################
  70 */
  71
  72 /*
  73  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
  74  *
  75  * This file was generated automatically and any changes may be lost.
  76  */
  77 #ifndef __HW_LPTMR_REGISTERS_H__
  78 #define __HW_LPTMR_REGISTERS_H__
  79
  80 #include "MK22F51212.h"
  81 #include "fsl_bitaccess.h"
  82
  83 /*
  84  * MK22F51212 LPTMR
  85  *
  86  * Low Power Timer
  87  *
  88  * Registers defined in this header file:
  89  * - HW_LPTMR_CSR - Low Power Timer Control Status Register
  90  * - HW_LPTMR_PSR - Low Power Timer Prescale Register
  91  * - HW_LPTMR_CMR - Low Power Timer Compare Register
  92  * - HW_LPTMR_CNR - Low Power Timer Counter Register
  93  *
  94  * - hw_lptmr_t - Struct containing all module registers.
  95  */
  96
  97 #define HW_LPTMR_INSTANCE_COUNT (1U) /*!< Number of instances of the LPTMR module. */
  98
  99 /*******************************************************************************
 100  * HW_LPTMR_CSR - Low Power Timer Control Status Register
 101  ******************************************************************************/
 102
 103 /*!
 104  * @brief HW_LPTMR_CSR - Low Power Timer Control Status Register (RW)
 105  *
 106  * Reset value: 0x00000000U
 107  */
 108 typedef union _hw_lptmr_csr
 109 {
 110     uint32_t U;
 111     struct _hw_lptmr_csr_bitfields
 112     {
 113         uint32_t TEN : 1;              /*!< [0] Timer Enable */
 114         uint32_t TMS : 1;              /*!< [1] Timer Mode Select */
 115         uint32_t TFC : 1;              /*!< [2] Timer Free-Running Counter */
 116         uint32_t TPP : 1;              /*!< [3] Timer Pin Polarity */
 117         uint32_t TPS : 2;              /*!< [5:4] Timer Pin Select */
 118         uint32_t TIE : 1;              /*!< [6] Timer Interrupt Enable */
 119         uint32_t TCF : 1;              /*!< [7] Timer Compare Flag */
 120         uint32_t RESERVED0 : 24;       /*!< [31:8]  */
 121     } B;
 122 } hw_lptmr_csr_t;
 123
 124 /*!
 125  * @name Constants and macros for entire LPTMR_CSR register
 126  */
 127 /*@{*/
 128 #define HW_LPTMR_CSR_ADDR(x)     ((x) + 0x0U)
 129
 130 #define HW_LPTMR_CSR(x)          (*(__IO hw_lptmr_csr_t *) HW_LPTMR_CSR_ADDR(x))
 131 #define HW_LPTMR_CSR_RD(x)       (HW_LPTMR_CSR(x).U)
 132 #define HW_LPTMR_CSR_WR(x, v)    (HW_LPTMR_CSR(x).U = (v))
 133 #define HW_LPTMR_CSR_SET(x, v)   (HW_LPTMR_CSR_WR(x, HW_LPTMR_CSR_RD(x) |  (v)))
 134 #define HW_LPTMR_CSR_CLR(x, v)   (HW_LPTMR_CSR_WR(x, HW_LPTMR_CSR_RD(x) & ~(v)))
 135 #define HW_LPTMR_CSR_TOG(x, v)   (HW_LPTMR_CSR_WR(x, HW_LPTMR_CSR_RD(x) ^  (v)))
 136 /*@}*/
 137
 138 /*
 139  * Constants & macros for individual LPTMR_CSR bitfields
 140  */
 141
 142 /*!
 143  * @name Register LPTMR_CSR, field TEN[0] (RW)
 144  *
 145  * When TEN is clear, it resets the LPTMR internal logic, including the CNR and
 146  * TCF. When TEN is set, the LPTMR is enabled. While writing 1 to this field,
 147  * CSR[5:1] must not be altered.
 148  *
 149  * Values:
 150  * - 0 - LPTMR is disabled and internal logic is reset.
 151  * - 1 - LPTMR is enabled.
 152  */
 153 /*@{*/
 154 #define BP_LPTMR_CSR_TEN     (0U)          /*!< Bit position for LPTMR_CSR_TEN. */
 155 #define BM_LPTMR_CSR_TEN     (0x00000001U) /*!< Bit mask for LPTMR_CSR_TEN. */
 156 #define BS_LPTMR_CSR_TEN     (1U)          /*!< Bit field size in bits for LPTMR_CSR_TEN. */
 157
 158 /*! @brief Read current value of the LPTMR_CSR_TEN field. */
 159 #define BR_LPTMR_CSR_TEN(x)  (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TEN))
 160
 161 /*! @brief Format value for bitfield LPTMR_CSR_TEN. */
 162 #define BF_LPTMR_CSR_TEN(v)  ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TEN) & BM_LPTMR_CSR_TEN)
 163
 164 /*! @brief Set the TEN field to a new value. */
 165 #define BW_LPTMR_CSR_TEN(x, v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TEN) = (v))
 166 /*@}*/
 167
 168 /*!
 169  * @name Register LPTMR_CSR, field TMS[1] (RW)
 170  *
 171  * Configures the mode of the LPTMR. TMS must be altered only when the LPTMR is
 172  * disabled.
 173  *
 174  * Values:
 175  * - 0 - Time Counter mode.
 176  * - 1 - Pulse Counter mode.
 177  */
 178 /*@{*/
 179 #define BP_LPTMR_CSR_TMS     (1U)          /*!< Bit position for LPTMR_CSR_TMS. */
 180 #define BM_LPTMR_CSR_TMS     (0x00000002U) /*!< Bit mask for LPTMR_CSR_TMS. */
 181 #define BS_LPTMR_CSR_TMS     (1U)          /*!< Bit field size in bits for LPTMR_CSR_TMS. */
 182
 183 /*! @brief Read current value of the LPTMR_CSR_TMS field. */
 184 #define BR_LPTMR_CSR_TMS(x)  (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TMS))
 185
 186 /*! @brief Format value for bitfield LPTMR_CSR_TMS. */
 187 #define BF_LPTMR_CSR_TMS(v)  ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TMS) & BM_LPTMR_CSR_TMS)
 188
 189 /*! @brief Set the TMS field to a new value. */
 190 #define BW_LPTMR_CSR_TMS(x, v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TMS) = (v))
 191 /*@}*/
 192
 193 /*!
 194  * @name Register LPTMR_CSR, field TFC[2] (RW)
 195  *
 196  * When clear, TFC configures the CNR to reset whenever TCF is set. When set,
 197  * TFC configures the CNR to reset on overflow. TFC must be altered only when the
 198  * LPTMR is disabled.
 199  *
 200  * Values:
 201  * - 0 - CNR is reset whenever TCF is set.
 202  * - 1 - CNR is reset on overflow.
 203  */
 204 /*@{*/
 205 #define BP_LPTMR_CSR_TFC     (2U)          /*!< Bit position for LPTMR_CSR_TFC. */
 206 #define BM_LPTMR_CSR_TFC     (0x00000004U) /*!< Bit mask for LPTMR_CSR_TFC. */
 207 #define BS_LPTMR_CSR_TFC     (1U)          /*!< Bit field size in bits for LPTMR_CSR_TFC. */
 208
 209 /*! @brief Read current value of the LPTMR_CSR_TFC field. */
 210 #define BR_LPTMR_CSR_TFC(x)  (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TFC))
 211
 212 /*! @brief Format value for bitfield LPTMR_CSR_TFC. */
 213 #define BF_LPTMR_CSR_TFC(v)  ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TFC) & BM_LPTMR_CSR_TFC)
 214
 215 /*! @brief Set the TFC field to a new value. */
 216 #define BW_LPTMR_CSR_TFC(x, v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TFC) = (v))
 217 /*@}*/
 218
 219 /*!
 220  * @name Register LPTMR_CSR, field TPP[3] (RW)
 221  *
 222  * Configures the polarity of the input source in Pulse Counter mode. TPP must
 223  * be changed only when the LPTMR is disabled.
 224  *
 225  * Values:
 226  * - 0 - Pulse Counter input source is active-high, and the CNR will increment
 227  *     on the rising-edge.
 228  * - 1 - Pulse Counter input source is active-low, and the CNR will increment on
 229  *     the falling-edge.
 230  */
 231 /*@{*/
 232 #define BP_LPTMR_CSR_TPP     (3U)          /*!< Bit position for LPTMR_CSR_TPP. */
 233 #define BM_LPTMR_CSR_TPP     (0x00000008U) /*!< Bit mask for LPTMR_CSR_TPP. */
 234 #define BS_LPTMR_CSR_TPP     (1U)          /*!< Bit field size in bits for LPTMR_CSR_TPP. */
 235
 236 /*! @brief Read current value of the LPTMR_CSR_TPP field. */
 237 #define BR_LPTMR_CSR_TPP(x)  (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TPP))
 238
 239 /*! @brief Format value for bitfield LPTMR_CSR_TPP. */
 240 #define BF_LPTMR_CSR_TPP(v)  ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TPP) & BM_LPTMR_CSR_TPP)
 241
 242 /*! @brief Set the TPP field to a new value. */
 243 #define BW_LPTMR_CSR_TPP(x, v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TPP) = (v))
 244 /*@}*/
 245
 246 /*!
 247  * @name Register LPTMR_CSR, field TPS[5:4] (RW)
 248  *
 249  * Configures the input source to be used in Pulse Counter mode. TPS must be
 250  * altered only when the LPTMR is disabled. The input connections vary by device.
 251  * See the chip configuration details for information on the connections to these
 252  * inputs.
 253  *
 254  * Values:
 255  * - 00 - Pulse counter input 0 is selected.
 256  * - 01 - Pulse counter input 1 is selected.
 257  * - 10 - Pulse counter input 2 is selected.
 258  * - 11 - Pulse counter input 3 is selected.
 259  */
 260 /*@{*/
 261 #define BP_LPTMR_CSR_TPS     (4U)          /*!< Bit position for LPTMR_CSR_TPS. */
 262 #define BM_LPTMR_CSR_TPS     (0x00000030U) /*!< Bit mask for LPTMR_CSR_TPS. */
 263 #define BS_LPTMR_CSR_TPS     (2U)          /*!< Bit field size in bits for LPTMR_CSR_TPS. */
 264
 265 /*! @brief Read current value of the LPTMR_CSR_TPS field. */
 266 #define BR_LPTMR_CSR_TPS(x)  (HW_LPTMR_CSR(x).B.TPS)
 267
 268 /*! @brief Format value for bitfield LPTMR_CSR_TPS. */
 269 #define BF_LPTMR_CSR_TPS(v)  ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TPS) & BM_LPTMR_CSR_TPS)
 270
 271 /*! @brief Set the TPS field to a new value. */
 272 #define BW_LPTMR_CSR_TPS(x, v) (HW_LPTMR_CSR_WR(x, (HW_LPTMR_CSR_RD(x) & ~BM_LPTMR_CSR_TPS) | BF_LPTMR_CSR_TPS(v)))
 273 /*@}*/
 274
 275 /*!
 276  * @name Register LPTMR_CSR, field TIE[6] (RW)
 277  *
 278  * When TIE is set, the LPTMR Interrupt is generated whenever TCF is also set.
 279  *
 280  * Values:
 281  * - 0 - Timer interrupt disabled.
 282  * - 1 - Timer interrupt enabled.
 283  */
 284 /*@{*/
 285 #define BP_LPTMR_CSR_TIE     (6U)          /*!< Bit position for LPTMR_CSR_TIE. */
 286 #define BM_LPTMR_CSR_TIE     (0x00000040U) /*!< Bit mask for LPTMR_CSR_TIE. */
 287 #define BS_LPTMR_CSR_TIE     (1U)          /*!< Bit field size in bits for LPTMR_CSR_TIE. */
 288
 289 /*! @brief Read current value of the LPTMR_CSR_TIE field. */
 290 #define BR_LPTMR_CSR_TIE(x)  (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TIE))
 291
 292 /*! @brief Format value for bitfield LPTMR_CSR_TIE. */
 293 #define BF_LPTMR_CSR_TIE(v)  ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TIE) & BM_LPTMR_CSR_TIE)
 294
 295 /*! @brief Set the TIE field to a new value. */
 296 #define BW_LPTMR_CSR_TIE(x, v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TIE) = (v))
 297 /*@}*/
 298
 299 /*!
 300  * @name Register LPTMR_CSR, field TCF[7] (W1C)
 301  *
 302  * TCF is set when the LPTMR is enabled and the CNR equals the CMR and
 303  * increments. TCF is cleared when the LPTMR is disabled or a logic 1 is written to it.
 304  *
 305  * Values:
 306  * - 0 - The value of CNR is not equal to CMR and increments.
 307  * - 1 - The value of CNR is equal to CMR and increments.
 308  */
 309 /*@{*/
 310 #define BP_LPTMR_CSR_TCF     (7U)          /*!< Bit position for LPTMR_CSR_TCF. */
 311 #define BM_LPTMR_CSR_TCF     (0x00000080U) /*!< Bit mask for LPTMR_CSR_TCF. */
 312 #define BS_LPTMR_CSR_TCF     (1U)          /*!< Bit field size in bits for LPTMR_CSR_TCF. */
 313
 314 /*! @brief Read current value of the LPTMR_CSR_TCF field. */
 315 #define BR_LPTMR_CSR_TCF(x)  (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TCF))
 316
 317 /*! @brief Format value for bitfield LPTMR_CSR_TCF. */
 318 #define BF_LPTMR_CSR_TCF(v)  ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TCF) & BM_LPTMR_CSR_TCF)
 319
 320 /*! @brief Set the TCF field to a new value. */
 321 #define BW_LPTMR_CSR_TCF(x, v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TCF) = (v))
 322 /*@}*/
 323
 324 /*******************************************************************************
 325  * HW_LPTMR_PSR - Low Power Timer Prescale Register
 326  ******************************************************************************/
 327
 328 /*!
 329  * @brief HW_LPTMR_PSR - Low Power Timer Prescale Register (RW)
 330  *
 331  * Reset value: 0x00000000U
 332  */
 333 typedef union _hw_lptmr_psr
 334 {
 335     uint32_t U;
 336     struct _hw_lptmr_psr_bitfields
 337     {
 338         uint32_t PCS : 2;              /*!< [1:0] Prescaler Clock Select */
 339         uint32_t PBYP : 1;             /*!< [2] Prescaler Bypass */
 340         uint32_t PRESCALE : 4;         /*!< [6:3] Prescale Value */
 341         uint32_t RESERVED0 : 25;       /*!< [31:7]  */
 342     } B;
 343 } hw_lptmr_psr_t;
 344
 345 /*!
 346  * @name Constants and macros for entire LPTMR_PSR register
 347  */
 348 /*@{*/
 349 #define HW_LPTMR_PSR_ADDR(x)     ((x) + 0x4U)
 350
 351 #define HW_LPTMR_PSR(x)          (*(__IO hw_lptmr_psr_t *) HW_LPTMR_PSR_ADDR(x))
 352 #define HW_LPTMR_PSR_RD(x)       (HW_LPTMR_PSR(x).U)
 353 #define HW_LPTMR_PSR_WR(x, v)    (HW_LPTMR_PSR(x).U = (v))
 354 #define HW_LPTMR_PSR_SET(x, v)   (HW_LPTMR_PSR_WR(x, HW_LPTMR_PSR_RD(x) |  (v)))
 355 #define HW_LPTMR_PSR_CLR(x, v)   (HW_LPTMR_PSR_WR(x, HW_LPTMR_PSR_RD(x) & ~(v)))
 356 #define HW_LPTMR_PSR_TOG(x, v)   (HW_LPTMR_PSR_WR(x, HW_LPTMR_PSR_RD(x) ^  (v)))
 357 /*@}*/
 358
 359 /*
 360  * Constants & macros for individual LPTMR_PSR bitfields
 361  */
 362
 363 /*!
 364  * @name Register LPTMR_PSR, field PCS[1:0] (RW)
 365  *
 366  * Selects the clock to be used by the LPTMR prescaler/glitch filter. PCS must
 367  * be altered only when the LPTMR is disabled. The clock connections vary by
 368  * device. See the chip configuration details for information on the connections to
 369  * these inputs.
 370  *
 371  * Values:
 372  * - 00 - Prescaler/glitch filter clock 0 selected.
 373  * - 01 - Prescaler/glitch filter clock 1 selected.
 374  * - 10 - Prescaler/glitch filter clock 2 selected.
 375  * - 11 - Prescaler/glitch filter clock 3 selected.
 376  */
 377 /*@{*/
 378 #define BP_LPTMR_PSR_PCS     (0U)          /*!< Bit position for LPTMR_PSR_PCS. */
 379 #define BM_LPTMR_PSR_PCS     (0x00000003U) /*!< Bit mask for LPTMR_PSR_PCS. */
 380 #define BS_LPTMR_PSR_PCS     (2U)          /*!< Bit field size in bits for LPTMR_PSR_PCS. */
 381
 382 /*! @brief Read current value of the LPTMR_PSR_PCS field. */
 383 #define BR_LPTMR_PSR_PCS(x)  (HW_LPTMR_PSR(x).B.PCS)
 384
 385 /*! @brief Format value for bitfield LPTMR_PSR_PCS. */
 386 #define BF_LPTMR_PSR_PCS(v)  ((uint32_t)((uint32_t)(v) << BP_LPTMR_PSR_PCS) & BM_LPTMR_PSR_PCS)
 387
 388 /*! @brief Set the PCS field to a new value. */
 389 #define BW_LPTMR_PSR_PCS(x, v) (HW_LPTMR_PSR_WR(x, (HW_LPTMR_PSR_RD(x) & ~BM_LPTMR_PSR_PCS) | BF_LPTMR_PSR_PCS(v)))
 390 /*@}*/
 391
 392 /*!
 393  * @name Register LPTMR_PSR, field PBYP[2] (RW)
 394  *
 395  * When PBYP is set, the selected prescaler clock in Time Counter mode or
 396  * selected input source in Pulse Counter mode directly clocks the CNR. When PBYP is
 397  * clear, the CNR is clocked by the output of the prescaler/glitch filter. PBYP
 398  * must be altered only when the LPTMR is disabled.
 399  *
 400  * Values:
 401  * - 0 - Prescaler/glitch filter is enabled.
 402  * - 1 - Prescaler/glitch filter is bypassed.
 403  */
 404 /*@{*/
 405 #define BP_LPTMR_PSR_PBYP    (2U)          /*!< Bit position for LPTMR_PSR_PBYP. */
 406 #define BM_LPTMR_PSR_PBYP    (0x00000004U) /*!< Bit mask for LPTMR_PSR_PBYP. */
 407 #define BS_LPTMR_PSR_PBYP    (1U)          /*!< Bit field size in bits for LPTMR_PSR_PBYP. */
 408
 409 /*! @brief Read current value of the LPTMR_PSR_PBYP field. */
 410 #define BR_LPTMR_PSR_PBYP(x) (BITBAND_ACCESS32(HW_LPTMR_PSR_ADDR(x), BP_LPTMR_PSR_PBYP))
 411
 412 /*! @brief Format value for bitfield LPTMR_PSR_PBYP. */
 413 #define BF_LPTMR_PSR_PBYP(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_PSR_PBYP) & BM_LPTMR_PSR_PBYP)
 414
 415 /*! @brief Set the PBYP field to a new value. */
 416 #define BW_LPTMR_PSR_PBYP(x, v) (BITBAND_ACCESS32(HW_LPTMR_PSR_ADDR(x), BP_LPTMR_PSR_PBYP) = (v))
 417 /*@}*/
 418
 419 /*!
 420  * @name Register LPTMR_PSR, field PRESCALE[6:3] (RW)
 421  *
 422  * Configures the size of the Prescaler in Time Counter mode or width of the
 423  * glitch filter in Pulse Counter mode. PRESCALE must be altered only when the LPTMR
 424  * is disabled.
 425  *
 426  * Values:
 427  * - 0000 - Prescaler divides the prescaler clock by 2; glitch filter does not
 428  *     support this configuration.
 429  * - 0001 - Prescaler divides the prescaler clock by 4; glitch filter recognizes
 430  *     change on input pin after 2 rising clock edges.
 431  * - 0010 - Prescaler divides the prescaler clock by 8; glitch filter recognizes
 432  *     change on input pin after 4 rising clock edges.
 433  * - 0011 - Prescaler divides the prescaler clock by 16; glitch filter
 434  *     recognizes change on input pin after 8 rising clock edges.
 435  * - 0100 - Prescaler divides the prescaler clock by 32; glitch filter
 436  *     recognizes change on input pin after 16 rising clock edges.
 437  * - 0101 - Prescaler divides the prescaler clock by 64; glitch filter
 438  *     recognizes change on input pin after 32 rising clock edges.
 439  * - 0110 - Prescaler divides the prescaler clock by 128; glitch filter
 440  *     recognizes change on input pin after 64 rising clock edges.
 441  * - 0111 - Prescaler divides the prescaler clock by 256; glitch filter
 442  *     recognizes change on input pin after 128 rising clock edges.
 443  * - 1000 - Prescaler divides the prescaler clock by 512; glitch filter
 444  *     recognizes change on input pin after 256 rising clock edges.
 445  * - 1001 - Prescaler divides the prescaler clock by 1024; glitch filter
 446  *     recognizes change on input pin after 512 rising clock edges.
 447  * - 1010 - Prescaler divides the prescaler clock by 2048; glitch filter
 448  *     recognizes change on input pin after 1024 rising clock edges.
 449  * - 1011 - Prescaler divides the prescaler clock by 4096; glitch filter
 450  *     recognizes change on input pin after 2048 rising clock edges.
 451  * - 1100 - Prescaler divides the prescaler clock by 8192; glitch filter
 452  *     recognizes change on input pin after 4096 rising clock edges.
 453  * - 1101 - Prescaler divides the prescaler clock by 16,384; glitch filter
 454  *     recognizes change on input pin after 8192 rising clock edges.
 455  * - 1110 - Prescaler divides the prescaler clock by 32,768; glitch filter
 456  *     recognizes change on input pin after 16,384 rising clock edges.
 457  * - 1111 - Prescaler divides the prescaler clock by 65,536; glitch filter
 458  *     recognizes change on input pin after 32,768 rising clock edges.
 459  */
 460 /*@{*/
 461 #define BP_LPTMR_PSR_PRESCALE (3U)         /*!< Bit position for LPTMR_PSR_PRESCALE. */
 462 #define BM_LPTMR_PSR_PRESCALE (0x00000078U) /*!< Bit mask for LPTMR_PSR_PRESCALE. */
 463 #define BS_LPTMR_PSR_PRESCALE (4U)         /*!< Bit field size in bits for LPTMR_PSR_PRESCALE. */
 464
 465 /*! @brief Read current value of the LPTMR_PSR_PRESCALE field. */
 466 #define BR_LPTMR_PSR_PRESCALE(x) (HW_LPTMR_PSR(x).B.PRESCALE)
 467
 468 /*! @brief Format value for bitfield LPTMR_PSR_PRESCALE. */
 469 #define BF_LPTMR_PSR_PRESCALE(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_PSR_PRESCALE) & BM_LPTMR_PSR_PRESCALE)
 470
 471 /*! @brief Set the PRESCALE field to a new value. */
 472 #define BW_LPTMR_PSR_PRESCALE(x, v) (HW_LPTMR_PSR_WR(x, (HW_LPTMR_PSR_RD(x) & ~BM_LPTMR_PSR_PRESCALE) | BF_LPTMR_PSR_PRESCALE(v)))
 473 /*@}*/
 474
 475 /*******************************************************************************
 476  * HW_LPTMR_CMR - Low Power Timer Compare Register
 477  ******************************************************************************/
 478
 479 /*!
 480  * @brief HW_LPTMR_CMR - Low Power Timer Compare Register (RW)
 481  *
 482  * Reset value: 0x00000000U
 483  */
 484 typedef union _hw_lptmr_cmr
 485 {
 486     uint32_t U;
 487     struct _hw_lptmr_cmr_bitfields
 488     {
 489         uint32_t COMPARE : 16;         /*!< [15:0] Compare Value */
 490         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
 491     } B;
 492 } hw_lptmr_cmr_t;
 493
 494 /*!
 495  * @name Constants and macros for entire LPTMR_CMR register
 496  */
 497 /*@{*/
 498 #define HW_LPTMR_CMR_ADDR(x)     ((x) + 0x8U)
 499
 500 #define HW_LPTMR_CMR(x)          (*(__IO hw_lptmr_cmr_t *) HW_LPTMR_CMR_ADDR(x))
 501 #define HW_LPTMR_CMR_RD(x)       (HW_LPTMR_CMR(x).U)
 502 #define HW_LPTMR_CMR_WR(x, v)    (HW_LPTMR_CMR(x).U = (v))
 503 #define HW_LPTMR_CMR_SET(x, v)   (HW_LPTMR_CMR_WR(x, HW_LPTMR_CMR_RD(x) |  (v)))
 504 #define HW_LPTMR_CMR_CLR(x, v)   (HW_LPTMR_CMR_WR(x, HW_LPTMR_CMR_RD(x) & ~(v)))
 505 #define HW_LPTMR_CMR_TOG(x, v)   (HW_LPTMR_CMR_WR(x, HW_LPTMR_CMR_RD(x) ^  (v)))
 506 /*@}*/
 507
 508 /*
 509  * Constants & macros for individual LPTMR_CMR bitfields
 510  */
 511
 512 /*!
 513  * @name Register LPTMR_CMR, field COMPARE[15:0] (RW)
 514  *
 515  * When the LPTMR is enabled and the CNR equals the value in the CMR and
 516  * increments, TCF is set and the hardware trigger asserts until the next time the CNR
 517  * increments. If the CMR is 0, the hardware trigger will remain asserted until
 518  * the LPTMR is disabled. If the LPTMR is enabled, the CMR must be altered only
 519  * when TCF is set.
 520  */
 521 /*@{*/
 522 #define BP_LPTMR_CMR_COMPARE (0U)          /*!< Bit position for LPTMR_CMR_COMPARE. */
 523 #define BM_LPTMR_CMR_COMPARE (0x0000FFFFU) /*!< Bit mask for LPTMR_CMR_COMPARE. */
 524 #define BS_LPTMR_CMR_COMPARE (16U)         /*!< Bit field size in bits for LPTMR_CMR_COMPARE. */
 525
 526 /*! @brief Read current value of the LPTMR_CMR_COMPARE field. */
 527 #define BR_LPTMR_CMR_COMPARE(x) (HW_LPTMR_CMR(x).B.COMPARE)
 528
 529 /*! @brief Format value for bitfield LPTMR_CMR_COMPARE. */
 530 #define BF_LPTMR_CMR_COMPARE(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CMR_COMPARE) & BM_LPTMR_CMR_COMPARE)
 531
 532 /*! @brief Set the COMPARE field to a new value. */
 533 #define BW_LPTMR_CMR_COMPARE(x, v) (HW_LPTMR_CMR_WR(x, (HW_LPTMR_CMR_RD(x) & ~BM_LPTMR_CMR_COMPARE) | BF_LPTMR_CMR_COMPARE(v)))
 534 /*@}*/
 535
 536 /*******************************************************************************
 537  * HW_LPTMR_CNR - Low Power Timer Counter Register
 538  ******************************************************************************/
 539
 540 /*!
 541  * @brief HW_LPTMR_CNR - Low Power Timer Counter Register (RW)
 542  *
 543  * Reset value: 0x00000000U
 544  */
 545 typedef union _hw_lptmr_cnr
 546 {
 547     uint32_t U;
 548     struct _hw_lptmr_cnr_bitfields
 549     {
 550         uint32_t COUNTER : 16;         /*!< [15:0] Counter Value */
 551         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
 552     } B;
 553 } hw_lptmr_cnr_t;
 554
 555 /*!
 556  * @name Constants and macros for entire LPTMR_CNR register
 557  */
 558 /*@{*/
 559 #define HW_LPTMR_CNR_ADDR(x)     ((x) + 0xCU)
 560
 561 #define HW_LPTMR_CNR(x)          (*(__IO hw_lptmr_cnr_t *) HW_LPTMR_CNR_ADDR(x))
 562 #define HW_LPTMR_CNR_RD(x)       (HW_LPTMR_CNR(x).U)
 563 #define HW_LPTMR_CNR_WR(x, v)    (HW_LPTMR_CNR(x).U = (v))
 564 #define HW_LPTMR_CNR_SET(x, v)   (HW_LPTMR_CNR_WR(x, HW_LPTMR_CNR_RD(x) |  (v)))
 565 #define HW_LPTMR_CNR_CLR(x, v)   (HW_LPTMR_CNR_WR(x, HW_LPTMR_CNR_RD(x) & ~(v)))
 566 #define HW_LPTMR_CNR_TOG(x, v)   (HW_LPTMR_CNR_WR(x, HW_LPTMR_CNR_RD(x) ^  (v)))
 567 /*@}*/
 568
 569 /*
 570  * Constants & macros for individual LPTMR_CNR bitfields
 571  */
 572
 573 /*!
 574  * @name Register LPTMR_CNR, field COUNTER[15:0] (RW)
 575  */
 576 /*@{*/
 577 #define BP_LPTMR_CNR_COUNTER (0U)          /*!< Bit position for LPTMR_CNR_COUNTER. */
 578 #define BM_LPTMR_CNR_COUNTER (0x0000FFFFU) /*!< Bit mask for LPTMR_CNR_COUNTER. */
 579 #define BS_LPTMR_CNR_COUNTER (16U)         /*!< Bit field size in bits for LPTMR_CNR_COUNTER. */
 580
 581 /*! @brief Read current value of the LPTMR_CNR_COUNTER field. */
 582 #define BR_LPTMR_CNR_COUNTER(x) (HW_LPTMR_CNR(x).B.COUNTER)
 583
 584 /*! @brief Format value for bitfield LPTMR_CNR_COUNTER. */
 585 #define BF_LPTMR_CNR_COUNTER(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CNR_COUNTER) & BM_LPTMR_CNR_COUNTER)
 586
 587 /*! @brief Set the COUNTER field to a new value. */
 588 #define BW_LPTMR_CNR_COUNTER(x, v) (HW_LPTMR_CNR_WR(x, (HW_LPTMR_CNR_RD(x) & ~BM_LPTMR_CNR_COUNTER) | BF_LPTMR_CNR_COUNTER(v)))
 589 /*@}*/
 590
 591 /*******************************************************************************
 592  * hw_lptmr_t - module struct
 593  ******************************************************************************/
 594 /*!
 595  * @brief All LPTMR module registers.
 596  */
 597 #pragma pack(1)
 598 typedef struct _hw_lptmr
 599 {
 600     __IO hw_lptmr_csr_t CSR;               /*!< [0x0] Low Power Timer Control Status Register */
 601     __IO hw_lptmr_psr_t PSR;               /*!< [0x4] Low Power Timer Prescale Register */
 602     __IO hw_lptmr_cmr_t CMR;               /*!< [0x8] Low Power Timer Compare Register */
 603     __IO hw_lptmr_cnr_t CNR;               /*!< [0xC] Low Power Timer Counter Register */
 604 } hw_lptmr_t;
 605 #pragma pack()
 606
 607 /*! @brief Macro to access all LPTMR registers. */
 608 /*! @param x LPTMR module instance base address. */
 609 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
 610  *     use the '&' operator, like <code>&HW_LPTMR(LPTMR0_BASE)</code>. */
 611 #define HW_LPTMR(x)    (*(hw_lptmr_t *)(x))
 612
 613 #endif /* __HW_LPTMR_REGISTERS_H__ */
 614 /* EOF */