tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_mcg.h

   1 /*
   2 ** ###################################################################
   3 **     Compilers:           Keil ARM C/C++ Compiler
   4 **                          Freescale C/C++ for Embedded ARM
   5 **                          GNU C Compiler
   6 **                          IAR ANSI C/C++ Compiler for ARM
   7 **
   8 **     Reference manual:    K22P121M120SF7RM, Rev. 1, March 24, 2014
   9 **     Version:             rev. 2.5, 2014-05-06
  10 **     Build:               b140604
  11 **
  12 **     Abstract:
  13 **         Extension to the CMSIS register access layer header.
  14 **
  15 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
  16 **     All rights reserved.
  17 **
  18 **     Redistribution and use in source and binary forms, with or without modification,
  19 **     are permitted provided that the following conditions are met:
  20 **
  21 **     o Redistributions of source code must retain the above copyright notice, this list
  22 **       of conditions and the following disclaimer.
  23 **
  24 **     o Redistributions in binary form must reproduce the above copyright notice, this
  25 **       list of conditions and the following disclaimer in the documentation and/or
  26 **       other materials provided with the distribution.
  27 **
  28 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  29 **       contributors may be used to endorse or promote products derived from this
  30 **       software without specific prior written permission.
  31 **
  32 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  33 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  34 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  35 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  36 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  37 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  38 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  39 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  41 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42 **
  43 **     http:                 www.freescale.com
  44 **     mail:                 support@freescale.com
  45 **
  46 **     Revisions:
  47 **     - rev. 1.0 (2013-07-23)
  48 **         Initial version.
  49 **     - rev. 1.1 (2013-09-17)
  50 **         RM rev. 0.4 update.
  51 **     - rev. 2.0 (2013-10-29)
  52 **         Register accessor macros added to the memory map.
  53 **         Symbols for Processor Expert memory map compatibility added to the memory map.
  54 **         Startup file for gcc has been updated according to CMSIS 3.2.
  55 **         System initialization updated.
  56 **     - rev. 2.1 (2013-10-30)
  57 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
  58 **     - rev. 2.2 (2013-12-20)
  59 **         Update according to reference manual rev. 0.6,
  60 **     - rev. 2.3 (2014-01-13)
  61 **         Update according to reference manual rev. 0.61,
  62 **     - rev. 2.4 (2014-02-10)
  63 **         The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
  64 **     - rev. 2.5 (2014-05-06)
  65 **         Update according to reference manual rev. 1.0,
  66 **         Update of system and startup files.
  67 **         Module access macro module_BASES replaced by module_BASE_PTRS.
  68 **
  69 ** ###################################################################
  70 */
  71
  72 /*
  73  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
  74  *
  75  * This file was generated automatically and any changes may be lost.
  76  */
  77 #ifndef __HW_MCG_REGISTERS_H__
  78 #define __HW_MCG_REGISTERS_H__
  79
  80 #include "MK22F51212.h"
  81 #include "fsl_bitaccess.h"
  82
  83 /*
  84  * MK22F51212 MCG
  85  *
  86  * Multipurpose Clock Generator module
  87  *
  88  * Registers defined in this header file:
  89  * - HW_MCG_C1 - MCG Control 1 Register
  90  * - HW_MCG_C2 - MCG Control 2 Register
  91  * - HW_MCG_C3 - MCG Control 3 Register
  92  * - HW_MCG_C4 - MCG Control 4 Register
  93  * - HW_MCG_C5 - MCG Control 5 Register
  94  * - HW_MCG_C6 - MCG Control 6 Register
  95  * - HW_MCG_S - MCG Status Register
  96  * - HW_MCG_SC - MCG Status and Control Register
  97  * - HW_MCG_ATCVH - MCG Auto Trim Compare Value High Register
  98  * - HW_MCG_ATCVL - MCG Auto Trim Compare Value Low Register
  99  * - HW_MCG_C7 - MCG Control 7 Register
 100  * - HW_MCG_C8 - MCG Control 8 Register
 101  *
 102  * - hw_mcg_t - Struct containing all module registers.
 103  */
 104
 105 #define HW_MCG_INSTANCE_COUNT (1U) /*!< Number of instances of the MCG module. */
 106
 107 /*******************************************************************************
 108  * HW_MCG_C1 - MCG Control 1 Register
 109  ******************************************************************************/
 110
 111 /*!
 112  * @brief HW_MCG_C1 - MCG Control 1 Register (RW)
 113  *
 114  * Reset value: 0x04U
 115  */
 116 typedef union _hw_mcg_c1
 117 {
 118     uint8_t U;
 119     struct _hw_mcg_c1_bitfields
 120     {
 121         uint8_t IREFSTEN : 1;          /*!< [0] Internal Reference Stop Enable */
 122         uint8_t IRCLKEN : 1;           /*!< [1] Internal Reference Clock Enable */
 123         uint8_t IREFS : 1;             /*!< [2] Internal Reference Select */
 124         uint8_t FRDIV : 3;             /*!< [5:3] FLL External Reference Divider */
 125         uint8_t CLKS : 2;              /*!< [7:6] Clock Source Select */
 126     } B;
 127 } hw_mcg_c1_t;
 128
 129 /*!
 130  * @name Constants and macros for entire MCG_C1 register
 131  */
 132 /*@{*/
 133 #define HW_MCG_C1_ADDR(x)        ((x) + 0x0U)
 134
 135 #define HW_MCG_C1(x)             (*(__IO hw_mcg_c1_t *) HW_MCG_C1_ADDR(x))
 136 #define HW_MCG_C1_RD(x)          (HW_MCG_C1(x).U)
 137 #define HW_MCG_C1_WR(x, v)       (HW_MCG_C1(x).U = (v))
 138 #define HW_MCG_C1_SET(x, v)      (HW_MCG_C1_WR(x, HW_MCG_C1_RD(x) |  (v)))
 139 #define HW_MCG_C1_CLR(x, v)      (HW_MCG_C1_WR(x, HW_MCG_C1_RD(x) & ~(v)))
 140 #define HW_MCG_C1_TOG(x, v)      (HW_MCG_C1_WR(x, HW_MCG_C1_RD(x) ^  (v)))
 141 /*@}*/
 142
 143 /*
 144  * Constants & macros for individual MCG_C1 bitfields
 145  */
 146
 147 /*!
 148  * @name Register MCG_C1, field IREFSTEN[0] (RW)
 149  *
 150  * Controls whether or not the internal reference clock remains enabled when the
 151  * MCG enters Stop mode.
 152  *
 153  * Values:
 154  * - 0 - Internal reference clock is disabled in Stop mode.
 155  * - 1 - Internal reference clock is enabled in Stop mode if IRCLKEN is set or
 156  *     if MCG is in FEI, FBI, or BLPI modes before entering Stop mode.
 157  */
 158 /*@{*/
 159 #define BP_MCG_C1_IREFSTEN   (0U)          /*!< Bit position for MCG_C1_IREFSTEN. */
 160 #define BM_MCG_C1_IREFSTEN   (0x01U)       /*!< Bit mask for MCG_C1_IREFSTEN. */
 161 #define BS_MCG_C1_IREFSTEN   (1U)          /*!< Bit field size in bits for MCG_C1_IREFSTEN. */
 162
 163 /*! @brief Read current value of the MCG_C1_IREFSTEN field. */
 164 #define BR_MCG_C1_IREFSTEN(x) (BITBAND_ACCESS8(HW_MCG_C1_ADDR(x), BP_MCG_C1_IREFSTEN))
 165
 166 /*! @brief Format value for bitfield MCG_C1_IREFSTEN. */
 167 #define BF_MCG_C1_IREFSTEN(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C1_IREFSTEN) & BM_MCG_C1_IREFSTEN)
 168
 169 /*! @brief Set the IREFSTEN field to a new value. */
 170 #define BW_MCG_C1_IREFSTEN(x, v) (BITBAND_ACCESS8(HW_MCG_C1_ADDR(x), BP_MCG_C1_IREFSTEN) = (v))
 171 /*@}*/
 172
 173 /*!
 174  * @name Register MCG_C1, field IRCLKEN[1] (RW)
 175  *
 176  * Enables the internal reference clock for use as MCGIRCLK.
 177  *
 178  * Values:
 179  * - 0 - MCGIRCLK inactive.
 180  * - 1 - MCGIRCLK active.
 181  */
 182 /*@{*/
 183 #define BP_MCG_C1_IRCLKEN    (1U)          /*!< Bit position for MCG_C1_IRCLKEN. */
 184 #define BM_MCG_C1_IRCLKEN    (0x02U)       /*!< Bit mask for MCG_C1_IRCLKEN. */
 185 #define BS_MCG_C1_IRCLKEN    (1U)          /*!< Bit field size in bits for MCG_C1_IRCLKEN. */
 186
 187 /*! @brief Read current value of the MCG_C1_IRCLKEN field. */
 188 #define BR_MCG_C1_IRCLKEN(x) (BITBAND_ACCESS8(HW_MCG_C1_ADDR(x), BP_MCG_C1_IRCLKEN))
 189
 190 /*! @brief Format value for bitfield MCG_C1_IRCLKEN. */
 191 #define BF_MCG_C1_IRCLKEN(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C1_IRCLKEN) & BM_MCG_C1_IRCLKEN)
 192
 193 /*! @brief Set the IRCLKEN field to a new value. */
 194 #define BW_MCG_C1_IRCLKEN(x, v) (BITBAND_ACCESS8(HW_MCG_C1_ADDR(x), BP_MCG_C1_IRCLKEN) = (v))
 195 /*@}*/
 196
 197 /*!
 198  * @name Register MCG_C1, field IREFS[2] (RW)
 199  *
 200  * Selects the reference clock source for the FLL.
 201  *
 202  * Values:
 203  * - 0 - External reference clock is selected.
 204  * - 1 - The slow internal reference clock is selected.
 205  */
 206 /*@{*/
 207 #define BP_MCG_C1_IREFS      (2U)          /*!< Bit position for MCG_C1_IREFS. */
 208 #define BM_MCG_C1_IREFS      (0x04U)       /*!< Bit mask for MCG_C1_IREFS. */
 209 #define BS_MCG_C1_IREFS      (1U)          /*!< Bit field size in bits for MCG_C1_IREFS. */
 210
 211 /*! @brief Read current value of the MCG_C1_IREFS field. */
 212 #define BR_MCG_C1_IREFS(x)   (BITBAND_ACCESS8(HW_MCG_C1_ADDR(x), BP_MCG_C1_IREFS))
 213
 214 /*! @brief Format value for bitfield MCG_C1_IREFS. */
 215 #define BF_MCG_C1_IREFS(v)   ((uint8_t)((uint8_t)(v) << BP_MCG_C1_IREFS) & BM_MCG_C1_IREFS)
 216
 217 /*! @brief Set the IREFS field to a new value. */
 218 #define BW_MCG_C1_IREFS(x, v) (BITBAND_ACCESS8(HW_MCG_C1_ADDR(x), BP_MCG_C1_IREFS) = (v))
 219 /*@}*/
 220
 221 /*!
 222  * @name Register MCG_C1, field FRDIV[5:3] (RW)
 223  *
 224  * Selects the amount to divide down the external reference clock for the FLL.
 225  * The resulting frequency must be in the range 31.25 kHz to 39.0625 kHz (This is
 226  * required when FLL/DCO is the clock source for MCGOUTCLK . In FBE mode, it is
 227  * not required to meet this range, but it is recommended in the cases when trying
 228  * to enter a FLL mode from FBE).
 229  *
 230  * Values:
 231  * - 000 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 1; for all other RANGE
 232  *     values, Divide Factor is 32.
 233  * - 001 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 2; for all other RANGE
 234  *     values, Divide Factor is 64.
 235  * - 010 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 4; for all other RANGE
 236  *     values, Divide Factor is 128.
 237  * - 011 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 8; for all other RANGE
 238  *     values, Divide Factor is 256.
 239  * - 100 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 16; for all other RANGE
 240  *     values, Divide Factor is 512.
 241  * - 101 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 32; for all other RANGE
 242  *     values, Divide Factor is 1024.
 243  * - 110 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 64; for all other RANGE
 244  *     values, Divide Factor is 1280 .
 245  * - 111 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 128; for all other RANGE
 246  *     values, Divide Factor is 1536 .
 247  */
 248 /*@{*/
 249 #define BP_MCG_C1_FRDIV      (3U)          /*!< Bit position for MCG_C1_FRDIV. */
 250 #define BM_MCG_C1_FRDIV      (0x38U)       /*!< Bit mask for MCG_C1_FRDIV. */
 251 #define BS_MCG_C1_FRDIV      (3U)          /*!< Bit field size in bits for MCG_C1_FRDIV. */
 252
 253 /*! @brief Read current value of the MCG_C1_FRDIV field. */
 254 #define BR_MCG_C1_FRDIV(x)   (HW_MCG_C1(x).B.FRDIV)
 255
 256 /*! @brief Format value for bitfield MCG_C1_FRDIV. */
 257 #define BF_MCG_C1_FRDIV(v)   ((uint8_t)((uint8_t)(v) << BP_MCG_C1_FRDIV) & BM_MCG_C1_FRDIV)
 258
 259 /*! @brief Set the FRDIV field to a new value. */
 260 #define BW_MCG_C1_FRDIV(x, v) (HW_MCG_C1_WR(x, (HW_MCG_C1_RD(x) & ~BM_MCG_C1_FRDIV) | BF_MCG_C1_FRDIV(v)))
 261 /*@}*/
 262
 263 /*!
 264  * @name Register MCG_C1, field CLKS[7:6] (RW)
 265  *
 266  * Selects the clock source for MCGOUTCLK .
 267  *
 268  * Values:
 269  * - 00 - Encoding 0 - Output of FLL or PLL is selected (depends on PLLS control
 270  *     bit).
 271  * - 01 - Encoding 1 - Internal reference clock is selected.
 272  * - 10 - Encoding 2 - External reference clock is selected.
 273  * - 11 - Encoding 3 - Reserved.
 274  */
 275 /*@{*/
 276 #define BP_MCG_C1_CLKS       (6U)          /*!< Bit position for MCG_C1_CLKS. */
 277 #define BM_MCG_C1_CLKS       (0xC0U)       /*!< Bit mask for MCG_C1_CLKS. */
 278 #define BS_MCG_C1_CLKS       (2U)          /*!< Bit field size in bits for MCG_C1_CLKS. */
 279
 280 /*! @brief Read current value of the MCG_C1_CLKS field. */
 281 #define BR_MCG_C1_CLKS(x)    (HW_MCG_C1(x).B.CLKS)
 282
 283 /*! @brief Format value for bitfield MCG_C1_CLKS. */
 284 #define BF_MCG_C1_CLKS(v)    ((uint8_t)((uint8_t)(v) << BP_MCG_C1_CLKS) & BM_MCG_C1_CLKS)
 285
 286 /*! @brief Set the CLKS field to a new value. */
 287 #define BW_MCG_C1_CLKS(x, v) (HW_MCG_C1_WR(x, (HW_MCG_C1_RD(x) & ~BM_MCG_C1_CLKS) | BF_MCG_C1_CLKS(v)))
 288 /*@}*/
 289
 290 /*******************************************************************************
 291  * HW_MCG_C2 - MCG Control 2 Register
 292  ******************************************************************************/
 293
 294 /*!
 295  * @brief HW_MCG_C2 - MCG Control 2 Register (RW)
 296  *
 297  * Reset value: 0x80U
 298  */
 299 typedef union _hw_mcg_c2
 300 {
 301     uint8_t U;
 302     struct _hw_mcg_c2_bitfields
 303     {
 304         uint8_t IRCS : 1;              /*!< [0] Internal Reference Clock Select */
 305         uint8_t LP : 1;                /*!< [1] Low Power Select */
 306         uint8_t EREFS : 1;             /*!< [2] External Reference Select */
 307         uint8_t HGO : 1;               /*!< [3] High Gain Oscillator Select */
 308         uint8_t RANGE : 2;             /*!< [5:4] Frequency Range Select */
 309         uint8_t FCFTRIM : 1;           /*!< [6] Fast Internal Reference Clock Fine Trim
 310                                         * */
 311         uint8_t LOCRE0 : 1;            /*!< [7] Loss of Clock Reset Enable */
 312     } B;
 313 } hw_mcg_c2_t;
 314
 315 /*!
 316  * @name Constants and macros for entire MCG_C2 register
 317  */
 318 /*@{*/
 319 #define HW_MCG_C2_ADDR(x)        ((x) + 0x1U)
 320
 321 #define HW_MCG_C2(x)             (*(__IO hw_mcg_c2_t *) HW_MCG_C2_ADDR(x))
 322 #define HW_MCG_C2_RD(x)          (HW_MCG_C2(x).U)
 323 #define HW_MCG_C2_WR(x, v)       (HW_MCG_C2(x).U = (v))
 324 #define HW_MCG_C2_SET(x, v)      (HW_MCG_C2_WR(x, HW_MCG_C2_RD(x) |  (v)))
 325 #define HW_MCG_C2_CLR(x, v)      (HW_MCG_C2_WR(x, HW_MCG_C2_RD(x) & ~(v)))
 326 #define HW_MCG_C2_TOG(x, v)      (HW_MCG_C2_WR(x, HW_MCG_C2_RD(x) ^  (v)))
 327 /*@}*/
 328
 329 /*
 330  * Constants & macros for individual MCG_C2 bitfields
 331  */
 332
 333 /*!
 334  * @name Register MCG_C2, field IRCS[0] (RW)
 335  *
 336  * Selects between the fast or slow internal reference clock source.
 337  *
 338  * Values:
 339  * - 0 - Slow internal reference clock selected.
 340  * - 1 - Fast internal reference clock selected.
 341  */
 342 /*@{*/
 343 #define BP_MCG_C2_IRCS       (0U)          /*!< Bit position for MCG_C2_IRCS. */
 344 #define BM_MCG_C2_IRCS       (0x01U)       /*!< Bit mask for MCG_C2_IRCS. */
 345 #define BS_MCG_C2_IRCS       (1U)          /*!< Bit field size in bits for MCG_C2_IRCS. */
 346
 347 /*! @brief Read current value of the MCG_C2_IRCS field. */
 348 #define BR_MCG_C2_IRCS(x)    (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_IRCS))
 349
 350 /*! @brief Format value for bitfield MCG_C2_IRCS. */
 351 #define BF_MCG_C2_IRCS(v)    ((uint8_t)((uint8_t)(v) << BP_MCG_C2_IRCS) & BM_MCG_C2_IRCS)
 352
 353 /*! @brief Set the IRCS field to a new value. */
 354 #define BW_MCG_C2_IRCS(x, v) (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_IRCS) = (v))
 355 /*@}*/
 356
 357 /*!
 358  * @name Register MCG_C2, field LP[1] (RW)
 359  *
 360  * Controls whether the FLL or PLL is disabled in BLPI and BLPE modes. In FBE or
 361  * PBE modes, setting this bit to 1 will transition the MCG into BLPE mode; in
 362  * FBI mode, setting this bit to 1 will transition the MCG into BLPI mode. In any
 363  * other MCG mode, LP bit has no affect.
 364  *
 365  * Values:
 366  * - 0 - FLL or PLL is not disabled in bypass modes.
 367  * - 1 - FLL or PLL is disabled in bypass modes (lower power)
 368  */
 369 /*@{*/
 370 #define BP_MCG_C2_LP         (1U)          /*!< Bit position for MCG_C2_LP. */
 371 #define BM_MCG_C2_LP         (0x02U)       /*!< Bit mask for MCG_C2_LP. */
 372 #define BS_MCG_C2_LP         (1U)          /*!< Bit field size in bits for MCG_C2_LP. */
 373
 374 /*! @brief Read current value of the MCG_C2_LP field. */
 375 #define BR_MCG_C2_LP(x)      (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_LP))
 376
 377 /*! @brief Format value for bitfield MCG_C2_LP. */
 378 #define BF_MCG_C2_LP(v)      ((uint8_t)((uint8_t)(v) << BP_MCG_C2_LP) & BM_MCG_C2_LP)
 379
 380 /*! @brief Set the LP field to a new value. */
 381 #define BW_MCG_C2_LP(x, v)   (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_LP) = (v))
 382 /*@}*/
 383
 384 /*!
 385  * @name Register MCG_C2, field EREFS[2] (RW)
 386  *
 387  * Selects the source for the external reference clock. See the Oscillator (OSC)
 388  * chapter for more details.
 389  *
 390  * Values:
 391  * - 0 - External reference clock requested.
 392  * - 1 - Oscillator requested.
 393  */
 394 /*@{*/
 395 #define BP_MCG_C2_EREFS      (2U)          /*!< Bit position for MCG_C2_EREFS. */
 396 #define BM_MCG_C2_EREFS      (0x04U)       /*!< Bit mask for MCG_C2_EREFS. */
 397 #define BS_MCG_C2_EREFS      (1U)          /*!< Bit field size in bits for MCG_C2_EREFS. */
 398
 399 /*! @brief Read current value of the MCG_C2_EREFS field. */
 400 #define BR_MCG_C2_EREFS(x)   (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_EREFS))
 401
 402 /*! @brief Format value for bitfield MCG_C2_EREFS. */
 403 #define BF_MCG_C2_EREFS(v)   ((uint8_t)((uint8_t)(v) << BP_MCG_C2_EREFS) & BM_MCG_C2_EREFS)
 404
 405 /*! @brief Set the EREFS field to a new value. */
 406 #define BW_MCG_C2_EREFS(x, v) (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_EREFS) = (v))
 407 /*@}*/
 408
 409 /*!
 410  * @name Register MCG_C2, field HGO[3] (RW)
 411  *
 412  * Controls the crystal oscillator mode of operation. See the Oscillator (OSC)
 413  * chapter for more details.
 414  *
 415  * Values:
 416  * - 0 - Configure crystal oscillator for low-power operation.
 417  * - 1 - Configure crystal oscillator for high-gain operation.
 418  */
 419 /*@{*/
 420 #define BP_MCG_C2_HGO        (3U)          /*!< Bit position for MCG_C2_HGO. */
 421 #define BM_MCG_C2_HGO        (0x08U)       /*!< Bit mask for MCG_C2_HGO. */
 422 #define BS_MCG_C2_HGO        (1U)          /*!< Bit field size in bits for MCG_C2_HGO. */
 423
 424 /*! @brief Read current value of the MCG_C2_HGO field. */
 425 #define BR_MCG_C2_HGO(x)     (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_HGO))
 426
 427 /*! @brief Format value for bitfield MCG_C2_HGO. */
 428 #define BF_MCG_C2_HGO(v)     ((uint8_t)((uint8_t)(v) << BP_MCG_C2_HGO) & BM_MCG_C2_HGO)
 429
 430 /*! @brief Set the HGO field to a new value. */
 431 #define BW_MCG_C2_HGO(x, v)  (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_HGO) = (v))
 432 /*@}*/
 433
 434 /*!
 435  * @name Register MCG_C2, field RANGE[5:4] (RW)
 436  *
 437  * Selects the frequency range for the crystal oscillator or external clock
 438  * source. See the Oscillator (OSC) chapter for more details and the device data
 439  * sheet for the frequency ranges used.
 440  *
 441  * Values:
 442  * - 00 - Encoding 0 - Low frequency range selected for the crystal oscillator .
 443  * - 01 - Encoding 1 - High frequency range selected for the crystal oscillator .
 444  */
 445 /*@{*/
 446 #define BP_MCG_C2_RANGE      (4U)          /*!< Bit position for MCG_C2_RANGE. */
 447 #define BM_MCG_C2_RANGE      (0x30U)       /*!< Bit mask for MCG_C2_RANGE. */
 448 #define BS_MCG_C2_RANGE      (2U)          /*!< Bit field size in bits for MCG_C2_RANGE. */
 449
 450 /*! @brief Read current value of the MCG_C2_RANGE field. */
 451 #define BR_MCG_C2_RANGE(x)   (HW_MCG_C2(x).B.RANGE)
 452
 453 /*! @brief Format value for bitfield MCG_C2_RANGE. */
 454 #define BF_MCG_C2_RANGE(v)   ((uint8_t)((uint8_t)(v) << BP_MCG_C2_RANGE) & BM_MCG_C2_RANGE)
 455
 456 /*! @brief Set the RANGE field to a new value. */
 457 #define BW_MCG_C2_RANGE(x, v) (HW_MCG_C2_WR(x, (HW_MCG_C2_RD(x) & ~BM_MCG_C2_RANGE) | BF_MCG_C2_RANGE(v)))
 458 /*@}*/
 459
 460 /*!
 461  * @name Register MCG_C2, field FCFTRIM[6] (RW)
 462  *
 463  * FCFTRIM controls the smallest adjustment of the fast internal reference clock
 464  * frequency. Setting FCFTRIM increases the period and clearing FCFTRIM
 465  * decreases the period by the smallest amount possible. If an FCFTRIM value stored in
 466  * nonvolatile memory is to be used, it is your responsibility to copy that value
 467  * from the nonvolatile memory location to this bit.
 468  */
 469 /*@{*/
 470 #define BP_MCG_C2_FCFTRIM    (6U)          /*!< Bit position for MCG_C2_FCFTRIM. */
 471 #define BM_MCG_C2_FCFTRIM    (0x40U)       /*!< Bit mask for MCG_C2_FCFTRIM. */
 472 #define BS_MCG_C2_FCFTRIM    (1U)          /*!< Bit field size in bits for MCG_C2_FCFTRIM. */
 473
 474 /*! @brief Read current value of the MCG_C2_FCFTRIM field. */
 475 #define BR_MCG_C2_FCFTRIM(x) (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_FCFTRIM))
 476
 477 /*! @brief Format value for bitfield MCG_C2_FCFTRIM. */
 478 #define BF_MCG_C2_FCFTRIM(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C2_FCFTRIM) & BM_MCG_C2_FCFTRIM)
 479
 480 /*! @brief Set the FCFTRIM field to a new value. */
 481 #define BW_MCG_C2_FCFTRIM(x, v) (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_FCFTRIM) = (v))
 482 /*@}*/
 483
 484 /*!
 485  * @name Register MCG_C2, field LOCRE0[7] (RW)
 486  *
 487  * Determines whether an interrupt or a reset request is made following a loss
 488  * of OSC0 external reference clock. The LOCRE0 only has an affect when CME0 is
 489  * set.
 490  *
 491  * Values:
 492  * - 0 - Interrupt request is generated on a loss of OSC0 external reference
 493  *     clock.
 494  * - 1 - Generate a reset request on a loss of OSC0 external reference clock.
 495  */
 496 /*@{*/
 497 #define BP_MCG_C2_LOCRE0     (7U)          /*!< Bit position for MCG_C2_LOCRE0. */
 498 #define BM_MCG_C2_LOCRE0     (0x80U)       /*!< Bit mask for MCG_C2_LOCRE0. */
 499 #define BS_MCG_C2_LOCRE0     (1U)          /*!< Bit field size in bits for MCG_C2_LOCRE0. */
 500
 501 /*! @brief Read current value of the MCG_C2_LOCRE0 field. */
 502 #define BR_MCG_C2_LOCRE0(x)  (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_LOCRE0))
 503
 504 /*! @brief Format value for bitfield MCG_C2_LOCRE0. */
 505 #define BF_MCG_C2_LOCRE0(v)  ((uint8_t)((uint8_t)(v) << BP_MCG_C2_LOCRE0) & BM_MCG_C2_LOCRE0)
 506
 507 /*! @brief Set the LOCRE0 field to a new value. */
 508 #define BW_MCG_C2_LOCRE0(x, v) (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_LOCRE0) = (v))
 509 /*@}*/
 510
 511 /*******************************************************************************
 512  * HW_MCG_C3 - MCG Control 3 Register
 513  ******************************************************************************/
 514
 515 /*!
 516  * @brief HW_MCG_C3 - MCG Control 3 Register (RW)
 517  *
 518  * Reset value: 0x00U
 519  */
 520 typedef union _hw_mcg_c3
 521 {
 522     uint8_t U;
 523     struct _hw_mcg_c3_bitfields
 524     {
 525         uint8_t SCTRIM : 8;            /*!< [7:0] Slow Internal Reference Clock Trim
 526                                         * Setting */
 527     } B;
 528 } hw_mcg_c3_t;
 529
 530 /*!
 531  * @name Constants and macros for entire MCG_C3 register
 532  */
 533 /*@{*/
 534 #define HW_MCG_C3_ADDR(x)        ((x) + 0x2U)
 535
 536 #define HW_MCG_C3(x)             (*(__IO hw_mcg_c3_t *) HW_MCG_C3_ADDR(x))
 537 #define HW_MCG_C3_RD(x)          (HW_MCG_C3(x).U)
 538 #define HW_MCG_C3_WR(x, v)       (HW_MCG_C3(x).U = (v))
 539 #define HW_MCG_C3_SET(x, v)      (HW_MCG_C3_WR(x, HW_MCG_C3_RD(x) |  (v)))
 540 #define HW_MCG_C3_CLR(x, v)      (HW_MCG_C3_WR(x, HW_MCG_C3_RD(x) & ~(v)))
 541 #define HW_MCG_C3_TOG(x, v)      (HW_MCG_C3_WR(x, HW_MCG_C3_RD(x) ^  (v)))
 542 /*@}*/
 543
 544 /*
 545  * Constants & macros for individual MCG_C3 bitfields
 546  */
 547
 548 /*!
 549  * @name Register MCG_C3, field SCTRIM[7:0] (RW)
 550  *
 551  * SCTRIM A value for SCTRIM is loaded during reset from a factory programmed
 552  * location. controls the slow internal reference clock frequency by controlling
 553  * the slow internal reference clock period. The SCTRIM bits are binary weighted,
 554  * that is, bit 1 adjusts twice as much as bit 0. Increasing the binary value
 555  * increases the period, and decreasing the value decreases the period. An additional
 556  * fine trim bit is available in C4 register as the SCFTRIM bit. Upon reset,
 557  * this value is loaded with a factory trim value. If an SCTRIM value stored in
 558  * nonvolatile memory is to be used, it is your responsibility to copy that value
 559  * from the nonvolatile memory location to this register.
 560  */
 561 /*@{*/
 562 #define BP_MCG_C3_SCTRIM     (0U)          /*!< Bit position for MCG_C3_SCTRIM. */
 563 #define BM_MCG_C3_SCTRIM     (0xFFU)       /*!< Bit mask for MCG_C3_SCTRIM. */
 564 #define BS_MCG_C3_SCTRIM     (8U)          /*!< Bit field size in bits for MCG_C3_SCTRIM. */
 565
 566 /*! @brief Read current value of the MCG_C3_SCTRIM field. */
 567 #define BR_MCG_C3_SCTRIM(x)  (HW_MCG_C3(x).U)
 568
 569 /*! @brief Format value for bitfield MCG_C3_SCTRIM. */
 570 #define BF_MCG_C3_SCTRIM(v)  ((uint8_t)((uint8_t)(v) << BP_MCG_C3_SCTRIM) & BM_MCG_C3_SCTRIM)
 571
 572 /*! @brief Set the SCTRIM field to a new value. */
 573 #define BW_MCG_C3_SCTRIM(x, v) (HW_MCG_C3_WR(x, v))
 574 /*@}*/
 575
 576 /*******************************************************************************
 577  * HW_MCG_C4 - MCG Control 4 Register
 578  ******************************************************************************/
 579
 580 /*!
 581  * @brief HW_MCG_C4 - MCG Control 4 Register (RW)
 582  *
 583  * Reset value: 0x00U
 584  *
 585  * Reset values for DRST and DMX32 bits are 0.
 586  */
 587 typedef union _hw_mcg_c4
 588 {
 589     uint8_t U;
 590     struct _hw_mcg_c4_bitfields
 591     {
 592         uint8_t SCFTRIM : 1;           /*!< [0] Slow Internal Reference Clock Fine Trim
 593                                         * */
 594         uint8_t FCTRIM : 4;            /*!< [4:1] Fast Internal Reference Clock Trim
 595                                         * Setting */
 596         uint8_t DRST_DRS : 2;          /*!< [6:5] DCO Range Select */
 597         uint8_t DMX32 : 1;             /*!< [7] DCO Maximum Frequency with 32.768 kHz
 598                                         * Reference */
 599     } B;
 600 } hw_mcg_c4_t;
 601
 602 /*!
 603  * @name Constants and macros for entire MCG_C4 register
 604  */
 605 /*@{*/
 606 #define HW_MCG_C4_ADDR(x)        ((x) + 0x3U)
 607
 608 #define HW_MCG_C4(x)             (*(__IO hw_mcg_c4_t *) HW_MCG_C4_ADDR(x))
 609 #define HW_MCG_C4_RD(x)          (HW_MCG_C4(x).U)
 610 #define HW_MCG_C4_WR(x, v)       (HW_MCG_C4(x).U = (v))
 611 #define HW_MCG_C4_SET(x, v)      (HW_MCG_C4_WR(x, HW_MCG_C4_RD(x) |  (v)))
 612 #define HW_MCG_C4_CLR(x, v)      (HW_MCG_C4_WR(x, HW_MCG_C4_RD(x) & ~(v)))
 613 #define HW_MCG_C4_TOG(x, v)      (HW_MCG_C4_WR(x, HW_MCG_C4_RD(x) ^  (v)))
 614 /*@}*/
 615
 616 /*
 617  * Constants & macros for individual MCG_C4 bitfields
 618  */
 619
 620 /*!
 621  * @name Register MCG_C4, field SCFTRIM[0] (RW)
 622  *
 623  * SCFTRIM A value for SCFTRIM is loaded during reset from a factory programmed
 624  * location . controls the smallest adjustment of the slow internal reference
 625  * clock frequency. Setting SCFTRIM increases the period and clearing SCFTRIM
 626  * decreases the period by the smallest amount possible. If an SCFTRIM value stored in
 627  * nonvolatile memory is to be used, it is your responsibility to copy that value
 628  * from the nonvolatile memory location to this bit.
 629  */
 630 /*@{*/
 631 #define BP_MCG_C4_SCFTRIM    (0U)          /*!< Bit position for MCG_C4_SCFTRIM. */
 632 #define BM_MCG_C4_SCFTRIM    (0x01U)       /*!< Bit mask for MCG_C4_SCFTRIM. */
 633 #define BS_MCG_C4_SCFTRIM    (1U)          /*!< Bit field size in bits for MCG_C4_SCFTRIM. */
 634
 635 /*! @brief Read current value of the MCG_C4_SCFTRIM field. */
 636 #define BR_MCG_C4_SCFTRIM(x) (BITBAND_ACCESS8(HW_MCG_C4_ADDR(x), BP_MCG_C4_SCFTRIM))
 637
 638 /*! @brief Format value for bitfield MCG_C4_SCFTRIM. */
 639 #define BF_MCG_C4_SCFTRIM(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C4_SCFTRIM) & BM_MCG_C4_SCFTRIM)
 640
 641 /*! @brief Set the SCFTRIM field to a new value. */
 642 #define BW_MCG_C4_SCFTRIM(x, v) (BITBAND_ACCESS8(HW_MCG_C4_ADDR(x), BP_MCG_C4_SCFTRIM) = (v))
 643 /*@}*/
 644
 645 /*!
 646  * @name Register MCG_C4, field FCTRIM[4:1] (RW)
 647  *
 648  * FCTRIM A value for FCTRIM is loaded during reset from a factory programmed
 649  * location. controls the fast internal reference clock frequency by controlling
 650  * the fast internal reference clock period. The FCTRIM bits are binary weighted,
 651  * that is, bit 1 adjusts twice as much as bit 0. Increasing the binary value
 652  * increases the period, and decreasing the value decreases the period. If an
 653  * FCTRIM[3:0] value stored in nonvolatile memory is to be used, it is your
 654  * responsibility to copy that value from the nonvolatile memory location to this register.
 655  */
 656 /*@{*/
 657 #define BP_MCG_C4_FCTRIM     (1U)          /*!< Bit position for MCG_C4_FCTRIM. */
 658 #define BM_MCG_C4_FCTRIM     (0x1EU)       /*!< Bit mask for MCG_C4_FCTRIM. */
 659 #define BS_MCG_C4_FCTRIM     (4U)          /*!< Bit field size in bits for MCG_C4_FCTRIM. */
 660
 661 /*! @brief Read current value of the MCG_C4_FCTRIM field. */
 662 #define BR_MCG_C4_FCTRIM(x)  (HW_MCG_C4(x).B.FCTRIM)
 663
 664 /*! @brief Format value for bitfield MCG_C4_FCTRIM. */
 665 #define BF_MCG_C4_FCTRIM(v)  ((uint8_t)((uint8_t)(v) << BP_MCG_C4_FCTRIM) & BM_MCG_C4_FCTRIM)
 666
 667 /*! @brief Set the FCTRIM field to a new value. */
 668 #define BW_MCG_C4_FCTRIM(x, v) (HW_MCG_C4_WR(x, (HW_MCG_C4_RD(x) & ~BM_MCG_C4_FCTRIM) | BF_MCG_C4_FCTRIM(v)))
 669 /*@}*/
 670
 671 /*!
 672  * @name Register MCG_C4, field DRST_DRS[6:5] (RW)
 673  *
 674  * The DRS bits select the frequency range for the FLL output, DCOOUT. When the
 675  * LP bit is set, writes to the DRS bits are ignored. The DRST read field
 676  * indicates the current frequency range for DCOOUT. The DRST field does not update
 677  * immediately after a write to the DRS field due to internal synchronization between
 678  * clock domains. See the DCO Frequency Range table for more details.
 679  *
 680  * Values:
 681  * - 00 - Encoding 0 - Low range (reset default).
 682  * - 01 - Encoding 1 - Mid range.
 683  * - 10 - Encoding 2 - Mid-high range.
 684  * - 11 - Encoding 3 - High range.
 685  */
 686 /*@{*/
 687 #define BP_MCG_C4_DRST_DRS   (5U)          /*!< Bit position for MCG_C4_DRST_DRS. */
 688 #define BM_MCG_C4_DRST_DRS   (0x60U)       /*!< Bit mask for MCG_C4_DRST_DRS. */
 689 #define BS_MCG_C4_DRST_DRS   (2U)          /*!< Bit field size in bits for MCG_C4_DRST_DRS. */
 690
 691 /*! @brief Read current value of the MCG_C4_DRST_DRS field. */
 692 #define BR_MCG_C4_DRST_DRS(x) (HW_MCG_C4(x).B.DRST_DRS)
 693
 694 /*! @brief Format value for bitfield MCG_C4_DRST_DRS. */
 695 #define BF_MCG_C4_DRST_DRS(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C4_DRST_DRS) & BM_MCG_C4_DRST_DRS)
 696
 697 /*! @brief Set the DRST_DRS field to a new value. */
 698 #define BW_MCG_C4_DRST_DRS(x, v) (HW_MCG_C4_WR(x, (HW_MCG_C4_RD(x) & ~BM_MCG_C4_DRST_DRS) | BF_MCG_C4_DRST_DRS(v)))
 699 /*@}*/
 700
 701 /*!
 702  * @name Register MCG_C4, field DMX32[7] (RW)
 703  *
 704  * The DMX32 bit controls whether the DCO frequency range is narrowed to its
 705  * maximum frequency with a 32.768 kHz reference. The following table identifies
 706  * settings for the DCO frequency range. The system clocks derived from this source
 707  * should not exceed their specified maximums. DRST_DRS DMX32 Reference Range FLL
 708  * Factor DCO Range 00 0 31.25-39.0625 kHz 640 20-25 MHz 1 32.768 kHz 732 24 MHz
 709  * 01 0 31.25-39.0625 kHz 1280 40-50 MHz 1 32.768 kHz 1464 48 MHz 10 0
 710  * 31.25-39.0625 kHz 1920 60-75 MHz 1 32.768 kHz 2197 72 MHz 11 0 31.25-39.0625 kHz 2560
 711  * 80-100 MHz 1 32.768 kHz 2929 96 MHz
 712  *
 713  * Values:
 714  * - 0 - DCO has a default range of 25%.
 715  * - 1 - DCO is fine-tuned for maximum frequency with 32.768 kHz reference.
 716  */
 717 /*@{*/
 718 #define BP_MCG_C4_DMX32      (7U)          /*!< Bit position for MCG_C4_DMX32. */
 719 #define BM_MCG_C4_DMX32      (0x80U)       /*!< Bit mask for MCG_C4_DMX32. */
 720 #define BS_MCG_C4_DMX32      (1U)          /*!< Bit field size in bits for MCG_C4_DMX32. */
 721
 722 /*! @brief Read current value of the MCG_C4_DMX32 field. */
 723 #define BR_MCG_C4_DMX32(x)   (BITBAND_ACCESS8(HW_MCG_C4_ADDR(x), BP_MCG_C4_DMX32))
 724
 725 /*! @brief Format value for bitfield MCG_C4_DMX32. */
 726 #define BF_MCG_C4_DMX32(v)   ((uint8_t)((uint8_t)(v) << BP_MCG_C4_DMX32) & BM_MCG_C4_DMX32)
 727
 728 /*! @brief Set the DMX32 field to a new value. */
 729 #define BW_MCG_C4_DMX32(x, v) (BITBAND_ACCESS8(HW_MCG_C4_ADDR(x), BP_MCG_C4_DMX32) = (v))
 730 /*@}*/
 731
 732 /*******************************************************************************
 733  * HW_MCG_C5 - MCG Control 5 Register
 734  ******************************************************************************/
 735
 736 /*!
 737  * @brief HW_MCG_C5 - MCG Control 5 Register (RW)
 738  *
 739  * Reset value: 0x00U
 740  */
 741 typedef union _hw_mcg_c5
 742 {
 743     uint8_t U;
 744     struct _hw_mcg_c5_bitfields
 745     {
 746         uint8_t PRDIV0 : 5;            /*!< [4:0] PLL External Reference Divider */
 747         uint8_t PLLSTEN0 : 1;          /*!< [5] PLL Stop Enable */
 748         uint8_t PLLCLKEN0 : 1;         /*!< [6] PLL Clock Enable */
 749         uint8_t RESERVED0 : 1;         /*!< [7]  */
 750     } B;
 751 } hw_mcg_c5_t;
 752
 753 /*!
 754  * @name Constants and macros for entire MCG_C5 register
 755  */
 756 /*@{*/
 757 #define HW_MCG_C5_ADDR(x)        ((x) + 0x4U)
 758
 759 #define HW_MCG_C5(x)             (*(__IO hw_mcg_c5_t *) HW_MCG_C5_ADDR(x))
 760 #define HW_MCG_C5_RD(x)          (HW_MCG_C5(x).U)
 761 #define HW_MCG_C5_WR(x, v)       (HW_MCG_C5(x).U = (v))
 762 #define HW_MCG_C5_SET(x, v)      (HW_MCG_C5_WR(x, HW_MCG_C5_RD(x) |  (v)))
 763 #define HW_MCG_C5_CLR(x, v)      (HW_MCG_C5_WR(x, HW_MCG_C5_RD(x) & ~(v)))
 764 #define HW_MCG_C5_TOG(x, v)      (HW_MCG_C5_WR(x, HW_MCG_C5_RD(x) ^  (v)))
 765 /*@}*/
 766
 767 /*
 768  * Constants & macros for individual MCG_C5 bitfields
 769  */
 770
 771 /*!
 772  * @name Register MCG_C5, field PRDIV0[4:0] (RW)
 773  *
 774  * Selects the amount to divide down the external reference clock for the PLL.
 775  * The resulting frequency must be in the range of 2 MHz to 4 MHz. After the PLL
 776  * is enabled (by setting either PLLCLKEN 0 or PLLS), the PRDIV 0 value must not
 777  * be changed when LOCK0 is zero. PLL External Reference Divide Factor PRDIV 0
 778  * Divide Factor PRDIV 0 Divide Factor PRDIV 0 Divide Factor PRDIV 0 Divide Factor
 779  * 00000 1 01000 9 10000 17 11000 25 00001 2 01001 10 10001 18 11001 Reserved
 780  * 00010 3 01010 11 10010 19 11010 Reserved 00011 4 01011 12 10011 20 11011 Reserved
 781  * 00100 5 01100 13 10100 21 11100 Reserved 00101 6 01101 14 10101 22 11101
 782  * Reserved 00110 7 01110 15 10110 23 11110 Reserved 00111 8 01111 16 10111 24 11111
 783  * Reserved
 784  */
 785 /*@{*/
 786 #define BP_MCG_C5_PRDIV0     (0U)          /*!< Bit position for MCG_C5_PRDIV0. */
 787 #define BM_MCG_C5_PRDIV0     (0x1FU)       /*!< Bit mask for MCG_C5_PRDIV0. */
 788 #define BS_MCG_C5_PRDIV0     (5U)          /*!< Bit field size in bits for MCG_C5_PRDIV0. */
 789
 790 /*! @brief Read current value of the MCG_C5_PRDIV0 field. */
 791 #define BR_MCG_C5_PRDIV0(x)  (HW_MCG_C5(x).B.PRDIV0)
 792
 793 /*! @brief Format value for bitfield MCG_C5_PRDIV0. */
 794 #define BF_MCG_C5_PRDIV0(v)  ((uint8_t)((uint8_t)(v) << BP_MCG_C5_PRDIV0) & BM_MCG_C5_PRDIV0)
 795
 796 /*! @brief Set the PRDIV0 field to a new value. */
 797 #define BW_MCG_C5_PRDIV0(x, v) (HW_MCG_C5_WR(x, (HW_MCG_C5_RD(x) & ~BM_MCG_C5_PRDIV0) | BF_MCG_C5_PRDIV0(v)))
 798 /*@}*/
 799
 800 /*!
 801  * @name Register MCG_C5, field PLLSTEN0[5] (RW)
 802  *
 803  * Enables the PLL Clock during Normal Stop. In Low Power Stop mode, the PLL
 804  * clock gets disabled even if PLLSTEN 0 =1. All other power modes, PLLSTEN 0 bit
 805  * has no affect and does not enable the PLL Clock to run if it is written to 1.
 806  *
 807  * Values:
 808  * - 0 - MCGPLLCLK is disabled in any of the Stop modes.
 809  * - 1 - MCGPLLCLK is enabled if system is in Normal Stop mode.
 810  */
 811 /*@{*/
 812 #define BP_MCG_C5_PLLSTEN0   (5U)          /*!< Bit position for MCG_C5_PLLSTEN0. */
 813 #define BM_MCG_C5_PLLSTEN0   (0x20U)       /*!< Bit mask for MCG_C5_PLLSTEN0. */
 814 #define BS_MCG_C5_PLLSTEN0   (1U)          /*!< Bit field size in bits for MCG_C5_PLLSTEN0. */
 815
 816 /*! @brief Read current value of the MCG_C5_PLLSTEN0 field. */
 817 #define BR_MCG_C5_PLLSTEN0(x) (BITBAND_ACCESS8(HW_MCG_C5_ADDR(x), BP_MCG_C5_PLLSTEN0))
 818
 819 /*! @brief Format value for bitfield MCG_C5_PLLSTEN0. */
 820 #define BF_MCG_C5_PLLSTEN0(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C5_PLLSTEN0) & BM_MCG_C5_PLLSTEN0)
 821
 822 /*! @brief Set the PLLSTEN0 field to a new value. */
 823 #define BW_MCG_C5_PLLSTEN0(x, v) (BITBAND_ACCESS8(HW_MCG_C5_ADDR(x), BP_MCG_C5_PLLSTEN0) = (v))
 824 /*@}*/
 825
 826 /*!
 827  * @name Register MCG_C5, field PLLCLKEN0[6] (RW)
 828  *
 829  * Enables the PLL independent of PLLS and enables the PLL clock for use as
 830  * MCGPLLCLK. (PRDIV 0 needs to be programmed to the correct divider to generate a
 831  * PLL reference clock in the range of 2 - 4 MHz range prior to setting the
 832  * PLLCLKEN 0 bit). Setting PLLCLKEN 0 will enable the external oscillator if not
 833  * already enabled. Whenever the PLL is being enabled by means of the PLLCLKEN 0 bit,
 834  * and the external oscillator is being used as the reference clock, the OSCINIT 0
 835  * bit should be checked to make sure it is set.
 836  *
 837  * Values:
 838  * - 0 - MCGPLLCLK is inactive.
 839  * - 1 - MCGPLLCLK is active.
 840  */
 841 /*@{*/
 842 #define BP_MCG_C5_PLLCLKEN0  (6U)          /*!< Bit position for MCG_C5_PLLCLKEN0. */
 843 #define BM_MCG_C5_PLLCLKEN0  (0x40U)       /*!< Bit mask for MCG_C5_PLLCLKEN0. */
 844 #define BS_MCG_C5_PLLCLKEN0  (1U)          /*!< Bit field size in bits for MCG_C5_PLLCLKEN0. */
 845
 846 /*! @brief Read current value of the MCG_C5_PLLCLKEN0 field. */
 847 #define BR_MCG_C5_PLLCLKEN0(x) (BITBAND_ACCESS8(HW_MCG_C5_ADDR(x), BP_MCG_C5_PLLCLKEN0))
 848
 849 /*! @brief Format value for bitfield MCG_C5_PLLCLKEN0. */
 850 #define BF_MCG_C5_PLLCLKEN0(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C5_PLLCLKEN0) & BM_MCG_C5_PLLCLKEN0)
 851
 852 /*! @brief Set the PLLCLKEN0 field to a new value. */
 853 #define BW_MCG_C5_PLLCLKEN0(x, v) (BITBAND_ACCESS8(HW_MCG_C5_ADDR(x), BP_MCG_C5_PLLCLKEN0) = (v))
 854 /*@}*/
 855
 856 /*******************************************************************************
 857  * HW_MCG_C6 - MCG Control 6 Register
 858  ******************************************************************************/
 859
 860 /*!
 861  * @brief HW_MCG_C6 - MCG Control 6 Register (RW)
 862  *
 863  * Reset value: 0x00U
 864  */
 865 typedef union _hw_mcg_c6
 866 {
 867     uint8_t U;
 868     struct _hw_mcg_c6_bitfields
 869     {
 870         uint8_t VDIV0 : 5;             /*!< [4:0] VCO 0 Divider */
 871         uint8_t CME0 : 1;              /*!< [5] Clock Monitor Enable */
 872         uint8_t PLLS : 1;              /*!< [6] PLL Select */
 873         uint8_t LOLIE0 : 1;            /*!< [7] Loss of Lock Interrrupt Enable */
 874     } B;
 875 } hw_mcg_c6_t;
 876
 877 /*!
 878  * @name Constants and macros for entire MCG_C6 register
 879  */
 880 /*@{*/
 881 #define HW_MCG_C6_ADDR(x)        ((x) + 0x5U)
 882
 883 #define HW_MCG_C6(x)             (*(__IO hw_mcg_c6_t *) HW_MCG_C6_ADDR(x))
 884 #define HW_MCG_C6_RD(x)          (HW_MCG_C6(x).U)
 885 #define HW_MCG_C6_WR(x, v)       (HW_MCG_C6(x).U = (v))
 886 #define HW_MCG_C6_SET(x, v)      (HW_MCG_C6_WR(x, HW_MCG_C6_RD(x) |  (v)))
 887 #define HW_MCG_C6_CLR(x, v)      (HW_MCG_C6_WR(x, HW_MCG_C6_RD(x) & ~(v)))
 888 #define HW_MCG_C6_TOG(x, v)      (HW_MCG_C6_WR(x, HW_MCG_C6_RD(x) ^  (v)))
 889 /*@}*/
 890
 891 /*
 892  * Constants & macros for individual MCG_C6 bitfields
 893  */
 894
 895 /*!
 896  * @name Register MCG_C6, field VDIV0[4:0] (RW)
 897  *
 898  * Selects the amount to divide the VCO output of the PLL. The VDIV 0 bits
 899  * establish the multiplication factor (M) applied to the reference clock frequency.
 900  * After the PLL is enabled (by setting either PLLCLKEN 0 or PLLS), the VDIV 0
 901  * value must not be changed when LOCK 0 is zero. PLL VCO Divide Factor VDIV 0
 902  * Multiply Factor VDIV 0 Multiply Factor VDIV 0 Multiply Factor VDIV 0 Multiply
 903  * Factor 00000 24 01000 32 10000 40 11000 48 00001 25 01001 33 10001 41 11001 49
 904  * 00010 26 01010 34 10010 42 11010 50 00011 27 01011 35 10011 43 11011 51 00100 28
 905  * 01100 36 10100 44 11100 52 00101 29 01101 37 10101 45 11101 53 00110 30 01110
 906  * 38 10110 46 11110 54 00111 31 01111 39 10111 47 11111 55
 907  */
 908 /*@{*/
 909 #define BP_MCG_C6_VDIV0      (0U)          /*!< Bit position for MCG_C6_VDIV0. */
 910 #define BM_MCG_C6_VDIV0      (0x1FU)       /*!< Bit mask for MCG_C6_VDIV0. */
 911 #define BS_MCG_C6_VDIV0      (5U)          /*!< Bit field size in bits for MCG_C6_VDIV0. */
 912
 913 /*! @brief Read current value of the MCG_C6_VDIV0 field. */
 914 #define BR_MCG_C6_VDIV0(x)   (HW_MCG_C6(x).B.VDIV0)
 915
 916 /*! @brief Format value for bitfield MCG_C6_VDIV0. */
 917 #define BF_MCG_C6_VDIV0(v)   ((uint8_t)((uint8_t)(v) << BP_MCG_C6_VDIV0) & BM_MCG_C6_VDIV0)
 918
 919 /*! @brief Set the VDIV0 field to a new value. */
 920 #define BW_MCG_C6_VDIV0(x, v) (HW_MCG_C6_WR(x, (HW_MCG_C6_RD(x) & ~BM_MCG_C6_VDIV0) | BF_MCG_C6_VDIV0(v)))
 921 /*@}*/
 922
 923 /*!
 924  * @name Register MCG_C6, field CME0[5] (RW)
 925  *
 926  * Enables the loss of clock monitoring circuit for the OSC0 external reference
 927  * mux select. The LOCRE0 bit will determine if a interrupt or a reset request is
 928  * generated following a loss of OSC0 indication. The CME0 bit must only be set
 929  * to a logic 1 when the MCG is in an operational mode that uses the external
 930  * clock (FEE, FBE, PEE, PBE, or BLPE) . Whenever the CME0 bit is set to a logic 1,
 931  * the value of the RANGE0 bits in the C2 register should not be changed. CME0
 932  * bit should be set to a logic 0 before the MCG enters any Stop mode. Otherwise, a
 933  * reset request may occur while in Stop mode. CME0 should also be set to a
 934  * logic 0 before entering VLPR or VLPW power modes if the MCG is in BLPE mode.
 935  *
 936  * Values:
 937  * - 0 - External clock monitor is disabled for OSC0.
 938  * - 1 - External clock monitor is enabled for OSC0.
 939  */
 940 /*@{*/
 941 #define BP_MCG_C6_CME0       (5U)          /*!< Bit position for MCG_C6_CME0. */
 942 #define BM_MCG_C6_CME0       (0x20U)       /*!< Bit mask for MCG_C6_CME0. */
 943 #define BS_MCG_C6_CME0       (1U)          /*!< Bit field size in bits for MCG_C6_CME0. */
 944
 945 /*! @brief Read current value of the MCG_C6_CME0 field. */
 946 #define BR_MCG_C6_CME0(x)    (BITBAND_ACCESS8(HW_MCG_C6_ADDR(x), BP_MCG_C6_CME0))
 947
 948 /*! @brief Format value for bitfield MCG_C6_CME0. */
 949 #define BF_MCG_C6_CME0(v)    ((uint8_t)((uint8_t)(v) << BP_MCG_C6_CME0) & BM_MCG_C6_CME0)
 950
 951 /*! @brief Set the CME0 field to a new value. */
 952 #define BW_MCG_C6_CME0(x, v) (BITBAND_ACCESS8(HW_MCG_C6_ADDR(x), BP_MCG_C6_CME0) = (v))
 953 /*@}*/
 954
 955 /*!
 956  * @name Register MCG_C6, field PLLS[6] (RW)
 957  *
 958  * Controls whether the PLL or FLL output is selected as the MCG source when
 959  * CLKS[1:0]=00. If the PLLS bit is cleared and PLLCLKEN 0 is not set, the PLL is
 960  * disabled in all modes. If the PLLS is set, the FLL is disabled in all modes.
 961  *
 962  * Values:
 963  * - 0 - FLL is selected.
 964  * - 1 - PLL is selected (PRDIV 0 need to be programmed to the correct divider
 965  *     to generate a PLL reference clock in the range of 2-4 MHz prior to setting
 966  *     the PLLS bit).
 967  */
 968 /*@{*/
 969 #define BP_MCG_C6_PLLS       (6U)          /*!< Bit position for MCG_C6_PLLS. */
 970 #define BM_MCG_C6_PLLS       (0x40U)       /*!< Bit mask for MCG_C6_PLLS. */
 971 #define BS_MCG_C6_PLLS       (1U)          /*!< Bit field size in bits for MCG_C6_PLLS. */
 972
 973 /*! @brief Read current value of the MCG_C6_PLLS field. */
 974 #define BR_MCG_C6_PLLS(x)    (BITBAND_ACCESS8(HW_MCG_C6_ADDR(x), BP_MCG_C6_PLLS))
 975
 976 /*! @brief Format value for bitfield MCG_C6_PLLS. */
 977 #define BF_MCG_C6_PLLS(v)    ((uint8_t)((uint8_t)(v) << BP_MCG_C6_PLLS) & BM_MCG_C6_PLLS)
 978
 979 /*! @brief Set the PLLS field to a new value. */
 980 #define BW_MCG_C6_PLLS(x, v) (BITBAND_ACCESS8(HW_MCG_C6_ADDR(x), BP_MCG_C6_PLLS) = (v))
 981 /*@}*/
 982
 983 /*!
 984  * @name Register MCG_C6, field LOLIE0[7] (RW)
 985  *
 986  * Determines if an interrupt request is made following a loss of lock
 987  * indication. This bit only has an effect when LOLS 0 is set.
 988  *
 989  * Values:
 990  * - 0 - No interrupt request is generated on loss of lock.
 991  * - 1 - Generate an interrupt request on loss of lock.
 992  */
 993 /*@{*/
 994 #define BP_MCG_C6_LOLIE0     (7U)          /*!< Bit position for MCG_C6_LOLIE0. */
 995 #define BM_MCG_C6_LOLIE0     (0x80U)       /*!< Bit mask for MCG_C6_LOLIE0. */
 996 #define BS_MCG_C6_LOLIE0     (1U)          /*!< Bit field size in bits for MCG_C6_LOLIE0. */
 997
 998 /*! @brief Read current value of the MCG_C6_LOLIE0 field. */
 999 #define BR_MCG_C6_LOLIE0(x)  (BITBAND_ACCESS8(HW_MCG_C6_ADDR(x), BP_MCG_C6_LOLIE0))
1000
1001 /*! @brief Format value for bitfield MCG_C6_LOLIE0. */
1002 #define BF_MCG_C6_LOLIE0(v)  ((uint8_t)((uint8_t)(v) << BP_MCG_C6_LOLIE0) & BM_MCG_C6_LOLIE0)
1003
1004 /*! @brief Set the LOLIE0 field to a new value. */
1005 #define BW_MCG_C6_LOLIE0(x, v) (BITBAND_ACCESS8(HW_MCG_C6_ADDR(x), BP_MCG_C6_LOLIE0) = (v))
1006 /*@}*/
1007
1008 /*******************************************************************************
1009  * HW_MCG_S - MCG Status Register
1010  ******************************************************************************/
1011
1012 /*!
1013  * @brief HW_MCG_S - MCG Status Register (RW)
1014  *
1015  * Reset value: 0x10U
1016  */
1017 typedef union _hw_mcg_s
1018 {
1019     uint8_t U;
1020     struct _hw_mcg_s_bitfields
1021     {
1022         uint8_t IRCST : 1;             /*!< [0] Internal Reference Clock Status */
1023         uint8_t OSCINIT0 : 1;          /*!< [1] OSC Initialization */
1024         uint8_t CLKST : 2;             /*!< [3:2] Clock Mode Status */
1025         uint8_t IREFST : 1;            /*!< [4] Internal Reference Status */
1026         uint8_t PLLST : 1;             /*!< [5] PLL Select Status */
1027         uint8_t LOCK0 : 1;             /*!< [6] Lock Status */
1028         uint8_t LOLS0 : 1;             /*!< [7] Loss of Lock Status */
1029     } B;
1030 } hw_mcg_s_t;
1031
1032 /*!
1033  * @name Constants and macros for entire MCG_S register
1034  */
1035 /*@{*/
1036 #define HW_MCG_S_ADDR(x)         ((x) + 0x6U)
1037
1038 #define HW_MCG_S(x)              (*(__IO hw_mcg_s_t *) HW_MCG_S_ADDR(x))
1039 #define HW_MCG_S_RD(x)           (HW_MCG_S(x).U)
1040 #define HW_MCG_S_WR(x, v)        (HW_MCG_S(x).U = (v))
1041 #define HW_MCG_S_SET(x, v)       (HW_MCG_S_WR(x, HW_MCG_S_RD(x) |  (v)))
1042 #define HW_MCG_S_CLR(x, v)       (HW_MCG_S_WR(x, HW_MCG_S_RD(x) & ~(v)))
1043 #define HW_MCG_S_TOG(x, v)       (HW_MCG_S_WR(x, HW_MCG_S_RD(x) ^  (v)))
1044 /*@}*/
1045
1046 /*
1047  * Constants & macros for individual MCG_S bitfields
1048  */
1049
1050 /*!
1051  * @name Register MCG_S, field IRCST[0] (RO)
1052  *
1053  * The IRCST bit indicates the current source for the internal reference clock
1054  * select clock (IRCSCLK). The IRCST bit does not update immediately after a write
1055  * to the IRCS bit due to internal synchronization between clock domains. The
1056  * IRCST bit will only be updated if the internal reference clock is enabled,
1057  * either by the MCG being in a mode that uses the IRC or by setting the C1[IRCLKEN]
1058  * bit .
1059  *
1060  * Values:
1061  * - 0 - Source of internal reference clock is the slow clock (32 kHz IRC).
1062  * - 1 - Source of internal reference clock is the fast clock (4 MHz IRC).
1063  */
1064 /*@{*/
1065 #define BP_MCG_S_IRCST       (0U)          /*!< Bit position for MCG_S_IRCST. */
1066 #define BM_MCG_S_IRCST       (0x01U)       /*!< Bit mask for MCG_S_IRCST. */
1067 #define BS_MCG_S_IRCST       (1U)          /*!< Bit field size in bits for MCG_S_IRCST. */
1068
1069 /*! @brief Read current value of the MCG_S_IRCST field. */
1070 #define BR_MCG_S_IRCST(x)    (BITBAND_ACCESS8(HW_MCG_S_ADDR(x), BP_MCG_S_IRCST))
1071 /*@}*/
1072
1073 /*!
1074  * @name Register MCG_S, field OSCINIT0[1] (RO)
1075  *
1076  * This bit, which resets to 0, is set to 1 after the initialization cycles of
1077  * the crystal oscillator clock have completed. After being set, the bit is
1078  * cleared to 0 if the OSC is subsequently disabled. See the OSC module's detailed
1079  * description for more information.
1080  */
1081 /*@{*/
1082 #define BP_MCG_S_OSCINIT0    (1U)          /*!< Bit position for MCG_S_OSCINIT0. */
1083 #define BM_MCG_S_OSCINIT0    (0x02U)       /*!< Bit mask for MCG_S_OSCINIT0. */
1084 #define BS_MCG_S_OSCINIT0    (1U)          /*!< Bit field size in bits for MCG_S_OSCINIT0. */
1085
1086 /*! @brief Read current value of the MCG_S_OSCINIT0 field. */
1087 #define BR_MCG_S_OSCINIT0(x) (BITBAND_ACCESS8(HW_MCG_S_ADDR(x), BP_MCG_S_OSCINIT0))
1088 /*@}*/
1089
1090 /*!
1091  * @name Register MCG_S, field CLKST[3:2] (RO)
1092  *
1093  * These bits indicate the current clock mode. The CLKST bits do not update
1094  * immediately after a write to the CLKS bits due to internal synchronization between
1095  * clock domains.
1096  *
1097  * Values:
1098  * - 00 - Encoding 0 - Output of the FLL is selected (reset default).
1099  * - 01 - Encoding 1 - Internal reference clock is selected.
1100  * - 10 - Encoding 2 - External reference clock is selected.
1101  * - 11 - Encoding 3 - Output of the PLL is selected.
1102  */
1103 /*@{*/
1104 #define BP_MCG_S_CLKST       (2U)          /*!< Bit position for MCG_S_CLKST. */
1105 #define BM_MCG_S_CLKST       (0x0CU)       /*!< Bit mask for MCG_S_CLKST. */
1106 #define BS_MCG_S_CLKST       (2U)          /*!< Bit field size in bits for MCG_S_CLKST. */
1107
1108 /*! @brief Read current value of the MCG_S_CLKST field. */
1109 #define BR_MCG_S_CLKST(x)    (HW_MCG_S(x).B.CLKST)
1110 /*@}*/
1111
1112 /*!
1113  * @name Register MCG_S, field IREFST[4] (RO)
1114  *
1115  * This bit indicates the current source for the FLL reference clock. The IREFST
1116  * bit does not update immediately after a write to the IREFS bit due to
1117  * internal synchronization between clock domains.
1118  *
1119  * Values:
1120  * - 0 - Source of FLL reference clock is the external reference clock.
1121  * - 1 - Source of FLL reference clock is the internal reference clock.
1122  */
1123 /*@{*/
1124 #define BP_MCG_S_IREFST      (4U)          /*!< Bit position for MCG_S_IREFST. */
1125 #define BM_MCG_S_IREFST      (0x10U)       /*!< Bit mask for MCG_S_IREFST. */
1126 #define BS_MCG_S_IREFST      (1U)          /*!< Bit field size in bits for MCG_S_IREFST. */
1127
1128 /*! @brief Read current value of the MCG_S_IREFST field. */
1129 #define BR_MCG_S_IREFST(x)   (BITBAND_ACCESS8(HW_MCG_S_ADDR(x), BP_MCG_S_IREFST))
1130 /*@}*/
1131
1132 /*!
1133  * @name Register MCG_S, field PLLST[5] (RO)
1134  *
1135  * This bit indicates the clock source selected by PLLS . The PLLST bit does not
1136  * update immediately after a write to the PLLS bit due to internal
1137  * synchronization between clock domains.
1138  *
1139  * Values:
1140  * - 0 - Source of PLLS clock is FLL clock.
1141  * - 1 - Source of PLLS clock is PLL output clock.
1142  */
1143 /*@{*/
1144 #define BP_MCG_S_PLLST       (5U)          /*!< Bit position for MCG_S_PLLST. */
1145 #define BM_MCG_S_PLLST       (0x20U)       /*!< Bit mask for MCG_S_PLLST. */
1146 #define BS_MCG_S_PLLST       (1U)          /*!< Bit field size in bits for MCG_S_PLLST. */
1147
1148 /*! @brief Read current value of the MCG_S_PLLST field. */
1149 #define BR_MCG_S_PLLST(x)    (BITBAND_ACCESS8(HW_MCG_S_ADDR(x), BP_MCG_S_PLLST))
1150 /*@}*/
1151
1152 /*!
1153  * @name Register MCG_S, field LOCK0[6] (RO)
1154  *
1155  * This bit indicates whether the PLL has acquired lock. Lock detection is only
1156  * enabled when the PLL is enabled (either through clock mode selection or
1157  * PLLCLKEN0=1 setting). While the PLL clock is locking to the desired frequency, the
1158  * MCG PLL clock (MCGPLLCLK) will be gated off until the LOCK bit gets asserted.
1159  * If the lock status bit is set, changing the value of the PRDIV0 [4:0] bits in
1160  * the C5 register or the VDIV0[4:0] bits in the C6 register causes the lock
1161  * status bit to clear and stay cleared until the PLL has reacquired lock. Loss of PLL
1162  * reference clock will also cause the LOCK0 bit to clear until the PLL has
1163  * reacquired lock. Entry into LLS, VLPS, or regular Stop with PLLSTEN=0 also causes
1164  * the lock status bit to clear and stay cleared until the Stop mode is exited
1165  * and the PLL has reacquired lock. Any time the PLL is enabled and the LOCK0 bit
1166  * is cleared, the MCGPLLCLK will be gated off until the LOCK0 bit is asserted
1167  * again.
1168  *
1169  * Values:
1170  * - 0 - PLL is currently unlocked.
1171  * - 1 - PLL is currently locked.
1172  */
1173 /*@{*/
1174 #define BP_MCG_S_LOCK0       (6U)          /*!< Bit position for MCG_S_LOCK0. */
1175 #define BM_MCG_S_LOCK0       (0x40U)       /*!< Bit mask for MCG_S_LOCK0. */
1176 #define BS_MCG_S_LOCK0       (1U)          /*!< Bit field size in bits for MCG_S_LOCK0. */
1177
1178 /*! @brief Read current value of the MCG_S_LOCK0 field. */
1179 #define BR_MCG_S_LOCK0(x)    (BITBAND_ACCESS8(HW_MCG_S_ADDR(x), BP_MCG_S_LOCK0))
1180 /*@}*/
1181
1182 /*!
1183  * @name Register MCG_S, field LOLS0[7] (W1C)
1184  *
1185  * This bit is a sticky bit indicating the lock status for the PLL. LOLS is set
1186  * if after acquiring lock, the PLL output frequency has fallen outside the lock
1187  * exit frequency tolerance, D unl . LOLIE determines whether an interrupt
1188  * request is made when LOLS is set. LOLRE determines whether a reset request is made
1189  * when LOLS is set. This bit is cleared by reset or by writing a logic 1 to it
1190  * when set. Writing a logic 0 to this bit has no effect.
1191  *
1192  * Values:
1193  * - 0 - PLL has not lost lock since LOLS 0 was last cleared.
1194  * - 1 - PLL has lost lock since LOLS 0 was last cleared.
1195  */
1196 /*@{*/
1197 #define BP_MCG_S_LOLS0       (7U)          /*!< Bit position for MCG_S_LOLS0. */
1198 #define BM_MCG_S_LOLS0       (0x80U)       /*!< Bit mask for MCG_S_LOLS0. */
1199 #define BS_MCG_S_LOLS0       (1U)          /*!< Bit field size in bits for MCG_S_LOLS0. */
1200
1201 /*! @brief Read current value of the MCG_S_LOLS0 field. */
1202 #define BR_MCG_S_LOLS0(x)    (BITBAND_ACCESS8(HW_MCG_S_ADDR(x), BP_MCG_S_LOLS0))
1203
1204 /*! @brief Format value for bitfield MCG_S_LOLS0. */
1205 #define BF_MCG_S_LOLS0(v)    ((uint8_t)((uint8_t)(v) << BP_MCG_S_LOLS0) & BM_MCG_S_LOLS0)
1206
1207 /*! @brief Set the LOLS0 field to a new value. */
1208 #define BW_MCG_S_LOLS0(x, v) (BITBAND_ACCESS8(HW_MCG_S_ADDR(x), BP_MCG_S_LOLS0) = (v))
1209 /*@}*/
1210
1211 /*******************************************************************************
1212  * HW_MCG_SC - MCG Status and Control Register
1213  ******************************************************************************/
1214
1215 /*!
1216  * @brief HW_MCG_SC - MCG Status and Control Register (RW)
1217  *
1218  * Reset value: 0x02U
1219  */
1220 typedef union _hw_mcg_sc
1221 {
1222     uint8_t U;
1223     struct _hw_mcg_sc_bitfields
1224     {
1225         uint8_t LOCS0 : 1;             /*!< [0] OSC0 Loss of Clock Status */
1226         uint8_t FCRDIV : 3;            /*!< [3:1] Fast Clock Internal Reference Divider
1227                                         * */
1228         uint8_t FLTPRSRV : 1;          /*!< [4] FLL Filter Preserve Enable */
1229         uint8_t ATMF : 1;              /*!< [5] Automatic Trim Machine Fail Flag */
1230         uint8_t ATMS : 1;              /*!< [6] Automatic Trim Machine Select */
1231         uint8_t ATME : 1;              /*!< [7] Automatic Trim Machine Enable */
1232     } B;
1233 } hw_mcg_sc_t;
1234
1235 /*!
1236  * @name Constants and macros for entire MCG_SC register
1237  */
1238 /*@{*/
1239 #define HW_MCG_SC_ADDR(x)        ((x) + 0x8U)
1240
1241 #define HW_MCG_SC(x)             (*(__IO hw_mcg_sc_t *) HW_MCG_SC_ADDR(x))
1242 #define HW_MCG_SC_RD(x)          (HW_MCG_SC(x).U)
1243 #define HW_MCG_SC_WR(x, v)       (HW_MCG_SC(x).U = (v))
1244 #define HW_MCG_SC_SET(x, v)      (HW_MCG_SC_WR(x, HW_MCG_SC_RD(x) |  (v)))
1245 #define HW_MCG_SC_CLR(x, v)      (HW_MCG_SC_WR(x, HW_MCG_SC_RD(x) & ~(v)))
1246 #define HW_MCG_SC_TOG(x, v)      (HW_MCG_SC_WR(x, HW_MCG_SC_RD(x) ^  (v)))
1247 /*@}*/
1248
1249 /*
1250  * Constants & macros for individual MCG_SC bitfields
1251  */
1252
1253 /*!
1254  * @name Register MCG_SC, field LOCS0[0] (W1C)
1255  *
1256  * The LOCS0 indicates when a loss of OSC0 reference clock has occurred. The
1257  * LOCS0 bit only has an effect when CME0 is set. This bit is cleared by writing a
1258  * logic 1 to it when set.
1259  *
1260  * Values:
1261  * - 0 - Loss of OSC0 has not occurred.
1262  * - 1 - Loss of OSC0 has occurred.
1263  */
1264 /*@{*/
1265 #define BP_MCG_SC_LOCS0      (0U)          /*!< Bit position for MCG_SC_LOCS0. */
1266 #define BM_MCG_SC_LOCS0      (0x01U)       /*!< Bit mask for MCG_SC_LOCS0. */
1267 #define BS_MCG_SC_LOCS0      (1U)          /*!< Bit field size in bits for MCG_SC_LOCS0. */
1268
1269 /*! @brief Read current value of the MCG_SC_LOCS0 field. */
1270 #define BR_MCG_SC_LOCS0(x)   (BITBAND_ACCESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_LOCS0))
1271
1272 /*! @brief Format value for bitfield MCG_SC_LOCS0. */
1273 #define BF_MCG_SC_LOCS0(v)   ((uint8_t)((uint8_t)(v) << BP_MCG_SC_LOCS0) & BM_MCG_SC_LOCS0)
1274
1275 /*! @brief Set the LOCS0 field to a new value. */
1276 #define BW_MCG_SC_LOCS0(x, v) (BITBAND_ACCESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_LOCS0) = (v))
1277 /*@}*/
1278
1279 /*!
1280  * @name Register MCG_SC, field FCRDIV[3:1] (RW)
1281  *
1282  * Selects the amount to divide down the fast internal reference clock. The
1283  * resulting frequency will be in the range 31.25 kHz to 4 MHz (Note: Changing the
1284  * divider when the Fast IRC is enabled is not supported).
1285  *
1286  * Values:
1287  * - 000 - Divide Factor is 1
1288  * - 001 - Divide Factor is 2.
1289  * - 010 - Divide Factor is 4.
1290  * - 011 - Divide Factor is 8.
1291  * - 100 - Divide Factor is 16
1292  * - 101 - Divide Factor is 32
1293  * - 110 - Divide Factor is 64
1294  * - 111 - Divide Factor is 128.
1295  */
1296 /*@{*/
1297 #define BP_MCG_SC_FCRDIV     (1U)          /*!< Bit position for MCG_SC_FCRDIV. */
1298 #define BM_MCG_SC_FCRDIV     (0x0EU)       /*!< Bit mask for MCG_SC_FCRDIV. */
1299 #define BS_MCG_SC_FCRDIV     (3U)          /*!< Bit field size in bits for MCG_SC_FCRDIV. */
1300
1301 /*! @brief Read current value of the MCG_SC_FCRDIV field. */
1302 #define BR_MCG_SC_FCRDIV(x)  (HW_MCG_SC(x).B.FCRDIV)
1303
1304 /*! @brief Format value for bitfield MCG_SC_FCRDIV. */
1305 #define BF_MCG_SC_FCRDIV(v)  ((uint8_t)((uint8_t)(v) << BP_MCG_SC_FCRDIV) & BM_MCG_SC_FCRDIV)
1306
1307 /*! @brief Set the FCRDIV field to a new value. */
1308 #define BW_MCG_SC_FCRDIV(x, v) (HW_MCG_SC_WR(x, (HW_MCG_SC_RD(x) & ~BM_MCG_SC_FCRDIV) | BF_MCG_SC_FCRDIV(v)))
1309 /*@}*/
1310
1311 /*!
1312  * @name Register MCG_SC, field FLTPRSRV[4] (RW)
1313  *
1314  * This bit will prevent the FLL filter values from resetting allowing the FLL
1315  * output frequency to remain the same during clock mode changes where the FLL/DCO
1316  * output is still valid. (Note: This requires that the FLL reference frequency
1317  * to remain the same as what it was prior to the new clock mode switch.
1318  * Otherwise FLL filter and frequency values will change.)
1319  *
1320  * Values:
1321  * - 0 - FLL filter and FLL frequency will reset on changes to currect clock
1322  *     mode.
1323  * - 1 - Fll filter and FLL frequency retain their previous values during new
1324  *     clock mode change.
1325  */
1326 /*@{*/
1327 #define BP_MCG_SC_FLTPRSRV   (4U)          /*!< Bit position for MCG_SC_FLTPRSRV. */
1328 #define BM_MCG_SC_FLTPRSRV   (0x10U)       /*!< Bit mask for MCG_SC_FLTPRSRV. */
1329 #define BS_MCG_SC_FLTPRSRV   (1U)          /*!< Bit field size in bits for MCG_SC_FLTPRSRV. */
1330
1331 /*! @brief Read current value of the MCG_SC_FLTPRSRV field. */
1332 #define BR_MCG_SC_FLTPRSRV(x) (BITBAND_ACCESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_FLTPRSRV))
1333
1334 /*! @brief Format value for bitfield MCG_SC_FLTPRSRV. */
1335 #define BF_MCG_SC_FLTPRSRV(v) ((uint8_t)((uint8_t)(v) << BP_MCG_SC_FLTPRSRV) & BM_MCG_SC_FLTPRSRV)
1336
1337 /*! @brief Set the FLTPRSRV field to a new value. */
1338 #define BW_MCG_SC_FLTPRSRV(x, v) (BITBAND_ACCESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_FLTPRSRV) = (v))
1339 /*@}*/
1340
1341 /*!
1342  * @name Register MCG_SC, field ATMF[5] (RW)
1343  *
1344  * Fail flag for the Automatic Trim Machine (ATM). This bit asserts when the
1345  * Automatic Trim Machine is enabled, ATME=1, and a write to the C1, C3, C4, and SC
1346  * registers is detected or the MCG enters into any Stop mode. A write to ATMF
1347  * clears the flag.
1348  *
1349  * Values:
1350  * - 0 - Automatic Trim Machine completed normally.
1351  * - 1 - Automatic Trim Machine failed.
1352  */
1353 /*@{*/
1354 #define BP_MCG_SC_ATMF       (5U)          /*!< Bit position for MCG_SC_ATMF. */
1355 #define BM_MCG_SC_ATMF       (0x20U)       /*!< Bit mask for MCG_SC_ATMF. */
1356 #define BS_MCG_SC_ATMF       (1U)          /*!< Bit field size in bits for MCG_SC_ATMF. */
1357
1358 /*! @brief Read current value of the MCG_SC_ATMF field. */
1359 #define BR_MCG_SC_ATMF(x)    (BITBAND_ACCESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_ATMF))
1360
1361 /*! @brief Format value for bitfield MCG_SC_ATMF. */
1362 #define BF_MCG_SC_ATMF(v)    ((uint8_t)((uint8_t)(v) << BP_MCG_SC_ATMF) & BM_MCG_SC_ATMF)
1363
1364 /*! @brief Set the ATMF field to a new value. */
1365 #define BW_MCG_SC_ATMF(x, v) (BITBAND_ACCESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_ATMF) = (v))
1366 /*@}*/
1367
1368 /*!
1369  * @name Register MCG_SC, field ATMS[6] (RW)
1370  *
1371  * Selects the IRCS clock for Auto Trim Test.
1372  *
1373  * Values:
1374  * - 0 - 32 kHz Internal Reference Clock selected.
1375  * - 1 - 4 MHz Internal Reference Clock selected.
1376  */
1377 /*@{*/
1378 #define BP_MCG_SC_ATMS       (6U)          /*!< Bit position for MCG_SC_ATMS. */
1379 #define BM_MCG_SC_ATMS       (0x40U)       /*!< Bit mask for MCG_SC_ATMS. */
1380 #define BS_MCG_SC_ATMS       (1U)          /*!< Bit field size in bits for MCG_SC_ATMS. */
1381
1382 /*! @brief Read current value of the MCG_SC_ATMS field. */
1383 #define BR_MCG_SC_ATMS(x)    (BITBAND_ACCESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_ATMS))
1384
1385 /*! @brief Format value for bitfield MCG_SC_ATMS. */
1386 #define BF_MCG_SC_ATMS(v)    ((uint8_t)((uint8_t)(v) << BP_MCG_SC_ATMS) & BM_MCG_SC_ATMS)
1387
1388 /*! @brief Set the ATMS field to a new value. */
1389 #define BW_MCG_SC_ATMS(x, v) (BITBAND_ACCESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_ATMS) = (v))
1390 /*@}*/
1391
1392 /*!
1393  * @name Register MCG_SC, field ATME[7] (RW)
1394  *
1395  * Enables the Auto Trim Machine to start automatically trimming the selected
1396  * Internal Reference Clock. ATME deasserts after the Auto Trim Machine has
1397  * completed trimming all trim bits of the IRCS clock selected by the ATMS bit. Writing
1398  * to C1, C3, C4, and SC registers or entering Stop mode aborts the auto trim
1399  * operation and clears this bit.
1400  *
1401  * Values:
1402  * - 0 - Auto Trim Machine disabled.
1403  * - 1 - Auto Trim Machine enabled.
1404  */
1405 /*@{*/
1406 #define BP_MCG_SC_ATME       (7U)          /*!< Bit position for MCG_SC_ATME. */
1407 #define BM_MCG_SC_ATME       (0x80U)       /*!< Bit mask for MCG_SC_ATME. */
1408 #define BS_MCG_SC_ATME       (1U)          /*!< Bit field size in bits for MCG_SC_ATME. */
1409
1410 /*! @brief Read current value of the MCG_SC_ATME field. */
1411 #define BR_MCG_SC_ATME(x)    (BITBAND_ACCESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_ATME))
1412
1413 /*! @brief Format value for bitfield MCG_SC_ATME. */
1414 #define BF_MCG_SC_ATME(v)    ((uint8_t)((uint8_t)(v) << BP_MCG_SC_ATME) & BM_MCG_SC_ATME)
1415
1416 /*! @brief Set the ATME field to a new value. */
1417 #define BW_MCG_SC_ATME(x, v) (BITBAND_ACCESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_ATME) = (v))
1418 /*@}*/
1419
1420 /*******************************************************************************
1421  * HW_MCG_ATCVH - MCG Auto Trim Compare Value High Register
1422  ******************************************************************************/
1423
1424 /*!
1425  * @brief HW_MCG_ATCVH - MCG Auto Trim Compare Value High Register (RW)
1426  *
1427  * Reset value: 0x00U
1428  */
1429 typedef union _hw_mcg_atcvh
1430 {
1431     uint8_t U;
1432     struct _hw_mcg_atcvh_bitfields
1433     {
1434         uint8_t ATCVH : 8;             /*!< [7:0] ATM Compare Value High */
1435     } B;
1436 } hw_mcg_atcvh_t;
1437
1438 /*!
1439  * @name Constants and macros for entire MCG_ATCVH register
1440  */
1441 /*@{*/
1442 #define HW_MCG_ATCVH_ADDR(x)     ((x) + 0xAU)
1443
1444 #define HW_MCG_ATCVH(x)          (*(__IO hw_mcg_atcvh_t *) HW_MCG_ATCVH_ADDR(x))
1445 #define HW_MCG_ATCVH_RD(x)       (HW_MCG_ATCVH(x).U)
1446 #define HW_MCG_ATCVH_WR(x, v)    (HW_MCG_ATCVH(x).U = (v))
1447 #define HW_MCG_ATCVH_SET(x, v)   (HW_MCG_ATCVH_WR(x, HW_MCG_ATCVH_RD(x) |  (v)))
1448 #define HW_MCG_ATCVH_CLR(x, v)   (HW_MCG_ATCVH_WR(x, HW_MCG_ATCVH_RD(x) & ~(v)))
1449 #define HW_MCG_ATCVH_TOG(x, v)   (HW_MCG_ATCVH_WR(x, HW_MCG_ATCVH_RD(x) ^  (v)))
1450 /*@}*/
1451
1452 /*
1453  * Constants & macros for individual MCG_ATCVH bitfields
1454  */
1455
1456 /*!
1457  * @name Register MCG_ATCVH, field ATCVH[7:0] (RW)
1458  *
1459  * Values are used by Auto Trim Machine to compare and adjust Internal Reference
1460  * trim values during ATM SAR conversion.
1461  */
1462 /*@{*/
1463 #define BP_MCG_ATCVH_ATCVH   (0U)          /*!< Bit position for MCG_ATCVH_ATCVH. */
1464 #define BM_MCG_ATCVH_ATCVH   (0xFFU)       /*!< Bit mask for MCG_ATCVH_ATCVH. */
1465 #define BS_MCG_ATCVH_ATCVH   (8U)          /*!< Bit field size in bits for MCG_ATCVH_ATCVH. */
1466
1467 /*! @brief Read current value of the MCG_ATCVH_ATCVH field. */
1468 #define BR_MCG_ATCVH_ATCVH(x) (HW_MCG_ATCVH(x).U)
1469
1470 /*! @brief Format value for bitfield MCG_ATCVH_ATCVH. */
1471 #define BF_MCG_ATCVH_ATCVH(v) ((uint8_t)((uint8_t)(v) << BP_MCG_ATCVH_ATCVH) & BM_MCG_ATCVH_ATCVH)
1472
1473 /*! @brief Set the ATCVH field to a new value. */
1474 #define BW_MCG_ATCVH_ATCVH(x, v) (HW_MCG_ATCVH_WR(x, v))
1475 /*@}*/
1476
1477 /*******************************************************************************
1478  * HW_MCG_ATCVL - MCG Auto Trim Compare Value Low Register
1479  ******************************************************************************/
1480
1481 /*!
1482  * @brief HW_MCG_ATCVL - MCG Auto Trim Compare Value Low Register (RW)
1483  *
1484  * Reset value: 0x00U
1485  */
1486 typedef union _hw_mcg_atcvl
1487 {
1488     uint8_t U;
1489     struct _hw_mcg_atcvl_bitfields
1490     {
1491         uint8_t ATCVL : 8;             /*!< [7:0] ATM Compare Value Low */
1492     } B;
1493 } hw_mcg_atcvl_t;
1494
1495 /*!
1496  * @name Constants and macros for entire MCG_ATCVL register
1497  */
1498 /*@{*/
1499 #define HW_MCG_ATCVL_ADDR(x)     ((x) + 0xBU)
1500
1501 #define HW_MCG_ATCVL(x)          (*(__IO hw_mcg_atcvl_t *) HW_MCG_ATCVL_ADDR(x))
1502 #define HW_MCG_ATCVL_RD(x)       (HW_MCG_ATCVL(x).U)
1503 #define HW_MCG_ATCVL_WR(x, v)    (HW_MCG_ATCVL(x).U = (v))
1504 #define HW_MCG_ATCVL_SET(x, v)   (HW_MCG_ATCVL_WR(x, HW_MCG_ATCVL_RD(x) |  (v)))
1505 #define HW_MCG_ATCVL_CLR(x, v)   (HW_MCG_ATCVL_WR(x, HW_MCG_ATCVL_RD(x) & ~(v)))
1506 #define HW_MCG_ATCVL_TOG(x, v)   (HW_MCG_ATCVL_WR(x, HW_MCG_ATCVL_RD(x) ^  (v)))
1507 /*@}*/
1508
1509 /*
1510  * Constants & macros for individual MCG_ATCVL bitfields
1511  */
1512
1513 /*!
1514  * @name Register MCG_ATCVL, field ATCVL[7:0] (RW)
1515  *
1516  * Values are used by Auto Trim Machine to compare and adjust Internal Reference
1517  * trim values during ATM SAR conversion.
1518  */
1519 /*@{*/
1520 #define BP_MCG_ATCVL_ATCVL   (0U)          /*!< Bit position for MCG_ATCVL_ATCVL. */
1521 #define BM_MCG_ATCVL_ATCVL   (0xFFU)       /*!< Bit mask for MCG_ATCVL_ATCVL. */
1522 #define BS_MCG_ATCVL_ATCVL   (8U)          /*!< Bit field size in bits for MCG_ATCVL_ATCVL. */
1523
1524 /*! @brief Read current value of the MCG_ATCVL_ATCVL field. */
1525 #define BR_MCG_ATCVL_ATCVL(x) (HW_MCG_ATCVL(x).U)
1526
1527 /*! @brief Format value for bitfield MCG_ATCVL_ATCVL. */
1528 #define BF_MCG_ATCVL_ATCVL(v) ((uint8_t)((uint8_t)(v) << BP_MCG_ATCVL_ATCVL) & BM_MCG_ATCVL_ATCVL)
1529
1530 /*! @brief Set the ATCVL field to a new value. */
1531 #define BW_MCG_ATCVL_ATCVL(x, v) (HW_MCG_ATCVL_WR(x, v))
1532 /*@}*/
1533
1534 /*******************************************************************************
1535  * HW_MCG_C7 - MCG Control 7 Register
1536  ******************************************************************************/
1537
1538 /*!
1539  * @brief HW_MCG_C7 - MCG Control 7 Register (RW)
1540  *
1541  * Reset value: 0x00U
1542  */
1543 typedef union _hw_mcg_c7
1544 {
1545     uint8_t U;
1546     struct _hw_mcg_c7_bitfields
1547     {
1548         uint8_t OSCSEL : 2;            /*!< [1:0] MCG OSC Clock Select */
1549         uint8_t RESERVED0 : 6;         /*!< [7:2]  */
1550     } B;
1551 } hw_mcg_c7_t;
1552
1553 /*!
1554  * @name Constants and macros for entire MCG_C7 register
1555  */
1556 /*@{*/
1557 #define HW_MCG_C7_ADDR(x)        ((x) + 0xCU)
1558
1559 #define HW_MCG_C7(x)             (*(__IO hw_mcg_c7_t *) HW_MCG_C7_ADDR(x))
1560 #define HW_MCG_C7_RD(x)          (HW_MCG_C7(x).U)
1561 #define HW_MCG_C7_WR(x, v)       (HW_MCG_C7(x).U = (v))
1562 #define HW_MCG_C7_SET(x, v)      (HW_MCG_C7_WR(x, HW_MCG_C7_RD(x) |  (v)))
1563 #define HW_MCG_C7_CLR(x, v)      (HW_MCG_C7_WR(x, HW_MCG_C7_RD(x) & ~(v)))
1564 #define HW_MCG_C7_TOG(x, v)      (HW_MCG_C7_WR(x, HW_MCG_C7_RD(x) ^  (v)))
1565 /*@}*/
1566
1567 /*
1568  * Constants & macros for individual MCG_C7 bitfields
1569  */
1570
1571 /*!
1572  * @name Register MCG_C7, field OSCSEL[1:0] (RW)
1573  *
1574  * Selects the MCG FLL external reference clock
1575  *
1576  * Values:
1577  * - 00 - Selects Oscillator (OSCCLK0).
1578  * - 01 - Selects 32 kHz RTC Oscillator.
1579  * - 10 - Selects Oscillator (OSCCLK1).
1580  * - 11 - RESERVED
1581  */
1582 /*@{*/
1583 #define BP_MCG_C7_OSCSEL     (0U)          /*!< Bit position for MCG_C7_OSCSEL. */
1584 #define BM_MCG_C7_OSCSEL     (0x03U)       /*!< Bit mask for MCG_C7_OSCSEL. */
1585 #define BS_MCG_C7_OSCSEL     (2U)          /*!< Bit field size in bits for MCG_C7_OSCSEL. */
1586
1587 /*! @brief Read current value of the MCG_C7_OSCSEL field. */
1588 #define BR_MCG_C7_OSCSEL(x)  (HW_MCG_C7(x).B.OSCSEL)
1589
1590 /*! @brief Format value for bitfield MCG_C7_OSCSEL. */
1591 #define BF_MCG_C7_OSCSEL(v)  ((uint8_t)((uint8_t)(v) << BP_MCG_C7_OSCSEL) & BM_MCG_C7_OSCSEL)
1592
1593 /*! @brief Set the OSCSEL field to a new value. */
1594 #define BW_MCG_C7_OSCSEL(x, v) (HW_MCG_C7_WR(x, (HW_MCG_C7_RD(x) & ~BM_MCG_C7_OSCSEL) | BF_MCG_C7_OSCSEL(v)))
1595 /*@}*/
1596
1597 /*******************************************************************************
1598  * HW_MCG_C8 - MCG Control 8 Register
1599  ******************************************************************************/
1600
1601 /*!
1602  * @brief HW_MCG_C8 - MCG Control 8 Register (RW)
1603  *
1604  * Reset value: 0x80U
1605  */
1606 typedef union _hw_mcg_c8
1607 {
1608     uint8_t U;
1609     struct _hw_mcg_c8_bitfields
1610     {
1611         uint8_t LOCS1 : 1;             /*!< [0] RTC Loss of Clock Status */
1612         uint8_t RESERVED0 : 4;         /*!< [4:1]  */
1613         uint8_t CME1 : 1;              /*!< [5] Clock Monitor Enable1 */
1614         uint8_t LOLRE : 1;             /*!< [6] PLL Loss of Lock Reset Enable */
1615         uint8_t LOCRE1 : 1;            /*!< [7] Loss of Clock Reset Enable */
1616     } B;
1617 } hw_mcg_c8_t;
1618
1619 /*!
1620  * @name Constants and macros for entire MCG_C8 register
1621  */
1622 /*@{*/
1623 #define HW_MCG_C8_ADDR(x)        ((x) + 0xDU)
1624
1625 #define HW_MCG_C8(x)             (*(__IO hw_mcg_c8_t *) HW_MCG_C8_ADDR(x))
1626 #define HW_MCG_C8_RD(x)          (HW_MCG_C8(x).U)
1627 #define HW_MCG_C8_WR(x, v)       (HW_MCG_C8(x).U = (v))
1628 #define HW_MCG_C8_SET(x, v)      (HW_MCG_C8_WR(x, HW_MCG_C8_RD(x) |  (v)))
1629 #define HW_MCG_C8_CLR(x, v)      (HW_MCG_C8_WR(x, HW_MCG_C8_RD(x) & ~(v)))
1630 #define HW_MCG_C8_TOG(x, v)      (HW_MCG_C8_WR(x, HW_MCG_C8_RD(x) ^  (v)))
1631 /*@}*/
1632
1633 /*
1634  * Constants & macros for individual MCG_C8 bitfields
1635  */
1636
1637 /*!
1638  * @name Register MCG_C8, field LOCS1[0] (W1C)
1639  *
1640  * This bit indicates when a loss of clock has occurred. This bit is cleared by
1641  * writing a logic 1 to it when set.
1642  *
1643  * Values:
1644  * - 0 - Loss of RTC has not occur.
1645  * - 1 - Loss of RTC has occur
1646  */
1647 /*@{*/
1648 #define BP_MCG_C8_LOCS1      (0U)          /*!< Bit position for MCG_C8_LOCS1. */
1649 #define BM_MCG_C8_LOCS1      (0x01U)       /*!< Bit mask for MCG_C8_LOCS1. */
1650 #define BS_MCG_C8_LOCS1      (1U)          /*!< Bit field size in bits for MCG_C8_LOCS1. */
1651
1652 /*! @brief Read current value of the MCG_C8_LOCS1 field. */
1653 #define BR_MCG_C8_LOCS1(x)   (BITBAND_ACCESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_LOCS1))
1654
1655 /*! @brief Format value for bitfield MCG_C8_LOCS1. */
1656 #define BF_MCG_C8_LOCS1(v)   ((uint8_t)((uint8_t)(v) << BP_MCG_C8_LOCS1) & BM_MCG_C8_LOCS1)
1657
1658 /*! @brief Set the LOCS1 field to a new value. */
1659 #define BW_MCG_C8_LOCS1(x, v) (BITBAND_ACCESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_LOCS1) = (v))
1660 /*@}*/
1661
1662 /*!
1663  * @name Register MCG_C8, field CME1[5] (RW)
1664  *
1665  * Enables the loss of clock monitoring circuit for the output of the RTC
1666  * external reference clock. The LOCRE1 bit will determine whether an interrupt or a
1667  * reset request is generated following a loss of RTC clock indication. The CME1
1668  * bit should be set to a logic 1 when the MCG is in an operational mode that uses
1669  * the RTC as its external reference clock or if the RTC is operational. CME1 bit
1670  * must be set to a logic 0 before the MCG enters any Stop mode. Otherwise, a
1671  * reset request may occur when in Stop mode. CME1 should also be set to a logic 0
1672  * before entering VLPR or VLPW power modes.
1673  *
1674  * Values:
1675  * - 0 - External clock monitor is disabled for RTC clock.
1676  * - 1 - External clock monitor is enabled for RTC clock.
1677  */
1678 /*@{*/
1679 #define BP_MCG_C8_CME1       (5U)          /*!< Bit position for MCG_C8_CME1. */
1680 #define BM_MCG_C8_CME1       (0x20U)       /*!< Bit mask for MCG_C8_CME1. */
1681 #define BS_MCG_C8_CME1       (1U)          /*!< Bit field size in bits for MCG_C8_CME1. */
1682
1683 /*! @brief Read current value of the MCG_C8_CME1 field. */
1684 #define BR_MCG_C8_CME1(x)    (BITBAND_ACCESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_CME1))
1685
1686 /*! @brief Format value for bitfield MCG_C8_CME1. */
1687 #define BF_MCG_C8_CME1(v)    ((uint8_t)((uint8_t)(v) << BP_MCG_C8_CME1) & BM_MCG_C8_CME1)
1688
1689 /*! @brief Set the CME1 field to a new value. */
1690 #define BW_MCG_C8_CME1(x, v) (BITBAND_ACCESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_CME1) = (v))
1691 /*@}*/
1692
1693 /*!
1694  * @name Register MCG_C8, field LOLRE[6] (RW)
1695  *
1696  * Determines if an interrupt or a reset request is made following a PLL loss of
1697  * lock.
1698  *
1699  * Values:
1700  * - 0 - Interrupt request is generated on a PLL loss of lock indication. The
1701  *     PLL loss of lock interrupt enable bit must also be set to generate the
1702  *     interrupt request.
1703  * - 1 - Generate a reset request on a PLL loss of lock indication.
1704  */
1705 /*@{*/
1706 #define BP_MCG_C8_LOLRE      (6U)          /*!< Bit position for MCG_C8_LOLRE. */
1707 #define BM_MCG_C8_LOLRE      (0x40U)       /*!< Bit mask for MCG_C8_LOLRE. */
1708 #define BS_MCG_C8_LOLRE      (1U)          /*!< Bit field size in bits for MCG_C8_LOLRE. */
1709
1710 /*! @brief Read current value of the MCG_C8_LOLRE field. */
1711 #define BR_MCG_C8_LOLRE(x)   (BITBAND_ACCESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_LOLRE))
1712
1713 /*! @brief Format value for bitfield MCG_C8_LOLRE. */
1714 #define BF_MCG_C8_LOLRE(v)   ((uint8_t)((uint8_t)(v) << BP_MCG_C8_LOLRE) & BM_MCG_C8_LOLRE)
1715
1716 /*! @brief Set the LOLRE field to a new value. */
1717 #define BW_MCG_C8_LOLRE(x, v) (BITBAND_ACCESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_LOLRE) = (v))
1718 /*@}*/
1719
1720 /*!
1721  * @name Register MCG_C8, field LOCRE1[7] (RW)
1722  *
1723  * Determines if a interrupt or a reset request is made following a loss of RTC
1724  * external reference clock. The LOCRE1 only has an affect when CME1 is set.
1725  *
1726  * Values:
1727  * - 0 - Interrupt request is generated on a loss of RTC external reference
1728  *     clock.
1729  * - 1 - Generate a reset request on a loss of RTC external reference clock
1730  */
1731 /*@{*/
1732 #define BP_MCG_C8_LOCRE1     (7U)          /*!< Bit position for MCG_C8_LOCRE1. */
1733 #define BM_MCG_C8_LOCRE1     (0x80U)       /*!< Bit mask for MCG_C8_LOCRE1. */
1734 #define BS_MCG_C8_LOCRE1     (1U)          /*!< Bit field size in bits for MCG_C8_LOCRE1. */
1735
1736 /*! @brief Read current value of the MCG_C8_LOCRE1 field. */
1737 #define BR_MCG_C8_LOCRE1(x)  (BITBAND_ACCESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_LOCRE1))
1738
1739 /*! @brief Format value for bitfield MCG_C8_LOCRE1. */
1740 #define BF_MCG_C8_LOCRE1(v)  ((uint8_t)((uint8_t)(v) << BP_MCG_C8_LOCRE1) & BM_MCG_C8_LOCRE1)
1741
1742 /*! @brief Set the LOCRE1 field to a new value. */
1743 #define BW_MCG_C8_LOCRE1(x, v) (BITBAND_ACCESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_LOCRE1) = (v))
1744 /*@}*/
1745
1746 /*******************************************************************************
1747  * hw_mcg_t - module struct
1748  ******************************************************************************/
1749 /*!
1750  * @brief All MCG module registers.
1751  */
1752 #pragma pack(1)
1753 typedef struct _hw_mcg
1754 {
1755     __IO hw_mcg_c1_t C1;                   /*!< [0x0] MCG Control 1 Register */
1756     __IO hw_mcg_c2_t C2;                   /*!< [0x1] MCG Control 2 Register */
1757     __IO hw_mcg_c3_t C3;                   /*!< [0x2] MCG Control 3 Register */
1758     __IO hw_mcg_c4_t C4;                   /*!< [0x3] MCG Control 4 Register */
1759     __IO hw_mcg_c5_t C5;                   /*!< [0x4] MCG Control 5 Register */
1760     __IO hw_mcg_c6_t C6;                   /*!< [0x5] MCG Control 6 Register */
1761     __IO hw_mcg_s_t S;                     /*!< [0x6] MCG Status Register */
1762     uint8_t _reserved0[1];
1763     __IO hw_mcg_sc_t SC;                   /*!< [0x8] MCG Status and Control Register */
1764     uint8_t _reserved1[1];
1765     __IO hw_mcg_atcvh_t ATCVH;             /*!< [0xA] MCG Auto Trim Compare Value High Register */
1766     __IO hw_mcg_atcvl_t ATCVL;             /*!< [0xB] MCG Auto Trim Compare Value Low Register */
1767     __IO hw_mcg_c7_t C7;                   /*!< [0xC] MCG Control 7 Register */
1768     __IO hw_mcg_c8_t C8;                   /*!< [0xD] MCG Control 8 Register */
1769 } hw_mcg_t;
1770 #pragma pack()
1771
1772 /*! @brief Macro to access all MCG registers. */
1773 /*! @param x MCG module instance base address. */
1774 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
1775  *     use the '&' operator, like <code>&HW_MCG(MCG_BASE)</code>. */
1776 #define HW_MCG(x)      (*(hw_mcg_t *)(x))
1777
1778 #endif /* __HW_MCG_REGISTERS_H__ */
1779 /* EOF */