tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_osc.h

   1 /*
   2 ** ###################################################################
   3 **     Compilers:           Keil ARM C/C++ Compiler
   4 **                          Freescale C/C++ for Embedded ARM
   5 **                          GNU C Compiler
   6 **                          IAR ANSI C/C++ Compiler for ARM
   7 **
   8 **     Reference manual:    K22P121M120SF7RM, Rev. 1, March 24, 2014
   9 **     Version:             rev. 2.5, 2014-05-06
  10 **     Build:               b140604
  11 **
  12 **     Abstract:
  13 **         Extension to the CMSIS register access layer header.
  14 **
  15 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
  16 **     All rights reserved.
  17 **
  18 **     Redistribution and use in source and binary forms, with or without modification,
  19 **     are permitted provided that the following conditions are met:
  20 **
  21 **     o Redistributions of source code must retain the above copyright notice, this list
  22 **       of conditions and the following disclaimer.
  23 **
  24 **     o Redistributions in binary form must reproduce the above copyright notice, this
  25 **       list of conditions and the following disclaimer in the documentation and/or
  26 **       other materials provided with the distribution.
  27 **
  28 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  29 **       contributors may be used to endorse or promote products derived from this
  30 **       software without specific prior written permission.
  31 **
  32 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  33 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  34 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  35 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  36 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  37 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  38 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  39 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  41 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42 **
  43 **     http:                 www.freescale.com
  44 **     mail:                 support@freescale.com
  45 **
  46 **     Revisions:
  47 **     - rev. 1.0 (2013-07-23)
  48 **         Initial version.
  49 **     - rev. 1.1 (2013-09-17)
  50 **         RM rev. 0.4 update.
  51 **     - rev. 2.0 (2013-10-29)
  52 **         Register accessor macros added to the memory map.
  53 **         Symbols for Processor Expert memory map compatibility added to the memory map.
  54 **         Startup file for gcc has been updated according to CMSIS 3.2.
  55 **         System initialization updated.
  56 **     - rev. 2.1 (2013-10-30)
  57 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
  58 **     - rev. 2.2 (2013-12-20)
  59 **         Update according to reference manual rev. 0.6,
  60 **     - rev. 2.3 (2014-01-13)
  61 **         Update according to reference manual rev. 0.61,
  62 **     - rev. 2.4 (2014-02-10)
  63 **         The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
  64 **     - rev. 2.5 (2014-05-06)
  65 **         Update according to reference manual rev. 1.0,
  66 **         Update of system and startup files.
  67 **         Module access macro module_BASES replaced by module_BASE_PTRS.
  68 **
  69 ** ###################################################################
  70 */
  71
  72 /*
  73  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
  74  *
  75  * This file was generated automatically and any changes may be lost.
  76  */
  77 #ifndef __HW_OSC_REGISTERS_H__
  78 #define __HW_OSC_REGISTERS_H__
  79
  80 #include "MK22F51212.h"
  81 #include "fsl_bitaccess.h"
  82
  83 /*
  84  * MK22F51212 OSC
  85  *
  86  * Oscillator
  87  *
  88  * Registers defined in this header file:
  89  * - HW_OSC_CR - OSC Control Register
  90  * - HW_OSC_DIV - OSC_DIV
  91  *
  92  * - hw_osc_t - Struct containing all module registers.
  93  */
  94
  95 #define HW_OSC_INSTANCE_COUNT (1U) /*!< Number of instances of the OSC module. */
  96
  97 /*******************************************************************************
  98  * HW_OSC_CR - OSC Control Register
  99  ******************************************************************************/
 100
 101 /*!
 102  * @brief HW_OSC_CR - OSC Control Register (RW)
 103  *
 104  * Reset value: 0x00U
 105  *
 106  * After OSC is enabled and starts generating the clocks, the configurations
 107  * such as low power and frequency range, must not be changed.
 108  */
 109 typedef union _hw_osc_cr
 110 {
 111     uint8_t U;
 112     struct _hw_osc_cr_bitfields
 113     {
 114         uint8_t SC16P : 1;             /*!< [0] Oscillator 16 pF Capacitor Load Configure
 115                                         * */
 116         uint8_t SC8P : 1;              /*!< [1] Oscillator 8 pF Capacitor Load Configure */
 117         uint8_t SC4P : 1;              /*!< [2] Oscillator 4 pF Capacitor Load Configure */
 118         uint8_t SC2P : 1;              /*!< [3] Oscillator 2 pF Capacitor Load Configure */
 119         uint8_t RESERVED0 : 1;         /*!< [4]  */
 120         uint8_t EREFSTEN : 1;          /*!< [5] External Reference Stop Enable */
 121         uint8_t RESERVED1 : 1;         /*!< [6]  */
 122         uint8_t ERCLKEN : 1;           /*!< [7] External Reference Enable */
 123     } B;
 124 } hw_osc_cr_t;
 125
 126 /*!
 127  * @name Constants and macros for entire OSC_CR register
 128  */
 129 /*@{*/
 130 #define HW_OSC_CR_ADDR(x)        ((x) + 0x0U)
 131
 132 #define HW_OSC_CR(x)             (*(__IO hw_osc_cr_t *) HW_OSC_CR_ADDR(x))
 133 #define HW_OSC_CR_RD(x)          (HW_OSC_CR(x).U)
 134 #define HW_OSC_CR_WR(x, v)       (HW_OSC_CR(x).U = (v))
 135 #define HW_OSC_CR_SET(x, v)      (HW_OSC_CR_WR(x, HW_OSC_CR_RD(x) |  (v)))
 136 #define HW_OSC_CR_CLR(x, v)      (HW_OSC_CR_WR(x, HW_OSC_CR_RD(x) & ~(v)))
 137 #define HW_OSC_CR_TOG(x, v)      (HW_OSC_CR_WR(x, HW_OSC_CR_RD(x) ^  (v)))
 138 /*@}*/
 139
 140 /*
 141  * Constants & macros for individual OSC_CR bitfields
 142  */
 143
 144 /*!
 145  * @name Register OSC_CR, field SC16P[0] (RW)
 146  *
 147  * Configures the oscillator load.
 148  *
 149  * Values:
 150  * - 0 - Disable the selection.
 151  * - 1 - Add 16 pF capacitor to the oscillator load.
 152  */
 153 /*@{*/
 154 #define BP_OSC_CR_SC16P      (0U)          /*!< Bit position for OSC_CR_SC16P. */
 155 #define BM_OSC_CR_SC16P      (0x01U)       /*!< Bit mask for OSC_CR_SC16P. */
 156 #define BS_OSC_CR_SC16P      (1U)          /*!< Bit field size in bits for OSC_CR_SC16P. */
 157
 158 /*! @brief Read current value of the OSC_CR_SC16P field. */
 159 #define BR_OSC_CR_SC16P(x)   (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC16P))
 160
 161 /*! @brief Format value for bitfield OSC_CR_SC16P. */
 162 #define BF_OSC_CR_SC16P(v)   ((uint8_t)((uint8_t)(v) << BP_OSC_CR_SC16P) & BM_OSC_CR_SC16P)
 163
 164 /*! @brief Set the SC16P field to a new value. */
 165 #define BW_OSC_CR_SC16P(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC16P) = (v))
 166 /*@}*/
 167
 168 /*!
 169  * @name Register OSC_CR, field SC8P[1] (RW)
 170  *
 171  * Configures the oscillator load.
 172  *
 173  * Values:
 174  * - 0 - Disable the selection.
 175  * - 1 - Add 8 pF capacitor to the oscillator load.
 176  */
 177 /*@{*/
 178 #define BP_OSC_CR_SC8P       (1U)          /*!< Bit position for OSC_CR_SC8P. */
 179 #define BM_OSC_CR_SC8P       (0x02U)       /*!< Bit mask for OSC_CR_SC8P. */
 180 #define BS_OSC_CR_SC8P       (1U)          /*!< Bit field size in bits for OSC_CR_SC8P. */
 181
 182 /*! @brief Read current value of the OSC_CR_SC8P field. */
 183 #define BR_OSC_CR_SC8P(x)    (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC8P))
 184
 185 /*! @brief Format value for bitfield OSC_CR_SC8P. */
 186 #define BF_OSC_CR_SC8P(v)    ((uint8_t)((uint8_t)(v) << BP_OSC_CR_SC8P) & BM_OSC_CR_SC8P)
 187
 188 /*! @brief Set the SC8P field to a new value. */
 189 #define BW_OSC_CR_SC8P(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC8P) = (v))
 190 /*@}*/
 191
 192 /*!
 193  * @name Register OSC_CR, field SC4P[2] (RW)
 194  *
 195  * Configures the oscillator load.
 196  *
 197  * Values:
 198  * - 0 - Disable the selection.
 199  * - 1 - Add 4 pF capacitor to the oscillator load.
 200  */
 201 /*@{*/
 202 #define BP_OSC_CR_SC4P       (2U)          /*!< Bit position for OSC_CR_SC4P. */
 203 #define BM_OSC_CR_SC4P       (0x04U)       /*!< Bit mask for OSC_CR_SC4P. */
 204 #define BS_OSC_CR_SC4P       (1U)          /*!< Bit field size in bits for OSC_CR_SC4P. */
 205
 206 /*! @brief Read current value of the OSC_CR_SC4P field. */
 207 #define BR_OSC_CR_SC4P(x)    (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC4P))
 208
 209 /*! @brief Format value for bitfield OSC_CR_SC4P. */
 210 #define BF_OSC_CR_SC4P(v)    ((uint8_t)((uint8_t)(v) << BP_OSC_CR_SC4P) & BM_OSC_CR_SC4P)
 211
 212 /*! @brief Set the SC4P field to a new value. */
 213 #define BW_OSC_CR_SC4P(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC4P) = (v))
 214 /*@}*/
 215
 216 /*!
 217  * @name Register OSC_CR, field SC2P[3] (RW)
 218  *
 219  * Configures the oscillator load.
 220  *
 221  * Values:
 222  * - 0 - Disable the selection.
 223  * - 1 - Add 2 pF capacitor to the oscillator load.
 224  */
 225 /*@{*/
 226 #define BP_OSC_CR_SC2P       (3U)          /*!< Bit position for OSC_CR_SC2P. */
 227 #define BM_OSC_CR_SC2P       (0x08U)       /*!< Bit mask for OSC_CR_SC2P. */
 228 #define BS_OSC_CR_SC2P       (1U)          /*!< Bit field size in bits for OSC_CR_SC2P. */
 229
 230 /*! @brief Read current value of the OSC_CR_SC2P field. */
 231 #define BR_OSC_CR_SC2P(x)    (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC2P))
 232
 233 /*! @brief Format value for bitfield OSC_CR_SC2P. */
 234 #define BF_OSC_CR_SC2P(v)    ((uint8_t)((uint8_t)(v) << BP_OSC_CR_SC2P) & BM_OSC_CR_SC2P)
 235
 236 /*! @brief Set the SC2P field to a new value. */
 237 #define BW_OSC_CR_SC2P(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC2P) = (v))
 238 /*@}*/
 239
 240 /*!
 241  * @name Register OSC_CR, field EREFSTEN[5] (RW)
 242  *
 243  * Controls whether or not the external reference clock (OSCERCLK) remains
 244  * enabled when MCU enters Stop mode.
 245  *
 246  * Values:
 247  * - 0 - External reference clock is disabled in Stop mode.
 248  * - 1 - External reference clock stays enabled in Stop mode if ERCLKEN is set
 249  *     before entering Stop mode.
 250  */
 251 /*@{*/
 252 #define BP_OSC_CR_EREFSTEN   (5U)          /*!< Bit position for OSC_CR_EREFSTEN. */
 253 #define BM_OSC_CR_EREFSTEN   (0x20U)       /*!< Bit mask for OSC_CR_EREFSTEN. */
 254 #define BS_OSC_CR_EREFSTEN   (1U)          /*!< Bit field size in bits for OSC_CR_EREFSTEN. */
 255
 256 /*! @brief Read current value of the OSC_CR_EREFSTEN field. */
 257 #define BR_OSC_CR_EREFSTEN(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_EREFSTEN))
 258
 259 /*! @brief Format value for bitfield OSC_CR_EREFSTEN. */
 260 #define BF_OSC_CR_EREFSTEN(v) ((uint8_t)((uint8_t)(v) << BP_OSC_CR_EREFSTEN) & BM_OSC_CR_EREFSTEN)
 261
 262 /*! @brief Set the EREFSTEN field to a new value. */
 263 #define BW_OSC_CR_EREFSTEN(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_EREFSTEN) = (v))
 264 /*@}*/
 265
 266 /*!
 267  * @name Register OSC_CR, field ERCLKEN[7] (RW)
 268  *
 269  * Enables external reference clock (OSCERCLK).
 270  *
 271  * Values:
 272  * - 0 - External reference clock is inactive.
 273  * - 1 - External reference clock is enabled.
 274  */
 275 /*@{*/
 276 #define BP_OSC_CR_ERCLKEN    (7U)          /*!< Bit position for OSC_CR_ERCLKEN. */
 277 #define BM_OSC_CR_ERCLKEN    (0x80U)       /*!< Bit mask for OSC_CR_ERCLKEN. */
 278 #define BS_OSC_CR_ERCLKEN    (1U)          /*!< Bit field size in bits for OSC_CR_ERCLKEN. */
 279
 280 /*! @brief Read current value of the OSC_CR_ERCLKEN field. */
 281 #define BR_OSC_CR_ERCLKEN(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_ERCLKEN))
 282
 283 /*! @brief Format value for bitfield OSC_CR_ERCLKEN. */
 284 #define BF_OSC_CR_ERCLKEN(v) ((uint8_t)((uint8_t)(v) << BP_OSC_CR_ERCLKEN) & BM_OSC_CR_ERCLKEN)
 285
 286 /*! @brief Set the ERCLKEN field to a new value. */
 287 #define BW_OSC_CR_ERCLKEN(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_ERCLKEN) = (v))
 288 /*@}*/
 289
 290 /*******************************************************************************
 291  * HW_OSC_DIV - OSC_DIV
 292  ******************************************************************************/
 293
 294 /*!
 295  * @brief HW_OSC_DIV - OSC_DIV (RW)
 296  *
 297  * Reset value: 0x00U
 298  *
 299  * OSC CLock divider register.
 300  */
 301 typedef union _hw_osc_div
 302 {
 303     uint8_t U;
 304     struct _hw_osc_div_bitfields
 305     {
 306         uint8_t RESERVED0 : 6;         /*!< [5:0]  */
 307         uint8_t ERPS : 2;              /*!< [7:6]  */
 308     } B;
 309 } hw_osc_div_t;
 310
 311 /*!
 312  * @name Constants and macros for entire OSC_DIV register
 313  */
 314 /*@{*/
 315 #define HW_OSC_DIV_ADDR(x)       ((x) + 0x2U)
 316
 317 #define HW_OSC_DIV(x)            (*(__IO hw_osc_div_t *) HW_OSC_DIV_ADDR(x))
 318 #define HW_OSC_DIV_RD(x)         (HW_OSC_DIV(x).U)
 319 #define HW_OSC_DIV_WR(x, v)      (HW_OSC_DIV(x).U = (v))
 320 #define HW_OSC_DIV_SET(x, v)     (HW_OSC_DIV_WR(x, HW_OSC_DIV_RD(x) |  (v)))
 321 #define HW_OSC_DIV_CLR(x, v)     (HW_OSC_DIV_WR(x, HW_OSC_DIV_RD(x) & ~(v)))
 322 #define HW_OSC_DIV_TOG(x, v)     (HW_OSC_DIV_WR(x, HW_OSC_DIV_RD(x) ^  (v)))
 323 /*@}*/
 324
 325 /*
 326  * Constants & macros for individual OSC_DIV bitfields
 327  */
 328
 329 /*!
 330  * @name Register OSC_DIV, field ERPS[7:6] (RW)
 331  *
 332  * ERCLK prescaler. These two bits are used to divide the ERCLK output. The
 333  * un-divided ERCLK output is not affected by these two bits.
 334  *
 335  * Values:
 336  * - 00 - The divisor ratio is 1.
 337  * - 01 - The divisor ratio is 2.
 338  * - 10 - The divisor ratio is 4.
 339  * - 11 - The divisor ratio is 8.
 340  */
 341 /*@{*/
 342 #define BP_OSC_DIV_ERPS      (6U)          /*!< Bit position for OSC_DIV_ERPS. */
 343 #define BM_OSC_DIV_ERPS      (0xC0U)       /*!< Bit mask for OSC_DIV_ERPS. */
 344 #define BS_OSC_DIV_ERPS      (2U)          /*!< Bit field size in bits for OSC_DIV_ERPS. */
 345
 346 /*! @brief Read current value of the OSC_DIV_ERPS field. */
 347 #define BR_OSC_DIV_ERPS(x)   (HW_OSC_DIV(x).B.ERPS)
 348
 349 /*! @brief Format value for bitfield OSC_DIV_ERPS. */
 350 #define BF_OSC_DIV_ERPS(v)   ((uint8_t)((uint8_t)(v) << BP_OSC_DIV_ERPS) & BM_OSC_DIV_ERPS)
 351
 352 /*! @brief Set the ERPS field to a new value. */
 353 #define BW_OSC_DIV_ERPS(x, v) (HW_OSC_DIV_WR(x, (HW_OSC_DIV_RD(x) & ~BM_OSC_DIV_ERPS) | BF_OSC_DIV_ERPS(v)))
 354 /*@}*/
 355
 356 /*******************************************************************************
 357  * hw_osc_t - module struct
 358  ******************************************************************************/
 359 /*!
 360  * @brief All OSC module registers.
 361  */
 362 #pragma pack(1)
 363 typedef struct _hw_osc
 364 {
 365     __IO hw_osc_cr_t CR;                   /*!< [0x0] OSC Control Register */
 366     uint8_t _reserved0[1];
 367     __IO hw_osc_div_t DIV;                 /*!< [0x2] OSC_DIV */
 368 } hw_osc_t;
 369 #pragma pack()
 370
 371 /*! @brief Macro to access all OSC registers. */
 372 /*! @param x OSC module instance base address. */
 373 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
 374  *     use the '&' operator, like <code>&HW_OSC(OSC_BASE)</code>. */
 375 #define HW_OSC(x)      (*(hw_osc_t *)(x))
 376
 377 #endif /* __HW_OSC_REGISTERS_H__ */
 378 /* EOF */