2 ** ###################################################################
3 ** Compilers: Keil ARM C/C++ Compiler
4 ** Freescale C/C++ for Embedded ARM
6 ** IAR ANSI C/C++ Compiler for ARM
8 ** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
9 ** Version: rev. 2.5, 2014-05-06
13 ** Extension to the CMSIS register access layer header.
15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
16 ** All rights reserved.
18 ** Redistribution and use in source and binary forms, with or without modification,
19 ** are permitted provided that the following conditions are met:
21 ** o Redistributions of source code must retain the above copyright notice, this list
22 ** of conditions and the following disclaimer.
24 ** o Redistributions in binary form must reproduce the above copyright notice, this
25 ** list of conditions and the following disclaimer in the documentation and/or
26 ** other materials provided with the distribution.
28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
29 ** contributors may be used to endorse or promote products derived from this
30 ** software without specific prior written permission.
32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 ** http: www.freescale.com
44 ** mail: support@freescale.com
47 ** - rev. 1.0 (2013-07-23)
49 ** - rev. 1.1 (2013-09-17)
50 ** RM rev. 0.4 update.
51 ** - rev. 2.0 (2013-10-29)
52 ** Register accessor macros added to the memory map.
53 ** Symbols for Processor Expert memory map compatibility added to the memory map.
54 ** Startup file for gcc has been updated according to CMSIS 3.2.
55 ** System initialization updated.
56 ** - rev. 2.1 (2013-10-30)
57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
58 ** - rev. 2.2 (2013-12-20)
59 ** Update according to reference manual rev. 0.6,
60 ** - rev. 2.3 (2014-01-13)
61 ** Update according to reference manual rev. 0.61,
62 ** - rev. 2.4 (2014-02-10)
63 ** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
64 ** - rev. 2.5 (2014-05-06)
65 ** Update according to reference manual rev. 1.0,
66 ** Update of system and startup files.
67 ** Module access macro module_BASES replaced by module_BASE_PTRS.
69 ** ###################################################################
73 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
75 * This file was generated automatically and any changes may be lost.
77 #ifndef __HW_PDB_REGISTERS_H__
78 #define __HW_PDB_REGISTERS_H__
80 #include "MK22F51212.h"
81 #include "fsl_bitaccess.h"
86 * Programmable Delay Block
88 * Registers defined in this header file:
89 * - HW_PDB_SC - Status and Control register
90 * - HW_PDB_MOD - Modulus register
91 * - HW_PDB_CNT - Counter register
92 * - HW_PDB_IDLY - Interrupt Delay register
93 * - HW_PDB_CHnC1 - Channel n Control register 1
94 * - HW_PDB_CHnS - Channel n Status register
95 * - HW_PDB_CHnDLY0 - Channel n Delay 0 register
96 * - HW_PDB_CHnDLY1 - Channel n Delay 1 register
97 * - HW_PDB_DACINTCn - DAC Interval Trigger n Control register
98 * - HW_PDB_DACINTn - DAC Interval n register
99 * - HW_PDB_POEN - Pulse-Out n Enable register
100 * - HW_PDB_POnDLY - Pulse-Out n Delay register
102 * - hw_pdb_t - Struct containing all module registers.
105 #define HW_PDB_INSTANCE_COUNT (1U) /*!< Number of instances of the PDB module. */
107 /*******************************************************************************
108 * HW_PDB_SC - Status and Control register
109 ******************************************************************************/
112 * @brief HW_PDB_SC - Status and Control register (RW)
114 * Reset value: 0x00000000U
116 typedef union _hw_pdb_sc
119 struct _hw_pdb_sc_bitfields
121 uint32_t LDOK
: 1; /*!< [0] Load OK */
122 uint32_t CONT
: 1; /*!< [1] Continuous Mode Enable */
123 uint32_t MULT
: 2; /*!< [3:2] Multiplication Factor Select for
125 uint32_t RESERVED0
: 1; /*!< [4] */
126 uint32_t PDBIE
: 1; /*!< [5] PDB Interrupt Enable */
127 uint32_t PDBIF
: 1; /*!< [6] PDB Interrupt Flag */
128 uint32_t PDBEN
: 1; /*!< [7] PDB Enable */
129 uint32_t TRGSEL
: 4; /*!< [11:8] Trigger Input Source Select */
130 uint32_t PRESCALER
: 3; /*!< [14:12] Prescaler Divider Select */
131 uint32_t DMAEN
: 1; /*!< [15] DMA Enable */
132 uint32_t SWTRIG
: 1; /*!< [16] Software Trigger */
133 uint32_t PDBEIE
: 1; /*!< [17] PDB Sequence Error Interrupt Enable */
134 uint32_t LDMOD
: 2; /*!< [19:18] Load Mode Select */
135 uint32_t RESERVED1
: 12; /*!< [31:20] */
140 * @name Constants and macros for entire PDB_SC register
143 #define HW_PDB_SC_ADDR(x) ((x) + 0x0U)
145 #define HW_PDB_SC(x) (*(__IO hw_pdb_sc_t *) HW_PDB_SC_ADDR(x))
146 #define HW_PDB_SC_RD(x) (HW_PDB_SC(x).U)
147 #define HW_PDB_SC_WR(x, v) (HW_PDB_SC(x).U = (v))
148 #define HW_PDB_SC_SET(x, v) (HW_PDB_SC_WR(x, HW_PDB_SC_RD(x) | (v)))
149 #define HW_PDB_SC_CLR(x, v) (HW_PDB_SC_WR(x, HW_PDB_SC_RD(x) & ~(v)))
150 #define HW_PDB_SC_TOG(x, v) (HW_PDB_SC_WR(x, HW_PDB_SC_RD(x) ^ (v)))
154 * Constants & macros for individual PDB_SC bitfields
158 * @name Register PDB_SC, field LDOK[0] (RW)
160 * Writing 1 to this bit updates the internal registers of MOD, IDLY, CHnDLYm,
161 * DACINTx,and POyDLY with the values written to their buffers. The MOD, IDLY,
162 * CHnDLYm, DACINTx, and POyDLY will take effect according to the LDMOD. After 1 is
163 * written to the LDOK field, the values in the buffers of above registers are
164 * not effective and the buffers cannot be written until the values in buffers are
165 * loaded into their internal registers. LDOK can be written only when PDBEN is
166 * set or it can be written at the same time with PDBEN being written to 1. It is
167 * automatically cleared when the values in buffers are loaded into the internal
168 * registers or the PDBEN is cleared. Writing 0 to it has no effect.
171 #define BP_PDB_SC_LDOK (0U) /*!< Bit position for PDB_SC_LDOK. */
172 #define BM_PDB_SC_LDOK (0x00000001U) /*!< Bit mask for PDB_SC_LDOK. */
173 #define BS_PDB_SC_LDOK (1U) /*!< Bit field size in bits for PDB_SC_LDOK. */
175 /*! @brief Read current value of the PDB_SC_LDOK field. */
176 #define BR_PDB_SC_LDOK(x) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_LDOK))
178 /*! @brief Format value for bitfield PDB_SC_LDOK. */
179 #define BF_PDB_SC_LDOK(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_LDOK) & BM_PDB_SC_LDOK)
181 /*! @brief Set the LDOK field to a new value. */
182 #define BW_PDB_SC_LDOK(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_LDOK) = (v))
186 * @name Register PDB_SC, field CONT[1] (RW)
188 * Enables the PDB operation in Continuous mode.
191 * - 0 - PDB operation in One-Shot mode
192 * - 1 - PDB operation in Continuous mode
195 #define BP_PDB_SC_CONT (1U) /*!< Bit position for PDB_SC_CONT. */
196 #define BM_PDB_SC_CONT (0x00000002U) /*!< Bit mask for PDB_SC_CONT. */
197 #define BS_PDB_SC_CONT (1U) /*!< Bit field size in bits for PDB_SC_CONT. */
199 /*! @brief Read current value of the PDB_SC_CONT field. */
200 #define BR_PDB_SC_CONT(x) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_CONT))
202 /*! @brief Format value for bitfield PDB_SC_CONT. */
203 #define BF_PDB_SC_CONT(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_CONT) & BM_PDB_SC_CONT)
205 /*! @brief Set the CONT field to a new value. */
206 #define BW_PDB_SC_CONT(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_CONT) = (v))
210 * @name Register PDB_SC, field MULT[3:2] (RW)
212 * Selects the multiplication factor of the prescaler divider for the counter
216 * - 00 - Multiplication factor is 1.
217 * - 01 - Multiplication factor is 10.
218 * - 10 - Multiplication factor is 20.
219 * - 11 - Multiplication factor is 40.
222 #define BP_PDB_SC_MULT (2U) /*!< Bit position for PDB_SC_MULT. */
223 #define BM_PDB_SC_MULT (0x0000000CU) /*!< Bit mask for PDB_SC_MULT. */
224 #define BS_PDB_SC_MULT (2U) /*!< Bit field size in bits for PDB_SC_MULT. */
226 /*! @brief Read current value of the PDB_SC_MULT field. */
227 #define BR_PDB_SC_MULT(x) (HW_PDB_SC(x).B.MULT)
229 /*! @brief Format value for bitfield PDB_SC_MULT. */
230 #define BF_PDB_SC_MULT(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_MULT) & BM_PDB_SC_MULT)
232 /*! @brief Set the MULT field to a new value. */
233 #define BW_PDB_SC_MULT(x, v) (HW_PDB_SC_WR(x, (HW_PDB_SC_RD(x) & ~BM_PDB_SC_MULT) | BF_PDB_SC_MULT(v)))
237 * @name Register PDB_SC, field PDBIE[5] (RW)
239 * Enables the PDB interrupt. When this field is set and DMAEN is cleared, PDBIF
240 * generates a PDB interrupt.
243 * - 0 - PDB interrupt disabled.
244 * - 1 - PDB interrupt enabled.
247 #define BP_PDB_SC_PDBIE (5U) /*!< Bit position for PDB_SC_PDBIE. */
248 #define BM_PDB_SC_PDBIE (0x00000020U) /*!< Bit mask for PDB_SC_PDBIE. */
249 #define BS_PDB_SC_PDBIE (1U) /*!< Bit field size in bits for PDB_SC_PDBIE. */
251 /*! @brief Read current value of the PDB_SC_PDBIE field. */
252 #define BR_PDB_SC_PDBIE(x) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBIE))
254 /*! @brief Format value for bitfield PDB_SC_PDBIE. */
255 #define BF_PDB_SC_PDBIE(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_PDBIE) & BM_PDB_SC_PDBIE)
257 /*! @brief Set the PDBIE field to a new value. */
258 #define BW_PDB_SC_PDBIE(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBIE) = (v))
262 * @name Register PDB_SC, field PDBIF[6] (RW)
264 * This field is set when the counter value is equal to the IDLY register.
265 * Writing zero clears this field.
268 #define BP_PDB_SC_PDBIF (6U) /*!< Bit position for PDB_SC_PDBIF. */
269 #define BM_PDB_SC_PDBIF (0x00000040U) /*!< Bit mask for PDB_SC_PDBIF. */
270 #define BS_PDB_SC_PDBIF (1U) /*!< Bit field size in bits for PDB_SC_PDBIF. */
272 /*! @brief Read current value of the PDB_SC_PDBIF field. */
273 #define BR_PDB_SC_PDBIF(x) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBIF))
275 /*! @brief Format value for bitfield PDB_SC_PDBIF. */
276 #define BF_PDB_SC_PDBIF(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_PDBIF) & BM_PDB_SC_PDBIF)
278 /*! @brief Set the PDBIF field to a new value. */
279 #define BW_PDB_SC_PDBIF(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBIF) = (v))
283 * @name Register PDB_SC, field PDBEN[7] (RW)
286 * - 0 - PDB disabled. Counter is off.
290 #define BP_PDB_SC_PDBEN (7U) /*!< Bit position for PDB_SC_PDBEN. */
291 #define BM_PDB_SC_PDBEN (0x00000080U) /*!< Bit mask for PDB_SC_PDBEN. */
292 #define BS_PDB_SC_PDBEN (1U) /*!< Bit field size in bits for PDB_SC_PDBEN. */
294 /*! @brief Read current value of the PDB_SC_PDBEN field. */
295 #define BR_PDB_SC_PDBEN(x) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBEN))
297 /*! @brief Format value for bitfield PDB_SC_PDBEN. */
298 #define BF_PDB_SC_PDBEN(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_PDBEN) & BM_PDB_SC_PDBEN)
300 /*! @brief Set the PDBEN field to a new value. */
301 #define BW_PDB_SC_PDBEN(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBEN) = (v))
305 * @name Register PDB_SC, field TRGSEL[11:8] (RW)
307 * Selects the trigger input source for the PDB. The trigger input source can be
308 * internal or external (EXTRG pin), or the software trigger. Refer to chip
309 * configuration details for the actual PDB input trigger connections.
312 * - 0000 - Trigger-In 0 is selected.
313 * - 0001 - Trigger-In 1 is selected.
314 * - 0010 - Trigger-In 2 is selected.
315 * - 0011 - Trigger-In 3 is selected.
316 * - 0100 - Trigger-In 4 is selected.
317 * - 0101 - Trigger-In 5 is selected.
318 * - 0110 - Trigger-In 6 is selected.
319 * - 0111 - Trigger-In 7 is selected.
320 * - 1000 - Trigger-In 8 is selected.
321 * - 1001 - Trigger-In 9 is selected.
322 * - 1010 - Trigger-In 10 is selected.
323 * - 1011 - Trigger-In 11 is selected.
324 * - 1100 - Trigger-In 12 is selected.
325 * - 1101 - Trigger-In 13 is selected.
326 * - 1110 - Trigger-In 14 is selected.
327 * - 1111 - Software trigger is selected.
330 #define BP_PDB_SC_TRGSEL (8U) /*!< Bit position for PDB_SC_TRGSEL. */
331 #define BM_PDB_SC_TRGSEL (0x00000F00U) /*!< Bit mask for PDB_SC_TRGSEL. */
332 #define BS_PDB_SC_TRGSEL (4U) /*!< Bit field size in bits for PDB_SC_TRGSEL. */
334 /*! @brief Read current value of the PDB_SC_TRGSEL field. */
335 #define BR_PDB_SC_TRGSEL(x) (HW_PDB_SC(x).B.TRGSEL)
337 /*! @brief Format value for bitfield PDB_SC_TRGSEL. */
338 #define BF_PDB_SC_TRGSEL(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_TRGSEL) & BM_PDB_SC_TRGSEL)
340 /*! @brief Set the TRGSEL field to a new value. */
341 #define BW_PDB_SC_TRGSEL(x, v) (HW_PDB_SC_WR(x, (HW_PDB_SC_RD(x) & ~BM_PDB_SC_TRGSEL) | BF_PDB_SC_TRGSEL(v)))
345 * @name Register PDB_SC, field PRESCALER[14:12] (RW)
348 * - 000 - Counting uses the peripheral clock divided by multiplication factor
350 * - 001 - Counting uses the peripheral clock divided by twice of the
351 * multiplication factor selected by MULT.
352 * - 010 - Counting uses the peripheral clock divided by four times of the
353 * multiplication factor selected by MULT.
354 * - 011 - Counting uses the peripheral clock divided by eight times of the
355 * multiplication factor selected by MULT.
356 * - 100 - Counting uses the peripheral clock divided by 16 times of the
357 * multiplication factor selected by MULT.
358 * - 101 - Counting uses the peripheral clock divided by 32 times of the
359 * multiplication factor selected by MULT.
360 * - 110 - Counting uses the peripheral clock divided by 64 times of the
361 * multiplication factor selected by MULT.
362 * - 111 - Counting uses the peripheral clock divided by 128 times of the
363 * multiplication factor selected by MULT.
366 #define BP_PDB_SC_PRESCALER (12U) /*!< Bit position for PDB_SC_PRESCALER. */
367 #define BM_PDB_SC_PRESCALER (0x00007000U) /*!< Bit mask for PDB_SC_PRESCALER. */
368 #define BS_PDB_SC_PRESCALER (3U) /*!< Bit field size in bits for PDB_SC_PRESCALER. */
370 /*! @brief Read current value of the PDB_SC_PRESCALER field. */
371 #define BR_PDB_SC_PRESCALER(x) (HW_PDB_SC(x).B.PRESCALER)
373 /*! @brief Format value for bitfield PDB_SC_PRESCALER. */
374 #define BF_PDB_SC_PRESCALER(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_PRESCALER) & BM_PDB_SC_PRESCALER)
376 /*! @brief Set the PRESCALER field to a new value. */
377 #define BW_PDB_SC_PRESCALER(x, v) (HW_PDB_SC_WR(x, (HW_PDB_SC_RD(x) & ~BM_PDB_SC_PRESCALER) | BF_PDB_SC_PRESCALER(v)))
381 * @name Register PDB_SC, field DMAEN[15] (RW)
383 * When DMA is enabled, the PDBIF flag generates a DMA request instead of an
387 * - 0 - DMA disabled.
391 #define BP_PDB_SC_DMAEN (15U) /*!< Bit position for PDB_SC_DMAEN. */
392 #define BM_PDB_SC_DMAEN (0x00008000U) /*!< Bit mask for PDB_SC_DMAEN. */
393 #define BS_PDB_SC_DMAEN (1U) /*!< Bit field size in bits for PDB_SC_DMAEN. */
395 /*! @brief Read current value of the PDB_SC_DMAEN field. */
396 #define BR_PDB_SC_DMAEN(x) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_DMAEN))
398 /*! @brief Format value for bitfield PDB_SC_DMAEN. */
399 #define BF_PDB_SC_DMAEN(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_DMAEN) & BM_PDB_SC_DMAEN)
401 /*! @brief Set the DMAEN field to a new value. */
402 #define BW_PDB_SC_DMAEN(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_DMAEN) = (v))
406 * @name Register PDB_SC, field SWTRIG[16] (WORZ)
408 * When PDB is enabled and the software trigger is selected as the trigger input
409 * source, writing 1 to this field resets and restarts the counter. Writing 0 to
410 * this field has no effect. Reading this field results 0.
413 #define BP_PDB_SC_SWTRIG (16U) /*!< Bit position for PDB_SC_SWTRIG. */
414 #define BM_PDB_SC_SWTRIG (0x00010000U) /*!< Bit mask for PDB_SC_SWTRIG. */
415 #define BS_PDB_SC_SWTRIG (1U) /*!< Bit field size in bits for PDB_SC_SWTRIG. */
417 /*! @brief Format value for bitfield PDB_SC_SWTRIG. */
418 #define BF_PDB_SC_SWTRIG(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_SWTRIG) & BM_PDB_SC_SWTRIG)
420 /*! @brief Set the SWTRIG field to a new value. */
421 #define BW_PDB_SC_SWTRIG(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_SWTRIG) = (v))
425 * @name Register PDB_SC, field PDBEIE[17] (RW)
427 * Enables the PDB sequence error interrupt. When this field is set, any of the
428 * PDB channel sequence error flags generates a PDB sequence error interrupt.
431 * - 0 - PDB sequence error interrupt disabled.
432 * - 1 - PDB sequence error interrupt enabled.
435 #define BP_PDB_SC_PDBEIE (17U) /*!< Bit position for PDB_SC_PDBEIE. */
436 #define BM_PDB_SC_PDBEIE (0x00020000U) /*!< Bit mask for PDB_SC_PDBEIE. */
437 #define BS_PDB_SC_PDBEIE (1U) /*!< Bit field size in bits for PDB_SC_PDBEIE. */
439 /*! @brief Read current value of the PDB_SC_PDBEIE field. */
440 #define BR_PDB_SC_PDBEIE(x) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBEIE))
442 /*! @brief Format value for bitfield PDB_SC_PDBEIE. */
443 #define BF_PDB_SC_PDBEIE(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_PDBEIE) & BM_PDB_SC_PDBEIE)
445 /*! @brief Set the PDBEIE field to a new value. */
446 #define BW_PDB_SC_PDBEIE(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBEIE) = (v))
450 * @name Register PDB_SC, field LDMOD[19:18] (RW)
452 * Selects the mode to load the MOD, IDLY, CHnDLYm, INTx, and POyDLY registers,
453 * after 1 is written to LDOK.
456 * - 00 - The internal registers are loaded with the values from their buffers
457 * immediately after 1 is written to LDOK.
458 * - 01 - The internal registers are loaded with the values from their buffers
459 * when the PDB counter reaches the MOD register value after 1 is written to
461 * - 10 - The internal registers are loaded with the values from their buffers
462 * when a trigger input event is detected after 1 is written to LDOK.
463 * - 11 - The internal registers are loaded with the values from their buffers
464 * when either the PDB counter reaches the MOD register value or a trigger
465 * input event is detected, after 1 is written to LDOK.
468 #define BP_PDB_SC_LDMOD (18U) /*!< Bit position for PDB_SC_LDMOD. */
469 #define BM_PDB_SC_LDMOD (0x000C0000U) /*!< Bit mask for PDB_SC_LDMOD. */
470 #define BS_PDB_SC_LDMOD (2U) /*!< Bit field size in bits for PDB_SC_LDMOD. */
472 /*! @brief Read current value of the PDB_SC_LDMOD field. */
473 #define BR_PDB_SC_LDMOD(x) (HW_PDB_SC(x).B.LDMOD)
475 /*! @brief Format value for bitfield PDB_SC_LDMOD. */
476 #define BF_PDB_SC_LDMOD(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_LDMOD) & BM_PDB_SC_LDMOD)
478 /*! @brief Set the LDMOD field to a new value. */
479 #define BW_PDB_SC_LDMOD(x, v) (HW_PDB_SC_WR(x, (HW_PDB_SC_RD(x) & ~BM_PDB_SC_LDMOD) | BF_PDB_SC_LDMOD(v)))
482 /*******************************************************************************
483 * HW_PDB_MOD - Modulus register
484 ******************************************************************************/
487 * @brief HW_PDB_MOD - Modulus register (RW)
489 * Reset value: 0x0000FFFFU
491 typedef union _hw_pdb_mod
494 struct _hw_pdb_mod_bitfields
496 uint32_t MOD
: 16; /*!< [15:0] PDB Modulus */
497 uint32_t RESERVED0
: 16; /*!< [31:16] */
502 * @name Constants and macros for entire PDB_MOD register
505 #define HW_PDB_MOD_ADDR(x) ((x) + 0x4U)
507 #define HW_PDB_MOD(x) (*(__IO hw_pdb_mod_t *) HW_PDB_MOD_ADDR(x))
508 #define HW_PDB_MOD_RD(x) (HW_PDB_MOD(x).U)
509 #define HW_PDB_MOD_WR(x, v) (HW_PDB_MOD(x).U = (v))
510 #define HW_PDB_MOD_SET(x, v) (HW_PDB_MOD_WR(x, HW_PDB_MOD_RD(x) | (v)))
511 #define HW_PDB_MOD_CLR(x, v) (HW_PDB_MOD_WR(x, HW_PDB_MOD_RD(x) & ~(v)))
512 #define HW_PDB_MOD_TOG(x, v) (HW_PDB_MOD_WR(x, HW_PDB_MOD_RD(x) ^ (v)))
516 * Constants & macros for individual PDB_MOD bitfields
520 * @name Register PDB_MOD, field MOD[15:0] (RW)
522 * Specifies the period of the counter. When the counter reaches this value, it
523 * will be reset back to zero. If the PDB is in Continuous mode, the count begins
524 * anew. Reading this field returns the value of the internal register that is
525 * effective for the current cycle of PDB.
528 #define BP_PDB_MOD_MOD (0U) /*!< Bit position for PDB_MOD_MOD. */
529 #define BM_PDB_MOD_MOD (0x0000FFFFU) /*!< Bit mask for PDB_MOD_MOD. */
530 #define BS_PDB_MOD_MOD (16U) /*!< Bit field size in bits for PDB_MOD_MOD. */
532 /*! @brief Read current value of the PDB_MOD_MOD field. */
533 #define BR_PDB_MOD_MOD(x) (HW_PDB_MOD(x).B.MOD)
535 /*! @brief Format value for bitfield PDB_MOD_MOD. */
536 #define BF_PDB_MOD_MOD(v) ((uint32_t)((uint32_t)(v) << BP_PDB_MOD_MOD) & BM_PDB_MOD_MOD)
538 /*! @brief Set the MOD field to a new value. */
539 #define BW_PDB_MOD_MOD(x, v) (HW_PDB_MOD_WR(x, (HW_PDB_MOD_RD(x) & ~BM_PDB_MOD_MOD) | BF_PDB_MOD_MOD(v)))
542 /*******************************************************************************
543 * HW_PDB_CNT - Counter register
544 ******************************************************************************/
547 * @brief HW_PDB_CNT - Counter register (RO)
549 * Reset value: 0x00000000U
551 typedef union _hw_pdb_cnt
554 struct _hw_pdb_cnt_bitfields
556 uint32_t CNT
: 16; /*!< [15:0] PDB Counter */
557 uint32_t RESERVED0
: 16; /*!< [31:16] */
562 * @name Constants and macros for entire PDB_CNT register
565 #define HW_PDB_CNT_ADDR(x) ((x) + 0x8U)
567 #define HW_PDB_CNT(x) (*(__I hw_pdb_cnt_t *) HW_PDB_CNT_ADDR(x))
568 #define HW_PDB_CNT_RD(x) (HW_PDB_CNT(x).U)
572 * Constants & macros for individual PDB_CNT bitfields
576 * @name Register PDB_CNT, field CNT[15:0] (RO)
578 * Contains the current value of the counter.
581 #define BP_PDB_CNT_CNT (0U) /*!< Bit position for PDB_CNT_CNT. */
582 #define BM_PDB_CNT_CNT (0x0000FFFFU) /*!< Bit mask for PDB_CNT_CNT. */
583 #define BS_PDB_CNT_CNT (16U) /*!< Bit field size in bits for PDB_CNT_CNT. */
585 /*! @brief Read current value of the PDB_CNT_CNT field. */
586 #define BR_PDB_CNT_CNT(x) (HW_PDB_CNT(x).B.CNT)
589 /*******************************************************************************
590 * HW_PDB_IDLY - Interrupt Delay register
591 ******************************************************************************/
594 * @brief HW_PDB_IDLY - Interrupt Delay register (RW)
596 * Reset value: 0x0000FFFFU
598 typedef union _hw_pdb_idly
601 struct _hw_pdb_idly_bitfields
603 uint32_t IDLY
: 16; /*!< [15:0] PDB Interrupt Delay */
604 uint32_t RESERVED0
: 16; /*!< [31:16] */
609 * @name Constants and macros for entire PDB_IDLY register
612 #define HW_PDB_IDLY_ADDR(x) ((x) + 0xCU)
614 #define HW_PDB_IDLY(x) (*(__IO hw_pdb_idly_t *) HW_PDB_IDLY_ADDR(x))
615 #define HW_PDB_IDLY_RD(x) (HW_PDB_IDLY(x).U)
616 #define HW_PDB_IDLY_WR(x, v) (HW_PDB_IDLY(x).U = (v))
617 #define HW_PDB_IDLY_SET(x, v) (HW_PDB_IDLY_WR(x, HW_PDB_IDLY_RD(x) | (v)))
618 #define HW_PDB_IDLY_CLR(x, v) (HW_PDB_IDLY_WR(x, HW_PDB_IDLY_RD(x) & ~(v)))
619 #define HW_PDB_IDLY_TOG(x, v) (HW_PDB_IDLY_WR(x, HW_PDB_IDLY_RD(x) ^ (v)))
623 * Constants & macros for individual PDB_IDLY bitfields
627 * @name Register PDB_IDLY, field IDLY[15:0] (RW)
629 * Specifies the delay value to schedule the PDB interrupt. It can be used to
630 * schedule an independent interrupt at some point in the PDB cycle. If enabled, a
631 * PDB interrupt is generated, when the counter is equal to the IDLY. Reading
632 * this field returns the value of internal register that is effective for the
633 * current cycle of the PDB.
636 #define BP_PDB_IDLY_IDLY (0U) /*!< Bit position for PDB_IDLY_IDLY. */
637 #define BM_PDB_IDLY_IDLY (0x0000FFFFU) /*!< Bit mask for PDB_IDLY_IDLY. */
638 #define BS_PDB_IDLY_IDLY (16U) /*!< Bit field size in bits for PDB_IDLY_IDLY. */
640 /*! @brief Read current value of the PDB_IDLY_IDLY field. */
641 #define BR_PDB_IDLY_IDLY(x) (HW_PDB_IDLY(x).B.IDLY)
643 /*! @brief Format value for bitfield PDB_IDLY_IDLY. */
644 #define BF_PDB_IDLY_IDLY(v) ((uint32_t)((uint32_t)(v) << BP_PDB_IDLY_IDLY) & BM_PDB_IDLY_IDLY)
646 /*! @brief Set the IDLY field to a new value. */
647 #define BW_PDB_IDLY_IDLY(x, v) (HW_PDB_IDLY_WR(x, (HW_PDB_IDLY_RD(x) & ~BM_PDB_IDLY_IDLY) | BF_PDB_IDLY_IDLY(v)))
650 /*******************************************************************************
651 * HW_PDB_CHnC1 - Channel n Control register 1
652 ******************************************************************************/
655 * @brief HW_PDB_CHnC1 - Channel n Control register 1 (RW)
657 * Reset value: 0x00000000U
659 * Each PDB channel has one control register, CHnC1. The bits in this register
660 * control the functionality of each PDB channel operation.
662 typedef union _hw_pdb_chnc1
665 struct _hw_pdb_chnc1_bitfields
667 uint32_t EN
: 8; /*!< [7:0] PDB Channel Pre-Trigger Enable */
668 uint32_t TOS
: 8; /*!< [15:8] PDB Channel Pre-Trigger Output Select */
669 uint32_t BB
: 8; /*!< [23:16] PDB Channel Pre-Trigger Back-to-Back
670 * Operation Enable */
671 uint32_t RESERVED0
: 8; /*!< [31:24] */
676 * @name Constants and macros for entire PDB_CHnC1 register
679 #define HW_PDB_CHnC1_COUNT (2U)
681 #define HW_PDB_CHnC1_ADDR(x, n) ((x) + 0x10U + (0x28U * (n)))
683 #define HW_PDB_CHnC1(x, n) (*(__IO hw_pdb_chnc1_t *) HW_PDB_CHnC1_ADDR(x, n))
684 #define HW_PDB_CHnC1_RD(x, n) (HW_PDB_CHnC1(x, n).U)
685 #define HW_PDB_CHnC1_WR(x, n, v) (HW_PDB_CHnC1(x, n).U = (v))
686 #define HW_PDB_CHnC1_SET(x, n, v) (HW_PDB_CHnC1_WR(x, n, HW_PDB_CHnC1_RD(x, n) | (v)))
687 #define HW_PDB_CHnC1_CLR(x, n, v) (HW_PDB_CHnC1_WR(x, n, HW_PDB_CHnC1_RD(x, n) & ~(v)))
688 #define HW_PDB_CHnC1_TOG(x, n, v) (HW_PDB_CHnC1_WR(x, n, HW_PDB_CHnC1_RD(x, n) ^ (v)))
692 * Constants & macros for individual PDB_CHnC1 bitfields
696 * @name Register PDB_CHnC1, field EN[7:0] (RW)
698 * These bits enable the PDB ADC pre-trigger outputs. Only lower M pre-trigger
699 * bits are implemented in this MCU.
702 * - 0 - PDB channel's corresponding pre-trigger disabled.
703 * - 1 - PDB channel's corresponding pre-trigger enabled.
706 #define BP_PDB_CHnC1_EN (0U) /*!< Bit position for PDB_CHnC1_EN. */
707 #define BM_PDB_CHnC1_EN (0x000000FFU) /*!< Bit mask for PDB_CHnC1_EN. */
708 #define BS_PDB_CHnC1_EN (8U) /*!< Bit field size in bits for PDB_CHnC1_EN. */
710 /*! @brief Read current value of the PDB_CHnC1_EN field. */
711 #define BR_PDB_CHnC1_EN(x, n) (HW_PDB_CHnC1(x, n).B.EN)
713 /*! @brief Format value for bitfield PDB_CHnC1_EN. */
714 #define BF_PDB_CHnC1_EN(v) ((uint32_t)((uint32_t)(v) << BP_PDB_CHnC1_EN) & BM_PDB_CHnC1_EN)
716 /*! @brief Set the EN field to a new value. */
717 #define BW_PDB_CHnC1_EN(x, n, v) (HW_PDB_CHnC1_WR(x, n, (HW_PDB_CHnC1_RD(x, n) & ~BM_PDB_CHnC1_EN) | BF_PDB_CHnC1_EN(v)))
721 * @name Register PDB_CHnC1, field TOS[15:8] (RW)
723 * Selects the PDB ADC pre-trigger outputs. Only lower M pre-trigger fields are
724 * implemented in this MCU.
727 * - 0 - PDB channel's corresponding pre-trigger is in bypassed mode. The
728 * pre-trigger asserts one peripheral clock cycle after a rising edge is detected
729 * on selected trigger input source or software trigger is selected and SWTRIG
731 * - 1 - PDB channel's corresponding pre-trigger asserts when the counter
732 * reaches the channel delay register and one peripheral clock cycle after a rising
733 * edge is detected on selected trigger input source or software trigger is
734 * selected and SETRIG is written with 1.
737 #define BP_PDB_CHnC1_TOS (8U) /*!< Bit position for PDB_CHnC1_TOS. */
738 #define BM_PDB_CHnC1_TOS (0x0000FF00U) /*!< Bit mask for PDB_CHnC1_TOS. */
739 #define BS_PDB_CHnC1_TOS (8U) /*!< Bit field size in bits for PDB_CHnC1_TOS. */
741 /*! @brief Read current value of the PDB_CHnC1_TOS field. */
742 #define BR_PDB_CHnC1_TOS(x, n) (HW_PDB_CHnC1(x, n).B.TOS)
744 /*! @brief Format value for bitfield PDB_CHnC1_TOS. */
745 #define BF_PDB_CHnC1_TOS(v) ((uint32_t)((uint32_t)(v) << BP_PDB_CHnC1_TOS) & BM_PDB_CHnC1_TOS)
747 /*! @brief Set the TOS field to a new value. */
748 #define BW_PDB_CHnC1_TOS(x, n, v) (HW_PDB_CHnC1_WR(x, n, (HW_PDB_CHnC1_RD(x, n) & ~BM_PDB_CHnC1_TOS) | BF_PDB_CHnC1_TOS(v)))
752 * @name Register PDB_CHnC1, field BB[23:16] (RW)
754 * These bits enable the PDB ADC pre-trigger operation as back-to-back mode.
755 * Only lower M pre-trigger bits are implemented in this MCU. Back-to-back operation
756 * enables the ADC conversions complete to trigger the next PDB channel
757 * pre-trigger and trigger output, so that the ADC conversions can be triggered on next
758 * set of configuration and results registers. Application code must only enable
759 * the back-to-back operation of the PDB pre-triggers at the leading of the
760 * back-to-back connection chain.
763 * - 0 - PDB channel's corresponding pre-trigger back-to-back operation disabled.
764 * - 1 - PDB channel's corresponding pre-trigger back-to-back operation enabled.
767 #define BP_PDB_CHnC1_BB (16U) /*!< Bit position for PDB_CHnC1_BB. */
768 #define BM_PDB_CHnC1_BB (0x00FF0000U) /*!< Bit mask for PDB_CHnC1_BB. */
769 #define BS_PDB_CHnC1_BB (8U) /*!< Bit field size in bits for PDB_CHnC1_BB. */
771 /*! @brief Read current value of the PDB_CHnC1_BB field. */
772 #define BR_PDB_CHnC1_BB(x, n) (HW_PDB_CHnC1(x, n).B.BB)
774 /*! @brief Format value for bitfield PDB_CHnC1_BB. */
775 #define BF_PDB_CHnC1_BB(v) ((uint32_t)((uint32_t)(v) << BP_PDB_CHnC1_BB) & BM_PDB_CHnC1_BB)
777 /*! @brief Set the BB field to a new value. */
778 #define BW_PDB_CHnC1_BB(x, n, v) (HW_PDB_CHnC1_WR(x, n, (HW_PDB_CHnC1_RD(x, n) & ~BM_PDB_CHnC1_BB) | BF_PDB_CHnC1_BB(v)))
780 /*******************************************************************************
781 * HW_PDB_CHnS - Channel n Status register
782 ******************************************************************************/
785 * @brief HW_PDB_CHnS - Channel n Status register (RW)
787 * Reset value: 0x00000000U
789 typedef union _hw_pdb_chns
792 struct _hw_pdb_chns_bitfields
794 uint32_t ERR
: 8; /*!< [7:0] PDB Channel Sequence Error Flags */
795 uint32_t RESERVED0
: 8; /*!< [15:8] */
796 uint32_t CF
: 8; /*!< [23:16] PDB Channel Flags */
797 uint32_t RESERVED1
: 8; /*!< [31:24] */
802 * @name Constants and macros for entire PDB_CHnS register
805 #define HW_PDB_CHnS_COUNT (2U)
807 #define HW_PDB_CHnS_ADDR(x, n) ((x) + 0x14U + (0x28U * (n)))
809 #define HW_PDB_CHnS(x, n) (*(__IO hw_pdb_chns_t *) HW_PDB_CHnS_ADDR(x, n))
810 #define HW_PDB_CHnS_RD(x, n) (HW_PDB_CHnS(x, n).U)
811 #define HW_PDB_CHnS_WR(x, n, v) (HW_PDB_CHnS(x, n).U = (v))
812 #define HW_PDB_CHnS_SET(x, n, v) (HW_PDB_CHnS_WR(x, n, HW_PDB_CHnS_RD(x, n) | (v)))
813 #define HW_PDB_CHnS_CLR(x, n, v) (HW_PDB_CHnS_WR(x, n, HW_PDB_CHnS_RD(x, n) & ~(v)))
814 #define HW_PDB_CHnS_TOG(x, n, v) (HW_PDB_CHnS_WR(x, n, HW_PDB_CHnS_RD(x, n) ^ (v)))
818 * Constants & macros for individual PDB_CHnS bitfields
822 * @name Register PDB_CHnS, field ERR[7:0] (RW)
824 * Only the lower M bits are implemented in this MCU.
827 * - 0 - Sequence error not detected on PDB channel's corresponding pre-trigger.
828 * - 1 - Sequence error detected on PDB channel's corresponding pre-trigger.
829 * ADCn block can be triggered for a conversion by one pre-trigger from PDB
830 * channel n. When one conversion, which is triggered by one of the pre-triggers
831 * from PDB channel n, is in progress, new trigger from PDB channel's
832 * corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set.
833 * Writing 0's to clear the sequence error flags.
836 #define BP_PDB_CHnS_ERR (0U) /*!< Bit position for PDB_CHnS_ERR. */
837 #define BM_PDB_CHnS_ERR (0x000000FFU) /*!< Bit mask for PDB_CHnS_ERR. */
838 #define BS_PDB_CHnS_ERR (8U) /*!< Bit field size in bits for PDB_CHnS_ERR. */
840 /*! @brief Read current value of the PDB_CHnS_ERR field. */
841 #define BR_PDB_CHnS_ERR(x, n) (HW_PDB_CHnS(x, n).B.ERR)
843 /*! @brief Format value for bitfield PDB_CHnS_ERR. */
844 #define BF_PDB_CHnS_ERR(v) ((uint32_t)((uint32_t)(v) << BP_PDB_CHnS_ERR) & BM_PDB_CHnS_ERR)
846 /*! @brief Set the ERR field to a new value. */
847 #define BW_PDB_CHnS_ERR(x, n, v) (HW_PDB_CHnS_WR(x, n, (HW_PDB_CHnS_RD(x, n) & ~BM_PDB_CHnS_ERR) | BF_PDB_CHnS_ERR(v)))
851 * @name Register PDB_CHnS, field CF[23:16] (RW)
853 * The CF[m] bit is set when the PDB counter matches the CHnDLYm. Write 0 to
857 #define BP_PDB_CHnS_CF (16U) /*!< Bit position for PDB_CHnS_CF. */
858 #define BM_PDB_CHnS_CF (0x00FF0000U) /*!< Bit mask for PDB_CHnS_CF. */
859 #define BS_PDB_CHnS_CF (8U) /*!< Bit field size in bits for PDB_CHnS_CF. */
861 /*! @brief Read current value of the PDB_CHnS_CF field. */
862 #define BR_PDB_CHnS_CF(x, n) (HW_PDB_CHnS(x, n).B.CF)
864 /*! @brief Format value for bitfield PDB_CHnS_CF. */
865 #define BF_PDB_CHnS_CF(v) ((uint32_t)((uint32_t)(v) << BP_PDB_CHnS_CF) & BM_PDB_CHnS_CF)
867 /*! @brief Set the CF field to a new value. */
868 #define BW_PDB_CHnS_CF(x, n, v) (HW_PDB_CHnS_WR(x, n, (HW_PDB_CHnS_RD(x, n) & ~BM_PDB_CHnS_CF) | BF_PDB_CHnS_CF(v)))
870 /*******************************************************************************
871 * HW_PDB_CHnDLY0 - Channel n Delay 0 register
872 ******************************************************************************/
875 * @brief HW_PDB_CHnDLY0 - Channel n Delay 0 register (RW)
877 * Reset value: 0x00000000U
879 typedef union _hw_pdb_chndly0
882 struct _hw_pdb_chndly0_bitfields
884 uint32_t DLY
: 16; /*!< [15:0] PDB Channel Delay */
885 uint32_t RESERVED0
: 16; /*!< [31:16] */
890 * @name Constants and macros for entire PDB_CHnDLY0 register
893 #define HW_PDB_CHnDLY0_COUNT (2U)
895 #define HW_PDB_CHnDLY0_ADDR(x, n) ((x) + 0x18U + (0x28U * (n)))
897 #define HW_PDB_CHnDLY0(x, n) (*(__IO hw_pdb_chndly0_t *) HW_PDB_CHnDLY0_ADDR(x, n))
898 #define HW_PDB_CHnDLY0_RD(x, n) (HW_PDB_CHnDLY0(x, n).U)
899 #define HW_PDB_CHnDLY0_WR(x, n, v) (HW_PDB_CHnDLY0(x, n).U = (v))
900 #define HW_PDB_CHnDLY0_SET(x, n, v) (HW_PDB_CHnDLY0_WR(x, n, HW_PDB_CHnDLY0_RD(x, n) | (v)))
901 #define HW_PDB_CHnDLY0_CLR(x, n, v) (HW_PDB_CHnDLY0_WR(x, n, HW_PDB_CHnDLY0_RD(x, n) & ~(v)))
902 #define HW_PDB_CHnDLY0_TOG(x, n, v) (HW_PDB_CHnDLY0_WR(x, n, HW_PDB_CHnDLY0_RD(x, n) ^ (v)))
906 * Constants & macros for individual PDB_CHnDLY0 bitfields
910 * @name Register PDB_CHnDLY0, field DLY[15:0] (RW)
912 * Specifies the delay value for the channel's corresponding pre-trigger. The
913 * pre-trigger asserts when the counter is equal to DLY. Reading this field returns
914 * the value of internal register that is effective for the current PDB cycle.
917 #define BP_PDB_CHnDLY0_DLY (0U) /*!< Bit position for PDB_CHnDLY0_DLY. */
918 #define BM_PDB_CHnDLY0_DLY (0x0000FFFFU) /*!< Bit mask for PDB_CHnDLY0_DLY. */
919 #define BS_PDB_CHnDLY0_DLY (16U) /*!< Bit field size in bits for PDB_CHnDLY0_DLY. */
921 /*! @brief Read current value of the PDB_CHnDLY0_DLY field. */
922 #define BR_PDB_CHnDLY0_DLY(x, n) (HW_PDB_CHnDLY0(x, n).B.DLY)
924 /*! @brief Format value for bitfield PDB_CHnDLY0_DLY. */
925 #define BF_PDB_CHnDLY0_DLY(v) ((uint32_t)((uint32_t)(v) << BP_PDB_CHnDLY0_DLY) & BM_PDB_CHnDLY0_DLY)
927 /*! @brief Set the DLY field to a new value. */
928 #define BW_PDB_CHnDLY0_DLY(x, n, v) (HW_PDB_CHnDLY0_WR(x, n, (HW_PDB_CHnDLY0_RD(x, n) & ~BM_PDB_CHnDLY0_DLY) | BF_PDB_CHnDLY0_DLY(v)))
930 /*******************************************************************************
931 * HW_PDB_CHnDLY1 - Channel n Delay 1 register
932 ******************************************************************************/
935 * @brief HW_PDB_CHnDLY1 - Channel n Delay 1 register (RW)
937 * Reset value: 0x00000000U
939 typedef union _hw_pdb_chndly1
942 struct _hw_pdb_chndly1_bitfields
944 uint32_t DLY
: 16; /*!< [15:0] PDB Channel Delay */
945 uint32_t RESERVED0
: 16; /*!< [31:16] */
950 * @name Constants and macros for entire PDB_CHnDLY1 register
953 #define HW_PDB_CHnDLY1_COUNT (2U)
955 #define HW_PDB_CHnDLY1_ADDR(x, n) ((x) + 0x1CU + (0x28U * (n)))
957 #define HW_PDB_CHnDLY1(x, n) (*(__IO hw_pdb_chndly1_t *) HW_PDB_CHnDLY1_ADDR(x, n))
958 #define HW_PDB_CHnDLY1_RD(x, n) (HW_PDB_CHnDLY1(x, n).U)
959 #define HW_PDB_CHnDLY1_WR(x, n, v) (HW_PDB_CHnDLY1(x, n).U = (v))
960 #define HW_PDB_CHnDLY1_SET(x, n, v) (HW_PDB_CHnDLY1_WR(x, n, HW_PDB_CHnDLY1_RD(x, n) | (v)))
961 #define HW_PDB_CHnDLY1_CLR(x, n, v) (HW_PDB_CHnDLY1_WR(x, n, HW_PDB_CHnDLY1_RD(x, n) & ~(v)))
962 #define HW_PDB_CHnDLY1_TOG(x, n, v) (HW_PDB_CHnDLY1_WR(x, n, HW_PDB_CHnDLY1_RD(x, n) ^ (v)))
966 * Constants & macros for individual PDB_CHnDLY1 bitfields
970 * @name Register PDB_CHnDLY1, field DLY[15:0] (RW)
972 * These bits specify the delay value for the channel's corresponding
973 * pre-trigger. The pre-trigger asserts when the counter is equal to DLY. Reading these
974 * bits returns the value of internal register that is effective for the current PDB
978 #define BP_PDB_CHnDLY1_DLY (0U) /*!< Bit position for PDB_CHnDLY1_DLY. */
979 #define BM_PDB_CHnDLY1_DLY (0x0000FFFFU) /*!< Bit mask for PDB_CHnDLY1_DLY. */
980 #define BS_PDB_CHnDLY1_DLY (16U) /*!< Bit field size in bits for PDB_CHnDLY1_DLY. */
982 /*! @brief Read current value of the PDB_CHnDLY1_DLY field. */
983 #define BR_PDB_CHnDLY1_DLY(x, n) (HW_PDB_CHnDLY1(x, n).B.DLY)
985 /*! @brief Format value for bitfield PDB_CHnDLY1_DLY. */
986 #define BF_PDB_CHnDLY1_DLY(v) ((uint32_t)((uint32_t)(v) << BP_PDB_CHnDLY1_DLY) & BM_PDB_CHnDLY1_DLY)
988 /*! @brief Set the DLY field to a new value. */
989 #define BW_PDB_CHnDLY1_DLY(x, n, v) (HW_PDB_CHnDLY1_WR(x, n, (HW_PDB_CHnDLY1_RD(x, n) & ~BM_PDB_CHnDLY1_DLY) | BF_PDB_CHnDLY1_DLY(v)))
992 /*******************************************************************************
993 * HW_PDB_DACINTCn - DAC Interval Trigger n Control register
994 ******************************************************************************/
997 * @brief HW_PDB_DACINTCn - DAC Interval Trigger n Control register (RW)
999 * Reset value: 0x00000000U
1001 typedef union _hw_pdb_dacintcn
1004 struct _hw_pdb_dacintcn_bitfields
1006 uint32_t TOE
: 1; /*!< [0] DAC Interval Trigger Enable */
1007 uint32_t EXT
: 1; /*!< [1] DAC External Trigger Input Enable */
1008 uint32_t RESERVED0
: 30; /*!< [31:2] */
1010 } hw_pdb_dacintcn_t
;
1013 * @name Constants and macros for entire PDB_DACINTCn register
1016 #define HW_PDB_DACINTCn_COUNT (2U)
1018 #define HW_PDB_DACINTCn_ADDR(x, n) ((x) + 0x150U + (0x8U * (n)))
1020 #define HW_PDB_DACINTCn(x, n) (*(__IO hw_pdb_dacintcn_t *) HW_PDB_DACINTCn_ADDR(x, n))
1021 #define HW_PDB_DACINTCn_RD(x, n) (HW_PDB_DACINTCn(x, n).U)
1022 #define HW_PDB_DACINTCn_WR(x, n, v) (HW_PDB_DACINTCn(x, n).U = (v))
1023 #define HW_PDB_DACINTCn_SET(x, n, v) (HW_PDB_DACINTCn_WR(x, n, HW_PDB_DACINTCn_RD(x, n) | (v)))
1024 #define HW_PDB_DACINTCn_CLR(x, n, v) (HW_PDB_DACINTCn_WR(x, n, HW_PDB_DACINTCn_RD(x, n) & ~(v)))
1025 #define HW_PDB_DACINTCn_TOG(x, n, v) (HW_PDB_DACINTCn_WR(x, n, HW_PDB_DACINTCn_RD(x, n) ^ (v)))
1029 * Constants & macros for individual PDB_DACINTCn bitfields
1033 * @name Register PDB_DACINTCn, field TOE[0] (RW)
1035 * This bit enables the DAC interval trigger.
1038 * - 0 - DAC interval trigger disabled.
1039 * - 1 - DAC interval trigger enabled.
1042 #define BP_PDB_DACINTCn_TOE (0U) /*!< Bit position for PDB_DACINTCn_TOE. */
1043 #define BM_PDB_DACINTCn_TOE (0x00000001U) /*!< Bit mask for PDB_DACINTCn_TOE. */
1044 #define BS_PDB_DACINTCn_TOE (1U) /*!< Bit field size in bits for PDB_DACINTCn_TOE. */
1046 /*! @brief Read current value of the PDB_DACINTCn_TOE field. */
1047 #define BR_PDB_DACINTCn_TOE(x, n) (BITBAND_ACCESS32(HW_PDB_DACINTCn_ADDR(x, n), BP_PDB_DACINTCn_TOE))
1049 /*! @brief Format value for bitfield PDB_DACINTCn_TOE. */
1050 #define BF_PDB_DACINTCn_TOE(v) ((uint32_t)((uint32_t)(v) << BP_PDB_DACINTCn_TOE) & BM_PDB_DACINTCn_TOE)
1052 /*! @brief Set the TOE field to a new value. */
1053 #define BW_PDB_DACINTCn_TOE(x, n, v) (BITBAND_ACCESS32(HW_PDB_DACINTCn_ADDR(x, n), BP_PDB_DACINTCn_TOE) = (v))
1057 * @name Register PDB_DACINTCn, field EXT[1] (RW)
1059 * Enables the external trigger for DAC interval counter.
1062 * - 0 - DAC external trigger input disabled. DAC interval counter is reset and
1063 * counting starts when a rising edge is detected on selected trigger input
1064 * source or software trigger is selected and SWTRIG is written with 1.
1065 * - 1 - DAC external trigger input enabled. DAC interval counter is bypassed
1066 * and DAC external trigger input triggers the DAC interval trigger.
1069 #define BP_PDB_DACINTCn_EXT (1U) /*!< Bit position for PDB_DACINTCn_EXT. */
1070 #define BM_PDB_DACINTCn_EXT (0x00000002U) /*!< Bit mask for PDB_DACINTCn_EXT. */
1071 #define BS_PDB_DACINTCn_EXT (1U) /*!< Bit field size in bits for PDB_DACINTCn_EXT. */
1073 /*! @brief Read current value of the PDB_DACINTCn_EXT field. */
1074 #define BR_PDB_DACINTCn_EXT(x, n) (BITBAND_ACCESS32(HW_PDB_DACINTCn_ADDR(x, n), BP_PDB_DACINTCn_EXT))
1076 /*! @brief Format value for bitfield PDB_DACINTCn_EXT. */
1077 #define BF_PDB_DACINTCn_EXT(v) ((uint32_t)((uint32_t)(v) << BP_PDB_DACINTCn_EXT) & BM_PDB_DACINTCn_EXT)
1079 /*! @brief Set the EXT field to a new value. */
1080 #define BW_PDB_DACINTCn_EXT(x, n, v) (BITBAND_ACCESS32(HW_PDB_DACINTCn_ADDR(x, n), BP_PDB_DACINTCn_EXT) = (v))
1082 /*******************************************************************************
1083 * HW_PDB_DACINTn - DAC Interval n register
1084 ******************************************************************************/
1087 * @brief HW_PDB_DACINTn - DAC Interval n register (RW)
1089 * Reset value: 0x00000000U
1091 typedef union _hw_pdb_dacintn
1094 struct _hw_pdb_dacintn_bitfields
1096 uint32_t INT
: 16; /*!< [15:0] DAC Interval */
1097 uint32_t RESERVED0
: 16; /*!< [31:16] */
1102 * @name Constants and macros for entire PDB_DACINTn register
1105 #define HW_PDB_DACINTn_COUNT (2U)
1107 #define HW_PDB_DACINTn_ADDR(x, n) ((x) + 0x154U + (0x8U * (n)))
1109 #define HW_PDB_DACINTn(x, n) (*(__IO hw_pdb_dacintn_t *) HW_PDB_DACINTn_ADDR(x, n))
1110 #define HW_PDB_DACINTn_RD(x, n) (HW_PDB_DACINTn(x, n).U)
1111 #define HW_PDB_DACINTn_WR(x, n, v) (HW_PDB_DACINTn(x, n).U = (v))
1112 #define HW_PDB_DACINTn_SET(x, n, v) (HW_PDB_DACINTn_WR(x, n, HW_PDB_DACINTn_RD(x, n) | (v)))
1113 #define HW_PDB_DACINTn_CLR(x, n, v) (HW_PDB_DACINTn_WR(x, n, HW_PDB_DACINTn_RD(x, n) & ~(v)))
1114 #define HW_PDB_DACINTn_TOG(x, n, v) (HW_PDB_DACINTn_WR(x, n, HW_PDB_DACINTn_RD(x, n) ^ (v)))
1118 * Constants & macros for individual PDB_DACINTn bitfields
1122 * @name Register PDB_DACINTn, field INT[15:0] (RW)
1124 * Specifies the interval value for DAC interval trigger. DAC interval trigger
1125 * triggers DAC[1:0] update when the DAC interval counter is equal to the DACINT.
1126 * Reading this field returns the value of internal register that is effective
1127 * for the current PDB cycle.
1130 #define BP_PDB_DACINTn_INT (0U) /*!< Bit position for PDB_DACINTn_INT. */
1131 #define BM_PDB_DACINTn_INT (0x0000FFFFU) /*!< Bit mask for PDB_DACINTn_INT. */
1132 #define BS_PDB_DACINTn_INT (16U) /*!< Bit field size in bits for PDB_DACINTn_INT. */
1134 /*! @brief Read current value of the PDB_DACINTn_INT field. */
1135 #define BR_PDB_DACINTn_INT(x, n) (HW_PDB_DACINTn(x, n).B.INT)
1137 /*! @brief Format value for bitfield PDB_DACINTn_INT. */
1138 #define BF_PDB_DACINTn_INT(v) ((uint32_t)((uint32_t)(v) << BP_PDB_DACINTn_INT) & BM_PDB_DACINTn_INT)
1140 /*! @brief Set the INT field to a new value. */
1141 #define BW_PDB_DACINTn_INT(x, n, v) (HW_PDB_DACINTn_WR(x, n, (HW_PDB_DACINTn_RD(x, n) & ~BM_PDB_DACINTn_INT) | BF_PDB_DACINTn_INT(v)))
1144 /*******************************************************************************
1145 * HW_PDB_POEN - Pulse-Out n Enable register
1146 ******************************************************************************/
1149 * @brief HW_PDB_POEN - Pulse-Out n Enable register (RW)
1151 * Reset value: 0x00000000U
1153 typedef union _hw_pdb_poen
1156 struct _hw_pdb_poen_bitfields
1158 uint32_t POEN
: 8; /*!< [7:0] PDB Pulse-Out Enable */
1159 uint32_t RESERVED0
: 24; /*!< [31:8] */
1164 * @name Constants and macros for entire PDB_POEN register
1167 #define HW_PDB_POEN_ADDR(x) ((x) + 0x190U)
1169 #define HW_PDB_POEN(x) (*(__IO hw_pdb_poen_t *) HW_PDB_POEN_ADDR(x))
1170 #define HW_PDB_POEN_RD(x) (HW_PDB_POEN(x).U)
1171 #define HW_PDB_POEN_WR(x, v) (HW_PDB_POEN(x).U = (v))
1172 #define HW_PDB_POEN_SET(x, v) (HW_PDB_POEN_WR(x, HW_PDB_POEN_RD(x) | (v)))
1173 #define HW_PDB_POEN_CLR(x, v) (HW_PDB_POEN_WR(x, HW_PDB_POEN_RD(x) & ~(v)))
1174 #define HW_PDB_POEN_TOG(x, v) (HW_PDB_POEN_WR(x, HW_PDB_POEN_RD(x) ^ (v)))
1178 * Constants & macros for individual PDB_POEN bitfields
1182 * @name Register PDB_POEN, field POEN[7:0] (RW)
1184 * Enables the pulse output. Only lower Y bits are implemented in this MCU.
1187 * - 0 - PDB Pulse-Out disabled
1188 * - 1 - PDB Pulse-Out enabled
1191 #define BP_PDB_POEN_POEN (0U) /*!< Bit position for PDB_POEN_POEN. */
1192 #define BM_PDB_POEN_POEN (0x000000FFU) /*!< Bit mask for PDB_POEN_POEN. */
1193 #define BS_PDB_POEN_POEN (8U) /*!< Bit field size in bits for PDB_POEN_POEN. */
1195 /*! @brief Read current value of the PDB_POEN_POEN field. */
1196 #define BR_PDB_POEN_POEN(x) (HW_PDB_POEN(x).B.POEN)
1198 /*! @brief Format value for bitfield PDB_POEN_POEN. */
1199 #define BF_PDB_POEN_POEN(v) ((uint32_t)((uint32_t)(v) << BP_PDB_POEN_POEN) & BM_PDB_POEN_POEN)
1201 /*! @brief Set the POEN field to a new value. */
1202 #define BW_PDB_POEN_POEN(x, v) (HW_PDB_POEN_WR(x, (HW_PDB_POEN_RD(x) & ~BM_PDB_POEN_POEN) | BF_PDB_POEN_POEN(v)))
1205 /*******************************************************************************
1206 * HW_PDB_POnDLY - Pulse-Out n Delay register
1207 ******************************************************************************/
1210 * @brief HW_PDB_POnDLY - Pulse-Out n Delay register (RW)
1212 * Reset value: 0x00000000U
1214 typedef union _hw_pdb_pondly
1217 struct _hw_pdb_pondly_bitfields
1219 uint32_t DLY2
: 16; /*!< [15:0] PDB Pulse-Out Delay 2 */
1220 uint32_t DLY1
: 16; /*!< [31:16] PDB Pulse-Out Delay 1 */
1225 * @name Constants and macros for entire PDB_POnDLY register
1228 #define HW_PDB_POnDLY_COUNT (2U)
1230 #define HW_PDB_POnDLY_ADDR(x, n) ((x) + 0x194U + (0x4U * (n)))
1232 #define HW_PDB_POnDLY(x, n) (*(__IO hw_pdb_pondly_t *) HW_PDB_POnDLY_ADDR(x, n))
1233 #define HW_PDB_POnDLY_RD(x, n) (HW_PDB_POnDLY(x, n).U)
1234 #define HW_PDB_POnDLY_WR(x, n, v) (HW_PDB_POnDLY(x, n).U = (v))
1235 #define HW_PDB_POnDLY_SET(x, n, v) (HW_PDB_POnDLY_WR(x, n, HW_PDB_POnDLY_RD(x, n) | (v)))
1236 #define HW_PDB_POnDLY_CLR(x, n, v) (HW_PDB_POnDLY_WR(x, n, HW_PDB_POnDLY_RD(x, n) & ~(v)))
1237 #define HW_PDB_POnDLY_TOG(x, n, v) (HW_PDB_POnDLY_WR(x, n, HW_PDB_POnDLY_RD(x, n) ^ (v)))
1241 * Constants & macros for individual PDB_POnDLY bitfields
1245 * @name Register PDB_POnDLY, field DLY2[15:0] (RW)
1247 * Specifies the delay 2 value for the PDB Pulse-Out. Pulse-Out goes low when
1248 * the PDB counter is equal to the DLY2. Reading this field returns the value of
1249 * internal register that is effective for the current PDB cycle.
1252 #define BP_PDB_POnDLY_DLY2 (0U) /*!< Bit position for PDB_POnDLY_DLY2. */
1253 #define BM_PDB_POnDLY_DLY2 (0x0000FFFFU) /*!< Bit mask for PDB_POnDLY_DLY2. */
1254 #define BS_PDB_POnDLY_DLY2 (16U) /*!< Bit field size in bits for PDB_POnDLY_DLY2. */
1256 /*! @brief Read current value of the PDB_POnDLY_DLY2 field. */
1257 #define BR_PDB_POnDLY_DLY2(x, n) (HW_PDB_POnDLY(x, n).B.DLY2)
1259 /*! @brief Format value for bitfield PDB_POnDLY_DLY2. */
1260 #define BF_PDB_POnDLY_DLY2(v) ((uint32_t)((uint32_t)(v) << BP_PDB_POnDLY_DLY2) & BM_PDB_POnDLY_DLY2)
1262 /*! @brief Set the DLY2 field to a new value. */
1263 #define BW_PDB_POnDLY_DLY2(x, n, v) (HW_PDB_POnDLY_WR(x, n, (HW_PDB_POnDLY_RD(x, n) & ~BM_PDB_POnDLY_DLY2) | BF_PDB_POnDLY_DLY2(v)))
1267 * @name Register PDB_POnDLY, field DLY1[31:16] (RW)
1269 * Specifies the delay 1 value for the PDB Pulse-Out. Pulse-Out goes high when
1270 * the PDB counter is equal to the DLY1. Reading this field returns the value of
1271 * internal register that is effective for the current PDB cycle.
1274 #define BP_PDB_POnDLY_DLY1 (16U) /*!< Bit position for PDB_POnDLY_DLY1. */
1275 #define BM_PDB_POnDLY_DLY1 (0xFFFF0000U) /*!< Bit mask for PDB_POnDLY_DLY1. */
1276 #define BS_PDB_POnDLY_DLY1 (16U) /*!< Bit field size in bits for PDB_POnDLY_DLY1. */
1278 /*! @brief Read current value of the PDB_POnDLY_DLY1 field. */
1279 #define BR_PDB_POnDLY_DLY1(x, n) (HW_PDB_POnDLY(x, n).B.DLY1)
1281 /*! @brief Format value for bitfield PDB_POnDLY_DLY1. */
1282 #define BF_PDB_POnDLY_DLY1(v) ((uint32_t)((uint32_t)(v) << BP_PDB_POnDLY_DLY1) & BM_PDB_POnDLY_DLY1)
1284 /*! @brief Set the DLY1 field to a new value. */
1285 #define BW_PDB_POnDLY_DLY1(x, n, v) (HW_PDB_POnDLY_WR(x, n, (HW_PDB_POnDLY_RD(x, n) & ~BM_PDB_POnDLY_DLY1) | BF_PDB_POnDLY_DLY1(v)))
1288 /*******************************************************************************
1289 * hw_pdb_t - module struct
1290 ******************************************************************************/
1292 * @brief All PDB module registers.
1295 typedef struct _hw_pdb
1297 __IO hw_pdb_sc_t SC
; /*!< [0x0] Status and Control register */
1298 __IO hw_pdb_mod_t MOD
; /*!< [0x4] Modulus register */
1299 __I hw_pdb_cnt_t CNT
; /*!< [0x8] Counter register */
1300 __IO hw_pdb_idly_t IDLY
; /*!< [0xC] Interrupt Delay register */
1302 __IO hw_pdb_chnc1_t CHnC1
; /*!< [0x10] Channel n Control register 1 */
1303 __IO hw_pdb_chns_t CHnS
; /*!< [0x14] Channel n Status register */
1304 __IO hw_pdb_chndly0_t CHnDLY0
; /*!< [0x18] Channel n Delay 0 register */
1305 __IO hw_pdb_chndly1_t CHnDLY1
; /*!< [0x1C] Channel n Delay 1 register */
1306 uint8_t _reserved0
[24];
1308 uint8_t _reserved0
[240];
1310 __IO hw_pdb_dacintcn_t DACINTCn
; /*!< [0x150] DAC Interval Trigger n Control register */
1311 __IO hw_pdb_dacintn_t DACINTn
; /*!< [0x154] DAC Interval n register */
1313 uint8_t _reserved1
[48];
1314 __IO hw_pdb_poen_t POEN
; /*!< [0x190] Pulse-Out n Enable register */
1315 __IO hw_pdb_pondly_t POnDLY
[2]; /*!< [0x194] Pulse-Out n Delay register */
1319 /*! @brief Macro to access all PDB registers. */
1320 /*! @param x PDB module instance base address. */
1321 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
1322 * use the '&' operator, like <code>&HW_PDB(PDB0_BASE)</code>. */
1323 #define HW_PDB(x) (*(hw_pdb_t *)(x))
1325 #endif /* __HW_PDB_REGISTERS_H__ */