tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_pmc.h

   1 /*
   2 ** ###################################################################
   3 **     Compilers:           Keil ARM C/C++ Compiler
   4 **                          Freescale C/C++ for Embedded ARM
   5 **                          GNU C Compiler
   6 **                          IAR ANSI C/C++ Compiler for ARM
   7 **
   8 **     Reference manual:    K22P121M120SF7RM, Rev. 1, March 24, 2014
   9 **     Version:             rev. 2.5, 2014-05-06
  10 **     Build:               b140604
  11 **
  12 **     Abstract:
  13 **         Extension to the CMSIS register access layer header.
  14 **
  15 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
  16 **     All rights reserved.
  17 **
  18 **     Redistribution and use in source and binary forms, with or without modification,
  19 **     are permitted provided that the following conditions are met:
  20 **
  21 **     o Redistributions of source code must retain the above copyright notice, this list
  22 **       of conditions and the following disclaimer.
  23 **
  24 **     o Redistributions in binary form must reproduce the above copyright notice, this
  25 **       list of conditions and the following disclaimer in the documentation and/or
  26 **       other materials provided with the distribution.
  27 **
  28 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  29 **       contributors may be used to endorse or promote products derived from this
  30 **       software without specific prior written permission.
  31 **
  32 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  33 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  34 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  35 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  36 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  37 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  38 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  39 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  41 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42 **
  43 **     http:                 www.freescale.com
  44 **     mail:                 support@freescale.com
  45 **
  46 **     Revisions:
  47 **     - rev. 1.0 (2013-07-23)
  48 **         Initial version.
  49 **     - rev. 1.1 (2013-09-17)
  50 **         RM rev. 0.4 update.
  51 **     - rev. 2.0 (2013-10-29)
  52 **         Register accessor macros added to the memory map.
  53 **         Symbols for Processor Expert memory map compatibility added to the memory map.
  54 **         Startup file for gcc has been updated according to CMSIS 3.2.
  55 **         System initialization updated.
  56 **     - rev. 2.1 (2013-10-30)
  57 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
  58 **     - rev. 2.2 (2013-12-20)
  59 **         Update according to reference manual rev. 0.6,
  60 **     - rev. 2.3 (2014-01-13)
  61 **         Update according to reference manual rev. 0.61,
  62 **     - rev. 2.4 (2014-02-10)
  63 **         The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
  64 **     - rev. 2.5 (2014-05-06)
  65 **         Update according to reference manual rev. 1.0,
  66 **         Update of system and startup files.
  67 **         Module access macro module_BASES replaced by module_BASE_PTRS.
  68 **
  69 ** ###################################################################
  70 */
  71
  72 /*
  73  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
  74  *
  75  * This file was generated automatically and any changes may be lost.
  76  */
  77 #ifndef __HW_PMC_REGISTERS_H__
  78 #define __HW_PMC_REGISTERS_H__
  79
  80 #include "MK22F51212.h"
  81 #include "fsl_bitaccess.h"
  82
  83 /*
  84  * MK22F51212 PMC
  85  *
  86  * Power Management Controller
  87  *
  88  * Registers defined in this header file:
  89  * - HW_PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register
  90  * - HW_PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register
  91  * - HW_PMC_REGSC - Regulator Status And Control register
  92  *
  93  * - hw_pmc_t - Struct containing all module registers.
  94  */
  95
  96 #define HW_PMC_INSTANCE_COUNT (1U) /*!< Number of instances of the PMC module. */
  97
  98 /*******************************************************************************
  99  * HW_PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register
 100  ******************************************************************************/
 101
 102 /*!
 103  * @brief HW_PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register (RW)
 104  *
 105  * Reset value: 0x10U
 106  *
 107  * This register contains status and control bits to support the low voltage
 108  * detect function. This register should be written during the reset initialization
 109  * program to set the desired controls even if the desired settings are the same
 110  * as the reset settings. While the device is in the very low power or low
 111  * leakage modes, the LVD system is disabled regardless of LVDSC1 settings. To protect
 112  * systems that must have LVD always on, configure the Power Mode Protection
 113  * (PMPROT) register of the SMC module (SMC_PMPROT) to disallow any very low power or
 114  * low leakage modes from being enabled. See the device's data sheet for the
 115  * exact LVD trip voltages. The LVDV bits are reset solely on a POR Only event. The
 116  * register's other bits are reset on Chip Reset Not VLLS. For more information
 117  * about these reset types, refer to the Reset section details.
 118  */
 119 typedef union _hw_pmc_lvdsc1
 120 {
 121     uint8_t U;
 122     struct _hw_pmc_lvdsc1_bitfields
 123     {
 124         uint8_t LVDV : 2;              /*!< [1:0] Low-Voltage Detect Voltage Select */
 125         uint8_t RESERVED0 : 2;         /*!< [3:2]  */
 126         uint8_t LVDRE : 1;             /*!< [4] Low-Voltage Detect Reset Enable */
 127         uint8_t LVDIE : 1;             /*!< [5] Low-Voltage Detect Interrupt Enable */
 128         uint8_t LVDACK : 1;            /*!< [6] Low-Voltage Detect Acknowledge */
 129         uint8_t LVDF : 1;              /*!< [7] Low-Voltage Detect Flag */
 130     } B;
 131 } hw_pmc_lvdsc1_t;
 132
 133 /*!
 134  * @name Constants and macros for entire PMC_LVDSC1 register
 135  */
 136 /*@{*/
 137 #define HW_PMC_LVDSC1_ADDR(x)    ((x) + 0x0U)
 138
 139 #define HW_PMC_LVDSC1(x)         (*(__IO hw_pmc_lvdsc1_t *) HW_PMC_LVDSC1_ADDR(x))
 140 #define HW_PMC_LVDSC1_RD(x)      (HW_PMC_LVDSC1(x).U)
 141 #define HW_PMC_LVDSC1_WR(x, v)   (HW_PMC_LVDSC1(x).U = (v))
 142 #define HW_PMC_LVDSC1_SET(x, v)  (HW_PMC_LVDSC1_WR(x, HW_PMC_LVDSC1_RD(x) |  (v)))
 143 #define HW_PMC_LVDSC1_CLR(x, v)  (HW_PMC_LVDSC1_WR(x, HW_PMC_LVDSC1_RD(x) & ~(v)))
 144 #define HW_PMC_LVDSC1_TOG(x, v)  (HW_PMC_LVDSC1_WR(x, HW_PMC_LVDSC1_RD(x) ^  (v)))
 145 /*@}*/
 146
 147 /*
 148  * Constants & macros for individual PMC_LVDSC1 bitfields
 149  */
 150
 151 /*!
 152  * @name Register PMC_LVDSC1, field LVDV[1:0] (RW)
 153  *
 154  * Selects the LVD trip point voltage (V LVD ).
 155  *
 156  * Values:
 157  * - 00 - Low trip point selected (V LVD = V LVDL )
 158  * - 01 - High trip point selected (V LVD = V LVDH )
 159  * - 10 - Reserved
 160  * - 11 - Reserved
 161  */
 162 /*@{*/
 163 #define BP_PMC_LVDSC1_LVDV   (0U)          /*!< Bit position for PMC_LVDSC1_LVDV. */
 164 #define BM_PMC_LVDSC1_LVDV   (0x03U)       /*!< Bit mask for PMC_LVDSC1_LVDV. */
 165 #define BS_PMC_LVDSC1_LVDV   (2U)          /*!< Bit field size in bits for PMC_LVDSC1_LVDV. */
 166
 167 /*! @brief Read current value of the PMC_LVDSC1_LVDV field. */
 168 #define BR_PMC_LVDSC1_LVDV(x) (HW_PMC_LVDSC1(x).B.LVDV)
 169
 170 /*! @brief Format value for bitfield PMC_LVDSC1_LVDV. */
 171 #define BF_PMC_LVDSC1_LVDV(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC1_LVDV) & BM_PMC_LVDSC1_LVDV)
 172
 173 /*! @brief Set the LVDV field to a new value. */
 174 #define BW_PMC_LVDSC1_LVDV(x, v) (HW_PMC_LVDSC1_WR(x, (HW_PMC_LVDSC1_RD(x) & ~BM_PMC_LVDSC1_LVDV) | BF_PMC_LVDSC1_LVDV(v)))
 175 /*@}*/
 176
 177 /*!
 178  * @name Register PMC_LVDSC1, field LVDRE[4] (RW)
 179  *
 180  * This write-once bit enables LVDF events to generate a hardware reset.
 181  * Additional writes are ignored.
 182  *
 183  * Values:
 184  * - 0 - LVDF does not generate hardware resets
 185  * - 1 - Force an MCU reset when LVDF = 1
 186  */
 187 /*@{*/
 188 #define BP_PMC_LVDSC1_LVDRE  (4U)          /*!< Bit position for PMC_LVDSC1_LVDRE. */
 189 #define BM_PMC_LVDSC1_LVDRE  (0x10U)       /*!< Bit mask for PMC_LVDSC1_LVDRE. */
 190 #define BS_PMC_LVDSC1_LVDRE  (1U)          /*!< Bit field size in bits for PMC_LVDSC1_LVDRE. */
 191
 192 /*! @brief Read current value of the PMC_LVDSC1_LVDRE field. */
 193 #define BR_PMC_LVDSC1_LVDRE(x) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDRE))
 194
 195 /*! @brief Format value for bitfield PMC_LVDSC1_LVDRE. */
 196 #define BF_PMC_LVDSC1_LVDRE(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC1_LVDRE) & BM_PMC_LVDSC1_LVDRE)
 197
 198 /*! @brief Set the LVDRE field to a new value. */
 199 #define BW_PMC_LVDSC1_LVDRE(x, v) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDRE) = (v))
 200 /*@}*/
 201
 202 /*!
 203  * @name Register PMC_LVDSC1, field LVDIE[5] (RW)
 204  *
 205  * Enables hardware interrupt requests for LVDF.
 206  *
 207  * Values:
 208  * - 0 - Hardware interrupt disabled (use polling)
 209  * - 1 - Request a hardware interrupt when LVDF = 1
 210  */
 211 /*@{*/
 212 #define BP_PMC_LVDSC1_LVDIE  (5U)          /*!< Bit position for PMC_LVDSC1_LVDIE. */
 213 #define BM_PMC_LVDSC1_LVDIE  (0x20U)       /*!< Bit mask for PMC_LVDSC1_LVDIE. */
 214 #define BS_PMC_LVDSC1_LVDIE  (1U)          /*!< Bit field size in bits for PMC_LVDSC1_LVDIE. */
 215
 216 /*! @brief Read current value of the PMC_LVDSC1_LVDIE field. */
 217 #define BR_PMC_LVDSC1_LVDIE(x) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDIE))
 218
 219 /*! @brief Format value for bitfield PMC_LVDSC1_LVDIE. */
 220 #define BF_PMC_LVDSC1_LVDIE(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC1_LVDIE) & BM_PMC_LVDSC1_LVDIE)
 221
 222 /*! @brief Set the LVDIE field to a new value. */
 223 #define BW_PMC_LVDSC1_LVDIE(x, v) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDIE) = (v))
 224 /*@}*/
 225
 226 /*!
 227  * @name Register PMC_LVDSC1, field LVDACK[6] (WORZ)
 228  *
 229  * This write-only field is used to acknowledge low voltage detection errors.
 230  * Write 1 to clear LVDF. Reads always return 0.
 231  */
 232 /*@{*/
 233 #define BP_PMC_LVDSC1_LVDACK (6U)          /*!< Bit position for PMC_LVDSC1_LVDACK. */
 234 #define BM_PMC_LVDSC1_LVDACK (0x40U)       /*!< Bit mask for PMC_LVDSC1_LVDACK. */
 235 #define BS_PMC_LVDSC1_LVDACK (1U)          /*!< Bit field size in bits for PMC_LVDSC1_LVDACK. */
 236
 237 /*! @brief Format value for bitfield PMC_LVDSC1_LVDACK. */
 238 #define BF_PMC_LVDSC1_LVDACK(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC1_LVDACK) & BM_PMC_LVDSC1_LVDACK)
 239
 240 /*! @brief Set the LVDACK field to a new value. */
 241 #define BW_PMC_LVDSC1_LVDACK(x, v) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDACK) = (v))
 242 /*@}*/
 243
 244 /*!
 245  * @name Register PMC_LVDSC1, field LVDF[7] (RO)
 246  *
 247  * This read-only status field indicates a low-voltage detect event.
 248  *
 249  * Values:
 250  * - 0 - Low-voltage event not detected
 251  * - 1 - Low-voltage event detected
 252  */
 253 /*@{*/
 254 #define BP_PMC_LVDSC1_LVDF   (7U)          /*!< Bit position for PMC_LVDSC1_LVDF. */
 255 #define BM_PMC_LVDSC1_LVDF   (0x80U)       /*!< Bit mask for PMC_LVDSC1_LVDF. */
 256 #define BS_PMC_LVDSC1_LVDF   (1U)          /*!< Bit field size in bits for PMC_LVDSC1_LVDF. */
 257
 258 /*! @brief Read current value of the PMC_LVDSC1_LVDF field. */
 259 #define BR_PMC_LVDSC1_LVDF(x) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDF))
 260 /*@}*/
 261
 262 /*******************************************************************************
 263  * HW_PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register
 264  ******************************************************************************/
 265
 266 /*!
 267  * @brief HW_PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register (RW)
 268  *
 269  * Reset value: 0x00U
 270  *
 271  * This register contains status and control bits to support the low voltage
 272  * warning function. While the device is in the very low power or low leakage modes,
 273  * the LVD system is disabled regardless of LVDSC2 settings. See the device's
 274  * data sheet for the exact LVD trip voltages. The LVW trip voltages depend on LVWV
 275  * and LVDV. LVWV is reset solely on a POR Only event. The other fields of the
 276  * register are reset on Chip Reset Not VLLS. For more information about these
 277  * reset types, refer to the Reset section details.
 278  */
 279 typedef union _hw_pmc_lvdsc2
 280 {
 281     uint8_t U;
 282     struct _hw_pmc_lvdsc2_bitfields
 283     {
 284         uint8_t LVWV : 2;              /*!< [1:0] Low-Voltage Warning Voltage Select */
 285         uint8_t RESERVED0 : 3;         /*!< [4:2]  */
 286         uint8_t LVWIE : 1;             /*!< [5] Low-Voltage Warning Interrupt Enable */
 287         uint8_t LVWACK : 1;            /*!< [6] Low-Voltage Warning Acknowledge */
 288         uint8_t LVWF : 1;              /*!< [7] Low-Voltage Warning Flag */
 289     } B;
 290 } hw_pmc_lvdsc2_t;
 291
 292 /*!
 293  * @name Constants and macros for entire PMC_LVDSC2 register
 294  */
 295 /*@{*/
 296 #define HW_PMC_LVDSC2_ADDR(x)    ((x) + 0x1U)
 297
 298 #define HW_PMC_LVDSC2(x)         (*(__IO hw_pmc_lvdsc2_t *) HW_PMC_LVDSC2_ADDR(x))
 299 #define HW_PMC_LVDSC2_RD(x)      (HW_PMC_LVDSC2(x).U)
 300 #define HW_PMC_LVDSC2_WR(x, v)   (HW_PMC_LVDSC2(x).U = (v))
 301 #define HW_PMC_LVDSC2_SET(x, v)  (HW_PMC_LVDSC2_WR(x, HW_PMC_LVDSC2_RD(x) |  (v)))
 302 #define HW_PMC_LVDSC2_CLR(x, v)  (HW_PMC_LVDSC2_WR(x, HW_PMC_LVDSC2_RD(x) & ~(v)))
 303 #define HW_PMC_LVDSC2_TOG(x, v)  (HW_PMC_LVDSC2_WR(x, HW_PMC_LVDSC2_RD(x) ^  (v)))
 304 /*@}*/
 305
 306 /*
 307  * Constants & macros for individual PMC_LVDSC2 bitfields
 308  */
 309
 310 /*!
 311  * @name Register PMC_LVDSC2, field LVWV[1:0] (RW)
 312  *
 313  * Selects the LVW trip point voltage (VLVW). The actual voltage for the warning
 314  * depends on LVDSC1[LVDV].
 315  *
 316  * Values:
 317  * - 00 - Low trip point selected (VLVW = VLVW1)
 318  * - 01 - Mid 1 trip point selected (VLVW = VLVW2)
 319  * - 10 - Mid 2 trip point selected (VLVW = VLVW3)
 320  * - 11 - High trip point selected (VLVW = VLVW4)
 321  */
 322 /*@{*/
 323 #define BP_PMC_LVDSC2_LVWV   (0U)          /*!< Bit position for PMC_LVDSC2_LVWV. */
 324 #define BM_PMC_LVDSC2_LVWV   (0x03U)       /*!< Bit mask for PMC_LVDSC2_LVWV. */
 325 #define BS_PMC_LVDSC2_LVWV   (2U)          /*!< Bit field size in bits for PMC_LVDSC2_LVWV. */
 326
 327 /*! @brief Read current value of the PMC_LVDSC2_LVWV field. */
 328 #define BR_PMC_LVDSC2_LVWV(x) (HW_PMC_LVDSC2(x).B.LVWV)
 329
 330 /*! @brief Format value for bitfield PMC_LVDSC2_LVWV. */
 331 #define BF_PMC_LVDSC2_LVWV(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC2_LVWV) & BM_PMC_LVDSC2_LVWV)
 332
 333 /*! @brief Set the LVWV field to a new value. */
 334 #define BW_PMC_LVDSC2_LVWV(x, v) (HW_PMC_LVDSC2_WR(x, (HW_PMC_LVDSC2_RD(x) & ~BM_PMC_LVDSC2_LVWV) | BF_PMC_LVDSC2_LVWV(v)))
 335 /*@}*/
 336
 337 /*!
 338  * @name Register PMC_LVDSC2, field LVWIE[5] (RW)
 339  *
 340  * Enables hardware interrupt requests for LVWF.
 341  *
 342  * Values:
 343  * - 0 - Hardware interrupt disabled (use polling)
 344  * - 1 - Request a hardware interrupt when LVWF = 1
 345  */
 346 /*@{*/
 347 #define BP_PMC_LVDSC2_LVWIE  (5U)          /*!< Bit position for PMC_LVDSC2_LVWIE. */
 348 #define BM_PMC_LVDSC2_LVWIE  (0x20U)       /*!< Bit mask for PMC_LVDSC2_LVWIE. */
 349 #define BS_PMC_LVDSC2_LVWIE  (1U)          /*!< Bit field size in bits for PMC_LVDSC2_LVWIE. */
 350
 351 /*! @brief Read current value of the PMC_LVDSC2_LVWIE field. */
 352 #define BR_PMC_LVDSC2_LVWIE(x) (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR(x), BP_PMC_LVDSC2_LVWIE))
 353
 354 /*! @brief Format value for bitfield PMC_LVDSC2_LVWIE. */
 355 #define BF_PMC_LVDSC2_LVWIE(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC2_LVWIE) & BM_PMC_LVDSC2_LVWIE)
 356
 357 /*! @brief Set the LVWIE field to a new value. */
 358 #define BW_PMC_LVDSC2_LVWIE(x, v) (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR(x), BP_PMC_LVDSC2_LVWIE) = (v))
 359 /*@}*/
 360
 361 /*!
 362  * @name Register PMC_LVDSC2, field LVWACK[6] (WORZ)
 363  *
 364  * This write-only field is used to acknowledge low voltage warning errors.
 365  * Write 1 to clear LVWF. Reads always return 0.
 366  */
 367 /*@{*/
 368 #define BP_PMC_LVDSC2_LVWACK (6U)          /*!< Bit position for PMC_LVDSC2_LVWACK. */
 369 #define BM_PMC_LVDSC2_LVWACK (0x40U)       /*!< Bit mask for PMC_LVDSC2_LVWACK. */
 370 #define BS_PMC_LVDSC2_LVWACK (1U)          /*!< Bit field size in bits for PMC_LVDSC2_LVWACK. */
 371
 372 /*! @brief Format value for bitfield PMC_LVDSC2_LVWACK. */
 373 #define BF_PMC_LVDSC2_LVWACK(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC2_LVWACK) & BM_PMC_LVDSC2_LVWACK)
 374
 375 /*! @brief Set the LVWACK field to a new value. */
 376 #define BW_PMC_LVDSC2_LVWACK(x, v) (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR(x), BP_PMC_LVDSC2_LVWACK) = (v))
 377 /*@}*/
 378
 379 /*!
 380  * @name Register PMC_LVDSC2, field LVWF[7] (RO)
 381  *
 382  * This read-only status field indicates a low-voltage warning event. LVWF is
 383  * set when VSupply transitions below the trip point, or after reset and VSupply is
 384  * already below VLVW. LVWF may be 1 after power-on reset, therefore, to use LVW
 385  * interrupt function, before enabling LVWIE, LVWF must be cleared by writing
 386  * LVWACK first.
 387  *
 388  * Values:
 389  * - 0 - Low-voltage warning event not detected
 390  * - 1 - Low-voltage warning event detected
 391  */
 392 /*@{*/
 393 #define BP_PMC_LVDSC2_LVWF   (7U)          /*!< Bit position for PMC_LVDSC2_LVWF. */
 394 #define BM_PMC_LVDSC2_LVWF   (0x80U)       /*!< Bit mask for PMC_LVDSC2_LVWF. */
 395 #define BS_PMC_LVDSC2_LVWF   (1U)          /*!< Bit field size in bits for PMC_LVDSC2_LVWF. */
 396
 397 /*! @brief Read current value of the PMC_LVDSC2_LVWF field. */
 398 #define BR_PMC_LVDSC2_LVWF(x) (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR(x), BP_PMC_LVDSC2_LVWF))
 399 /*@}*/
 400
 401 /*******************************************************************************
 402  * HW_PMC_REGSC - Regulator Status And Control register
 403  ******************************************************************************/
 404
 405 /*!
 406  * @brief HW_PMC_REGSC - Regulator Status And Control register (RW)
 407  *
 408  * Reset value: 0x04U
 409  *
 410  * The PMC contains an internal voltage regulator. The voltage regulator design
 411  * uses a bandgap reference that is also available through a buffer as input to
 412  * certain internal peripherals, such as the CMP and ADC. The internal regulator
 413  * provides a status bit (REGONS) indicating the regulator is in run regulation.
 414  * This register is reset on Chip Reset Not VLLS and by reset types that trigger
 415  * Chip Reset not VLLS. See the Reset section details for more information.
 416  */
 417 typedef union _hw_pmc_regsc
 418 {
 419     uint8_t U;
 420     struct _hw_pmc_regsc_bitfields
 421     {
 422         uint8_t BGBE : 1;              /*!< [0] Bandgap Buffer Enable */
 423         uint8_t RESERVED0 : 1;         /*!< [1]  */
 424         uint8_t REGONS : 1;            /*!< [2] Regulator In Run Regulation Status */
 425         uint8_t ACKISO : 1;            /*!< [3] Acknowledge Isolation */
 426         uint8_t BGEN : 1;              /*!< [4] Bandgap Enable In VLPx Operation */
 427         uint8_t RESERVED1 : 3;         /*!< [7:5]  */
 428     } B;
 429 } hw_pmc_regsc_t;
 430
 431 /*!
 432  * @name Constants and macros for entire PMC_REGSC register
 433  */
 434 /*@{*/
 435 #define HW_PMC_REGSC_ADDR(x)     ((x) + 0x2U)
 436
 437 #define HW_PMC_REGSC(x)          (*(__IO hw_pmc_regsc_t *) HW_PMC_REGSC_ADDR(x))
 438 #define HW_PMC_REGSC_RD(x)       (HW_PMC_REGSC(x).U)
 439 #define HW_PMC_REGSC_WR(x, v)    (HW_PMC_REGSC(x).U = (v))
 440 #define HW_PMC_REGSC_SET(x, v)   (HW_PMC_REGSC_WR(x, HW_PMC_REGSC_RD(x) |  (v)))
 441 #define HW_PMC_REGSC_CLR(x, v)   (HW_PMC_REGSC_WR(x, HW_PMC_REGSC_RD(x) & ~(v)))
 442 #define HW_PMC_REGSC_TOG(x, v)   (HW_PMC_REGSC_WR(x, HW_PMC_REGSC_RD(x) ^  (v)))
 443 /*@}*/
 444
 445 /*
 446  * Constants & macros for individual PMC_REGSC bitfields
 447  */
 448
 449 /*!
 450  * @name Register PMC_REGSC, field BGBE[0] (RW)
 451  *
 452  * Enables the bandgap buffer.
 453  *
 454  * Values:
 455  * - 0 - Bandgap buffer not enabled
 456  * - 1 - Bandgap buffer enabled
 457  */
 458 /*@{*/
 459 #define BP_PMC_REGSC_BGBE    (0U)          /*!< Bit position for PMC_REGSC_BGBE. */
 460 #define BM_PMC_REGSC_BGBE    (0x01U)       /*!< Bit mask for PMC_REGSC_BGBE. */
 461 #define BS_PMC_REGSC_BGBE    (1U)          /*!< Bit field size in bits for PMC_REGSC_BGBE. */
 462
 463 /*! @brief Read current value of the PMC_REGSC_BGBE field. */
 464 #define BR_PMC_REGSC_BGBE(x) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_BGBE))
 465
 466 /*! @brief Format value for bitfield PMC_REGSC_BGBE. */
 467 #define BF_PMC_REGSC_BGBE(v) ((uint8_t)((uint8_t)(v) << BP_PMC_REGSC_BGBE) & BM_PMC_REGSC_BGBE)
 468
 469 /*! @brief Set the BGBE field to a new value. */
 470 #define BW_PMC_REGSC_BGBE(x, v) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_BGBE) = (v))
 471 /*@}*/
 472
 473 /*!
 474  * @name Register PMC_REGSC, field REGONS[2] (RO)
 475  *
 476  * This read-only field provides the current status of the internal voltage
 477  * regulator.
 478  *
 479  * Values:
 480  * - 0 - Regulator is in stop regulation or in transition to/from it
 481  * - 1 - Regulator is in run regulation
 482  */
 483 /*@{*/
 484 #define BP_PMC_REGSC_REGONS  (2U)          /*!< Bit position for PMC_REGSC_REGONS. */
 485 #define BM_PMC_REGSC_REGONS  (0x04U)       /*!< Bit mask for PMC_REGSC_REGONS. */
 486 #define BS_PMC_REGSC_REGONS  (1U)          /*!< Bit field size in bits for PMC_REGSC_REGONS. */
 487
 488 /*! @brief Read current value of the PMC_REGSC_REGONS field. */
 489 #define BR_PMC_REGSC_REGONS(x) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_REGONS))
 490 /*@}*/
 491
 492 /*!
 493  * @name Register PMC_REGSC, field ACKISO[3] (W1C)
 494  *
 495  * Reading this field indicates whether certain peripherals and the I/O pads are
 496  * in a latched state as a result of having been in a VLLS mode. Writing 1 to
 497  * this field when it is set releases the I/O pads and certain peripherals to their
 498  * normal run mode state. After recovering from a VLLS mode, user should restore
 499  * chip configuration before clearing ACKISO. In particular, pin configuration
 500  * for enabled LLWU wakeup pins should be restored to avoid any LLWU flag from
 501  * being falsely set when ACKISO is cleared.
 502  *
 503  * Values:
 504  * - 0 - Peripherals and I/O pads are in normal run state.
 505  * - 1 - Certain peripherals and I/O pads are in an isolated and latched state.
 506  */
 507 /*@{*/
 508 #define BP_PMC_REGSC_ACKISO  (3U)          /*!< Bit position for PMC_REGSC_ACKISO. */
 509 #define BM_PMC_REGSC_ACKISO  (0x08U)       /*!< Bit mask for PMC_REGSC_ACKISO. */
 510 #define BS_PMC_REGSC_ACKISO  (1U)          /*!< Bit field size in bits for PMC_REGSC_ACKISO. */
 511
 512 /*! @brief Read current value of the PMC_REGSC_ACKISO field. */
 513 #define BR_PMC_REGSC_ACKISO(x) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_ACKISO))
 514
 515 /*! @brief Format value for bitfield PMC_REGSC_ACKISO. */
 516 #define BF_PMC_REGSC_ACKISO(v) ((uint8_t)((uint8_t)(v) << BP_PMC_REGSC_ACKISO) & BM_PMC_REGSC_ACKISO)
 517
 518 /*! @brief Set the ACKISO field to a new value. */
 519 #define BW_PMC_REGSC_ACKISO(x, v) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_ACKISO) = (v))
 520 /*@}*/
 521
 522 /*!
 523  * @name Register PMC_REGSC, field BGEN[4] (RW)
 524  *
 525  * BGEN controls whether the bandgap is enabled in lower power modes of
 526  * operation (VLPx, LLS, and VLLSx). When on-chip peripherals require the bandgap voltage
 527  * reference in low power modes of operation, set BGEN to continue to enable the
 528  * bandgap operation. When the bandgap voltage reference is not needed in low
 529  * power modes, clear BGEN to avoid excess power consumption.
 530  *
 531  * Values:
 532  * - 0 - Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes.
 533  * - 1 - Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes.
 534  */
 535 /*@{*/
 536 #define BP_PMC_REGSC_BGEN    (4U)          /*!< Bit position for PMC_REGSC_BGEN. */
 537 #define BM_PMC_REGSC_BGEN    (0x10U)       /*!< Bit mask for PMC_REGSC_BGEN. */
 538 #define BS_PMC_REGSC_BGEN    (1U)          /*!< Bit field size in bits for PMC_REGSC_BGEN. */
 539
 540 /*! @brief Read current value of the PMC_REGSC_BGEN field. */
 541 #define BR_PMC_REGSC_BGEN(x) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_BGEN))
 542
 543 /*! @brief Format value for bitfield PMC_REGSC_BGEN. */
 544 #define BF_PMC_REGSC_BGEN(v) ((uint8_t)((uint8_t)(v) << BP_PMC_REGSC_BGEN) & BM_PMC_REGSC_BGEN)
 545
 546 /*! @brief Set the BGEN field to a new value. */
 547 #define BW_PMC_REGSC_BGEN(x, v) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_BGEN) = (v))
 548 /*@}*/
 549
 550 /*******************************************************************************
 551  * hw_pmc_t - module struct
 552  ******************************************************************************/
 553 /*!
 554  * @brief All PMC module registers.
 555  */
 556 #pragma pack(1)
 557 typedef struct _hw_pmc
 558 {
 559     __IO hw_pmc_lvdsc1_t LVDSC1;           /*!< [0x0] Low Voltage Detect Status And Control 1 register */
 560     __IO hw_pmc_lvdsc2_t LVDSC2;           /*!< [0x1] Low Voltage Detect Status And Control 2 register */
 561     __IO hw_pmc_regsc_t REGSC;             /*!< [0x2] Regulator Status And Control register */
 562 } hw_pmc_t;
 563 #pragma pack()
 564
 565 /*! @brief Macro to access all PMC registers. */
 566 /*! @param x PMC module instance base address. */
 567 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
 568  *     use the '&' operator, like <code>&HW_PMC(PMC_BASE)</code>. */
 569 #define HW_PMC(x)      (*(hw_pmc_t *)(x))
 570
 571 #endif /* __HW_PMC_REGISTERS_H__ */
 572 /* EOF */