tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_rng.h

   1 /*
   2 ** ###################################################################
   3 **     Compilers:           Keil ARM C/C++ Compiler
   4 **                          Freescale C/C++ for Embedded ARM
   5 **                          GNU C Compiler
   6 **                          IAR ANSI C/C++ Compiler for ARM
   7 **
   8 **     Reference manual:    K22P121M120SF7RM, Rev. 1, March 24, 2014
   9 **     Version:             rev. 2.5, 2014-05-06
  10 **     Build:               b140604
  11 **
  12 **     Abstract:
  13 **         Extension to the CMSIS register access layer header.
  14 **
  15 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
  16 **     All rights reserved.
  17 **
  18 **     Redistribution and use in source and binary forms, with or without modification,
  19 **     are permitted provided that the following conditions are met:
  20 **
  21 **     o Redistributions of source code must retain the above copyright notice, this list
  22 **       of conditions and the following disclaimer.
  23 **
  24 **     o Redistributions in binary form must reproduce the above copyright notice, this
  25 **       list of conditions and the following disclaimer in the documentation and/or
  26 **       other materials provided with the distribution.
  27 **
  28 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  29 **       contributors may be used to endorse or promote products derived from this
  30 **       software without specific prior written permission.
  31 **
  32 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  33 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  34 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  35 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  36 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  37 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  38 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  39 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  41 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42 **
  43 **     http:                 www.freescale.com
  44 **     mail:                 support@freescale.com
  45 **
  46 **     Revisions:
  47 **     - rev. 1.0 (2013-07-23)
  48 **         Initial version.
  49 **     - rev. 1.1 (2013-09-17)
  50 **         RM rev. 0.4 update.
  51 **     - rev. 2.0 (2013-10-29)
  52 **         Register accessor macros added to the memory map.
  53 **         Symbols for Processor Expert memory map compatibility added to the memory map.
  54 **         Startup file for gcc has been updated according to CMSIS 3.2.
  55 **         System initialization updated.
  56 **     - rev. 2.1 (2013-10-30)
  57 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
  58 **     - rev. 2.2 (2013-12-20)
  59 **         Update according to reference manual rev. 0.6,
  60 **     - rev. 2.3 (2014-01-13)
  61 **         Update according to reference manual rev. 0.61,
  62 **     - rev. 2.4 (2014-02-10)
  63 **         The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
  64 **     - rev. 2.5 (2014-05-06)
  65 **         Update according to reference manual rev. 1.0,
  66 **         Update of system and startup files.
  67 **         Module access macro module_BASES replaced by module_BASE_PTRS.
  68 **
  69 ** ###################################################################
  70 */
  71
  72 /*
  73  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
  74  *
  75  * This file was generated automatically and any changes may be lost.
  76  */
  77 #ifndef __HW_RNG_REGISTERS_H__
  78 #define __HW_RNG_REGISTERS_H__
  79
  80 #include "MK22F51212.h"
  81 #include "fsl_bitaccess.h"
  82
  83 /*
  84  * MK22F51212 RNG
  85  *
  86  * Random Number Generator Accelerator
  87  *
  88  * Registers defined in this header file:
  89  * - HW_RNG_CR - RNGA Control Register
  90  * - HW_RNG_SR - RNGA Status Register
  91  * - HW_RNG_ER - RNGA Entropy Register
  92  * - HW_RNG_OR - RNGA Output Register
  93  *
  94  * - hw_rng_t - Struct containing all module registers.
  95  */
  96
  97 #define HW_RNG_INSTANCE_COUNT (1U) /*!< Number of instances of the RNG module. */
  98
  99 /*******************************************************************************
 100  * HW_RNG_CR - RNGA Control Register
 101  ******************************************************************************/
 102
 103 /*!
 104  * @brief HW_RNG_CR - RNGA Control Register (RW)
 105  *
 106  * Reset value: 0x00000000U
 107  *
 108  * Controls the operation of RNGA.
 109  */
 110 typedef union _hw_rng_cr
 111 {
 112     uint32_t U;
 113     struct _hw_rng_cr_bitfields
 114     {
 115         uint32_t GO : 1;               /*!< [0] Go */
 116         uint32_t HA : 1;               /*!< [1] High Assurance */
 117         uint32_t INTM : 1;             /*!< [2] Interrupt Mask */
 118         uint32_t CLRI : 1;             /*!< [3] Clear Interrupt */
 119         uint32_t SLP : 1;              /*!< [4] Sleep */
 120         uint32_t RESERVED0 : 27;       /*!< [31:5]  */
 121     } B;
 122 } hw_rng_cr_t;
 123
 124 /*!
 125  * @name Constants and macros for entire RNG_CR register
 126  */
 127 /*@{*/
 128 #define HW_RNG_CR_ADDR(x)        ((x) + 0x0U)
 129
 130 #define HW_RNG_CR(x)             (*(__IO hw_rng_cr_t *) HW_RNG_CR_ADDR(x))
 131 #define HW_RNG_CR_RD(x)          (HW_RNG_CR(x).U)
 132 #define HW_RNG_CR_WR(x, v)       (HW_RNG_CR(x).U = (v))
 133 #define HW_RNG_CR_SET(x, v)      (HW_RNG_CR_WR(x, HW_RNG_CR_RD(x) |  (v)))
 134 #define HW_RNG_CR_CLR(x, v)      (HW_RNG_CR_WR(x, HW_RNG_CR_RD(x) & ~(v)))
 135 #define HW_RNG_CR_TOG(x, v)      (HW_RNG_CR_WR(x, HW_RNG_CR_RD(x) ^  (v)))
 136 /*@}*/
 137
 138 /*
 139  * Constants & macros for individual RNG_CR bitfields
 140  */
 141
 142 /*!
 143  * @name Register RNG_CR, field GO[0] (RW)
 144  *
 145  * Specifies whether random-data generation and loading (into OR[RANDOUT]) is
 146  * enabled.This field is sticky. You must reset RNGA to stop RNGA from loading
 147  * OR[RANDOUT] with data.
 148  *
 149  * Values:
 150  * - 0 - Disabled
 151  * - 1 - Enabled
 152  */
 153 /*@{*/
 154 #define BP_RNG_CR_GO         (0U)          /*!< Bit position for RNG_CR_GO. */
 155 #define BM_RNG_CR_GO         (0x00000001U) /*!< Bit mask for RNG_CR_GO. */
 156 #define BS_RNG_CR_GO         (1U)          /*!< Bit field size in bits for RNG_CR_GO. */
 157
 158 /*! @brief Read current value of the RNG_CR_GO field. */
 159 #define BR_RNG_CR_GO(x)      (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_GO))
 160
 161 /*! @brief Format value for bitfield RNG_CR_GO. */
 162 #define BF_RNG_CR_GO(v)      ((uint32_t)((uint32_t)(v) << BP_RNG_CR_GO) & BM_RNG_CR_GO)
 163
 164 /*! @brief Set the GO field to a new value. */
 165 #define BW_RNG_CR_GO(x, v)   (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_GO) = (v))
 166 /*@}*/
 167
 168 /*!
 169  * @name Register RNG_CR, field HA[1] (RW)
 170  *
 171  * Enables notification of security violations (via SR[SECV]). A security
 172  * violation occurs when you read OR[RANDOUT] and SR[OREG_LVL]=0. This field is sticky.
 173  * After enabling notification of security violations, you must reset RNGA to
 174  * disable them again.
 175  *
 176  * Values:
 177  * - 0 - Disabled
 178  * - 1 - Enabled
 179  */
 180 /*@{*/
 181 #define BP_RNG_CR_HA         (1U)          /*!< Bit position for RNG_CR_HA. */
 182 #define BM_RNG_CR_HA         (0x00000002U) /*!< Bit mask for RNG_CR_HA. */
 183 #define BS_RNG_CR_HA         (1U)          /*!< Bit field size in bits for RNG_CR_HA. */
 184
 185 /*! @brief Read current value of the RNG_CR_HA field. */
 186 #define BR_RNG_CR_HA(x)      (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_HA))
 187
 188 /*! @brief Format value for bitfield RNG_CR_HA. */
 189 #define BF_RNG_CR_HA(v)      ((uint32_t)((uint32_t)(v) << BP_RNG_CR_HA) & BM_RNG_CR_HA)
 190
 191 /*! @brief Set the HA field to a new value. */
 192 #define BW_RNG_CR_HA(x, v)   (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_HA) = (v))
 193 /*@}*/
 194
 195 /*!
 196  * @name Register RNG_CR, field INTM[2] (RW)
 197  *
 198  * Masks the triggering of an error interrupt to the interrupt controller when
 199  * an OR underflow condition occurs. An OR underflow condition occurs when you
 200  * read OR[RANDOUT] and SR[OREG_LVL]=0. See the Output Register (OR) description.
 201  *
 202  * Values:
 203  * - 0 - Not masked
 204  * - 1 - Masked
 205  */
 206 /*@{*/
 207 #define BP_RNG_CR_INTM       (2U)          /*!< Bit position for RNG_CR_INTM. */
 208 #define BM_RNG_CR_INTM       (0x00000004U) /*!< Bit mask for RNG_CR_INTM. */
 209 #define BS_RNG_CR_INTM       (1U)          /*!< Bit field size in bits for RNG_CR_INTM. */
 210
 211 /*! @brief Read current value of the RNG_CR_INTM field. */
 212 #define BR_RNG_CR_INTM(x)    (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_INTM))
 213
 214 /*! @brief Format value for bitfield RNG_CR_INTM. */
 215 #define BF_RNG_CR_INTM(v)    ((uint32_t)((uint32_t)(v) << BP_RNG_CR_INTM) & BM_RNG_CR_INTM)
 216
 217 /*! @brief Set the INTM field to a new value. */
 218 #define BW_RNG_CR_INTM(x, v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_INTM) = (v))
 219 /*@}*/
 220
 221 /*!
 222  * @name Register RNG_CR, field CLRI[3] (WORZ)
 223  *
 224  * Clears the interrupt by resetting the error-interrupt indicator (SR[ERRI]).
 225  *
 226  * Values:
 227  * - 0 - Do not clear the interrupt.
 228  * - 1 - Clear the interrupt. When you write 1 to this field, RNGA then resets
 229  *     the error-interrupt indicator (SR[ERRI]). This bit always reads as 0.
 230  */
 231 /*@{*/
 232 #define BP_RNG_CR_CLRI       (3U)          /*!< Bit position for RNG_CR_CLRI. */
 233 #define BM_RNG_CR_CLRI       (0x00000008U) /*!< Bit mask for RNG_CR_CLRI. */
 234 #define BS_RNG_CR_CLRI       (1U)          /*!< Bit field size in bits for RNG_CR_CLRI. */
 235
 236 /*! @brief Format value for bitfield RNG_CR_CLRI. */
 237 #define BF_RNG_CR_CLRI(v)    ((uint32_t)((uint32_t)(v) << BP_RNG_CR_CLRI) & BM_RNG_CR_CLRI)
 238
 239 /*! @brief Set the CLRI field to a new value. */
 240 #define BW_RNG_CR_CLRI(x, v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_CLRI) = (v))
 241 /*@}*/
 242
 243 /*!
 244  * @name Register RNG_CR, field SLP[4] (RW)
 245  *
 246  * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep
 247  * mode by asserting the DOZE signal.
 248  *
 249  * Values:
 250  * - 0 - Normal mode
 251  * - 1 - Sleep (low-power) mode
 252  */
 253 /*@{*/
 254 #define BP_RNG_CR_SLP        (4U)          /*!< Bit position for RNG_CR_SLP. */
 255 #define BM_RNG_CR_SLP        (0x00000010U) /*!< Bit mask for RNG_CR_SLP. */
 256 #define BS_RNG_CR_SLP        (1U)          /*!< Bit field size in bits for RNG_CR_SLP. */
 257
 258 /*! @brief Read current value of the RNG_CR_SLP field. */
 259 #define BR_RNG_CR_SLP(x)     (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_SLP))
 260
 261 /*! @brief Format value for bitfield RNG_CR_SLP. */
 262 #define BF_RNG_CR_SLP(v)     ((uint32_t)((uint32_t)(v) << BP_RNG_CR_SLP) & BM_RNG_CR_SLP)
 263
 264 /*! @brief Set the SLP field to a new value. */
 265 #define BW_RNG_CR_SLP(x, v)  (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_SLP) = (v))
 266 /*@}*/
 267
 268 /*******************************************************************************
 269  * HW_RNG_SR - RNGA Status Register
 270  ******************************************************************************/
 271
 272 /*!
 273  * @brief HW_RNG_SR - RNGA Status Register (RO)
 274  *
 275  * Reset value: 0x00010000U
 276  *
 277  * Indicates the status of RNGA. This register is read-only.
 278  */
 279 typedef union _hw_rng_sr
 280 {
 281     uint32_t U;
 282     struct _hw_rng_sr_bitfields
 283     {
 284         uint32_t SECV : 1;             /*!< [0] Security Violation */
 285         uint32_t LRS : 1;              /*!< [1] Last Read Status */
 286         uint32_t ORU : 1;              /*!< [2] Output Register Underflow */
 287         uint32_t ERRI : 1;             /*!< [3] Error Interrupt */
 288         uint32_t SLP : 1;              /*!< [4] Sleep */
 289         uint32_t RESERVED0 : 3;        /*!< [7:5]  */
 290         uint32_t OREG_LVL : 8;         /*!< [15:8] Output Register Level */
 291         uint32_t OREG_SIZE : 8;        /*!< [23:16] Output Register Size */
 292         uint32_t RESERVED1 : 8;        /*!< [31:24]  */
 293     } B;
 294 } hw_rng_sr_t;
 295
 296 /*!
 297  * @name Constants and macros for entire RNG_SR register
 298  */
 299 /*@{*/
 300 #define HW_RNG_SR_ADDR(x)        ((x) + 0x4U)
 301
 302 #define HW_RNG_SR(x)             (*(__I hw_rng_sr_t *) HW_RNG_SR_ADDR(x))
 303 #define HW_RNG_SR_RD(x)          (HW_RNG_SR(x).U)
 304 /*@}*/
 305
 306 /*
 307  * Constants & macros for individual RNG_SR bitfields
 308  */
 309
 310 /*!
 311  * @name Register RNG_SR, field SECV[0] (RO)
 312  *
 313  * Used only when high assurance is enabled (CR[HA]). Indicates that a security
 314  * violation has occurred.This field is sticky. To clear SR[SECV], you must reset
 315  * RNGA.
 316  *
 317  * Values:
 318  * - 0 - No security violation
 319  * - 1 - Security violation
 320  */
 321 /*@{*/
 322 #define BP_RNG_SR_SECV       (0U)          /*!< Bit position for RNG_SR_SECV. */
 323 #define BM_RNG_SR_SECV       (0x00000001U) /*!< Bit mask for RNG_SR_SECV. */
 324 #define BS_RNG_SR_SECV       (1U)          /*!< Bit field size in bits for RNG_SR_SECV. */
 325
 326 /*! @brief Read current value of the RNG_SR_SECV field. */
 327 #define BR_RNG_SR_SECV(x)    (BITBAND_ACCESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_SECV))
 328 /*@}*/
 329
 330 /*!
 331  * @name Register RNG_SR, field LRS[1] (RO)
 332  *
 333  * Indicates whether the most recent read of OR[RANDOUT] caused an OR underflow
 334  * condition, regardless of whether the error interrupt is masked (CR[INTM]). An
 335  * OR underflow condition occurs when you read OR[RANDOUT] and SR[OREG_LVL]=0.
 336  * After you read this register, RNGA writes 0 to this field.
 337  *
 338  * Values:
 339  * - 0 - No underflow
 340  * - 1 - Underflow
 341  */
 342 /*@{*/
 343 #define BP_RNG_SR_LRS        (1U)          /*!< Bit position for RNG_SR_LRS. */
 344 #define BM_RNG_SR_LRS        (0x00000002U) /*!< Bit mask for RNG_SR_LRS. */
 345 #define BS_RNG_SR_LRS        (1U)          /*!< Bit field size in bits for RNG_SR_LRS. */
 346
 347 /*! @brief Read current value of the RNG_SR_LRS field. */
 348 #define BR_RNG_SR_LRS(x)     (BITBAND_ACCESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_LRS))
 349 /*@}*/
 350
 351 /*!
 352  * @name Register RNG_SR, field ORU[2] (RO)
 353  *
 354  * Indicates whether an OR underflow condition has occurred since you last read
 355  * this register (SR) or RNGA was reset, regardless of whether the error
 356  * interrupt is masked (CR[INTM]). An OR underflow condition occurs when you read
 357  * OR[RANDOUT] and SR[OREG_LVL]=0. After you read this register, RNGA writes 0 to this
 358  * field.
 359  *
 360  * Values:
 361  * - 0 - No underflow
 362  * - 1 - Underflow
 363  */
 364 /*@{*/
 365 #define BP_RNG_SR_ORU        (2U)          /*!< Bit position for RNG_SR_ORU. */
 366 #define BM_RNG_SR_ORU        (0x00000004U) /*!< Bit mask for RNG_SR_ORU. */
 367 #define BS_RNG_SR_ORU        (1U)          /*!< Bit field size in bits for RNG_SR_ORU. */
 368
 369 /*! @brief Read current value of the RNG_SR_ORU field. */
 370 #define BR_RNG_SR_ORU(x)     (BITBAND_ACCESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_ORU))
 371 /*@}*/
 372
 373 /*!
 374  * @name Register RNG_SR, field ERRI[3] (RO)
 375  *
 376  * Indicates whether an OR underflow condition has occurred since you last
 377  * cleared the error interrupt (CR[CLRI]) or RNGA was reset, regardless of whether the
 378  * error interrupt is masked (CR[INTM]). An OR underflow condition occurs when
 379  * you read OR[RANDOUT] and SR[OREG_LVL]=0. After you reset the error-interrupt
 380  * indicator (via CR[CLRI]), RNGA writes 0 to this field.
 381  *
 382  * Values:
 383  * - 0 - No underflow
 384  * - 1 - Underflow
 385  */
 386 /*@{*/
 387 #define BP_RNG_SR_ERRI       (3U)          /*!< Bit position for RNG_SR_ERRI. */
 388 #define BM_RNG_SR_ERRI       (0x00000008U) /*!< Bit mask for RNG_SR_ERRI. */
 389 #define BS_RNG_SR_ERRI       (1U)          /*!< Bit field size in bits for RNG_SR_ERRI. */
 390
 391 /*! @brief Read current value of the RNG_SR_ERRI field. */
 392 #define BR_RNG_SR_ERRI(x)    (BITBAND_ACCESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_ERRI))
 393 /*@}*/
 394
 395 /*!
 396  * @name Register RNG_SR, field SLP[4] (RO)
 397  *
 398  * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep
 399  * mode by asserting the DOZE signal.
 400  *
 401  * Values:
 402  * - 0 - Normal mode
 403  * - 1 - Sleep (low-power) mode
 404  */
 405 /*@{*/
 406 #define BP_RNG_SR_SLP        (4U)          /*!< Bit position for RNG_SR_SLP. */
 407 #define BM_RNG_SR_SLP        (0x00000010U) /*!< Bit mask for RNG_SR_SLP. */
 408 #define BS_RNG_SR_SLP        (1U)          /*!< Bit field size in bits for RNG_SR_SLP. */
 409
 410 /*! @brief Read current value of the RNG_SR_SLP field. */
 411 #define BR_RNG_SR_SLP(x)     (BITBAND_ACCESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_SLP))
 412 /*@}*/
 413
 414 /*!
 415  * @name Register RNG_SR, field OREG_LVL[15:8] (RO)
 416  *
 417  * Indicates the number of random-data words that are in OR[RANDOUT], which
 418  * indicates whether OR[RANDOUT] is valid.If you read OR[RANDOUT] when SR[OREG_LVL]
 419  * is not 0, then the contents of a random number contained in OR[RANDOUT] are
 420  * returned, and RNGA writes 0 to both OR[RANDOUT] and SR[OREG_LVL].
 421  *
 422  * Values:
 423  * - 0 - No words (empty)
 424  * - 1 - One word (valid)
 425  */
 426 /*@{*/
 427 #define BP_RNG_SR_OREG_LVL   (8U)          /*!< Bit position for RNG_SR_OREG_LVL. */
 428 #define BM_RNG_SR_OREG_LVL   (0x0000FF00U) /*!< Bit mask for RNG_SR_OREG_LVL. */
 429 #define BS_RNG_SR_OREG_LVL   (8U)          /*!< Bit field size in bits for RNG_SR_OREG_LVL. */
 430
 431 /*! @brief Read current value of the RNG_SR_OREG_LVL field. */
 432 #define BR_RNG_SR_OREG_LVL(x) (HW_RNG_SR(x).B.OREG_LVL)
 433 /*@}*/
 434
 435 /*!
 436  * @name Register RNG_SR, field OREG_SIZE[23:16] (RO)
 437  *
 438  * Indicates the size of the Output (OR) register in terms of the number of
 439  * 32-bit random-data words it can hold.
 440  *
 441  * Values:
 442  * - 1 - One word (this value is fixed)
 443  */
 444 /*@{*/
 445 #define BP_RNG_SR_OREG_SIZE  (16U)         /*!< Bit position for RNG_SR_OREG_SIZE. */
 446 #define BM_RNG_SR_OREG_SIZE  (0x00FF0000U) /*!< Bit mask for RNG_SR_OREG_SIZE. */
 447 #define BS_RNG_SR_OREG_SIZE  (8U)          /*!< Bit field size in bits for RNG_SR_OREG_SIZE. */
 448
 449 /*! @brief Read current value of the RNG_SR_OREG_SIZE field. */
 450 #define BR_RNG_SR_OREG_SIZE(x) (HW_RNG_SR(x).B.OREG_SIZE)
 451 /*@}*/
 452
 453 /*******************************************************************************
 454  * HW_RNG_ER - RNGA Entropy Register
 455  ******************************************************************************/
 456
 457 /*!
 458  * @brief HW_RNG_ER - RNGA Entropy Register (WORZ)
 459  *
 460  * Reset value: 0x00000000U
 461  *
 462  * Specifies an entropy value that RNGA uses in addition to its ring oscillators
 463  * to seed its pseudorandom algorithm. This is a write-only register; reads
 464  * return all zeros.
 465  */
 466 typedef union _hw_rng_er
 467 {
 468     uint32_t U;
 469     struct _hw_rng_er_bitfields
 470     {
 471         uint32_t EXT_ENT : 32;         /*!< [31:0] External Entropy */
 472     } B;
 473 } hw_rng_er_t;
 474
 475 /*!
 476  * @name Constants and macros for entire RNG_ER register
 477  */
 478 /*@{*/
 479 #define HW_RNG_ER_ADDR(x)        ((x) + 0x8U)
 480
 481 #define HW_RNG_ER(x)             (*(__O hw_rng_er_t *) HW_RNG_ER_ADDR(x))
 482 #define HW_RNG_ER_RD(x)          (HW_RNG_ER(x).U)
 483 #define HW_RNG_ER_WR(x, v)       (HW_RNG_ER(x).U = (v))
 484 /*@}*/
 485
 486 /*
 487  * Constants & macros for individual RNG_ER bitfields
 488  */
 489
 490 /*!
 491  * @name Register RNG_ER, field EXT_ENT[31:0] (WORZ)
 492  *
 493  * Specifies an entropy value that RNGA uses in addition to its ring oscillators
 494  * to seed its pseudorandom algorithm.Specifying a value for this field is
 495  * optional but recommended. You can write to this field at any time during operation.
 496  */
 497 /*@{*/
 498 #define BP_RNG_ER_EXT_ENT    (0U)          /*!< Bit position for RNG_ER_EXT_ENT. */
 499 #define BM_RNG_ER_EXT_ENT    (0xFFFFFFFFU) /*!< Bit mask for RNG_ER_EXT_ENT. */
 500 #define BS_RNG_ER_EXT_ENT    (32U)         /*!< Bit field size in bits for RNG_ER_EXT_ENT. */
 501
 502 /*! @brief Format value for bitfield RNG_ER_EXT_ENT. */
 503 #define BF_RNG_ER_EXT_ENT(v) ((uint32_t)((uint32_t)(v) << BP_RNG_ER_EXT_ENT) & BM_RNG_ER_EXT_ENT)
 504
 505 /*! @brief Set the EXT_ENT field to a new value. */
 506 #define BW_RNG_ER_EXT_ENT(x, v) (HW_RNG_ER_WR(x, v))
 507 /*@}*/
 508
 509 /*******************************************************************************
 510  * HW_RNG_OR - RNGA Output Register
 511  ******************************************************************************/
 512
 513 /*!
 514  * @brief HW_RNG_OR - RNGA Output Register (RO)
 515  *
 516  * Reset value: 0x00000000U
 517  *
 518  * Stores a random-data word generated by RNGA.
 519  */
 520 typedef union _hw_rng_or
 521 {
 522     uint32_t U;
 523     struct _hw_rng_or_bitfields
 524     {
 525         uint32_t RANDOUT : 32;         /*!< [31:0] Random Output */
 526     } B;
 527 } hw_rng_or_t;
 528
 529 /*!
 530  * @name Constants and macros for entire RNG_OR register
 531  */
 532 /*@{*/
 533 #define HW_RNG_OR_ADDR(x)        ((x) + 0xCU)
 534
 535 #define HW_RNG_OR(x)             (*(__I hw_rng_or_t *) HW_RNG_OR_ADDR(x))
 536 #define HW_RNG_OR_RD(x)          (HW_RNG_OR(x).U)
 537 /*@}*/
 538
 539 /*
 540  * Constants & macros for individual RNG_OR bitfields
 541  */
 542
 543 /*!
 544  * @name Register RNG_OR, field RANDOUT[31:0] (RO)
 545  *
 546  * Stores a random-data word generated by RNGA. This is a read-only field.Before
 547  * reading RANDOUT, be sure it is valid (SR[OREG_LVL]=1).
 548  *
 549  * Values:
 550  * - 0 - Invalid data (if you read this field when it is 0 and SR[OREG_LVL] is
 551  *     0, RNGA then writes 1 to SR[ERRI], SR[ORU], and SR[LRS]; when the error
 552  *     interrupt is not masked (CR[INTM]=0), RNGA also asserts an error interrupt
 553  *     request to the interrupt controller).
 554  */
 555 /*@{*/
 556 #define BP_RNG_OR_RANDOUT    (0U)          /*!< Bit position for RNG_OR_RANDOUT. */
 557 #define BM_RNG_OR_RANDOUT    (0xFFFFFFFFU) /*!< Bit mask for RNG_OR_RANDOUT. */
 558 #define BS_RNG_OR_RANDOUT    (32U)         /*!< Bit field size in bits for RNG_OR_RANDOUT. */
 559
 560 /*! @brief Read current value of the RNG_OR_RANDOUT field. */
 561 #define BR_RNG_OR_RANDOUT(x) (HW_RNG_OR(x).U)
 562 /*@}*/
 563
 564 /*******************************************************************************
 565  * hw_rng_t - module struct
 566  ******************************************************************************/
 567 /*!
 568  * @brief All RNG module registers.
 569  */
 570 #pragma pack(1)
 571 typedef struct _hw_rng
 572 {
 573     __IO hw_rng_cr_t CR;                   /*!< [0x0] RNGA Control Register */
 574     __I hw_rng_sr_t SR;                    /*!< [0x4] RNGA Status Register */
 575     __O hw_rng_er_t ER;                    /*!< [0x8] RNGA Entropy Register */
 576     __I hw_rng_or_t OR;                    /*!< [0xC] RNGA Output Register */
 577 } hw_rng_t;
 578 #pragma pack()
 579
 580 /*! @brief Macro to access all RNG registers. */
 581 /*! @param x RNG module instance base address. */
 582 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
 583  *     use the '&' operator, like <code>&HW_RNG(RNG_BASE)</code>. */
 584 #define HW_RNG(x)      (*(hw_rng_t *)(x))
 585
 586 #endif /* __HW_RNG_REGISTERS_H__ */
 587 /* EOF */