2 ** ###################################################################
3 ** Compilers: Keil ARM C/C++ Compiler
4 ** Freescale C/C++ for Embedded ARM
6 ** IAR ANSI C/C++ Compiler for ARM
8 ** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
9 ** Version: rev. 2.5, 2014-05-06
13 ** Extension to the CMSIS register access layer header.
15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
16 ** All rights reserved.
18 ** Redistribution and use in source and binary forms, with or without modification,
19 ** are permitted provided that the following conditions are met:
21 ** o Redistributions of source code must retain the above copyright notice, this list
22 ** of conditions and the following disclaimer.
24 ** o Redistributions in binary form must reproduce the above copyright notice, this
25 ** list of conditions and the following disclaimer in the documentation and/or
26 ** other materials provided with the distribution.
28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
29 ** contributors may be used to endorse or promote products derived from this
30 ** software without specific prior written permission.
32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 ** http: www.freescale.com
44 ** mail: support@freescale.com
47 ** - rev. 1.0 (2013-07-23)
49 ** - rev. 1.1 (2013-09-17)
50 ** RM rev. 0.4 update.
51 ** - rev. 2.0 (2013-10-29)
52 ** Register accessor macros added to the memory map.
53 ** Symbols for Processor Expert memory map compatibility added to the memory map.
54 ** Startup file for gcc has been updated according to CMSIS 3.2.
55 ** System initialization updated.
56 ** - rev. 2.1 (2013-10-30)
57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
58 ** - rev. 2.2 (2013-12-20)
59 ** Update according to reference manual rev. 0.6,
60 ** - rev. 2.3 (2014-01-13)
61 ** Update according to reference manual rev. 0.61,
62 ** - rev. 2.4 (2014-02-10)
63 ** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
64 ** - rev. 2.5 (2014-05-06)
65 ** Update according to reference manual rev. 1.0,
66 ** Update of system and startup files.
67 ** Module access macro module_BASES replaced by module_BASE_PTRS.
69 ** ###################################################################
73 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
75 * This file was generated automatically and any changes may be lost.
77 #ifndef __HW_USB_REGISTERS_H__
78 #define __HW_USB_REGISTERS_H__
80 #include "MK22F51212.h"
81 #include "fsl_bitaccess.h"
86 * Universal Serial Bus, OTG Capable Controller
88 * Registers defined in this header file:
89 * - HW_USB_PERID - Peripheral ID register
90 * - HW_USB_IDCOMP - Peripheral ID Complement register
91 * - HW_USB_REV - Peripheral Revision register
92 * - HW_USB_ADDINFO - Peripheral Additional Info register
93 * - HW_USB_OTGISTAT - OTG Interrupt Status register
94 * - HW_USB_OTGICR - OTG Interrupt Control register
95 * - HW_USB_OTGSTAT - OTG Status register
96 * - HW_USB_OTGCTL - OTG Control register
97 * - HW_USB_ISTAT - Interrupt Status register
98 * - HW_USB_INTEN - Interrupt Enable register
99 * - HW_USB_ERRSTAT - Error Interrupt Status register
100 * - HW_USB_ERREN - Error Interrupt Enable register
101 * - HW_USB_STAT - Status register
102 * - HW_USB_CTL - Control register
103 * - HW_USB_ADDR - Address register
104 * - HW_USB_BDTPAGE1 - BDT Page register 1
105 * - HW_USB_FRMNUML - Frame Number register Low
106 * - HW_USB_FRMNUMH - Frame Number register High
107 * - HW_USB_TOKEN - Token register
108 * - HW_USB_SOFTHLD - SOF Threshold register
109 * - HW_USB_BDTPAGE2 - BDT Page Register 2
110 * - HW_USB_BDTPAGE3 - BDT Page Register 3
111 * - HW_USB_ENDPTn - Endpoint Control register
112 * - HW_USB_USBCTRL - USB Control register
113 * - HW_USB_OBSERVE - USB OTG Observe register
114 * - HW_USB_CONTROL - USB OTG Control register
115 * - HW_USB_USBTRC0 - USB Transceiver Control register 0
116 * - HW_USB_USBFRMADJUST - Frame Adjust Register
117 * - HW_USB_CLK_RECOVER_CTRL - USB Clock recovery control
118 * - HW_USB_CLK_RECOVER_IRC_EN - IRC48M oscillator enable register
119 * - HW_USB_CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status
121 * - hw_usb_t - Struct containing all module registers.
124 #define HW_USB_INSTANCE_COUNT (1U) /*!< Number of instances of the USB module. */
126 /*******************************************************************************
127 * HW_USB_PERID - Peripheral ID register
128 ******************************************************************************/
131 * @brief HW_USB_PERID - Peripheral ID register (RO)
135 * Reads back the value of 0x04. This value is defined for the USB peripheral.
137 typedef union _hw_usb_perid
140 struct _hw_usb_perid_bitfields
142 uint8_t ID
: 6; /*!< [5:0] Peripheral Identification */
143 uint8_t RESERVED0
: 2; /*!< [7:6] */
148 * @name Constants and macros for entire USB_PERID register
151 #define HW_USB_PERID_ADDR(x) ((x) + 0x0U)
153 #define HW_USB_PERID(x) (*(__I hw_usb_perid_t *) HW_USB_PERID_ADDR(x))
154 #define HW_USB_PERID_RD(x) (HW_USB_PERID(x).U)
158 * Constants & macros for individual USB_PERID bitfields
162 * @name Register USB_PERID, field ID[5:0] (RO)
164 * This field always reads 0x4h.
167 #define BP_USB_PERID_ID (0U) /*!< Bit position for USB_PERID_ID. */
168 #define BM_USB_PERID_ID (0x3FU) /*!< Bit mask for USB_PERID_ID. */
169 #define BS_USB_PERID_ID (6U) /*!< Bit field size in bits for USB_PERID_ID. */
171 /*! @brief Read current value of the USB_PERID_ID field. */
172 #define BR_USB_PERID_ID(x) (HW_USB_PERID(x).B.ID)
175 /*******************************************************************************
176 * HW_USB_IDCOMP - Peripheral ID Complement register
177 ******************************************************************************/
180 * @brief HW_USB_IDCOMP - Peripheral ID Complement register (RO)
184 * Reads back the complement of the Peripheral ID register. For the USB
185 * peripheral, the value is 0xFB.
187 typedef union _hw_usb_idcomp
190 struct _hw_usb_idcomp_bitfields
192 uint8_t NID
: 6; /*!< [5:0] */
193 uint8_t RESERVED0
: 2; /*!< [7:6] */
198 * @name Constants and macros for entire USB_IDCOMP register
201 #define HW_USB_IDCOMP_ADDR(x) ((x) + 0x4U)
203 #define HW_USB_IDCOMP(x) (*(__I hw_usb_idcomp_t *) HW_USB_IDCOMP_ADDR(x))
204 #define HW_USB_IDCOMP_RD(x) (HW_USB_IDCOMP(x).U)
208 * Constants & macros for individual USB_IDCOMP bitfields
212 * @name Register USB_IDCOMP, field NID[5:0] (RO)
214 * Ones' complement of PERID[ID]. bits.
217 #define BP_USB_IDCOMP_NID (0U) /*!< Bit position for USB_IDCOMP_NID. */
218 #define BM_USB_IDCOMP_NID (0x3FU) /*!< Bit mask for USB_IDCOMP_NID. */
219 #define BS_USB_IDCOMP_NID (6U) /*!< Bit field size in bits for USB_IDCOMP_NID. */
221 /*! @brief Read current value of the USB_IDCOMP_NID field. */
222 #define BR_USB_IDCOMP_NID(x) (HW_USB_IDCOMP(x).B.NID)
225 /*******************************************************************************
226 * HW_USB_REV - Peripheral Revision register
227 ******************************************************************************/
230 * @brief HW_USB_REV - Peripheral Revision register (RO)
234 * Contains the revision number of the USB module.
236 typedef union _hw_usb_rev
239 struct _hw_usb_rev_bitfields
241 uint8_t REV
: 8; /*!< [7:0] Revision */
246 * @name Constants and macros for entire USB_REV register
249 #define HW_USB_REV_ADDR(x) ((x) + 0x8U)
251 #define HW_USB_REV(x) (*(__I hw_usb_rev_t *) HW_USB_REV_ADDR(x))
252 #define HW_USB_REV_RD(x) (HW_USB_REV(x).U)
256 * Constants & macros for individual USB_REV bitfields
260 * @name Register USB_REV, field REV[7:0] (RO)
262 * Indicates the revision number of the USB Core.
265 #define BP_USB_REV_REV (0U) /*!< Bit position for USB_REV_REV. */
266 #define BM_USB_REV_REV (0xFFU) /*!< Bit mask for USB_REV_REV. */
267 #define BS_USB_REV_REV (8U) /*!< Bit field size in bits for USB_REV_REV. */
269 /*! @brief Read current value of the USB_REV_REV field. */
270 #define BR_USB_REV_REV(x) (HW_USB_REV(x).U)
273 /*******************************************************************************
274 * HW_USB_ADDINFO - Peripheral Additional Info register
275 ******************************************************************************/
278 * @brief HW_USB_ADDINFO - Peripheral Additional Info register (RO)
282 * Reads back the value of the Host Enable bit.
284 typedef union _hw_usb_addinfo
287 struct _hw_usb_addinfo_bitfields
289 uint8_t IEHOST
: 1; /*!< [0] */
290 uint8_t RESERVED0
: 7; /*!< [7:1] */
295 * @name Constants and macros for entire USB_ADDINFO register
298 #define HW_USB_ADDINFO_ADDR(x) ((x) + 0xCU)
300 #define HW_USB_ADDINFO(x) (*(__I hw_usb_addinfo_t *) HW_USB_ADDINFO_ADDR(x))
301 #define HW_USB_ADDINFO_RD(x) (HW_USB_ADDINFO(x).U)
305 * Constants & macros for individual USB_ADDINFO bitfields
309 * @name Register USB_ADDINFO, field IEHOST[0] (RO)
311 * This bit is set if host mode is enabled.
314 #define BP_USB_ADDINFO_IEHOST (0U) /*!< Bit position for USB_ADDINFO_IEHOST. */
315 #define BM_USB_ADDINFO_IEHOST (0x01U) /*!< Bit mask for USB_ADDINFO_IEHOST. */
316 #define BS_USB_ADDINFO_IEHOST (1U) /*!< Bit field size in bits for USB_ADDINFO_IEHOST. */
318 /*! @brief Read current value of the USB_ADDINFO_IEHOST field. */
319 #define BR_USB_ADDINFO_IEHOST(x) (BITBAND_ACCESS8(HW_USB_ADDINFO_ADDR(x), BP_USB_ADDINFO_IEHOST))
322 /*******************************************************************************
323 * HW_USB_OTGISTAT - OTG Interrupt Status register
324 ******************************************************************************/
327 * @brief HW_USB_OTGISTAT - OTG Interrupt Status register (RW)
331 * Records changes of the ID sense and VBUS signals. Software can read this
332 * register to determine the event that triggers interrupt. Only bits that have
333 * changed since the last software read are set. Writing a one to a bit clears the
334 * associated interrupt.
336 typedef union _hw_usb_otgistat
339 struct _hw_usb_otgistat_bitfields
341 uint8_t AVBUSCHG
: 1; /*!< [0] */
342 uint8_t RESERVED0
: 1; /*!< [1] */
343 uint8_t B_SESS_CHG
: 1; /*!< [2] */
344 uint8_t SESSVLDCHG
: 1; /*!< [3] */
345 uint8_t RESERVED1
: 1; /*!< [4] */
346 uint8_t LINE_STATE_CHG
: 1; /*!< [5] */
347 uint8_t ONEMSEC
: 1; /*!< [6] */
348 uint8_t IDCHG
: 1; /*!< [7] */
353 * @name Constants and macros for entire USB_OTGISTAT register
356 #define HW_USB_OTGISTAT_ADDR(x) ((x) + 0x10U)
358 #define HW_USB_OTGISTAT(x) (*(__IO hw_usb_otgistat_t *) HW_USB_OTGISTAT_ADDR(x))
359 #define HW_USB_OTGISTAT_RD(x) (HW_USB_OTGISTAT(x).U)
360 #define HW_USB_OTGISTAT_WR(x, v) (HW_USB_OTGISTAT(x).U = (v))
361 #define HW_USB_OTGISTAT_SET(x, v) (HW_USB_OTGISTAT_WR(x, HW_USB_OTGISTAT_RD(x) | (v)))
362 #define HW_USB_OTGISTAT_CLR(x, v) (HW_USB_OTGISTAT_WR(x, HW_USB_OTGISTAT_RD(x) & ~(v)))
363 #define HW_USB_OTGISTAT_TOG(x, v) (HW_USB_OTGISTAT_WR(x, HW_USB_OTGISTAT_RD(x) ^ (v)))
367 * Constants & macros for individual USB_OTGISTAT bitfields
371 * @name Register USB_OTGISTAT, field AVBUSCHG[0] (RW)
373 * This bit is set when a change in VBUS is detected on an A device.
376 #define BP_USB_OTGISTAT_AVBUSCHG (0U) /*!< Bit position for USB_OTGISTAT_AVBUSCHG. */
377 #define BM_USB_OTGISTAT_AVBUSCHG (0x01U) /*!< Bit mask for USB_OTGISTAT_AVBUSCHG. */
378 #define BS_USB_OTGISTAT_AVBUSCHG (1U) /*!< Bit field size in bits for USB_OTGISTAT_AVBUSCHG. */
380 /*! @brief Read current value of the USB_OTGISTAT_AVBUSCHG field. */
381 #define BR_USB_OTGISTAT_AVBUSCHG(x) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_AVBUSCHG))
383 /*! @brief Format value for bitfield USB_OTGISTAT_AVBUSCHG. */
384 #define BF_USB_OTGISTAT_AVBUSCHG(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGISTAT_AVBUSCHG) & BM_USB_OTGISTAT_AVBUSCHG)
386 /*! @brief Set the AVBUSCHG field to a new value. */
387 #define BW_USB_OTGISTAT_AVBUSCHG(x, v) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_AVBUSCHG) = (v))
391 * @name Register USB_OTGISTAT, field B_SESS_CHG[2] (RW)
393 * This bit is set when a change in VBUS is detected on a B device.
396 #define BP_USB_OTGISTAT_B_SESS_CHG (2U) /*!< Bit position for USB_OTGISTAT_B_SESS_CHG. */
397 #define BM_USB_OTGISTAT_B_SESS_CHG (0x04U) /*!< Bit mask for USB_OTGISTAT_B_SESS_CHG. */
398 #define BS_USB_OTGISTAT_B_SESS_CHG (1U) /*!< Bit field size in bits for USB_OTGISTAT_B_SESS_CHG. */
400 /*! @brief Read current value of the USB_OTGISTAT_B_SESS_CHG field. */
401 #define BR_USB_OTGISTAT_B_SESS_CHG(x) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_B_SESS_CHG))
403 /*! @brief Format value for bitfield USB_OTGISTAT_B_SESS_CHG. */
404 #define BF_USB_OTGISTAT_B_SESS_CHG(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGISTAT_B_SESS_CHG) & BM_USB_OTGISTAT_B_SESS_CHG)
406 /*! @brief Set the B_SESS_CHG field to a new value. */
407 #define BW_USB_OTGISTAT_B_SESS_CHG(x, v) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_B_SESS_CHG) = (v))
411 * @name Register USB_OTGISTAT, field SESSVLDCHG[3] (RW)
413 * This bit is set when a change in VBUS is detected indicating a session valid
414 * or a session no longer valid.
417 #define BP_USB_OTGISTAT_SESSVLDCHG (3U) /*!< Bit position for USB_OTGISTAT_SESSVLDCHG. */
418 #define BM_USB_OTGISTAT_SESSVLDCHG (0x08U) /*!< Bit mask for USB_OTGISTAT_SESSVLDCHG. */
419 #define BS_USB_OTGISTAT_SESSVLDCHG (1U) /*!< Bit field size in bits for USB_OTGISTAT_SESSVLDCHG. */
421 /*! @brief Read current value of the USB_OTGISTAT_SESSVLDCHG field. */
422 #define BR_USB_OTGISTAT_SESSVLDCHG(x) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_SESSVLDCHG))
424 /*! @brief Format value for bitfield USB_OTGISTAT_SESSVLDCHG. */
425 #define BF_USB_OTGISTAT_SESSVLDCHG(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGISTAT_SESSVLDCHG) & BM_USB_OTGISTAT_SESSVLDCHG)
427 /*! @brief Set the SESSVLDCHG field to a new value. */
428 #define BW_USB_OTGISTAT_SESSVLDCHG(x, v) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_SESSVLDCHG) = (v))
432 * @name Register USB_OTGISTAT, field LINE_STATE_CHG[5] (RW)
434 * This interrupt is set when the USB line state (CTL[SE0] and CTL[JSTATE] bits)
435 * are stable without change for 1 millisecond, and the value of the line state
436 * is different from the last time when the line state was stable. It is set on
437 * transitions between SE0 and J-state, SE0 and K-state, and J-state and K-state.
438 * Changes in J-state while SE0 is true do not cause an interrupt. This interrupt
439 * can be used in detecting Reset, Resume, Connect, and Data Line Pulse
443 #define BP_USB_OTGISTAT_LINE_STATE_CHG (5U) /*!< Bit position for USB_OTGISTAT_LINE_STATE_CHG. */
444 #define BM_USB_OTGISTAT_LINE_STATE_CHG (0x20U) /*!< Bit mask for USB_OTGISTAT_LINE_STATE_CHG. */
445 #define BS_USB_OTGISTAT_LINE_STATE_CHG (1U) /*!< Bit field size in bits for USB_OTGISTAT_LINE_STATE_CHG. */
447 /*! @brief Read current value of the USB_OTGISTAT_LINE_STATE_CHG field. */
448 #define BR_USB_OTGISTAT_LINE_STATE_CHG(x) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_LINE_STATE_CHG))
450 /*! @brief Format value for bitfield USB_OTGISTAT_LINE_STATE_CHG. */
451 #define BF_USB_OTGISTAT_LINE_STATE_CHG(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGISTAT_LINE_STATE_CHG) & BM_USB_OTGISTAT_LINE_STATE_CHG)
453 /*! @brief Set the LINE_STATE_CHG field to a new value. */
454 #define BW_USB_OTGISTAT_LINE_STATE_CHG(x, v) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_LINE_STATE_CHG) = (v))
458 * @name Register USB_OTGISTAT, field ONEMSEC[6] (RW)
460 * This bit is set when the 1 millisecond timer expires. This bit stays asserted
461 * until cleared by software. The interrupt must be serviced every millisecond
462 * to avoid losing 1msec counts.
465 #define BP_USB_OTGISTAT_ONEMSEC (6U) /*!< Bit position for USB_OTGISTAT_ONEMSEC. */
466 #define BM_USB_OTGISTAT_ONEMSEC (0x40U) /*!< Bit mask for USB_OTGISTAT_ONEMSEC. */
467 #define BS_USB_OTGISTAT_ONEMSEC (1U) /*!< Bit field size in bits for USB_OTGISTAT_ONEMSEC. */
469 /*! @brief Read current value of the USB_OTGISTAT_ONEMSEC field. */
470 #define BR_USB_OTGISTAT_ONEMSEC(x) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_ONEMSEC))
472 /*! @brief Format value for bitfield USB_OTGISTAT_ONEMSEC. */
473 #define BF_USB_OTGISTAT_ONEMSEC(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGISTAT_ONEMSEC) & BM_USB_OTGISTAT_ONEMSEC)
475 /*! @brief Set the ONEMSEC field to a new value. */
476 #define BW_USB_OTGISTAT_ONEMSEC(x, v) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_ONEMSEC) = (v))
480 * @name Register USB_OTGISTAT, field IDCHG[7] (RW)
482 * This bit is set when a change in the ID Signal from the USB connector is
486 #define BP_USB_OTGISTAT_IDCHG (7U) /*!< Bit position for USB_OTGISTAT_IDCHG. */
487 #define BM_USB_OTGISTAT_IDCHG (0x80U) /*!< Bit mask for USB_OTGISTAT_IDCHG. */
488 #define BS_USB_OTGISTAT_IDCHG (1U) /*!< Bit field size in bits for USB_OTGISTAT_IDCHG. */
490 /*! @brief Read current value of the USB_OTGISTAT_IDCHG field. */
491 #define BR_USB_OTGISTAT_IDCHG(x) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_IDCHG))
493 /*! @brief Format value for bitfield USB_OTGISTAT_IDCHG. */
494 #define BF_USB_OTGISTAT_IDCHG(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGISTAT_IDCHG) & BM_USB_OTGISTAT_IDCHG)
496 /*! @brief Set the IDCHG field to a new value. */
497 #define BW_USB_OTGISTAT_IDCHG(x, v) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_IDCHG) = (v))
500 /*******************************************************************************
501 * HW_USB_OTGICR - OTG Interrupt Control register
502 ******************************************************************************/
505 * @brief HW_USB_OTGICR - OTG Interrupt Control register (RW)
509 * Enables the corresponding interrupt status bits defined in the OTG Interrupt
512 typedef union _hw_usb_otgicr
515 struct _hw_usb_otgicr_bitfields
517 uint8_t AVBUSEN
: 1; /*!< [0] A VBUS Valid Interrupt Enable */
518 uint8_t RESERVED0
: 1; /*!< [1] */
519 uint8_t BSESSEN
: 1; /*!< [2] B Session END Interrupt Enable */
520 uint8_t SESSVLDEN
: 1; /*!< [3] Session Valid Interrupt Enable */
521 uint8_t RESERVED1
: 1; /*!< [4] */
522 uint8_t LINESTATEEN
: 1; /*!< [5] Line State Change Interrupt Enable
524 uint8_t ONEMSECEN
: 1; /*!< [6] One Millisecond Interrupt Enable */
525 uint8_t IDEN
: 1; /*!< [7] ID Interrupt Enable */
530 * @name Constants and macros for entire USB_OTGICR register
533 #define HW_USB_OTGICR_ADDR(x) ((x) + 0x14U)
535 #define HW_USB_OTGICR(x) (*(__IO hw_usb_otgicr_t *) HW_USB_OTGICR_ADDR(x))
536 #define HW_USB_OTGICR_RD(x) (HW_USB_OTGICR(x).U)
537 #define HW_USB_OTGICR_WR(x, v) (HW_USB_OTGICR(x).U = (v))
538 #define HW_USB_OTGICR_SET(x, v) (HW_USB_OTGICR_WR(x, HW_USB_OTGICR_RD(x) | (v)))
539 #define HW_USB_OTGICR_CLR(x, v) (HW_USB_OTGICR_WR(x, HW_USB_OTGICR_RD(x) & ~(v)))
540 #define HW_USB_OTGICR_TOG(x, v) (HW_USB_OTGICR_WR(x, HW_USB_OTGICR_RD(x) ^ (v)))
544 * Constants & macros for individual USB_OTGICR bitfields
548 * @name Register USB_OTGICR, field AVBUSEN[0] (RW)
551 * - 0 - Disables the AVBUSCHG interrupt.
552 * - 1 - Enables the AVBUSCHG interrupt.
555 #define BP_USB_OTGICR_AVBUSEN (0U) /*!< Bit position for USB_OTGICR_AVBUSEN. */
556 #define BM_USB_OTGICR_AVBUSEN (0x01U) /*!< Bit mask for USB_OTGICR_AVBUSEN. */
557 #define BS_USB_OTGICR_AVBUSEN (1U) /*!< Bit field size in bits for USB_OTGICR_AVBUSEN. */
559 /*! @brief Read current value of the USB_OTGICR_AVBUSEN field. */
560 #define BR_USB_OTGICR_AVBUSEN(x) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_AVBUSEN))
562 /*! @brief Format value for bitfield USB_OTGICR_AVBUSEN. */
563 #define BF_USB_OTGICR_AVBUSEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGICR_AVBUSEN) & BM_USB_OTGICR_AVBUSEN)
565 /*! @brief Set the AVBUSEN field to a new value. */
566 #define BW_USB_OTGICR_AVBUSEN(x, v) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_AVBUSEN) = (v))
570 * @name Register USB_OTGICR, field BSESSEN[2] (RW)
573 * - 0 - Disables the B_SESS_CHG interrupt.
574 * - 1 - Enables the B_SESS_CHG interrupt.
577 #define BP_USB_OTGICR_BSESSEN (2U) /*!< Bit position for USB_OTGICR_BSESSEN. */
578 #define BM_USB_OTGICR_BSESSEN (0x04U) /*!< Bit mask for USB_OTGICR_BSESSEN. */
579 #define BS_USB_OTGICR_BSESSEN (1U) /*!< Bit field size in bits for USB_OTGICR_BSESSEN. */
581 /*! @brief Read current value of the USB_OTGICR_BSESSEN field. */
582 #define BR_USB_OTGICR_BSESSEN(x) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_BSESSEN))
584 /*! @brief Format value for bitfield USB_OTGICR_BSESSEN. */
585 #define BF_USB_OTGICR_BSESSEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGICR_BSESSEN) & BM_USB_OTGICR_BSESSEN)
587 /*! @brief Set the BSESSEN field to a new value. */
588 #define BW_USB_OTGICR_BSESSEN(x, v) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_BSESSEN) = (v))
592 * @name Register USB_OTGICR, field SESSVLDEN[3] (RW)
595 * - 0 - Disables the SESSVLDCHG interrupt.
596 * - 1 - Enables the SESSVLDCHG interrupt.
599 #define BP_USB_OTGICR_SESSVLDEN (3U) /*!< Bit position for USB_OTGICR_SESSVLDEN. */
600 #define BM_USB_OTGICR_SESSVLDEN (0x08U) /*!< Bit mask for USB_OTGICR_SESSVLDEN. */
601 #define BS_USB_OTGICR_SESSVLDEN (1U) /*!< Bit field size in bits for USB_OTGICR_SESSVLDEN. */
603 /*! @brief Read current value of the USB_OTGICR_SESSVLDEN field. */
604 #define BR_USB_OTGICR_SESSVLDEN(x) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_SESSVLDEN))
606 /*! @brief Format value for bitfield USB_OTGICR_SESSVLDEN. */
607 #define BF_USB_OTGICR_SESSVLDEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGICR_SESSVLDEN) & BM_USB_OTGICR_SESSVLDEN)
609 /*! @brief Set the SESSVLDEN field to a new value. */
610 #define BW_USB_OTGICR_SESSVLDEN(x, v) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_SESSVLDEN) = (v))
614 * @name Register USB_OTGICR, field LINESTATEEN[5] (RW)
617 * - 0 - Disables the LINE_STAT_CHG interrupt.
618 * - 1 - Enables the LINE_STAT_CHG interrupt.
621 #define BP_USB_OTGICR_LINESTATEEN (5U) /*!< Bit position for USB_OTGICR_LINESTATEEN. */
622 #define BM_USB_OTGICR_LINESTATEEN (0x20U) /*!< Bit mask for USB_OTGICR_LINESTATEEN. */
623 #define BS_USB_OTGICR_LINESTATEEN (1U) /*!< Bit field size in bits for USB_OTGICR_LINESTATEEN. */
625 /*! @brief Read current value of the USB_OTGICR_LINESTATEEN field. */
626 #define BR_USB_OTGICR_LINESTATEEN(x) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_LINESTATEEN))
628 /*! @brief Format value for bitfield USB_OTGICR_LINESTATEEN. */
629 #define BF_USB_OTGICR_LINESTATEEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGICR_LINESTATEEN) & BM_USB_OTGICR_LINESTATEEN)
631 /*! @brief Set the LINESTATEEN field to a new value. */
632 #define BW_USB_OTGICR_LINESTATEEN(x, v) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_LINESTATEEN) = (v))
636 * @name Register USB_OTGICR, field ONEMSECEN[6] (RW)
639 * - 0 - Diables the 1ms timer interrupt.
640 * - 1 - Enables the 1ms timer interrupt.
643 #define BP_USB_OTGICR_ONEMSECEN (6U) /*!< Bit position for USB_OTGICR_ONEMSECEN. */
644 #define BM_USB_OTGICR_ONEMSECEN (0x40U) /*!< Bit mask for USB_OTGICR_ONEMSECEN. */
645 #define BS_USB_OTGICR_ONEMSECEN (1U) /*!< Bit field size in bits for USB_OTGICR_ONEMSECEN. */
647 /*! @brief Read current value of the USB_OTGICR_ONEMSECEN field. */
648 #define BR_USB_OTGICR_ONEMSECEN(x) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_ONEMSECEN))
650 /*! @brief Format value for bitfield USB_OTGICR_ONEMSECEN. */
651 #define BF_USB_OTGICR_ONEMSECEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGICR_ONEMSECEN) & BM_USB_OTGICR_ONEMSECEN)
653 /*! @brief Set the ONEMSECEN field to a new value. */
654 #define BW_USB_OTGICR_ONEMSECEN(x, v) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_ONEMSECEN) = (v))
658 * @name Register USB_OTGICR, field IDEN[7] (RW)
661 * - 0 - The ID interrupt is disabled
662 * - 1 - The ID interrupt is enabled
665 #define BP_USB_OTGICR_IDEN (7U) /*!< Bit position for USB_OTGICR_IDEN. */
666 #define BM_USB_OTGICR_IDEN (0x80U) /*!< Bit mask for USB_OTGICR_IDEN. */
667 #define BS_USB_OTGICR_IDEN (1U) /*!< Bit field size in bits for USB_OTGICR_IDEN. */
669 /*! @brief Read current value of the USB_OTGICR_IDEN field. */
670 #define BR_USB_OTGICR_IDEN(x) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_IDEN))
672 /*! @brief Format value for bitfield USB_OTGICR_IDEN. */
673 #define BF_USB_OTGICR_IDEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGICR_IDEN) & BM_USB_OTGICR_IDEN)
675 /*! @brief Set the IDEN field to a new value. */
676 #define BW_USB_OTGICR_IDEN(x, v) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_IDEN) = (v))
679 /*******************************************************************************
680 * HW_USB_OTGSTAT - OTG Status register
681 ******************************************************************************/
684 * @brief HW_USB_OTGSTAT - OTG Status register (RW)
688 * Displays the actual value from the external comparator outputs of the ID pin
691 typedef union _hw_usb_otgstat
694 struct _hw_usb_otgstat_bitfields
696 uint8_t AVBUSVLD
: 1; /*!< [0] A VBUS Valid */
697 uint8_t RESERVED0
: 1; /*!< [1] */
698 uint8_t BSESSEND
: 1; /*!< [2] B Session End */
699 uint8_t SESS_VLD
: 1; /*!< [3] Session Valid */
700 uint8_t RESERVED1
: 1; /*!< [4] */
701 uint8_t LINESTATESTABLE
: 1; /*!< [5] */
702 uint8_t ONEMSECEN
: 1; /*!< [6] */
703 uint8_t ID
: 1; /*!< [7] */
708 * @name Constants and macros for entire USB_OTGSTAT register
711 #define HW_USB_OTGSTAT_ADDR(x) ((x) + 0x18U)
713 #define HW_USB_OTGSTAT(x) (*(__IO hw_usb_otgstat_t *) HW_USB_OTGSTAT_ADDR(x))
714 #define HW_USB_OTGSTAT_RD(x) (HW_USB_OTGSTAT(x).U)
715 #define HW_USB_OTGSTAT_WR(x, v) (HW_USB_OTGSTAT(x).U = (v))
716 #define HW_USB_OTGSTAT_SET(x, v) (HW_USB_OTGSTAT_WR(x, HW_USB_OTGSTAT_RD(x) | (v)))
717 #define HW_USB_OTGSTAT_CLR(x, v) (HW_USB_OTGSTAT_WR(x, HW_USB_OTGSTAT_RD(x) & ~(v)))
718 #define HW_USB_OTGSTAT_TOG(x, v) (HW_USB_OTGSTAT_WR(x, HW_USB_OTGSTAT_RD(x) ^ (v)))
722 * Constants & macros for individual USB_OTGSTAT bitfields
726 * @name Register USB_OTGSTAT, field AVBUSVLD[0] (RW)
729 * - 0 - The VBUS voltage is below the A VBUS Valid threshold.
730 * - 1 - The VBUS voltage is above the A VBUS Valid threshold.
733 #define BP_USB_OTGSTAT_AVBUSVLD (0U) /*!< Bit position for USB_OTGSTAT_AVBUSVLD. */
734 #define BM_USB_OTGSTAT_AVBUSVLD (0x01U) /*!< Bit mask for USB_OTGSTAT_AVBUSVLD. */
735 #define BS_USB_OTGSTAT_AVBUSVLD (1U) /*!< Bit field size in bits for USB_OTGSTAT_AVBUSVLD. */
737 /*! @brief Read current value of the USB_OTGSTAT_AVBUSVLD field. */
738 #define BR_USB_OTGSTAT_AVBUSVLD(x) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_AVBUSVLD))
740 /*! @brief Format value for bitfield USB_OTGSTAT_AVBUSVLD. */
741 #define BF_USB_OTGSTAT_AVBUSVLD(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGSTAT_AVBUSVLD) & BM_USB_OTGSTAT_AVBUSVLD)
743 /*! @brief Set the AVBUSVLD field to a new value. */
744 #define BW_USB_OTGSTAT_AVBUSVLD(x, v) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_AVBUSVLD) = (v))
748 * @name Register USB_OTGSTAT, field BSESSEND[2] (RW)
751 * - 0 - The VBUS voltage is above the B session end threshold.
752 * - 1 - The VBUS voltage is below the B session end threshold.
755 #define BP_USB_OTGSTAT_BSESSEND (2U) /*!< Bit position for USB_OTGSTAT_BSESSEND. */
756 #define BM_USB_OTGSTAT_BSESSEND (0x04U) /*!< Bit mask for USB_OTGSTAT_BSESSEND. */
757 #define BS_USB_OTGSTAT_BSESSEND (1U) /*!< Bit field size in bits for USB_OTGSTAT_BSESSEND. */
759 /*! @brief Read current value of the USB_OTGSTAT_BSESSEND field. */
760 #define BR_USB_OTGSTAT_BSESSEND(x) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_BSESSEND))
762 /*! @brief Format value for bitfield USB_OTGSTAT_BSESSEND. */
763 #define BF_USB_OTGSTAT_BSESSEND(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGSTAT_BSESSEND) & BM_USB_OTGSTAT_BSESSEND)
765 /*! @brief Set the BSESSEND field to a new value. */
766 #define BW_USB_OTGSTAT_BSESSEND(x, v) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_BSESSEND) = (v))
770 * @name Register USB_OTGSTAT, field SESS_VLD[3] (RW)
773 * - 0 - The VBUS voltage is below the B session valid threshold
774 * - 1 - The VBUS voltage is above the B session valid threshold.
777 #define BP_USB_OTGSTAT_SESS_VLD (3U) /*!< Bit position for USB_OTGSTAT_SESS_VLD. */
778 #define BM_USB_OTGSTAT_SESS_VLD (0x08U) /*!< Bit mask for USB_OTGSTAT_SESS_VLD. */
779 #define BS_USB_OTGSTAT_SESS_VLD (1U) /*!< Bit field size in bits for USB_OTGSTAT_SESS_VLD. */
781 /*! @brief Read current value of the USB_OTGSTAT_SESS_VLD field. */
782 #define BR_USB_OTGSTAT_SESS_VLD(x) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_SESS_VLD))
784 /*! @brief Format value for bitfield USB_OTGSTAT_SESS_VLD. */
785 #define BF_USB_OTGSTAT_SESS_VLD(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGSTAT_SESS_VLD) & BM_USB_OTGSTAT_SESS_VLD)
787 /*! @brief Set the SESS_VLD field to a new value. */
788 #define BW_USB_OTGSTAT_SESS_VLD(x, v) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_SESS_VLD) = (v))
792 * @name Register USB_OTGSTAT, field LINESTATESTABLE[5] (RW)
794 * Indicates that the internal signals that control the LINE_STATE_CHG field of
795 * OTGISTAT are stable for at least 1 millisecond. First read LINE_STATE_CHG
796 * field and then read this field. If this field reads as 1, then the value of
797 * LINE_STATE_CHG can be considered stable.
800 * - 0 - The LINE_STAT_CHG bit is not yet stable.
801 * - 1 - The LINE_STAT_CHG bit has been debounced and is stable.
804 #define BP_USB_OTGSTAT_LINESTATESTABLE (5U) /*!< Bit position for USB_OTGSTAT_LINESTATESTABLE. */
805 #define BM_USB_OTGSTAT_LINESTATESTABLE (0x20U) /*!< Bit mask for USB_OTGSTAT_LINESTATESTABLE. */
806 #define BS_USB_OTGSTAT_LINESTATESTABLE (1U) /*!< Bit field size in bits for USB_OTGSTAT_LINESTATESTABLE. */
808 /*! @brief Read current value of the USB_OTGSTAT_LINESTATESTABLE field. */
809 #define BR_USB_OTGSTAT_LINESTATESTABLE(x) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_LINESTATESTABLE))
811 /*! @brief Format value for bitfield USB_OTGSTAT_LINESTATESTABLE. */
812 #define BF_USB_OTGSTAT_LINESTATESTABLE(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGSTAT_LINESTATESTABLE) & BM_USB_OTGSTAT_LINESTATESTABLE)
814 /*! @brief Set the LINESTATESTABLE field to a new value. */
815 #define BW_USB_OTGSTAT_LINESTATESTABLE(x, v) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_LINESTATESTABLE) = (v))
819 * @name Register USB_OTGSTAT, field ONEMSECEN[6] (RW)
821 * This bit is reserved for the 1ms count, but it is not useful to software.
824 #define BP_USB_OTGSTAT_ONEMSECEN (6U) /*!< Bit position for USB_OTGSTAT_ONEMSECEN. */
825 #define BM_USB_OTGSTAT_ONEMSECEN (0x40U) /*!< Bit mask for USB_OTGSTAT_ONEMSECEN. */
826 #define BS_USB_OTGSTAT_ONEMSECEN (1U) /*!< Bit field size in bits for USB_OTGSTAT_ONEMSECEN. */
828 /*! @brief Read current value of the USB_OTGSTAT_ONEMSECEN field. */
829 #define BR_USB_OTGSTAT_ONEMSECEN(x) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_ONEMSECEN))
831 /*! @brief Format value for bitfield USB_OTGSTAT_ONEMSECEN. */
832 #define BF_USB_OTGSTAT_ONEMSECEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGSTAT_ONEMSECEN) & BM_USB_OTGSTAT_ONEMSECEN)
834 /*! @brief Set the ONEMSECEN field to a new value. */
835 #define BW_USB_OTGSTAT_ONEMSECEN(x, v) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_ONEMSECEN) = (v))
839 * @name Register USB_OTGSTAT, field ID[7] (RW)
841 * Indicates the current state of the ID pin on the USB connector
844 * - 0 - Indicates a Type A cable is plugged into the USB connector.
845 * - 1 - Indicates no cable is attached or a Type B cable is plugged into the
849 #define BP_USB_OTGSTAT_ID (7U) /*!< Bit position for USB_OTGSTAT_ID. */
850 #define BM_USB_OTGSTAT_ID (0x80U) /*!< Bit mask for USB_OTGSTAT_ID. */
851 #define BS_USB_OTGSTAT_ID (1U) /*!< Bit field size in bits for USB_OTGSTAT_ID. */
853 /*! @brief Read current value of the USB_OTGSTAT_ID field. */
854 #define BR_USB_OTGSTAT_ID(x) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_ID))
856 /*! @brief Format value for bitfield USB_OTGSTAT_ID. */
857 #define BF_USB_OTGSTAT_ID(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGSTAT_ID) & BM_USB_OTGSTAT_ID)
859 /*! @brief Set the ID field to a new value. */
860 #define BW_USB_OTGSTAT_ID(x, v) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_ID) = (v))
863 /*******************************************************************************
864 * HW_USB_OTGCTL - OTG Control register
865 ******************************************************************************/
868 * @brief HW_USB_OTGCTL - OTG Control register (RW)
872 * Controls the operation of VBUS and Data Line termination resistors.
874 typedef union _hw_usb_otgctl
877 struct _hw_usb_otgctl_bitfields
879 uint8_t RESERVED0
: 2; /*!< [1:0] */
880 uint8_t OTGEN
: 1; /*!< [2] On-The-Go pullup/pulldown resistor enable
882 uint8_t RESERVED1
: 1; /*!< [3] */
883 uint8_t DMLOW
: 1; /*!< [4] D- Data Line pull-down resistor enable */
884 uint8_t DPLOW
: 1; /*!< [5] D+ Data Line pull-down resistor enable */
885 uint8_t RESERVED2
: 1; /*!< [6] */
886 uint8_t DPHIGH
: 1; /*!< [7] D+ Data Line pullup resistor enable */
891 * @name Constants and macros for entire USB_OTGCTL register
894 #define HW_USB_OTGCTL_ADDR(x) ((x) + 0x1CU)
896 #define HW_USB_OTGCTL(x) (*(__IO hw_usb_otgctl_t *) HW_USB_OTGCTL_ADDR(x))
897 #define HW_USB_OTGCTL_RD(x) (HW_USB_OTGCTL(x).U)
898 #define HW_USB_OTGCTL_WR(x, v) (HW_USB_OTGCTL(x).U = (v))
899 #define HW_USB_OTGCTL_SET(x, v) (HW_USB_OTGCTL_WR(x, HW_USB_OTGCTL_RD(x) | (v)))
900 #define HW_USB_OTGCTL_CLR(x, v) (HW_USB_OTGCTL_WR(x, HW_USB_OTGCTL_RD(x) & ~(v)))
901 #define HW_USB_OTGCTL_TOG(x, v) (HW_USB_OTGCTL_WR(x, HW_USB_OTGCTL_RD(x) ^ (v)))
905 * Constants & macros for individual USB_OTGCTL bitfields
909 * @name Register USB_OTGCTL, field OTGEN[2] (RW)
912 * - 0 - If USB_EN is 1 and HOST_MODE is 0 in the Control Register (CTL), then
913 * the D+ Data Line pull-up resistors are enabled. If HOST_MODE is 1 the D+
914 * and D- Data Line pull-down resistors are engaged.
915 * - 1 - The pull-up and pull-down controls in this register are used.
918 #define BP_USB_OTGCTL_OTGEN (2U) /*!< Bit position for USB_OTGCTL_OTGEN. */
919 #define BM_USB_OTGCTL_OTGEN (0x04U) /*!< Bit mask for USB_OTGCTL_OTGEN. */
920 #define BS_USB_OTGCTL_OTGEN (1U) /*!< Bit field size in bits for USB_OTGCTL_OTGEN. */
922 /*! @brief Read current value of the USB_OTGCTL_OTGEN field. */
923 #define BR_USB_OTGCTL_OTGEN(x) (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR(x), BP_USB_OTGCTL_OTGEN))
925 /*! @brief Format value for bitfield USB_OTGCTL_OTGEN. */
926 #define BF_USB_OTGCTL_OTGEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGCTL_OTGEN) & BM_USB_OTGCTL_OTGEN)
928 /*! @brief Set the OTGEN field to a new value. */
929 #define BW_USB_OTGCTL_OTGEN(x, v) (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR(x), BP_USB_OTGCTL_OTGEN) = (v))
933 * @name Register USB_OTGCTL, field DMLOW[4] (RW)
936 * - 0 - D- pulldown resistor is not enabled.
937 * - 1 - D- pulldown resistor is enabled.
940 #define BP_USB_OTGCTL_DMLOW (4U) /*!< Bit position for USB_OTGCTL_DMLOW. */
941 #define BM_USB_OTGCTL_DMLOW (0x10U) /*!< Bit mask for USB_OTGCTL_DMLOW. */
942 #define BS_USB_OTGCTL_DMLOW (1U) /*!< Bit field size in bits for USB_OTGCTL_DMLOW. */
944 /*! @brief Read current value of the USB_OTGCTL_DMLOW field. */
945 #define BR_USB_OTGCTL_DMLOW(x) (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR(x), BP_USB_OTGCTL_DMLOW))
947 /*! @brief Format value for bitfield USB_OTGCTL_DMLOW. */
948 #define BF_USB_OTGCTL_DMLOW(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGCTL_DMLOW) & BM_USB_OTGCTL_DMLOW)
950 /*! @brief Set the DMLOW field to a new value. */
951 #define BW_USB_OTGCTL_DMLOW(x, v) (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR(x), BP_USB_OTGCTL_DMLOW) = (v))
955 * @name Register USB_OTGCTL, field DPLOW[5] (RW)
957 * This bit should always be enabled together with bit 4 (DMLOW)
960 * - 0 - D+ pulldown resistor is not enabled.
961 * - 1 - D+ pulldown resistor is enabled.
964 #define BP_USB_OTGCTL_DPLOW (5U) /*!< Bit position for USB_OTGCTL_DPLOW. */
965 #define BM_USB_OTGCTL_DPLOW (0x20U) /*!< Bit mask for USB_OTGCTL_DPLOW. */
966 #define BS_USB_OTGCTL_DPLOW (1U) /*!< Bit field size in bits for USB_OTGCTL_DPLOW. */
968 /*! @brief Read current value of the USB_OTGCTL_DPLOW field. */
969 #define BR_USB_OTGCTL_DPLOW(x) (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR(x), BP_USB_OTGCTL_DPLOW))
971 /*! @brief Format value for bitfield USB_OTGCTL_DPLOW. */
972 #define BF_USB_OTGCTL_DPLOW(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGCTL_DPLOW) & BM_USB_OTGCTL_DPLOW)
974 /*! @brief Set the DPLOW field to a new value. */
975 #define BW_USB_OTGCTL_DPLOW(x, v) (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR(x), BP_USB_OTGCTL_DPLOW) = (v))
979 * @name Register USB_OTGCTL, field DPHIGH[7] (RW)
982 * - 0 - D+ pullup resistor is not enabled
983 * - 1 - D+ pullup resistor is enabled
986 #define BP_USB_OTGCTL_DPHIGH (7U) /*!< Bit position for USB_OTGCTL_DPHIGH. */
987 #define BM_USB_OTGCTL_DPHIGH (0x80U) /*!< Bit mask for USB_OTGCTL_DPHIGH. */
988 #define BS_USB_OTGCTL_DPHIGH (1U) /*!< Bit field size in bits for USB_OTGCTL_DPHIGH. */
990 /*! @brief Read current value of the USB_OTGCTL_DPHIGH field. */
991 #define BR_USB_OTGCTL_DPHIGH(x) (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR(x), BP_USB_OTGCTL_DPHIGH))
993 /*! @brief Format value for bitfield USB_OTGCTL_DPHIGH. */
994 #define BF_USB_OTGCTL_DPHIGH(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGCTL_DPHIGH) & BM_USB_OTGCTL_DPHIGH)
996 /*! @brief Set the DPHIGH field to a new value. */
997 #define BW_USB_OTGCTL_DPHIGH(x, v) (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR(x), BP_USB_OTGCTL_DPHIGH) = (v))
1000 /*******************************************************************************
1001 * HW_USB_ISTAT - Interrupt Status register
1002 ******************************************************************************/
1005 * @brief HW_USB_ISTAT - Interrupt Status register (W1C)
1007 * Reset value: 0x00U
1009 * Contains fields for each of the interrupt sources within the USB Module. Each
1010 * of these fields are qualified with their respective interrupt enable bits.
1011 * All fields of this register are logically OR'd together along with the OTG
1012 * Interrupt Status Register (OTGSTAT) to form a single interrupt source for the
1013 * processor's interrupt controller. After an interrupt bit has been set it may only
1014 * be cleared by writing a one to the respective interrupt bit. This register
1015 * contains the value of 0x00 after a reset.
1017 typedef union _hw_usb_istat
1020 struct _hw_usb_istat_bitfields
1022 uint8_t USBRST
: 1; /*!< [0] */
1023 uint8_t ERROR
: 1; /*!< [1] */
1024 uint8_t SOFTOK
: 1; /*!< [2] */
1025 uint8_t TOKDNE
: 1; /*!< [3] */
1026 uint8_t SLEEP
: 1; /*!< [4] */
1027 uint8_t RESUME
: 1; /*!< [5] */
1028 uint8_t ATTACH
: 1; /*!< [6] Attach Interrupt */
1029 uint8_t STALL
: 1; /*!< [7] Stall Interrupt */
1034 * @name Constants and macros for entire USB_ISTAT register
1037 #define HW_USB_ISTAT_ADDR(x) ((x) + 0x80U)
1039 #define HW_USB_ISTAT(x) (*(__IO hw_usb_istat_t *) HW_USB_ISTAT_ADDR(x))
1040 #define HW_USB_ISTAT_RD(x) (HW_USB_ISTAT(x).U)
1041 #define HW_USB_ISTAT_WR(x, v) (HW_USB_ISTAT(x).U = (v))
1042 #define HW_USB_ISTAT_SET(x, v) (HW_USB_ISTAT_WR(x, HW_USB_ISTAT_RD(x) | (v)))
1043 #define HW_USB_ISTAT_CLR(x, v) (HW_USB_ISTAT_WR(x, HW_USB_ISTAT_RD(x) & ~(v)))
1044 #define HW_USB_ISTAT_TOG(x, v) (HW_USB_ISTAT_WR(x, HW_USB_ISTAT_RD(x) ^ (v)))
1048 * Constants & macros for individual USB_ISTAT bitfields
1052 * @name Register USB_ISTAT, field USBRST[0] (W1C)
1054 * This bit is set when the USB Module has decoded a valid USB reset. This
1055 * informs the processor that it should write 0x00 into the address register and
1056 * enable endpoint 0. USBRST is set after a USB reset has been detected for 2.5
1057 * microseconds. It is not asserted again until the USB reset condition has been
1058 * removed and then reasserted.
1061 #define BP_USB_ISTAT_USBRST (0U) /*!< Bit position for USB_ISTAT_USBRST. */
1062 #define BM_USB_ISTAT_USBRST (0x01U) /*!< Bit mask for USB_ISTAT_USBRST. */
1063 #define BS_USB_ISTAT_USBRST (1U) /*!< Bit field size in bits for USB_ISTAT_USBRST. */
1065 /*! @brief Read current value of the USB_ISTAT_USBRST field. */
1066 #define BR_USB_ISTAT_USBRST(x) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_USBRST))
1068 /*! @brief Format value for bitfield USB_ISTAT_USBRST. */
1069 #define BF_USB_ISTAT_USBRST(v) ((uint8_t)((uint8_t)(v) << BP_USB_ISTAT_USBRST) & BM_USB_ISTAT_USBRST)
1071 /*! @brief Set the USBRST field to a new value. */
1072 #define BW_USB_ISTAT_USBRST(x, v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_USBRST) = (v))
1076 * @name Register USB_ISTAT, field ERROR[1] (W1C)
1078 * This bit is set when any of the error conditions within Error Interrupt
1079 * Status (ERRSTAT) register occur. The processor must then read the ERRSTAT register
1080 * to determine the source of the error.
1083 #define BP_USB_ISTAT_ERROR (1U) /*!< Bit position for USB_ISTAT_ERROR. */
1084 #define BM_USB_ISTAT_ERROR (0x02U) /*!< Bit mask for USB_ISTAT_ERROR. */
1085 #define BS_USB_ISTAT_ERROR (1U) /*!< Bit field size in bits for USB_ISTAT_ERROR. */
1087 /*! @brief Read current value of the USB_ISTAT_ERROR field. */
1088 #define BR_USB_ISTAT_ERROR(x) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_ERROR))
1090 /*! @brief Format value for bitfield USB_ISTAT_ERROR. */
1091 #define BF_USB_ISTAT_ERROR(v) ((uint8_t)((uint8_t)(v) << BP_USB_ISTAT_ERROR) & BM_USB_ISTAT_ERROR)
1093 /*! @brief Set the ERROR field to a new value. */
1094 #define BW_USB_ISTAT_ERROR(x, v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_ERROR) = (v))
1098 * @name Register USB_ISTAT, field SOFTOK[2] (W1C)
1100 * This bit is set when the USB Module receives a Start Of Frame (SOF) token. In
1101 * Host mode this field is set when the SOF threshold is reached, so that
1102 * software can prepare for the next SOF.
1105 #define BP_USB_ISTAT_SOFTOK (2U) /*!< Bit position for USB_ISTAT_SOFTOK. */
1106 #define BM_USB_ISTAT_SOFTOK (0x04U) /*!< Bit mask for USB_ISTAT_SOFTOK. */
1107 #define BS_USB_ISTAT_SOFTOK (1U) /*!< Bit field size in bits for USB_ISTAT_SOFTOK. */
1109 /*! @brief Read current value of the USB_ISTAT_SOFTOK field. */
1110 #define BR_USB_ISTAT_SOFTOK(x) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_SOFTOK))
1112 /*! @brief Format value for bitfield USB_ISTAT_SOFTOK. */
1113 #define BF_USB_ISTAT_SOFTOK(v) ((uint8_t)((uint8_t)(v) << BP_USB_ISTAT_SOFTOK) & BM_USB_ISTAT_SOFTOK)
1115 /*! @brief Set the SOFTOK field to a new value. */
1116 #define BW_USB_ISTAT_SOFTOK(x, v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_SOFTOK) = (v))
1120 * @name Register USB_ISTAT, field TOKDNE[3] (W1C)
1122 * This bit is set when the current token being processed has completed. The
1123 * processor must immediately read the STATUS (STAT) register to determine the
1124 * EndPoint and BD used for this token. Clearing this bit (by writing a one) causes
1125 * STAT to be cleared or the STAT holding register to be loaded into the STAT
1129 #define BP_USB_ISTAT_TOKDNE (3U) /*!< Bit position for USB_ISTAT_TOKDNE. */
1130 #define BM_USB_ISTAT_TOKDNE (0x08U) /*!< Bit mask for USB_ISTAT_TOKDNE. */
1131 #define BS_USB_ISTAT_TOKDNE (1U) /*!< Bit field size in bits for USB_ISTAT_TOKDNE. */
1133 /*! @brief Read current value of the USB_ISTAT_TOKDNE field. */
1134 #define BR_USB_ISTAT_TOKDNE(x) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_TOKDNE))
1136 /*! @brief Format value for bitfield USB_ISTAT_TOKDNE. */
1137 #define BF_USB_ISTAT_TOKDNE(v) ((uint8_t)((uint8_t)(v) << BP_USB_ISTAT_TOKDNE) & BM_USB_ISTAT_TOKDNE)
1139 /*! @brief Set the TOKDNE field to a new value. */
1140 #define BW_USB_ISTAT_TOKDNE(x, v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_TOKDNE) = (v))
1144 * @name Register USB_ISTAT, field SLEEP[4] (W1C)
1146 * This bit is set when the USB Module detects a constant idle on the USB bus
1147 * for 3 ms. The sleep timer is reset by activity on the USB bus.
1150 #define BP_USB_ISTAT_SLEEP (4U) /*!< Bit position for USB_ISTAT_SLEEP. */
1151 #define BM_USB_ISTAT_SLEEP (0x10U) /*!< Bit mask for USB_ISTAT_SLEEP. */
1152 #define BS_USB_ISTAT_SLEEP (1U) /*!< Bit field size in bits for USB_ISTAT_SLEEP. */
1154 /*! @brief Read current value of the USB_ISTAT_SLEEP field. */
1155 #define BR_USB_ISTAT_SLEEP(x) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_SLEEP))
1157 /*! @brief Format value for bitfield USB_ISTAT_SLEEP. */
1158 #define BF_USB_ISTAT_SLEEP(v) ((uint8_t)((uint8_t)(v) << BP_USB_ISTAT_SLEEP) & BM_USB_ISTAT_SLEEP)
1160 /*! @brief Set the SLEEP field to a new value. */
1161 #define BW_USB_ISTAT_SLEEP(x, v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_SLEEP) = (v))
1165 * @name Register USB_ISTAT, field RESUME[5] (W1C)
1167 * This bit is set when a K-state is observed on the DP/DM signals for 2.5 us.
1168 * When not in suspend mode this interrupt must be disabled.
1171 #define BP_USB_ISTAT_RESUME (5U) /*!< Bit position for USB_ISTAT_RESUME. */
1172 #define BM_USB_ISTAT_RESUME (0x20U) /*!< Bit mask for USB_ISTAT_RESUME. */
1173 #define BS_USB_ISTAT_RESUME (1U) /*!< Bit field size in bits for USB_ISTAT_RESUME. */
1175 /*! @brief Read current value of the USB_ISTAT_RESUME field. */
1176 #define BR_USB_ISTAT_RESUME(x) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_RESUME))
1178 /*! @brief Format value for bitfield USB_ISTAT_RESUME. */
1179 #define BF_USB_ISTAT_RESUME(v) ((uint8_t)((uint8_t)(v) << BP_USB_ISTAT_RESUME) & BM_USB_ISTAT_RESUME)
1181 /*! @brief Set the RESUME field to a new value. */
1182 #define BW_USB_ISTAT_RESUME(x, v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_RESUME) = (v))
1186 * @name Register USB_ISTAT, field ATTACH[6] (W1C)
1188 * This bit is set when the USB Module detects an attach of a USB device. This
1189 * signal is only valid if HOSTMODEEN is true. This interrupt signifies that a
1190 * peripheral is now present and must be configured; it is asserted if there have
1191 * been no transitions on the USB for 2.5 us and the current bus state is not SE0."
1194 #define BP_USB_ISTAT_ATTACH (6U) /*!< Bit position for USB_ISTAT_ATTACH. */
1195 #define BM_USB_ISTAT_ATTACH (0x40U) /*!< Bit mask for USB_ISTAT_ATTACH. */
1196 #define BS_USB_ISTAT_ATTACH (1U) /*!< Bit field size in bits for USB_ISTAT_ATTACH. */
1198 /*! @brief Read current value of the USB_ISTAT_ATTACH field. */
1199 #define BR_USB_ISTAT_ATTACH(x) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_ATTACH))
1201 /*! @brief Format value for bitfield USB_ISTAT_ATTACH. */
1202 #define BF_USB_ISTAT_ATTACH(v) ((uint8_t)((uint8_t)(v) << BP_USB_ISTAT_ATTACH) & BM_USB_ISTAT_ATTACH)
1204 /*! @brief Set the ATTACH field to a new value. */
1205 #define BW_USB_ISTAT_ATTACH(x, v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_ATTACH) = (v))
1209 * @name Register USB_ISTAT, field STALL[7] (W1C)
1211 * In Target mode this bit is asserted when a STALL handshake is sent by the
1212 * SIE. In Host mode this bit is set when the USB Module detects a STALL acknowledge
1213 * during the handshake phase of a USB transaction.This interrupt can be used to
1214 * determine whether the last USB transaction was completed successfully or
1218 #define BP_USB_ISTAT_STALL (7U) /*!< Bit position for USB_ISTAT_STALL. */
1219 #define BM_USB_ISTAT_STALL (0x80U) /*!< Bit mask for USB_ISTAT_STALL. */
1220 #define BS_USB_ISTAT_STALL (1U) /*!< Bit field size in bits for USB_ISTAT_STALL. */
1222 /*! @brief Read current value of the USB_ISTAT_STALL field. */
1223 #define BR_USB_ISTAT_STALL(x) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_STALL))
1225 /*! @brief Format value for bitfield USB_ISTAT_STALL. */
1226 #define BF_USB_ISTAT_STALL(v) ((uint8_t)((uint8_t)(v) << BP_USB_ISTAT_STALL) & BM_USB_ISTAT_STALL)
1228 /*! @brief Set the STALL field to a new value. */
1229 #define BW_USB_ISTAT_STALL(x, v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_STALL) = (v))
1232 /*******************************************************************************
1233 * HW_USB_INTEN - Interrupt Enable register
1234 ******************************************************************************/
1237 * @brief HW_USB_INTEN - Interrupt Enable register (RW)
1239 * Reset value: 0x00U
1241 * Contains enable fields for each of the interrupt sources within the USB
1242 * Module. Setting any of these bits enables the respective interrupt source in the
1243 * ISTAT register. This register contains the value of 0x00 after a reset.
1245 typedef union _hw_usb_inten
1248 struct _hw_usb_inten_bitfields
1250 uint8_t USBRSTEN
: 1; /*!< [0] USBRST Interrupt Enable */
1251 uint8_t ERROREN
: 1; /*!< [1] ERROR Interrupt Enable */
1252 uint8_t SOFTOKEN
: 1; /*!< [2] SOFTOK Interrupt Enable */
1253 uint8_t TOKDNEEN
: 1; /*!< [3] TOKDNE Interrupt Enable */
1254 uint8_t SLEEPEN
: 1; /*!< [4] SLEEP Interrupt Enable */
1255 uint8_t RESUMEEN
: 1; /*!< [5] RESUME Interrupt Enable */
1256 uint8_t ATTACHEN
: 1; /*!< [6] ATTACH Interrupt Enable */
1257 uint8_t STALLEN
: 1; /*!< [7] STALL Interrupt Enable */
1262 * @name Constants and macros for entire USB_INTEN register
1265 #define HW_USB_INTEN_ADDR(x) ((x) + 0x84U)
1267 #define HW_USB_INTEN(x) (*(__IO hw_usb_inten_t *) HW_USB_INTEN_ADDR(x))
1268 #define HW_USB_INTEN_RD(x) (HW_USB_INTEN(x).U)
1269 #define HW_USB_INTEN_WR(x, v) (HW_USB_INTEN(x).U = (v))
1270 #define HW_USB_INTEN_SET(x, v) (HW_USB_INTEN_WR(x, HW_USB_INTEN_RD(x) | (v)))
1271 #define HW_USB_INTEN_CLR(x, v) (HW_USB_INTEN_WR(x, HW_USB_INTEN_RD(x) & ~(v)))
1272 #define HW_USB_INTEN_TOG(x, v) (HW_USB_INTEN_WR(x, HW_USB_INTEN_RD(x) ^ (v)))
1276 * Constants & macros for individual USB_INTEN bitfields
1280 * @name Register USB_INTEN, field USBRSTEN[0] (RW)
1283 * - 0 - Disables the USBRST interrupt.
1284 * - 1 - Enables the USBRST interrupt.
1287 #define BP_USB_INTEN_USBRSTEN (0U) /*!< Bit position for USB_INTEN_USBRSTEN. */
1288 #define BM_USB_INTEN_USBRSTEN (0x01U) /*!< Bit mask for USB_INTEN_USBRSTEN. */
1289 #define BS_USB_INTEN_USBRSTEN (1U) /*!< Bit field size in bits for USB_INTEN_USBRSTEN. */
1291 /*! @brief Read current value of the USB_INTEN_USBRSTEN field. */
1292 #define BR_USB_INTEN_USBRSTEN(x) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_USBRSTEN))
1294 /*! @brief Format value for bitfield USB_INTEN_USBRSTEN. */
1295 #define BF_USB_INTEN_USBRSTEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_INTEN_USBRSTEN) & BM_USB_INTEN_USBRSTEN)
1297 /*! @brief Set the USBRSTEN field to a new value. */
1298 #define BW_USB_INTEN_USBRSTEN(x, v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_USBRSTEN) = (v))
1302 * @name Register USB_INTEN, field ERROREN[1] (RW)
1305 * - 0 - Disables the ERROR interrupt.
1306 * - 1 - Enables the ERROR interrupt.
1309 #define BP_USB_INTEN_ERROREN (1U) /*!< Bit position for USB_INTEN_ERROREN. */
1310 #define BM_USB_INTEN_ERROREN (0x02U) /*!< Bit mask for USB_INTEN_ERROREN. */
1311 #define BS_USB_INTEN_ERROREN (1U) /*!< Bit field size in bits for USB_INTEN_ERROREN. */
1313 /*! @brief Read current value of the USB_INTEN_ERROREN field. */
1314 #define BR_USB_INTEN_ERROREN(x) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_ERROREN))
1316 /*! @brief Format value for bitfield USB_INTEN_ERROREN. */
1317 #define BF_USB_INTEN_ERROREN(v) ((uint8_t)((uint8_t)(v) << BP_USB_INTEN_ERROREN) & BM_USB_INTEN_ERROREN)
1319 /*! @brief Set the ERROREN field to a new value. */
1320 #define BW_USB_INTEN_ERROREN(x, v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_ERROREN) = (v))
1324 * @name Register USB_INTEN, field SOFTOKEN[2] (RW)
1327 * - 0 - Disbles the SOFTOK interrupt.
1328 * - 1 - Enables the SOFTOK interrupt.
1331 #define BP_USB_INTEN_SOFTOKEN (2U) /*!< Bit position for USB_INTEN_SOFTOKEN. */
1332 #define BM_USB_INTEN_SOFTOKEN (0x04U) /*!< Bit mask for USB_INTEN_SOFTOKEN. */
1333 #define BS_USB_INTEN_SOFTOKEN (1U) /*!< Bit field size in bits for USB_INTEN_SOFTOKEN. */
1335 /*! @brief Read current value of the USB_INTEN_SOFTOKEN field. */
1336 #define BR_USB_INTEN_SOFTOKEN(x) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_SOFTOKEN))
1338 /*! @brief Format value for bitfield USB_INTEN_SOFTOKEN. */
1339 #define BF_USB_INTEN_SOFTOKEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_INTEN_SOFTOKEN) & BM_USB_INTEN_SOFTOKEN)
1341 /*! @brief Set the SOFTOKEN field to a new value. */
1342 #define BW_USB_INTEN_SOFTOKEN(x, v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_SOFTOKEN) = (v))
1346 * @name Register USB_INTEN, field TOKDNEEN[3] (RW)
1349 * - 0 - Disables the TOKDNE interrupt.
1350 * - 1 - Enables the TOKDNE interrupt.
1353 #define BP_USB_INTEN_TOKDNEEN (3U) /*!< Bit position for USB_INTEN_TOKDNEEN. */
1354 #define BM_USB_INTEN_TOKDNEEN (0x08U) /*!< Bit mask for USB_INTEN_TOKDNEEN. */
1355 #define BS_USB_INTEN_TOKDNEEN (1U) /*!< Bit field size in bits for USB_INTEN_TOKDNEEN. */
1357 /*! @brief Read current value of the USB_INTEN_TOKDNEEN field. */
1358 #define BR_USB_INTEN_TOKDNEEN(x) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_TOKDNEEN))
1360 /*! @brief Format value for bitfield USB_INTEN_TOKDNEEN. */
1361 #define BF_USB_INTEN_TOKDNEEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_INTEN_TOKDNEEN) & BM_USB_INTEN_TOKDNEEN)
1363 /*! @brief Set the TOKDNEEN field to a new value. */
1364 #define BW_USB_INTEN_TOKDNEEN(x, v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_TOKDNEEN) = (v))
1368 * @name Register USB_INTEN, field SLEEPEN[4] (RW)
1371 * - 0 - Disables the SLEEP interrupt.
1372 * - 1 - Enables the SLEEP interrupt.
1375 #define BP_USB_INTEN_SLEEPEN (4U) /*!< Bit position for USB_INTEN_SLEEPEN. */
1376 #define BM_USB_INTEN_SLEEPEN (0x10U) /*!< Bit mask for USB_INTEN_SLEEPEN. */
1377 #define BS_USB_INTEN_SLEEPEN (1U) /*!< Bit field size in bits for USB_INTEN_SLEEPEN. */
1379 /*! @brief Read current value of the USB_INTEN_SLEEPEN field. */
1380 #define BR_USB_INTEN_SLEEPEN(x) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_SLEEPEN))
1382 /*! @brief Format value for bitfield USB_INTEN_SLEEPEN. */
1383 #define BF_USB_INTEN_SLEEPEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_INTEN_SLEEPEN) & BM_USB_INTEN_SLEEPEN)
1385 /*! @brief Set the SLEEPEN field to a new value. */
1386 #define BW_USB_INTEN_SLEEPEN(x, v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_SLEEPEN) = (v))
1390 * @name Register USB_INTEN, field RESUMEEN[5] (RW)
1393 * - 0 - Disables the RESUME interrupt.
1394 * - 1 - Enables the RESUME interrupt.
1397 #define BP_USB_INTEN_RESUMEEN (5U) /*!< Bit position for USB_INTEN_RESUMEEN. */
1398 #define BM_USB_INTEN_RESUMEEN (0x20U) /*!< Bit mask for USB_INTEN_RESUMEEN. */
1399 #define BS_USB_INTEN_RESUMEEN (1U) /*!< Bit field size in bits for USB_INTEN_RESUMEEN. */
1401 /*! @brief Read current value of the USB_INTEN_RESUMEEN field. */
1402 #define BR_USB_INTEN_RESUMEEN(x) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_RESUMEEN))
1404 /*! @brief Format value for bitfield USB_INTEN_RESUMEEN. */
1405 #define BF_USB_INTEN_RESUMEEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_INTEN_RESUMEEN) & BM_USB_INTEN_RESUMEEN)
1407 /*! @brief Set the RESUMEEN field to a new value. */
1408 #define BW_USB_INTEN_RESUMEEN(x, v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_RESUMEEN) = (v))
1412 * @name Register USB_INTEN, field ATTACHEN[6] (RW)
1415 * - 0 - Disables the ATTACH interrupt.
1416 * - 1 - Enables the ATTACH interrupt.
1419 #define BP_USB_INTEN_ATTACHEN (6U) /*!< Bit position for USB_INTEN_ATTACHEN. */
1420 #define BM_USB_INTEN_ATTACHEN (0x40U) /*!< Bit mask for USB_INTEN_ATTACHEN. */
1421 #define BS_USB_INTEN_ATTACHEN (1U) /*!< Bit field size in bits for USB_INTEN_ATTACHEN. */
1423 /*! @brief Read current value of the USB_INTEN_ATTACHEN field. */
1424 #define BR_USB_INTEN_ATTACHEN(x) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_ATTACHEN))
1426 /*! @brief Format value for bitfield USB_INTEN_ATTACHEN. */
1427 #define BF_USB_INTEN_ATTACHEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_INTEN_ATTACHEN) & BM_USB_INTEN_ATTACHEN)
1429 /*! @brief Set the ATTACHEN field to a new value. */
1430 #define BW_USB_INTEN_ATTACHEN(x, v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_ATTACHEN) = (v))
1434 * @name Register USB_INTEN, field STALLEN[7] (RW)
1437 * - 0 - Diasbles the STALL interrupt.
1438 * - 1 - Enables the STALL interrupt.
1441 #define BP_USB_INTEN_STALLEN (7U) /*!< Bit position for USB_INTEN_STALLEN. */
1442 #define BM_USB_INTEN_STALLEN (0x80U) /*!< Bit mask for USB_INTEN_STALLEN. */
1443 #define BS_USB_INTEN_STALLEN (1U) /*!< Bit field size in bits for USB_INTEN_STALLEN. */
1445 /*! @brief Read current value of the USB_INTEN_STALLEN field. */
1446 #define BR_USB_INTEN_STALLEN(x) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_STALLEN))
1448 /*! @brief Format value for bitfield USB_INTEN_STALLEN. */
1449 #define BF_USB_INTEN_STALLEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_INTEN_STALLEN) & BM_USB_INTEN_STALLEN)
1451 /*! @brief Set the STALLEN field to a new value. */
1452 #define BW_USB_INTEN_STALLEN(x, v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_STALLEN) = (v))
1455 /*******************************************************************************
1456 * HW_USB_ERRSTAT - Error Interrupt Status register
1457 ******************************************************************************/
1460 * @brief HW_USB_ERRSTAT - Error Interrupt Status register (RW)
1462 * Reset value: 0x00U
1464 * Contains enable bits for each of the error sources within the USB Module.
1465 * Each of these bits are qualified with their respective error enable bits. All
1466 * bits of this register are logically OR'd together and the result placed in the
1467 * ERROR bit of the ISTAT register. After an interrupt bit has been set it may only
1468 * be cleared by writing a one to the respective interrupt bit. Each bit is set
1469 * as soon as the error condition is detected. Therefore, the interrupt does not
1470 * typically correspond with the end of a token being processed. This register
1471 * contains the value of 0x00 after a reset.
1473 typedef union _hw_usb_errstat
1476 struct _hw_usb_errstat_bitfields
1478 uint8_t PIDERR
: 1; /*!< [0] */
1479 uint8_t CRC5EOF
: 1; /*!< [1] */
1480 uint8_t CRC16
: 1; /*!< [2] */
1481 uint8_t DFN8
: 1; /*!< [3] */
1482 uint8_t BTOERR
: 1; /*!< [4] */
1483 uint8_t DMAERR
: 1; /*!< [5] */
1484 uint8_t RESERVED0
: 1; /*!< [6] */
1485 uint8_t BTSERR
: 1; /*!< [7] */
1490 * @name Constants and macros for entire USB_ERRSTAT register
1493 #define HW_USB_ERRSTAT_ADDR(x) ((x) + 0x88U)
1495 #define HW_USB_ERRSTAT(x) (*(__IO hw_usb_errstat_t *) HW_USB_ERRSTAT_ADDR(x))
1496 #define HW_USB_ERRSTAT_RD(x) (HW_USB_ERRSTAT(x).U)
1497 #define HW_USB_ERRSTAT_WR(x, v) (HW_USB_ERRSTAT(x).U = (v))
1498 #define HW_USB_ERRSTAT_SET(x, v) (HW_USB_ERRSTAT_WR(x, HW_USB_ERRSTAT_RD(x) | (v)))
1499 #define HW_USB_ERRSTAT_CLR(x, v) (HW_USB_ERRSTAT_WR(x, HW_USB_ERRSTAT_RD(x) & ~(v)))
1500 #define HW_USB_ERRSTAT_TOG(x, v) (HW_USB_ERRSTAT_WR(x, HW_USB_ERRSTAT_RD(x) ^ (v)))
1504 * Constants & macros for individual USB_ERRSTAT bitfields
1508 * @name Register USB_ERRSTAT, field PIDERR[0] (W1C)
1510 * This bit is set when the PID check field fails.
1513 #define BP_USB_ERRSTAT_PIDERR (0U) /*!< Bit position for USB_ERRSTAT_PIDERR. */
1514 #define BM_USB_ERRSTAT_PIDERR (0x01U) /*!< Bit mask for USB_ERRSTAT_PIDERR. */
1515 #define BS_USB_ERRSTAT_PIDERR (1U) /*!< Bit field size in bits for USB_ERRSTAT_PIDERR. */
1517 /*! @brief Read current value of the USB_ERRSTAT_PIDERR field. */
1518 #define BR_USB_ERRSTAT_PIDERR(x) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_PIDERR))
1520 /*! @brief Format value for bitfield USB_ERRSTAT_PIDERR. */
1521 #define BF_USB_ERRSTAT_PIDERR(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERRSTAT_PIDERR) & BM_USB_ERRSTAT_PIDERR)
1523 /*! @brief Set the PIDERR field to a new value. */
1524 #define BW_USB_ERRSTAT_PIDERR(x, v) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_PIDERR) = (v))
1528 * @name Register USB_ERRSTAT, field CRC5EOF[1] (W1C)
1530 * This error interrupt has two functions. When the USB Module is operating in
1531 * peripheral mode (HOSTMODEEN=0), this interrupt detects CRC5 errors in the token
1532 * packets generated by the host. If set the token packet was rejected due to a
1533 * CRC5 error. When the USB Module is operating in host mode (HOSTMODEEN=1), this
1534 * interrupt detects End Of Frame (EOF) error conditions. This occurs when the
1535 * USB Module is transmitting or receiving data and the SOF counter reaches zero.
1536 * This interrupt is useful when developing USB packet scheduling software to
1537 * ensure that no USB transactions cross the start of the next frame.
1540 #define BP_USB_ERRSTAT_CRC5EOF (1U) /*!< Bit position for USB_ERRSTAT_CRC5EOF. */
1541 #define BM_USB_ERRSTAT_CRC5EOF (0x02U) /*!< Bit mask for USB_ERRSTAT_CRC5EOF. */
1542 #define BS_USB_ERRSTAT_CRC5EOF (1U) /*!< Bit field size in bits for USB_ERRSTAT_CRC5EOF. */
1544 /*! @brief Read current value of the USB_ERRSTAT_CRC5EOF field. */
1545 #define BR_USB_ERRSTAT_CRC5EOF(x) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_CRC5EOF))
1547 /*! @brief Format value for bitfield USB_ERRSTAT_CRC5EOF. */
1548 #define BF_USB_ERRSTAT_CRC5EOF(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERRSTAT_CRC5EOF) & BM_USB_ERRSTAT_CRC5EOF)
1550 /*! @brief Set the CRC5EOF field to a new value. */
1551 #define BW_USB_ERRSTAT_CRC5EOF(x, v) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_CRC5EOF) = (v))
1555 * @name Register USB_ERRSTAT, field CRC16[2] (W1C)
1557 * This bit is set when a data packet is rejected due to a CRC16 error.
1560 #define BP_USB_ERRSTAT_CRC16 (2U) /*!< Bit position for USB_ERRSTAT_CRC16. */
1561 #define BM_USB_ERRSTAT_CRC16 (0x04U) /*!< Bit mask for USB_ERRSTAT_CRC16. */
1562 #define BS_USB_ERRSTAT_CRC16 (1U) /*!< Bit field size in bits for USB_ERRSTAT_CRC16. */
1564 /*! @brief Read current value of the USB_ERRSTAT_CRC16 field. */
1565 #define BR_USB_ERRSTAT_CRC16(x) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_CRC16))
1567 /*! @brief Format value for bitfield USB_ERRSTAT_CRC16. */
1568 #define BF_USB_ERRSTAT_CRC16(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERRSTAT_CRC16) & BM_USB_ERRSTAT_CRC16)
1570 /*! @brief Set the CRC16 field to a new value. */
1571 #define BW_USB_ERRSTAT_CRC16(x, v) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_CRC16) = (v))
1575 * @name Register USB_ERRSTAT, field DFN8[3] (W1C)
1577 * This bit is set if the data field received was not 8 bits in length. USB
1578 * Specification 1.0 requires that data fields be an integral number of bytes. If the
1579 * data field was not an integral number of bytes, this bit is set.
1582 #define BP_USB_ERRSTAT_DFN8 (3U) /*!< Bit position for USB_ERRSTAT_DFN8. */
1583 #define BM_USB_ERRSTAT_DFN8 (0x08U) /*!< Bit mask for USB_ERRSTAT_DFN8. */
1584 #define BS_USB_ERRSTAT_DFN8 (1U) /*!< Bit field size in bits for USB_ERRSTAT_DFN8. */
1586 /*! @brief Read current value of the USB_ERRSTAT_DFN8 field. */
1587 #define BR_USB_ERRSTAT_DFN8(x) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_DFN8))
1589 /*! @brief Format value for bitfield USB_ERRSTAT_DFN8. */
1590 #define BF_USB_ERRSTAT_DFN8(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERRSTAT_DFN8) & BM_USB_ERRSTAT_DFN8)
1592 /*! @brief Set the DFN8 field to a new value. */
1593 #define BW_USB_ERRSTAT_DFN8(x, v) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_DFN8) = (v))
1597 * @name Register USB_ERRSTAT, field BTOERR[4] (W1C)
1599 * This bit is set when a bus turnaround timeout error occurs. The USB module
1600 * contains a bus turnaround timer that keeps track of the amount of time elapsed
1601 * between the token and data phases of a SETUP or OUT TOKEN or the data and
1602 * handshake phases of a IN TOKEN. If more than 16 bit times are counted from the
1603 * previous EOP before a transition from IDLE, a bus turnaround timeout error occurs.
1606 #define BP_USB_ERRSTAT_BTOERR (4U) /*!< Bit position for USB_ERRSTAT_BTOERR. */
1607 #define BM_USB_ERRSTAT_BTOERR (0x10U) /*!< Bit mask for USB_ERRSTAT_BTOERR. */
1608 #define BS_USB_ERRSTAT_BTOERR (1U) /*!< Bit field size in bits for USB_ERRSTAT_BTOERR. */
1610 /*! @brief Read current value of the USB_ERRSTAT_BTOERR field. */
1611 #define BR_USB_ERRSTAT_BTOERR(x) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_BTOERR))
1613 /*! @brief Format value for bitfield USB_ERRSTAT_BTOERR. */
1614 #define BF_USB_ERRSTAT_BTOERR(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERRSTAT_BTOERR) & BM_USB_ERRSTAT_BTOERR)
1616 /*! @brief Set the BTOERR field to a new value. */
1617 #define BW_USB_ERRSTAT_BTOERR(x, v) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_BTOERR) = (v))
1621 * @name Register USB_ERRSTAT, field DMAERR[5] (W1C)
1623 * This bit is set if the USB Module has requested a DMA access to read a new
1624 * BDT but has not been given the bus before it needs to receive or transmit data.
1625 * If processing a TX transfer this would cause a transmit data underflow
1626 * condition. If processing a RX transfer this would cause a receive data overflow
1627 * condition. This interrupt is useful when developing device arbitration hardware for
1628 * the microprocessor and the USB module to minimize bus request and bus grant
1629 * latency. This bit is also set if a data packet to or from the host is larger
1630 * than the buffer size allocated in the BDT. In this case the data packet is
1631 * truncated as it is put in buffer memory.
1634 #define BP_USB_ERRSTAT_DMAERR (5U) /*!< Bit position for USB_ERRSTAT_DMAERR. */
1635 #define BM_USB_ERRSTAT_DMAERR (0x20U) /*!< Bit mask for USB_ERRSTAT_DMAERR. */
1636 #define BS_USB_ERRSTAT_DMAERR (1U) /*!< Bit field size in bits for USB_ERRSTAT_DMAERR. */
1638 /*! @brief Read current value of the USB_ERRSTAT_DMAERR field. */
1639 #define BR_USB_ERRSTAT_DMAERR(x) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_DMAERR))
1641 /*! @brief Format value for bitfield USB_ERRSTAT_DMAERR. */
1642 #define BF_USB_ERRSTAT_DMAERR(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERRSTAT_DMAERR) & BM_USB_ERRSTAT_DMAERR)
1644 /*! @brief Set the DMAERR field to a new value. */
1645 #define BW_USB_ERRSTAT_DMAERR(x, v) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_DMAERR) = (v))
1649 * @name Register USB_ERRSTAT, field BTSERR[7] (W1C)
1651 * This bit is set when a bit stuff error is detected. If set, the corresponding
1652 * packet is rejected due to the error.
1655 #define BP_USB_ERRSTAT_BTSERR (7U) /*!< Bit position for USB_ERRSTAT_BTSERR. */
1656 #define BM_USB_ERRSTAT_BTSERR (0x80U) /*!< Bit mask for USB_ERRSTAT_BTSERR. */
1657 #define BS_USB_ERRSTAT_BTSERR (1U) /*!< Bit field size in bits for USB_ERRSTAT_BTSERR. */
1659 /*! @brief Read current value of the USB_ERRSTAT_BTSERR field. */
1660 #define BR_USB_ERRSTAT_BTSERR(x) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_BTSERR))
1662 /*! @brief Format value for bitfield USB_ERRSTAT_BTSERR. */
1663 #define BF_USB_ERRSTAT_BTSERR(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERRSTAT_BTSERR) & BM_USB_ERRSTAT_BTSERR)
1665 /*! @brief Set the BTSERR field to a new value. */
1666 #define BW_USB_ERRSTAT_BTSERR(x, v) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_BTSERR) = (v))
1669 /*******************************************************************************
1670 * HW_USB_ERREN - Error Interrupt Enable register
1671 ******************************************************************************/
1674 * @brief HW_USB_ERREN - Error Interrupt Enable register (RW)
1676 * Reset value: 0x00U
1678 * Contains enable bits for each of the error interrupt sources within the USB
1679 * module. Setting any of these bits enables the respective interrupt source in
1680 * ERRSTAT. Each bit is set as soon as the error condition is detected. Therefore,
1681 * the interrupt does not typically correspond with the end of a token being
1682 * processed. This register contains the value of 0x00 after a reset.
1684 typedef union _hw_usb_erren
1687 struct _hw_usb_erren_bitfields
1689 uint8_t PIDERREN
: 1; /*!< [0] PIDERR Interrupt Enable */
1690 uint8_t CRC5EOFEN
: 1; /*!< [1] CRC5/EOF Interrupt Enable */
1691 uint8_t CRC16EN
: 1; /*!< [2] CRC16 Interrupt Enable */
1692 uint8_t DFN8EN
: 1; /*!< [3] DFN8 Interrupt Enable */
1693 uint8_t BTOERREN
: 1; /*!< [4] BTOERR Interrupt Enable */
1694 uint8_t DMAERREN
: 1; /*!< [5] DMAERR Interrupt Enable */
1695 uint8_t RESERVED0
: 1; /*!< [6] */
1696 uint8_t BTSERREN
: 1; /*!< [7] BTSERR Interrupt Enable */
1701 * @name Constants and macros for entire USB_ERREN register
1704 #define HW_USB_ERREN_ADDR(x) ((x) + 0x8CU)
1706 #define HW_USB_ERREN(x) (*(__IO hw_usb_erren_t *) HW_USB_ERREN_ADDR(x))
1707 #define HW_USB_ERREN_RD(x) (HW_USB_ERREN(x).U)
1708 #define HW_USB_ERREN_WR(x, v) (HW_USB_ERREN(x).U = (v))
1709 #define HW_USB_ERREN_SET(x, v) (HW_USB_ERREN_WR(x, HW_USB_ERREN_RD(x) | (v)))
1710 #define HW_USB_ERREN_CLR(x, v) (HW_USB_ERREN_WR(x, HW_USB_ERREN_RD(x) & ~(v)))
1711 #define HW_USB_ERREN_TOG(x, v) (HW_USB_ERREN_WR(x, HW_USB_ERREN_RD(x) ^ (v)))
1715 * Constants & macros for individual USB_ERREN bitfields
1719 * @name Register USB_ERREN, field PIDERREN[0] (RW)
1722 * - 0 - Disables the PIDERR interrupt.
1723 * - 1 - Enters the PIDERR interrupt.
1726 #define BP_USB_ERREN_PIDERREN (0U) /*!< Bit position for USB_ERREN_PIDERREN. */
1727 #define BM_USB_ERREN_PIDERREN (0x01U) /*!< Bit mask for USB_ERREN_PIDERREN. */
1728 #define BS_USB_ERREN_PIDERREN (1U) /*!< Bit field size in bits for USB_ERREN_PIDERREN. */
1730 /*! @brief Read current value of the USB_ERREN_PIDERREN field. */
1731 #define BR_USB_ERREN_PIDERREN(x) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_PIDERREN))
1733 /*! @brief Format value for bitfield USB_ERREN_PIDERREN. */
1734 #define BF_USB_ERREN_PIDERREN(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERREN_PIDERREN) & BM_USB_ERREN_PIDERREN)
1736 /*! @brief Set the PIDERREN field to a new value. */
1737 #define BW_USB_ERREN_PIDERREN(x, v) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_PIDERREN) = (v))
1741 * @name Register USB_ERREN, field CRC5EOFEN[1] (RW)
1744 * - 0 - Disables the CRC5/EOF interrupt.
1745 * - 1 - Enables the CRC5/EOF interrupt.
1748 #define BP_USB_ERREN_CRC5EOFEN (1U) /*!< Bit position for USB_ERREN_CRC5EOFEN. */
1749 #define BM_USB_ERREN_CRC5EOFEN (0x02U) /*!< Bit mask for USB_ERREN_CRC5EOFEN. */
1750 #define BS_USB_ERREN_CRC5EOFEN (1U) /*!< Bit field size in bits for USB_ERREN_CRC5EOFEN. */
1752 /*! @brief Read current value of the USB_ERREN_CRC5EOFEN field. */
1753 #define BR_USB_ERREN_CRC5EOFEN(x) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_CRC5EOFEN))
1755 /*! @brief Format value for bitfield USB_ERREN_CRC5EOFEN. */
1756 #define BF_USB_ERREN_CRC5EOFEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERREN_CRC5EOFEN) & BM_USB_ERREN_CRC5EOFEN)
1758 /*! @brief Set the CRC5EOFEN field to a new value. */
1759 #define BW_USB_ERREN_CRC5EOFEN(x, v) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_CRC5EOFEN) = (v))
1763 * @name Register USB_ERREN, field CRC16EN[2] (RW)
1766 * - 0 - Disables the CRC16 interrupt.
1767 * - 1 - Enables the CRC16 interrupt.
1770 #define BP_USB_ERREN_CRC16EN (2U) /*!< Bit position for USB_ERREN_CRC16EN. */
1771 #define BM_USB_ERREN_CRC16EN (0x04U) /*!< Bit mask for USB_ERREN_CRC16EN. */
1772 #define BS_USB_ERREN_CRC16EN (1U) /*!< Bit field size in bits for USB_ERREN_CRC16EN. */
1774 /*! @brief Read current value of the USB_ERREN_CRC16EN field. */
1775 #define BR_USB_ERREN_CRC16EN(x) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_CRC16EN))
1777 /*! @brief Format value for bitfield USB_ERREN_CRC16EN. */
1778 #define BF_USB_ERREN_CRC16EN(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERREN_CRC16EN) & BM_USB_ERREN_CRC16EN)
1780 /*! @brief Set the CRC16EN field to a new value. */
1781 #define BW_USB_ERREN_CRC16EN(x, v) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_CRC16EN) = (v))
1785 * @name Register USB_ERREN, field DFN8EN[3] (RW)
1788 * - 0 - Disables the DFN8 interrupt.
1789 * - 1 - Enables the DFN8 interrupt.
1792 #define BP_USB_ERREN_DFN8EN (3U) /*!< Bit position for USB_ERREN_DFN8EN. */
1793 #define BM_USB_ERREN_DFN8EN (0x08U) /*!< Bit mask for USB_ERREN_DFN8EN. */
1794 #define BS_USB_ERREN_DFN8EN (1U) /*!< Bit field size in bits for USB_ERREN_DFN8EN. */
1796 /*! @brief Read current value of the USB_ERREN_DFN8EN field. */
1797 #define BR_USB_ERREN_DFN8EN(x) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_DFN8EN))
1799 /*! @brief Format value for bitfield USB_ERREN_DFN8EN. */
1800 #define BF_USB_ERREN_DFN8EN(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERREN_DFN8EN) & BM_USB_ERREN_DFN8EN)
1802 /*! @brief Set the DFN8EN field to a new value. */
1803 #define BW_USB_ERREN_DFN8EN(x, v) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_DFN8EN) = (v))
1807 * @name Register USB_ERREN, field BTOERREN[4] (RW)
1810 * - 0 - Disables the BTOERR interrupt.
1811 * - 1 - Enables the BTOERR interrupt.
1814 #define BP_USB_ERREN_BTOERREN (4U) /*!< Bit position for USB_ERREN_BTOERREN. */
1815 #define BM_USB_ERREN_BTOERREN (0x10U) /*!< Bit mask for USB_ERREN_BTOERREN. */
1816 #define BS_USB_ERREN_BTOERREN (1U) /*!< Bit field size in bits for USB_ERREN_BTOERREN. */
1818 /*! @brief Read current value of the USB_ERREN_BTOERREN field. */
1819 #define BR_USB_ERREN_BTOERREN(x) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_BTOERREN))
1821 /*! @brief Format value for bitfield USB_ERREN_BTOERREN. */
1822 #define BF_USB_ERREN_BTOERREN(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERREN_BTOERREN) & BM_USB_ERREN_BTOERREN)
1824 /*! @brief Set the BTOERREN field to a new value. */
1825 #define BW_USB_ERREN_BTOERREN(x, v) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_BTOERREN) = (v))
1829 * @name Register USB_ERREN, field DMAERREN[5] (RW)
1832 * - 0 - Disables the DMAERR interrupt.
1833 * - 1 - Enables the DMAERR interrupt.
1836 #define BP_USB_ERREN_DMAERREN (5U) /*!< Bit position for USB_ERREN_DMAERREN. */
1837 #define BM_USB_ERREN_DMAERREN (0x20U) /*!< Bit mask for USB_ERREN_DMAERREN. */
1838 #define BS_USB_ERREN_DMAERREN (1U) /*!< Bit field size in bits for USB_ERREN_DMAERREN. */
1840 /*! @brief Read current value of the USB_ERREN_DMAERREN field. */
1841 #define BR_USB_ERREN_DMAERREN(x) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_DMAERREN))
1843 /*! @brief Format value for bitfield USB_ERREN_DMAERREN. */
1844 #define BF_USB_ERREN_DMAERREN(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERREN_DMAERREN) & BM_USB_ERREN_DMAERREN)
1846 /*! @brief Set the DMAERREN field to a new value. */
1847 #define BW_USB_ERREN_DMAERREN(x, v) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_DMAERREN) = (v))
1851 * @name Register USB_ERREN, field BTSERREN[7] (RW)
1854 * - 0 - Disables the BTSERR interrupt.
1855 * - 1 - Enables the BTSERR interrupt.
1858 #define BP_USB_ERREN_BTSERREN (7U) /*!< Bit position for USB_ERREN_BTSERREN. */
1859 #define BM_USB_ERREN_BTSERREN (0x80U) /*!< Bit mask for USB_ERREN_BTSERREN. */
1860 #define BS_USB_ERREN_BTSERREN (1U) /*!< Bit field size in bits for USB_ERREN_BTSERREN. */
1862 /*! @brief Read current value of the USB_ERREN_BTSERREN field. */
1863 #define BR_USB_ERREN_BTSERREN(x) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_BTSERREN))
1865 /*! @brief Format value for bitfield USB_ERREN_BTSERREN. */
1866 #define BF_USB_ERREN_BTSERREN(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERREN_BTSERREN) & BM_USB_ERREN_BTSERREN)
1868 /*! @brief Set the BTSERREN field to a new value. */
1869 #define BW_USB_ERREN_BTSERREN(x, v) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_BTSERREN) = (v))
1872 /*******************************************************************************
1873 * HW_USB_STAT - Status register
1874 ******************************************************************************/
1877 * @brief HW_USB_STAT - Status register (RO)
1879 * Reset value: 0x00U
1881 * Reports the transaction status within the USB module. When the processor's
1882 * interrupt controller has received a TOKDNE, interrupt the Status Register must
1883 * be read to determine the status of the previous endpoint communication. The
1884 * data in the status register is valid when TOKDNE interrupt is asserted. The
1885 * Status register is actually a read window into a status FIFO maintained by the USB
1886 * module. When the USB module uses a BD, it updates the Status register. If
1887 * another USB transaction is performed before the TOKDNE interrupt is serviced, the
1888 * USB module stores the status of the next transaction in the STAT FIFO. Thus
1889 * STAT is actually a four byte FIFO that allows the processor core to process one
1890 * transaction while the SIE is processing the next transaction. Clearing the
1891 * TOKDNE bit in the ISTAT register causes the SIE to update STAT with the contents
1892 * of the next STAT value. If the data in the STAT holding register is valid, the
1893 * SIE immediately reasserts to TOKDNE interrupt.
1895 typedef union _hw_usb_stat
1898 struct _hw_usb_stat_bitfields
1900 uint8_t RESERVED0
: 2; /*!< [1:0] */
1901 uint8_t ODD
: 1; /*!< [2] */
1902 uint8_t TX
: 1; /*!< [3] Transmit Indicator */
1903 uint8_t ENDP
: 4; /*!< [7:4] */
1908 * @name Constants and macros for entire USB_STAT register
1911 #define HW_USB_STAT_ADDR(x) ((x) + 0x90U)
1913 #define HW_USB_STAT(x) (*(__I hw_usb_stat_t *) HW_USB_STAT_ADDR(x))
1914 #define HW_USB_STAT_RD(x) (HW_USB_STAT(x).U)
1918 * Constants & macros for individual USB_STAT bitfields
1922 * @name Register USB_STAT, field ODD[2] (RO)
1924 * This bit is set if the last buffer descriptor updated was in the odd bank of
1928 #define BP_USB_STAT_ODD (2U) /*!< Bit position for USB_STAT_ODD. */
1929 #define BM_USB_STAT_ODD (0x04U) /*!< Bit mask for USB_STAT_ODD. */
1930 #define BS_USB_STAT_ODD (1U) /*!< Bit field size in bits for USB_STAT_ODD. */
1932 /*! @brief Read current value of the USB_STAT_ODD field. */
1933 #define BR_USB_STAT_ODD(x) (BITBAND_ACCESS8(HW_USB_STAT_ADDR(x), BP_USB_STAT_ODD))
1937 * @name Register USB_STAT, field TX[3] (RO)
1940 * - 0 - The most recent transaction was a receive operation.
1941 * - 1 - The most recent transaction was a transmit operation.
1944 #define BP_USB_STAT_TX (3U) /*!< Bit position for USB_STAT_TX. */
1945 #define BM_USB_STAT_TX (0x08U) /*!< Bit mask for USB_STAT_TX. */
1946 #define BS_USB_STAT_TX (1U) /*!< Bit field size in bits for USB_STAT_TX. */
1948 /*! @brief Read current value of the USB_STAT_TX field. */
1949 #define BR_USB_STAT_TX(x) (BITBAND_ACCESS8(HW_USB_STAT_ADDR(x), BP_USB_STAT_TX))
1953 * @name Register USB_STAT, field ENDP[7:4] (RO)
1955 * This four-bit field encodes the endpoint address that received or transmitted
1956 * the previous token. This allows the processor core to determine the BDT entry
1957 * that was updated by the last USB transaction.
1960 #define BP_USB_STAT_ENDP (4U) /*!< Bit position for USB_STAT_ENDP. */
1961 #define BM_USB_STAT_ENDP (0xF0U) /*!< Bit mask for USB_STAT_ENDP. */
1962 #define BS_USB_STAT_ENDP (4U) /*!< Bit field size in bits for USB_STAT_ENDP. */
1964 /*! @brief Read current value of the USB_STAT_ENDP field. */
1965 #define BR_USB_STAT_ENDP(x) (HW_USB_STAT(x).B.ENDP)
1968 /*******************************************************************************
1969 * HW_USB_CTL - Control register
1970 ******************************************************************************/
1973 * @brief HW_USB_CTL - Control register (RW)
1975 * Reset value: 0x00U
1977 * Provides various control and configuration information for the USB module.
1979 typedef union _hw_usb_ctl
1982 struct _hw_usb_ctl_bitfields
1984 uint8_t USBENSOFEN
: 1; /*!< [0] USB Enable */
1985 uint8_t ODDRST
: 1; /*!< [1] */
1986 uint8_t RESUME
: 1; /*!< [2] */
1987 uint8_t HOSTMODEEN
: 1; /*!< [3] */
1988 uint8_t RESET
: 1; /*!< [4] */
1989 uint8_t TXSUSPENDTOKENBUSY
: 1; /*!< [5] */
1990 uint8_t SE0
: 1; /*!< [6] Live USB Single Ended Zero signal */
1991 uint8_t JSTATE
: 1; /*!< [7] Live USB differential receiver JSTATE
1997 * @name Constants and macros for entire USB_CTL register
2000 #define HW_USB_CTL_ADDR(x) ((x) + 0x94U)
2002 #define HW_USB_CTL(x) (*(__IO hw_usb_ctl_t *) HW_USB_CTL_ADDR(x))
2003 #define HW_USB_CTL_RD(x) (HW_USB_CTL(x).U)
2004 #define HW_USB_CTL_WR(x, v) (HW_USB_CTL(x).U = (v))
2005 #define HW_USB_CTL_SET(x, v) (HW_USB_CTL_WR(x, HW_USB_CTL_RD(x) | (v)))
2006 #define HW_USB_CTL_CLR(x, v) (HW_USB_CTL_WR(x, HW_USB_CTL_RD(x) & ~(v)))
2007 #define HW_USB_CTL_TOG(x, v) (HW_USB_CTL_WR(x, HW_USB_CTL_RD(x) ^ (v)))
2011 * Constants & macros for individual USB_CTL bitfields
2015 * @name Register USB_CTL, field USBENSOFEN[0] (RW)
2017 * Setting this bit enables the USB-FS to operate; clearing it disables the
2018 * USB-FS. Setting the bit causes the SIE to reset all of its ODD bits to the BDTs.
2019 * Therefore, setting this bit resets much of the logic in the SIE. When host mode
2020 * is enabled, clearing this bit causes the SIE to stop sending SOF tokens.
2023 * - 0 - Disables the USB Module.
2024 * - 1 - Enables the USB Module.
2027 #define BP_USB_CTL_USBENSOFEN (0U) /*!< Bit position for USB_CTL_USBENSOFEN. */
2028 #define BM_USB_CTL_USBENSOFEN (0x01U) /*!< Bit mask for USB_CTL_USBENSOFEN. */
2029 #define BS_USB_CTL_USBENSOFEN (1U) /*!< Bit field size in bits for USB_CTL_USBENSOFEN. */
2031 /*! @brief Read current value of the USB_CTL_USBENSOFEN field. */
2032 #define BR_USB_CTL_USBENSOFEN(x) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_USBENSOFEN))
2034 /*! @brief Format value for bitfield USB_CTL_USBENSOFEN. */
2035 #define BF_USB_CTL_USBENSOFEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_CTL_USBENSOFEN) & BM_USB_CTL_USBENSOFEN)
2037 /*! @brief Set the USBENSOFEN field to a new value. */
2038 #define BW_USB_CTL_USBENSOFEN(x, v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_USBENSOFEN) = (v))
2042 * @name Register USB_CTL, field ODDRST[1] (RW)
2044 * Setting this bit to 1 resets all the BDT ODD ping/pong fields to 0, which
2045 * then specifies the EVEN BDT bank.
2048 #define BP_USB_CTL_ODDRST (1U) /*!< Bit position for USB_CTL_ODDRST. */
2049 #define BM_USB_CTL_ODDRST (0x02U) /*!< Bit mask for USB_CTL_ODDRST. */
2050 #define BS_USB_CTL_ODDRST (1U) /*!< Bit field size in bits for USB_CTL_ODDRST. */
2052 /*! @brief Read current value of the USB_CTL_ODDRST field. */
2053 #define BR_USB_CTL_ODDRST(x) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_ODDRST))
2055 /*! @brief Format value for bitfield USB_CTL_ODDRST. */
2056 #define BF_USB_CTL_ODDRST(v) ((uint8_t)((uint8_t)(v) << BP_USB_CTL_ODDRST) & BM_USB_CTL_ODDRST)
2058 /*! @brief Set the ODDRST field to a new value. */
2059 #define BW_USB_CTL_ODDRST(x, v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_ODDRST) = (v))
2063 * @name Register USB_CTL, field RESUME[2] (RW)
2065 * When set to 1 this bit enables the USB Module to execute resume signaling.
2066 * This allows the USB Module to perform remote wake-up. Software must set RESUME
2067 * to 1 for the required amount of time and then clear it to 0. If the HOSTMODEEN
2068 * bit is set, the USB module appends a Low Speed End of Packet to the Resume
2069 * signaling when the RESUME bit is cleared. For more information on RESUME
2070 * signaling see Section 7.1.4.5 of the USB specification version 1.0.
2073 #define BP_USB_CTL_RESUME (2U) /*!< Bit position for USB_CTL_RESUME. */
2074 #define BM_USB_CTL_RESUME (0x04U) /*!< Bit mask for USB_CTL_RESUME. */
2075 #define BS_USB_CTL_RESUME (1U) /*!< Bit field size in bits for USB_CTL_RESUME. */
2077 /*! @brief Read current value of the USB_CTL_RESUME field. */
2078 #define BR_USB_CTL_RESUME(x) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_RESUME))
2080 /*! @brief Format value for bitfield USB_CTL_RESUME. */
2081 #define BF_USB_CTL_RESUME(v) ((uint8_t)((uint8_t)(v) << BP_USB_CTL_RESUME) & BM_USB_CTL_RESUME)
2083 /*! @brief Set the RESUME field to a new value. */
2084 #define BW_USB_CTL_RESUME(x, v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_RESUME) = (v))
2088 * @name Register USB_CTL, field HOSTMODEEN[3] (RW)
2090 * When set to 1, this bit enables the USB Module to operate in Host mode. In
2091 * host mode, the USB module performs USB transactions under the programmed control
2092 * of the host processor.
2095 #define BP_USB_CTL_HOSTMODEEN (3U) /*!< Bit position for USB_CTL_HOSTMODEEN. */
2096 #define BM_USB_CTL_HOSTMODEEN (0x08U) /*!< Bit mask for USB_CTL_HOSTMODEEN. */
2097 #define BS_USB_CTL_HOSTMODEEN (1U) /*!< Bit field size in bits for USB_CTL_HOSTMODEEN. */
2099 /*! @brief Read current value of the USB_CTL_HOSTMODEEN field. */
2100 #define BR_USB_CTL_HOSTMODEEN(x) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_HOSTMODEEN))
2102 /*! @brief Format value for bitfield USB_CTL_HOSTMODEEN. */
2103 #define BF_USB_CTL_HOSTMODEEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_CTL_HOSTMODEEN) & BM_USB_CTL_HOSTMODEEN)
2105 /*! @brief Set the HOSTMODEEN field to a new value. */
2106 #define BW_USB_CTL_HOSTMODEEN(x, v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_HOSTMODEEN) = (v))
2110 * @name Register USB_CTL, field RESET[4] (RW)
2112 * Setting this bit enables the USB Module to generate USB reset signaling. This
2113 * allows the USB Module to reset USB peripherals. This control signal is only
2114 * valid in Host mode (HOSTMODEEN=1). Software must set RESET to 1 for the
2115 * required amount of time and then clear it to 0 to end reset signaling. For more
2116 * information on reset signaling see Section 7.1.4.3 of the USB specification version
2120 #define BP_USB_CTL_RESET (4U) /*!< Bit position for USB_CTL_RESET. */
2121 #define BM_USB_CTL_RESET (0x10U) /*!< Bit mask for USB_CTL_RESET. */
2122 #define BS_USB_CTL_RESET (1U) /*!< Bit field size in bits for USB_CTL_RESET. */
2124 /*! @brief Read current value of the USB_CTL_RESET field. */
2125 #define BR_USB_CTL_RESET(x) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_RESET))
2127 /*! @brief Format value for bitfield USB_CTL_RESET. */
2128 #define BF_USB_CTL_RESET(v) ((uint8_t)((uint8_t)(v) << BP_USB_CTL_RESET) & BM_USB_CTL_RESET)
2130 /*! @brief Set the RESET field to a new value. */
2131 #define BW_USB_CTL_RESET(x, v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_RESET) = (v))
2135 * @name Register USB_CTL, field TXSUSPENDTOKENBUSY[5] (RW)
2137 * In Host mode, TOKEN_BUSY is set when the USB module is busy executing a USB
2138 * token. Software must not write more token commands to the Token Register when
2139 * TOKEN_BUSY is set. Software should check this field before writing any tokens
2140 * to the Token Register to ensure that token commands are not lost. In Target
2141 * mode, TXD_SUSPEND is set when the SIE has disabled packet transmission and
2142 * reception. Clearing this bit allows the SIE to continue token processing. This bit
2143 * is set by the SIE when a SETUP Token is received allowing software to dequeue
2144 * any pending packet transactions in the BDT before resuming token processing.
2147 #define BP_USB_CTL_TXSUSPENDTOKENBUSY (5U) /*!< Bit position for USB_CTL_TXSUSPENDTOKENBUSY. */
2148 #define BM_USB_CTL_TXSUSPENDTOKENBUSY (0x20U) /*!< Bit mask for USB_CTL_TXSUSPENDTOKENBUSY. */
2149 #define BS_USB_CTL_TXSUSPENDTOKENBUSY (1U) /*!< Bit field size in bits for USB_CTL_TXSUSPENDTOKENBUSY. */
2151 /*! @brief Read current value of the USB_CTL_TXSUSPENDTOKENBUSY field. */
2152 #define BR_USB_CTL_TXSUSPENDTOKENBUSY(x) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_TXSUSPENDTOKENBUSY))
2154 /*! @brief Format value for bitfield USB_CTL_TXSUSPENDTOKENBUSY. */
2155 #define BF_USB_CTL_TXSUSPENDTOKENBUSY(v) ((uint8_t)((uint8_t)(v) << BP_USB_CTL_TXSUSPENDTOKENBUSY) & BM_USB_CTL_TXSUSPENDTOKENBUSY)
2157 /*! @brief Set the TXSUSPENDTOKENBUSY field to a new value. */
2158 #define BW_USB_CTL_TXSUSPENDTOKENBUSY(x, v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_TXSUSPENDTOKENBUSY) = (v))
2162 * @name Register USB_CTL, field SE0[6] (RW)
2165 #define BP_USB_CTL_SE0 (6U) /*!< Bit position for USB_CTL_SE0. */
2166 #define BM_USB_CTL_SE0 (0x40U) /*!< Bit mask for USB_CTL_SE0. */
2167 #define BS_USB_CTL_SE0 (1U) /*!< Bit field size in bits for USB_CTL_SE0. */
2169 /*! @brief Read current value of the USB_CTL_SE0 field. */
2170 #define BR_USB_CTL_SE0(x) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_SE0))
2172 /*! @brief Format value for bitfield USB_CTL_SE0. */
2173 #define BF_USB_CTL_SE0(v) ((uint8_t)((uint8_t)(v) << BP_USB_CTL_SE0) & BM_USB_CTL_SE0)
2175 /*! @brief Set the SE0 field to a new value. */
2176 #define BW_USB_CTL_SE0(x, v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_SE0) = (v))
2180 * @name Register USB_CTL, field JSTATE[7] (RW)
2182 * The polarity of this signal is affected by the current state of LSEN .
2185 #define BP_USB_CTL_JSTATE (7U) /*!< Bit position for USB_CTL_JSTATE. */
2186 #define BM_USB_CTL_JSTATE (0x80U) /*!< Bit mask for USB_CTL_JSTATE. */
2187 #define BS_USB_CTL_JSTATE (1U) /*!< Bit field size in bits for USB_CTL_JSTATE. */
2189 /*! @brief Read current value of the USB_CTL_JSTATE field. */
2190 #define BR_USB_CTL_JSTATE(x) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_JSTATE))
2192 /*! @brief Format value for bitfield USB_CTL_JSTATE. */
2193 #define BF_USB_CTL_JSTATE(v) ((uint8_t)((uint8_t)(v) << BP_USB_CTL_JSTATE) & BM_USB_CTL_JSTATE)
2195 /*! @brief Set the JSTATE field to a new value. */
2196 #define BW_USB_CTL_JSTATE(x, v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_JSTATE) = (v))
2199 /*******************************************************************************
2200 * HW_USB_ADDR - Address register
2201 ******************************************************************************/
2204 * @brief HW_USB_ADDR - Address register (RW)
2206 * Reset value: 0x00U
2208 * Holds the unique USB address that the USB module decodes when in Peripheral
2209 * mode (HOSTMODEEN=0). When operating in Host mode (HOSTMODEEN=1) the USB module
2210 * transmits this address with a TOKEN packet. This enables the USB module to
2211 * uniquely address any USB peripheral. In either mode, CTL[USBENSOFEN] must be 1.
2212 * The Address register is reset to 0x00 after the reset input becomes active or
2213 * the USB module decodes a USB reset signal. This action initializes the Address
2214 * register to decode address 0x00 as required by the USB specification.
2216 typedef union _hw_usb_addr
2219 struct _hw_usb_addr_bitfields
2221 uint8_t ADDR
: 7; /*!< [6:0] USB Address */
2222 uint8_t LSEN
: 1; /*!< [7] Low Speed Enable bit */
2227 * @name Constants and macros for entire USB_ADDR register
2230 #define HW_USB_ADDR_ADDR(x) ((x) + 0x98U)
2232 #define HW_USB_ADDR(x) (*(__IO hw_usb_addr_t *) HW_USB_ADDR_ADDR(x))
2233 #define HW_USB_ADDR_RD(x) (HW_USB_ADDR(x).U)
2234 #define HW_USB_ADDR_WR(x, v) (HW_USB_ADDR(x).U = (v))
2235 #define HW_USB_ADDR_SET(x, v) (HW_USB_ADDR_WR(x, HW_USB_ADDR_RD(x) | (v)))
2236 #define HW_USB_ADDR_CLR(x, v) (HW_USB_ADDR_WR(x, HW_USB_ADDR_RD(x) & ~(v)))
2237 #define HW_USB_ADDR_TOG(x, v) (HW_USB_ADDR_WR(x, HW_USB_ADDR_RD(x) ^ (v)))
2241 * Constants & macros for individual USB_ADDR bitfields
2245 * @name Register USB_ADDR, field ADDR[6:0] (RW)
2247 * Defines the USB address that the USB module decodes in peripheral mode, or
2248 * transmits when in host mode.
2251 #define BP_USB_ADDR_ADDR (0U) /*!< Bit position for USB_ADDR_ADDR. */
2252 #define BM_USB_ADDR_ADDR (0x7FU) /*!< Bit mask for USB_ADDR_ADDR. */
2253 #define BS_USB_ADDR_ADDR (7U) /*!< Bit field size in bits for USB_ADDR_ADDR. */
2255 /*! @brief Read current value of the USB_ADDR_ADDR field. */
2256 #define BR_USB_ADDR_ADDR(x) (HW_USB_ADDR(x).B.ADDR)
2258 /*! @brief Format value for bitfield USB_ADDR_ADDR. */
2259 #define BF_USB_ADDR_ADDR(v) ((uint8_t)((uint8_t)(v) << BP_USB_ADDR_ADDR) & BM_USB_ADDR_ADDR)
2261 /*! @brief Set the ADDR field to a new value. */
2262 #define BW_USB_ADDR_ADDR(x, v) (HW_USB_ADDR_WR(x, (HW_USB_ADDR_RD(x) & ~BM_USB_ADDR_ADDR) | BF_USB_ADDR_ADDR(v)))
2266 * @name Register USB_ADDR, field LSEN[7] (RW)
2268 * Informs the USB module that the next token command written to the token
2269 * register must be performed at low speed. This enables the USB module to perform the
2270 * necessary preamble required for low-speed data transmissions.
2273 #define BP_USB_ADDR_LSEN (7U) /*!< Bit position for USB_ADDR_LSEN. */
2274 #define BM_USB_ADDR_LSEN (0x80U) /*!< Bit mask for USB_ADDR_LSEN. */
2275 #define BS_USB_ADDR_LSEN (1U) /*!< Bit field size in bits for USB_ADDR_LSEN. */
2277 /*! @brief Read current value of the USB_ADDR_LSEN field. */
2278 #define BR_USB_ADDR_LSEN(x) (BITBAND_ACCESS8(HW_USB_ADDR_ADDR(x), BP_USB_ADDR_LSEN))
2280 /*! @brief Format value for bitfield USB_ADDR_LSEN. */
2281 #define BF_USB_ADDR_LSEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_ADDR_LSEN) & BM_USB_ADDR_LSEN)
2283 /*! @brief Set the LSEN field to a new value. */
2284 #define BW_USB_ADDR_LSEN(x, v) (BITBAND_ACCESS8(HW_USB_ADDR_ADDR(x), BP_USB_ADDR_LSEN) = (v))
2287 /*******************************************************************************
2288 * HW_USB_BDTPAGE1 - BDT Page register 1
2289 ******************************************************************************/
2292 * @brief HW_USB_BDTPAGE1 - BDT Page register 1 (RW)
2294 * Reset value: 0x00U
2296 * Provides address bits 15 through 9 of the base address where the current
2297 * Buffer Descriptor Table (BDT) resides in system memory. The 32-bit BDT Base
2298 * Address is always aligned on 512-byte boundaries, so bits 8 through 0 of the base
2299 * address are always zero.
2301 typedef union _hw_usb_bdtpage1
2304 struct _hw_usb_bdtpage1_bitfields
2306 uint8_t RESERVED0
: 1; /*!< [0] */
2307 uint8_t BDTBA
: 7; /*!< [7:1] */
2309 } hw_usb_bdtpage1_t
;
2312 * @name Constants and macros for entire USB_BDTPAGE1 register
2315 #define HW_USB_BDTPAGE1_ADDR(x) ((x) + 0x9CU)
2317 #define HW_USB_BDTPAGE1(x) (*(__IO hw_usb_bdtpage1_t *) HW_USB_BDTPAGE1_ADDR(x))
2318 #define HW_USB_BDTPAGE1_RD(x) (HW_USB_BDTPAGE1(x).U)
2319 #define HW_USB_BDTPAGE1_WR(x, v) (HW_USB_BDTPAGE1(x).U = (v))
2320 #define HW_USB_BDTPAGE1_SET(x, v) (HW_USB_BDTPAGE1_WR(x, HW_USB_BDTPAGE1_RD(x) | (v)))
2321 #define HW_USB_BDTPAGE1_CLR(x, v) (HW_USB_BDTPAGE1_WR(x, HW_USB_BDTPAGE1_RD(x) & ~(v)))
2322 #define HW_USB_BDTPAGE1_TOG(x, v) (HW_USB_BDTPAGE1_WR(x, HW_USB_BDTPAGE1_RD(x) ^ (v)))
2326 * Constants & macros for individual USB_BDTPAGE1 bitfields
2330 * @name Register USB_BDTPAGE1, field BDTBA[7:1] (RW)
2332 * Provides address bits 15 through 9 of the BDT base address.
2335 #define BP_USB_BDTPAGE1_BDTBA (1U) /*!< Bit position for USB_BDTPAGE1_BDTBA. */
2336 #define BM_USB_BDTPAGE1_BDTBA (0xFEU) /*!< Bit mask for USB_BDTPAGE1_BDTBA. */
2337 #define BS_USB_BDTPAGE1_BDTBA (7U) /*!< Bit field size in bits for USB_BDTPAGE1_BDTBA. */
2339 /*! @brief Read current value of the USB_BDTPAGE1_BDTBA field. */
2340 #define BR_USB_BDTPAGE1_BDTBA(x) (HW_USB_BDTPAGE1(x).B.BDTBA)
2342 /*! @brief Format value for bitfield USB_BDTPAGE1_BDTBA. */
2343 #define BF_USB_BDTPAGE1_BDTBA(v) ((uint8_t)((uint8_t)(v) << BP_USB_BDTPAGE1_BDTBA) & BM_USB_BDTPAGE1_BDTBA)
2345 /*! @brief Set the BDTBA field to a new value. */
2346 #define BW_USB_BDTPAGE1_BDTBA(x, v) (HW_USB_BDTPAGE1_WR(x, (HW_USB_BDTPAGE1_RD(x) & ~BM_USB_BDTPAGE1_BDTBA) | BF_USB_BDTPAGE1_BDTBA(v)))
2349 /*******************************************************************************
2350 * HW_USB_FRMNUML - Frame Number register Low
2351 ******************************************************************************/
2354 * @brief HW_USB_FRMNUML - Frame Number register Low (RW)
2356 * Reset value: 0x00U
2358 * The Frame Number registers (low and high) contain the 11-bit frame number.
2359 * These registers are updated with the current frame number whenever a SOF TOKEN
2362 typedef union _hw_usb_frmnuml
2365 struct _hw_usb_frmnuml_bitfields
2367 uint8_t FRM
: 8; /*!< [7:0] */
2372 * @name Constants and macros for entire USB_FRMNUML register
2375 #define HW_USB_FRMNUML_ADDR(x) ((x) + 0xA0U)
2377 #define HW_USB_FRMNUML(x) (*(__IO hw_usb_frmnuml_t *) HW_USB_FRMNUML_ADDR(x))
2378 #define HW_USB_FRMNUML_RD(x) (HW_USB_FRMNUML(x).U)
2379 #define HW_USB_FRMNUML_WR(x, v) (HW_USB_FRMNUML(x).U = (v))
2380 #define HW_USB_FRMNUML_SET(x, v) (HW_USB_FRMNUML_WR(x, HW_USB_FRMNUML_RD(x) | (v)))
2381 #define HW_USB_FRMNUML_CLR(x, v) (HW_USB_FRMNUML_WR(x, HW_USB_FRMNUML_RD(x) & ~(v)))
2382 #define HW_USB_FRMNUML_TOG(x, v) (HW_USB_FRMNUML_WR(x, HW_USB_FRMNUML_RD(x) ^ (v)))
2386 * Constants & macros for individual USB_FRMNUML bitfields
2390 * @name Register USB_FRMNUML, field FRM[7:0] (RW)
2392 * This 8-bit field and the 3-bit field in the Frame Number Register High are
2393 * used to compute the address where the current Buffer Descriptor Table (BDT)
2394 * resides in system memory.
2397 #define BP_USB_FRMNUML_FRM (0U) /*!< Bit position for USB_FRMNUML_FRM. */
2398 #define BM_USB_FRMNUML_FRM (0xFFU) /*!< Bit mask for USB_FRMNUML_FRM. */
2399 #define BS_USB_FRMNUML_FRM (8U) /*!< Bit field size in bits for USB_FRMNUML_FRM. */
2401 /*! @brief Read current value of the USB_FRMNUML_FRM field. */
2402 #define BR_USB_FRMNUML_FRM(x) (HW_USB_FRMNUML(x).U)
2404 /*! @brief Format value for bitfield USB_FRMNUML_FRM. */
2405 #define BF_USB_FRMNUML_FRM(v) ((uint8_t)((uint8_t)(v) << BP_USB_FRMNUML_FRM) & BM_USB_FRMNUML_FRM)
2407 /*! @brief Set the FRM field to a new value. */
2408 #define BW_USB_FRMNUML_FRM(x, v) (HW_USB_FRMNUML_WR(x, v))
2411 /*******************************************************************************
2412 * HW_USB_FRMNUMH - Frame Number register High
2413 ******************************************************************************/
2416 * @brief HW_USB_FRMNUMH - Frame Number register High (RW)
2418 * Reset value: 0x00U
2420 * The Frame Number registers (low and high) contain the 11-bit frame number.
2421 * These registers are updated with the current frame number whenever a SOF TOKEN
2424 typedef union _hw_usb_frmnumh
2427 struct _hw_usb_frmnumh_bitfields
2429 uint8_t FRM
: 3; /*!< [2:0] */
2430 uint8_t RESERVED0
: 5; /*!< [7:3] */
2435 * @name Constants and macros for entire USB_FRMNUMH register
2438 #define HW_USB_FRMNUMH_ADDR(x) ((x) + 0xA4U)
2440 #define HW_USB_FRMNUMH(x) (*(__IO hw_usb_frmnumh_t *) HW_USB_FRMNUMH_ADDR(x))
2441 #define HW_USB_FRMNUMH_RD(x) (HW_USB_FRMNUMH(x).U)
2442 #define HW_USB_FRMNUMH_WR(x, v) (HW_USB_FRMNUMH(x).U = (v))
2443 #define HW_USB_FRMNUMH_SET(x, v) (HW_USB_FRMNUMH_WR(x, HW_USB_FRMNUMH_RD(x) | (v)))
2444 #define HW_USB_FRMNUMH_CLR(x, v) (HW_USB_FRMNUMH_WR(x, HW_USB_FRMNUMH_RD(x) & ~(v)))
2445 #define HW_USB_FRMNUMH_TOG(x, v) (HW_USB_FRMNUMH_WR(x, HW_USB_FRMNUMH_RD(x) ^ (v)))
2449 * Constants & macros for individual USB_FRMNUMH bitfields
2453 * @name Register USB_FRMNUMH, field FRM[2:0] (RW)
2455 * This 3-bit field and the 8-bit field in the Frame Number Register Low are
2456 * used to compute the address where the current Buffer Descriptor Table (BDT)
2457 * resides in system memory.
2460 #define BP_USB_FRMNUMH_FRM (0U) /*!< Bit position for USB_FRMNUMH_FRM. */
2461 #define BM_USB_FRMNUMH_FRM (0x07U) /*!< Bit mask for USB_FRMNUMH_FRM. */
2462 #define BS_USB_FRMNUMH_FRM (3U) /*!< Bit field size in bits for USB_FRMNUMH_FRM. */
2464 /*! @brief Read current value of the USB_FRMNUMH_FRM field. */
2465 #define BR_USB_FRMNUMH_FRM(x) (HW_USB_FRMNUMH(x).B.FRM)
2467 /*! @brief Format value for bitfield USB_FRMNUMH_FRM. */
2468 #define BF_USB_FRMNUMH_FRM(v) ((uint8_t)((uint8_t)(v) << BP_USB_FRMNUMH_FRM) & BM_USB_FRMNUMH_FRM)
2470 /*! @brief Set the FRM field to a new value. */
2471 #define BW_USB_FRMNUMH_FRM(x, v) (HW_USB_FRMNUMH_WR(x, (HW_USB_FRMNUMH_RD(x) & ~BM_USB_FRMNUMH_FRM) | BF_USB_FRMNUMH_FRM(v)))
2474 /*******************************************************************************
2475 * HW_USB_TOKEN - Token register
2476 ******************************************************************************/
2479 * @brief HW_USB_TOKEN - Token register (RW)
2481 * Reset value: 0x00U
2483 * Used to initiate USB transactions when in host mode (HOSTMODEEN=1). When the
2484 * software needs to execute a USB transaction to a peripheral, it writes the
2485 * TOKEN type and endpoint to this register. After this register has been written,
2486 * the USB module begins the specified USB transaction to the address contained in
2487 * the address register. The processor core must always check that the
2488 * TOKEN_BUSY bit in the control register is not 1 before writing to the Token Register.
2489 * This ensures that the token commands are not overwritten before they can be
2490 * executed. The address register and endpoint control register 0 are also used when
2491 * performing a token command and therefore must also be written before the
2492 * Token Register. The address register is used to select the USB peripheral address
2493 * transmitted by the token command. The endpoint control register determines the
2494 * handshake and retry policies used during the transfer.
2496 typedef union _hw_usb_token
2499 struct _hw_usb_token_bitfields
2501 uint8_t TOKENENDPT
: 4; /*!< [3:0] */
2502 uint8_t TOKENPID
: 4; /*!< [7:4] */
2507 * @name Constants and macros for entire USB_TOKEN register
2510 #define HW_USB_TOKEN_ADDR(x) ((x) + 0xA8U)
2512 #define HW_USB_TOKEN(x) (*(__IO hw_usb_token_t *) HW_USB_TOKEN_ADDR(x))
2513 #define HW_USB_TOKEN_RD(x) (HW_USB_TOKEN(x).U)
2514 #define HW_USB_TOKEN_WR(x, v) (HW_USB_TOKEN(x).U = (v))
2515 #define HW_USB_TOKEN_SET(x, v) (HW_USB_TOKEN_WR(x, HW_USB_TOKEN_RD(x) | (v)))
2516 #define HW_USB_TOKEN_CLR(x, v) (HW_USB_TOKEN_WR(x, HW_USB_TOKEN_RD(x) & ~(v)))
2517 #define HW_USB_TOKEN_TOG(x, v) (HW_USB_TOKEN_WR(x, HW_USB_TOKEN_RD(x) ^ (v)))
2521 * Constants & macros for individual USB_TOKEN bitfields
2525 * @name Register USB_TOKEN, field TOKENENDPT[3:0] (RW)
2527 * Holds the Endpoint address for the token command. The four bit value written
2528 * must be a valid endpoint.
2531 #define BP_USB_TOKEN_TOKENENDPT (0U) /*!< Bit position for USB_TOKEN_TOKENENDPT. */
2532 #define BM_USB_TOKEN_TOKENENDPT (0x0FU) /*!< Bit mask for USB_TOKEN_TOKENENDPT. */
2533 #define BS_USB_TOKEN_TOKENENDPT (4U) /*!< Bit field size in bits for USB_TOKEN_TOKENENDPT. */
2535 /*! @brief Read current value of the USB_TOKEN_TOKENENDPT field. */
2536 #define BR_USB_TOKEN_TOKENENDPT(x) (HW_USB_TOKEN(x).B.TOKENENDPT)
2538 /*! @brief Format value for bitfield USB_TOKEN_TOKENENDPT. */
2539 #define BF_USB_TOKEN_TOKENENDPT(v) ((uint8_t)((uint8_t)(v) << BP_USB_TOKEN_TOKENENDPT) & BM_USB_TOKEN_TOKENENDPT)
2541 /*! @brief Set the TOKENENDPT field to a new value. */
2542 #define BW_USB_TOKEN_TOKENENDPT(x, v) (HW_USB_TOKEN_WR(x, (HW_USB_TOKEN_RD(x) & ~BM_USB_TOKEN_TOKENENDPT) | BF_USB_TOKEN_TOKENENDPT(v)))
2546 * @name Register USB_TOKEN, field TOKENPID[7:4] (RW)
2548 * Contains the token type executed by the USB module.
2551 * - 0001 - OUT Token. USB Module performs an OUT (TX) transaction.
2552 * - 1001 - IN Token. USB Module performs an In (RX) transaction.
2553 * - 1101 - SETUP Token. USB Module performs a SETUP (TX) transaction
2556 #define BP_USB_TOKEN_TOKENPID (4U) /*!< Bit position for USB_TOKEN_TOKENPID. */
2557 #define BM_USB_TOKEN_TOKENPID (0xF0U) /*!< Bit mask for USB_TOKEN_TOKENPID. */
2558 #define BS_USB_TOKEN_TOKENPID (4U) /*!< Bit field size in bits for USB_TOKEN_TOKENPID. */
2560 /*! @brief Read current value of the USB_TOKEN_TOKENPID field. */
2561 #define BR_USB_TOKEN_TOKENPID(x) (HW_USB_TOKEN(x).B.TOKENPID)
2563 /*! @brief Format value for bitfield USB_TOKEN_TOKENPID. */
2564 #define BF_USB_TOKEN_TOKENPID(v) ((uint8_t)((uint8_t)(v) << BP_USB_TOKEN_TOKENPID) & BM_USB_TOKEN_TOKENPID)
2566 /*! @brief Set the TOKENPID field to a new value. */
2567 #define BW_USB_TOKEN_TOKENPID(x, v) (HW_USB_TOKEN_WR(x, (HW_USB_TOKEN_RD(x) & ~BM_USB_TOKEN_TOKENPID) | BF_USB_TOKEN_TOKENPID(v)))
2570 /*******************************************************************************
2571 * HW_USB_SOFTHLD - SOF Threshold register
2572 ******************************************************************************/
2575 * @brief HW_USB_SOFTHLD - SOF Threshold register (RW)
2577 * Reset value: 0x00U
2579 * The SOF Threshold Register is used only in Host mode (HOSTMODEEN=1). When in
2580 * Host mode, the 14-bit SOF counter counts the interval between SOF frames. The
2581 * SOF must be transmitted every 1ms so therefore the SOF counter is loaded with
2582 * a value of 12000. When the SOF counter reaches zero, a Start Of Frame (SOF)
2583 * token is transmitted. The SOF threshold register is used to program the number
2584 * of USB byte times before the SOF to stop initiating token packet transactions.
2585 * This register must be set to a value that ensures that other packets are not
2586 * actively being transmitted when the SOF time counts to zero. When the SOF
2587 * counter reaches the threshold value, no more tokens are transmitted until after the
2588 * SOF has been transmitted. The value programmed into the threshold register
2589 * must reserve enough time to ensure the worst case transaction completes. In
2590 * general the worst case transaction is an IN token followed by a data packet from
2591 * the target followed by the response from the host. The actual time required is
2592 * a function of the maximum packet size on the bus. Typical values for the SOF
2593 * threshold are: 64-byte packets=74; 32-byte packets=42; 16-byte packets=26;
2594 * 8-byte packets=18.
2596 typedef union _hw_usb_softhld
2599 struct _hw_usb_softhld_bitfields
2601 uint8_t CNT
: 8; /*!< [7:0] */
2606 * @name Constants and macros for entire USB_SOFTHLD register
2609 #define HW_USB_SOFTHLD_ADDR(x) ((x) + 0xACU)
2611 #define HW_USB_SOFTHLD(x) (*(__IO hw_usb_softhld_t *) HW_USB_SOFTHLD_ADDR(x))
2612 #define HW_USB_SOFTHLD_RD(x) (HW_USB_SOFTHLD(x).U)
2613 #define HW_USB_SOFTHLD_WR(x, v) (HW_USB_SOFTHLD(x).U = (v))
2614 #define HW_USB_SOFTHLD_SET(x, v) (HW_USB_SOFTHLD_WR(x, HW_USB_SOFTHLD_RD(x) | (v)))
2615 #define HW_USB_SOFTHLD_CLR(x, v) (HW_USB_SOFTHLD_WR(x, HW_USB_SOFTHLD_RD(x) & ~(v)))
2616 #define HW_USB_SOFTHLD_TOG(x, v) (HW_USB_SOFTHLD_WR(x, HW_USB_SOFTHLD_RD(x) ^ (v)))
2620 * Constants & macros for individual USB_SOFTHLD bitfields
2624 * @name Register USB_SOFTHLD, field CNT[7:0] (RW)
2626 * Represents the SOF count threshold in byte times.
2629 #define BP_USB_SOFTHLD_CNT (0U) /*!< Bit position for USB_SOFTHLD_CNT. */
2630 #define BM_USB_SOFTHLD_CNT (0xFFU) /*!< Bit mask for USB_SOFTHLD_CNT. */
2631 #define BS_USB_SOFTHLD_CNT (8U) /*!< Bit field size in bits for USB_SOFTHLD_CNT. */
2633 /*! @brief Read current value of the USB_SOFTHLD_CNT field. */
2634 #define BR_USB_SOFTHLD_CNT(x) (HW_USB_SOFTHLD(x).U)
2636 /*! @brief Format value for bitfield USB_SOFTHLD_CNT. */
2637 #define BF_USB_SOFTHLD_CNT(v) ((uint8_t)((uint8_t)(v) << BP_USB_SOFTHLD_CNT) & BM_USB_SOFTHLD_CNT)
2639 /*! @brief Set the CNT field to a new value. */
2640 #define BW_USB_SOFTHLD_CNT(x, v) (HW_USB_SOFTHLD_WR(x, v))
2643 /*******************************************************************************
2644 * HW_USB_BDTPAGE2 - BDT Page Register 2
2645 ******************************************************************************/
2648 * @brief HW_USB_BDTPAGE2 - BDT Page Register 2 (RW)
2650 * Reset value: 0x00U
2652 * Contains an 8-bit value used to compute the address where the current Buffer
2653 * Descriptor Table (BDT) resides in system memory.
2655 typedef union _hw_usb_bdtpage2
2658 struct _hw_usb_bdtpage2_bitfields
2660 uint8_t BDTBA
: 8; /*!< [7:0] */
2662 } hw_usb_bdtpage2_t
;
2665 * @name Constants and macros for entire USB_BDTPAGE2 register
2668 #define HW_USB_BDTPAGE2_ADDR(x) ((x) + 0xB0U)
2670 #define HW_USB_BDTPAGE2(x) (*(__IO hw_usb_bdtpage2_t *) HW_USB_BDTPAGE2_ADDR(x))
2671 #define HW_USB_BDTPAGE2_RD(x) (HW_USB_BDTPAGE2(x).U)
2672 #define HW_USB_BDTPAGE2_WR(x, v) (HW_USB_BDTPAGE2(x).U = (v))
2673 #define HW_USB_BDTPAGE2_SET(x, v) (HW_USB_BDTPAGE2_WR(x, HW_USB_BDTPAGE2_RD(x) | (v)))
2674 #define HW_USB_BDTPAGE2_CLR(x, v) (HW_USB_BDTPAGE2_WR(x, HW_USB_BDTPAGE2_RD(x) & ~(v)))
2675 #define HW_USB_BDTPAGE2_TOG(x, v) (HW_USB_BDTPAGE2_WR(x, HW_USB_BDTPAGE2_RD(x) ^ (v)))
2679 * Constants & macros for individual USB_BDTPAGE2 bitfields
2683 * @name Register USB_BDTPAGE2, field BDTBA[7:0] (RW)
2685 * Provides address bits 23 through 16 of the BDT base address that defines the
2686 * location of Buffer Descriptor Table resides in system memory.
2689 #define BP_USB_BDTPAGE2_BDTBA (0U) /*!< Bit position for USB_BDTPAGE2_BDTBA. */
2690 #define BM_USB_BDTPAGE2_BDTBA (0xFFU) /*!< Bit mask for USB_BDTPAGE2_BDTBA. */
2691 #define BS_USB_BDTPAGE2_BDTBA (8U) /*!< Bit field size in bits for USB_BDTPAGE2_BDTBA. */
2693 /*! @brief Read current value of the USB_BDTPAGE2_BDTBA field. */
2694 #define BR_USB_BDTPAGE2_BDTBA(x) (HW_USB_BDTPAGE2(x).U)
2696 /*! @brief Format value for bitfield USB_BDTPAGE2_BDTBA. */
2697 #define BF_USB_BDTPAGE2_BDTBA(v) ((uint8_t)((uint8_t)(v) << BP_USB_BDTPAGE2_BDTBA) & BM_USB_BDTPAGE2_BDTBA)
2699 /*! @brief Set the BDTBA field to a new value. */
2700 #define BW_USB_BDTPAGE2_BDTBA(x, v) (HW_USB_BDTPAGE2_WR(x, v))
2703 /*******************************************************************************
2704 * HW_USB_BDTPAGE3 - BDT Page Register 3
2705 ******************************************************************************/
2708 * @brief HW_USB_BDTPAGE3 - BDT Page Register 3 (RW)
2710 * Reset value: 0x00U
2712 * Contains an 8-bit value used to compute the address where the current Buffer
2713 * Descriptor Table (BDT) resides in system memory.
2715 typedef union _hw_usb_bdtpage3
2718 struct _hw_usb_bdtpage3_bitfields
2720 uint8_t BDTBA
: 8; /*!< [7:0] */
2722 } hw_usb_bdtpage3_t
;
2725 * @name Constants and macros for entire USB_BDTPAGE3 register
2728 #define HW_USB_BDTPAGE3_ADDR(x) ((x) + 0xB4U)
2730 #define HW_USB_BDTPAGE3(x) (*(__IO hw_usb_bdtpage3_t *) HW_USB_BDTPAGE3_ADDR(x))
2731 #define HW_USB_BDTPAGE3_RD(x) (HW_USB_BDTPAGE3(x).U)
2732 #define HW_USB_BDTPAGE3_WR(x, v) (HW_USB_BDTPAGE3(x).U = (v))
2733 #define HW_USB_BDTPAGE3_SET(x, v) (HW_USB_BDTPAGE3_WR(x, HW_USB_BDTPAGE3_RD(x) | (v)))
2734 #define HW_USB_BDTPAGE3_CLR(x, v) (HW_USB_BDTPAGE3_WR(x, HW_USB_BDTPAGE3_RD(x) & ~(v)))
2735 #define HW_USB_BDTPAGE3_TOG(x, v) (HW_USB_BDTPAGE3_WR(x, HW_USB_BDTPAGE3_RD(x) ^ (v)))
2739 * Constants & macros for individual USB_BDTPAGE3 bitfields
2743 * @name Register USB_BDTPAGE3, field BDTBA[7:0] (RW)
2745 * Provides address bits 31 through 24 of the BDT base address that defines the
2746 * location of Buffer Descriptor Table resides in system memory.
2749 #define BP_USB_BDTPAGE3_BDTBA (0U) /*!< Bit position for USB_BDTPAGE3_BDTBA. */
2750 #define BM_USB_BDTPAGE3_BDTBA (0xFFU) /*!< Bit mask for USB_BDTPAGE3_BDTBA. */
2751 #define BS_USB_BDTPAGE3_BDTBA (8U) /*!< Bit field size in bits for USB_BDTPAGE3_BDTBA. */
2753 /*! @brief Read current value of the USB_BDTPAGE3_BDTBA field. */
2754 #define BR_USB_BDTPAGE3_BDTBA(x) (HW_USB_BDTPAGE3(x).U)
2756 /*! @brief Format value for bitfield USB_BDTPAGE3_BDTBA. */
2757 #define BF_USB_BDTPAGE3_BDTBA(v) ((uint8_t)((uint8_t)(v) << BP_USB_BDTPAGE3_BDTBA) & BM_USB_BDTPAGE3_BDTBA)
2759 /*! @brief Set the BDTBA field to a new value. */
2760 #define BW_USB_BDTPAGE3_BDTBA(x, v) (HW_USB_BDTPAGE3_WR(x, v))
2763 /*******************************************************************************
2764 * HW_USB_ENDPTn - Endpoint Control register
2765 ******************************************************************************/
2768 * @brief HW_USB_ENDPTn - Endpoint Control register (RW)
2770 * Reset value: 0x00U
2772 * Contains the endpoint control bits for each of the 16 endpoints available
2773 * within the USB module for a decoded address. The format for these registers is
2774 * shown in the following figure. Endpoint 0 (ENDPT0) is associated with control
2775 * pipe 0, which is required for all USB functions. Therefore, after a USBRST
2776 * interrupt occurs the processor core should set ENDPT0 to contain 0x0D. In Host mode
2777 * ENDPT0 is used to determine the handshake, retry and low speed
2778 * characteristics of the host transfer. For Control, Bulk and Interrupt transfers, the EPHSHK
2779 * bit should be 1. For Isochronous transfers it should be 0. Common values to
2780 * use for ENDPT0 in host mode are 0x4D for Control, Bulk, and Interrupt transfers,
2781 * and 0x4C for Isochronous transfers.
2783 typedef union _hw_usb_endptn
2786 struct _hw_usb_endptn_bitfields
2788 uint8_t EPHSHK
: 1; /*!< [0] */
2789 uint8_t EPSTALL
: 1; /*!< [1] */
2790 uint8_t EPTXEN
: 1; /*!< [2] */
2791 uint8_t EPRXEN
: 1; /*!< [3] */
2792 uint8_t EPCTLDIS
: 1; /*!< [4] */
2793 uint8_t RESERVED0
: 1; /*!< [5] */
2794 uint8_t RETRYDIS
: 1; /*!< [6] */
2795 uint8_t HOSTWOHUB
: 1; /*!< [7] */
2800 * @name Constants and macros for entire USB_ENDPTn register
2803 #define HW_USB_ENDPTn_COUNT (16U)
2805 #define HW_USB_ENDPTn_ADDR(x, n) ((x) + 0xC0U + (0x4U * (n)))
2807 #define HW_USB_ENDPTn(x, n) (*(__IO hw_usb_endptn_t *) HW_USB_ENDPTn_ADDR(x, n))
2808 #define HW_USB_ENDPTn_RD(x, n) (HW_USB_ENDPTn(x, n).U)
2809 #define HW_USB_ENDPTn_WR(x, n, v) (HW_USB_ENDPTn(x, n).U = (v))
2810 #define HW_USB_ENDPTn_SET(x, n, v) (HW_USB_ENDPTn_WR(x, n, HW_USB_ENDPTn_RD(x, n) | (v)))
2811 #define HW_USB_ENDPTn_CLR(x, n, v) (HW_USB_ENDPTn_WR(x, n, HW_USB_ENDPTn_RD(x, n) & ~(v)))
2812 #define HW_USB_ENDPTn_TOG(x, n, v) (HW_USB_ENDPTn_WR(x, n, HW_USB_ENDPTn_RD(x, n) ^ (v)))
2816 * Constants & macros for individual USB_ENDPTn bitfields
2820 * @name Register USB_ENDPTn, field EPHSHK[0] (RW)
2822 * When set this bit enables an endpoint to perform handshaking during a
2823 * transaction to this endpoint. This bit is generally 1 unless the endpoint is
2827 #define BP_USB_ENDPTn_EPHSHK (0U) /*!< Bit position for USB_ENDPTn_EPHSHK. */
2828 #define BM_USB_ENDPTn_EPHSHK (0x01U) /*!< Bit mask for USB_ENDPTn_EPHSHK. */
2829 #define BS_USB_ENDPTn_EPHSHK (1U) /*!< Bit field size in bits for USB_ENDPTn_EPHSHK. */
2831 /*! @brief Read current value of the USB_ENDPTn_EPHSHK field. */
2832 #define BR_USB_ENDPTn_EPHSHK(x, n) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_EPHSHK))
2834 /*! @brief Format value for bitfield USB_ENDPTn_EPHSHK. */
2835 #define BF_USB_ENDPTn_EPHSHK(v) ((uint8_t)((uint8_t)(v) << BP_USB_ENDPTn_EPHSHK) & BM_USB_ENDPTn_EPHSHK)
2837 /*! @brief Set the EPHSHK field to a new value. */
2838 #define BW_USB_ENDPTn_EPHSHK(x, n, v) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_EPHSHK) = (v))
2842 * @name Register USB_ENDPTn, field EPSTALL[1] (RW)
2844 * When set this bit indicates that the endpoint is called. This bit has
2845 * priority over all other control bits in the EndPoint Enable Register, but it is only
2846 * valid if EPTXEN=1 or EPRXEN=1. Any access to this endpoint causes the USB
2847 * Module to return a STALL handshake. After an endpoint is stalled it requires
2848 * intervention from the Host Controller.
2851 #define BP_USB_ENDPTn_EPSTALL (1U) /*!< Bit position for USB_ENDPTn_EPSTALL. */
2852 #define BM_USB_ENDPTn_EPSTALL (0x02U) /*!< Bit mask for USB_ENDPTn_EPSTALL. */
2853 #define BS_USB_ENDPTn_EPSTALL (1U) /*!< Bit field size in bits for USB_ENDPTn_EPSTALL. */
2855 /*! @brief Read current value of the USB_ENDPTn_EPSTALL field. */
2856 #define BR_USB_ENDPTn_EPSTALL(x, n) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_EPSTALL))
2858 /*! @brief Format value for bitfield USB_ENDPTn_EPSTALL. */
2859 #define BF_USB_ENDPTn_EPSTALL(v) ((uint8_t)((uint8_t)(v) << BP_USB_ENDPTn_EPSTALL) & BM_USB_ENDPTn_EPSTALL)
2861 /*! @brief Set the EPSTALL field to a new value. */
2862 #define BW_USB_ENDPTn_EPSTALL(x, n, v) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_EPSTALL) = (v))
2866 * @name Register USB_ENDPTn, field EPTXEN[2] (RW)
2868 * This bit, when set, enables the endpoint for TX transfers.
2871 #define BP_USB_ENDPTn_EPTXEN (2U) /*!< Bit position for USB_ENDPTn_EPTXEN. */
2872 #define BM_USB_ENDPTn_EPTXEN (0x04U) /*!< Bit mask for USB_ENDPTn_EPTXEN. */
2873 #define BS_USB_ENDPTn_EPTXEN (1U) /*!< Bit field size in bits for USB_ENDPTn_EPTXEN. */
2875 /*! @brief Read current value of the USB_ENDPTn_EPTXEN field. */
2876 #define BR_USB_ENDPTn_EPTXEN(x, n) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_EPTXEN))
2878 /*! @brief Format value for bitfield USB_ENDPTn_EPTXEN. */
2879 #define BF_USB_ENDPTn_EPTXEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_ENDPTn_EPTXEN) & BM_USB_ENDPTn_EPTXEN)
2881 /*! @brief Set the EPTXEN field to a new value. */
2882 #define BW_USB_ENDPTn_EPTXEN(x, n, v) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_EPTXEN) = (v))
2886 * @name Register USB_ENDPTn, field EPRXEN[3] (RW)
2888 * This bit, when set, enables the endpoint for RX transfers.
2891 #define BP_USB_ENDPTn_EPRXEN (3U) /*!< Bit position for USB_ENDPTn_EPRXEN. */
2892 #define BM_USB_ENDPTn_EPRXEN (0x08U) /*!< Bit mask for USB_ENDPTn_EPRXEN. */
2893 #define BS_USB_ENDPTn_EPRXEN (1U) /*!< Bit field size in bits for USB_ENDPTn_EPRXEN. */
2895 /*! @brief Read current value of the USB_ENDPTn_EPRXEN field. */
2896 #define BR_USB_ENDPTn_EPRXEN(x, n) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_EPRXEN))
2898 /*! @brief Format value for bitfield USB_ENDPTn_EPRXEN. */
2899 #define BF_USB_ENDPTn_EPRXEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_ENDPTn_EPRXEN) & BM_USB_ENDPTn_EPRXEN)
2901 /*! @brief Set the EPRXEN field to a new value. */
2902 #define BW_USB_ENDPTn_EPRXEN(x, n, v) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_EPRXEN) = (v))
2906 * @name Register USB_ENDPTn, field EPCTLDIS[4] (RW)
2908 * This bit, when set, disables control (SETUP) transfers. When cleared, control
2909 * transfers are enabled. This applies if and only if the EPRXEN and EPTXEN bits
2913 #define BP_USB_ENDPTn_EPCTLDIS (4U) /*!< Bit position for USB_ENDPTn_EPCTLDIS. */
2914 #define BM_USB_ENDPTn_EPCTLDIS (0x10U) /*!< Bit mask for USB_ENDPTn_EPCTLDIS. */
2915 #define BS_USB_ENDPTn_EPCTLDIS (1U) /*!< Bit field size in bits for USB_ENDPTn_EPCTLDIS. */
2917 /*! @brief Read current value of the USB_ENDPTn_EPCTLDIS field. */
2918 #define BR_USB_ENDPTn_EPCTLDIS(x, n) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_EPCTLDIS))
2920 /*! @brief Format value for bitfield USB_ENDPTn_EPCTLDIS. */
2921 #define BF_USB_ENDPTn_EPCTLDIS(v) ((uint8_t)((uint8_t)(v) << BP_USB_ENDPTn_EPCTLDIS) & BM_USB_ENDPTn_EPCTLDIS)
2923 /*! @brief Set the EPCTLDIS field to a new value. */
2924 #define BW_USB_ENDPTn_EPCTLDIS(x, n, v) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_EPCTLDIS) = (v))
2928 * @name Register USB_ENDPTn, field RETRYDIS[6] (RW)
2930 * This is a Host mode only bit and is present in the control register for
2931 * endpoint 0 (ENDPT0) only. When set this bit causes the host to not retry NAK'ed
2932 * (Negative Acknowledgement) transactions. When a transaction is NAKed, the BDT PID
2933 * field is updated with the NAK PID, and the TOKEN_DNE interrupt is set. When
2934 * this bit is cleared, NAKed transactions are retried in hardware. This bit must
2935 * be set when the host is attempting to poll an interrupt endpoint.
2938 #define BP_USB_ENDPTn_RETRYDIS (6U) /*!< Bit position for USB_ENDPTn_RETRYDIS. */
2939 #define BM_USB_ENDPTn_RETRYDIS (0x40U) /*!< Bit mask for USB_ENDPTn_RETRYDIS. */
2940 #define BS_USB_ENDPTn_RETRYDIS (1U) /*!< Bit field size in bits for USB_ENDPTn_RETRYDIS. */
2942 /*! @brief Read current value of the USB_ENDPTn_RETRYDIS field. */
2943 #define BR_USB_ENDPTn_RETRYDIS(x, n) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_RETRYDIS))
2945 /*! @brief Format value for bitfield USB_ENDPTn_RETRYDIS. */
2946 #define BF_USB_ENDPTn_RETRYDIS(v) ((uint8_t)((uint8_t)(v) << BP_USB_ENDPTn_RETRYDIS) & BM_USB_ENDPTn_RETRYDIS)
2948 /*! @brief Set the RETRYDIS field to a new value. */
2949 #define BW_USB_ENDPTn_RETRYDIS(x, n, v) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_RETRYDIS) = (v))
2953 * @name Register USB_ENDPTn, field HOSTWOHUB[7] (RW)
2955 * This is a Host mode only field and is present in the control register for
2956 * endpoint 0 (ENDPT0) only. When set this bit allows the host to communicate to a
2957 * directly connected low speed device. When cleared, the host produces the
2958 * PRE_PID. It then switches to low-speed signaling when sending a token to a low speed
2959 * device as required to communicate with a low speed device through a hub.
2962 #define BP_USB_ENDPTn_HOSTWOHUB (7U) /*!< Bit position for USB_ENDPTn_HOSTWOHUB. */
2963 #define BM_USB_ENDPTn_HOSTWOHUB (0x80U) /*!< Bit mask for USB_ENDPTn_HOSTWOHUB. */
2964 #define BS_USB_ENDPTn_HOSTWOHUB (1U) /*!< Bit field size in bits for USB_ENDPTn_HOSTWOHUB. */
2966 /*! @brief Read current value of the USB_ENDPTn_HOSTWOHUB field. */
2967 #define BR_USB_ENDPTn_HOSTWOHUB(x, n) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_HOSTWOHUB))
2969 /*! @brief Format value for bitfield USB_ENDPTn_HOSTWOHUB. */
2970 #define BF_USB_ENDPTn_HOSTWOHUB(v) ((uint8_t)((uint8_t)(v) << BP_USB_ENDPTn_HOSTWOHUB) & BM_USB_ENDPTn_HOSTWOHUB)
2972 /*! @brief Set the HOSTWOHUB field to a new value. */
2973 #define BW_USB_ENDPTn_HOSTWOHUB(x, n, v) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_HOSTWOHUB) = (v))
2976 /*******************************************************************************
2977 * HW_USB_USBCTRL - USB Control register
2978 ******************************************************************************/
2981 * @brief HW_USB_USBCTRL - USB Control register (RW)
2983 * Reset value: 0xC0U
2985 typedef union _hw_usb_usbctrl
2988 struct _hw_usb_usbctrl_bitfields
2990 uint8_t RESERVED0
: 6; /*!< [5:0] */
2991 uint8_t PDE
: 1; /*!< [6] */
2992 uint8_t SUSP
: 1; /*!< [7] */
2997 * @name Constants and macros for entire USB_USBCTRL register
3000 #define HW_USB_USBCTRL_ADDR(x) ((x) + 0x100U)
3002 #define HW_USB_USBCTRL(x) (*(__IO hw_usb_usbctrl_t *) HW_USB_USBCTRL_ADDR(x))
3003 #define HW_USB_USBCTRL_RD(x) (HW_USB_USBCTRL(x).U)
3004 #define HW_USB_USBCTRL_WR(x, v) (HW_USB_USBCTRL(x).U = (v))
3005 #define HW_USB_USBCTRL_SET(x, v) (HW_USB_USBCTRL_WR(x, HW_USB_USBCTRL_RD(x) | (v)))
3006 #define HW_USB_USBCTRL_CLR(x, v) (HW_USB_USBCTRL_WR(x, HW_USB_USBCTRL_RD(x) & ~(v)))
3007 #define HW_USB_USBCTRL_TOG(x, v) (HW_USB_USBCTRL_WR(x, HW_USB_USBCTRL_RD(x) ^ (v)))
3011 * Constants & macros for individual USB_USBCTRL bitfields
3015 * @name Register USB_USBCTRL, field PDE[6] (RW)
3017 * Enables the weak pulldowns on the USB transceiver.
3020 * - 0 - Weak pulldowns are disabled on D+ and D-.
3021 * - 1 - Weak pulldowns are enabled on D+ and D-.
3024 #define BP_USB_USBCTRL_PDE (6U) /*!< Bit position for USB_USBCTRL_PDE. */
3025 #define BM_USB_USBCTRL_PDE (0x40U) /*!< Bit mask for USB_USBCTRL_PDE. */
3026 #define BS_USB_USBCTRL_PDE (1U) /*!< Bit field size in bits for USB_USBCTRL_PDE. */
3028 /*! @brief Read current value of the USB_USBCTRL_PDE field. */
3029 #define BR_USB_USBCTRL_PDE(x) (BITBAND_ACCESS8(HW_USB_USBCTRL_ADDR(x), BP_USB_USBCTRL_PDE))
3031 /*! @brief Format value for bitfield USB_USBCTRL_PDE. */
3032 #define BF_USB_USBCTRL_PDE(v) ((uint8_t)((uint8_t)(v) << BP_USB_USBCTRL_PDE) & BM_USB_USBCTRL_PDE)
3034 /*! @brief Set the PDE field to a new value. */
3035 #define BW_USB_USBCTRL_PDE(x, v) (BITBAND_ACCESS8(HW_USB_USBCTRL_ADDR(x), BP_USB_USBCTRL_PDE) = (v))
3039 * @name Register USB_USBCTRL, field SUSP[7] (RW)
3041 * Places the USB transceiver into the suspend state.
3044 * - 0 - USB transceiver is not in suspend state.
3045 * - 1 - USB transceiver is in suspend state.
3048 #define BP_USB_USBCTRL_SUSP (7U) /*!< Bit position for USB_USBCTRL_SUSP. */
3049 #define BM_USB_USBCTRL_SUSP (0x80U) /*!< Bit mask for USB_USBCTRL_SUSP. */
3050 #define BS_USB_USBCTRL_SUSP (1U) /*!< Bit field size in bits for USB_USBCTRL_SUSP. */
3052 /*! @brief Read current value of the USB_USBCTRL_SUSP field. */
3053 #define BR_USB_USBCTRL_SUSP(x) (BITBAND_ACCESS8(HW_USB_USBCTRL_ADDR(x), BP_USB_USBCTRL_SUSP))
3055 /*! @brief Format value for bitfield USB_USBCTRL_SUSP. */
3056 #define BF_USB_USBCTRL_SUSP(v) ((uint8_t)((uint8_t)(v) << BP_USB_USBCTRL_SUSP) & BM_USB_USBCTRL_SUSP)
3058 /*! @brief Set the SUSP field to a new value. */
3059 #define BW_USB_USBCTRL_SUSP(x, v) (BITBAND_ACCESS8(HW_USB_USBCTRL_ADDR(x), BP_USB_USBCTRL_SUSP) = (v))
3062 /*******************************************************************************
3063 * HW_USB_OBSERVE - USB OTG Observe register
3064 ******************************************************************************/
3067 * @brief HW_USB_OBSERVE - USB OTG Observe register (RO)
3069 * Reset value: 0x50U
3071 * Provides visibility on the state of the pull-ups and pull-downs at the
3072 * transceiver. Useful when interfacing to an external OTG control module via a serial
3075 typedef union _hw_usb_observe
3078 struct _hw_usb_observe_bitfields
3080 uint8_t RESERVED0
: 4; /*!< [3:0] */
3081 uint8_t DMPD
: 1; /*!< [4] */
3082 uint8_t RESERVED1
: 1; /*!< [5] */
3083 uint8_t DPPD
: 1; /*!< [6] */
3084 uint8_t DPPU
: 1; /*!< [7] */
3089 * @name Constants and macros for entire USB_OBSERVE register
3092 #define HW_USB_OBSERVE_ADDR(x) ((x) + 0x104U)
3094 #define HW_USB_OBSERVE(x) (*(__I hw_usb_observe_t *) HW_USB_OBSERVE_ADDR(x))
3095 #define HW_USB_OBSERVE_RD(x) (HW_USB_OBSERVE(x).U)
3099 * Constants & macros for individual USB_OBSERVE bitfields
3103 * @name Register USB_OBSERVE, field DMPD[4] (RO)
3105 * Provides observability of the D- Pulldown enable at the USB transceiver.
3108 * - 0 - D- pulldown disabled.
3109 * - 1 - D- pulldown enabled.
3112 #define BP_USB_OBSERVE_DMPD (4U) /*!< Bit position for USB_OBSERVE_DMPD. */
3113 #define BM_USB_OBSERVE_DMPD (0x10U) /*!< Bit mask for USB_OBSERVE_DMPD. */
3114 #define BS_USB_OBSERVE_DMPD (1U) /*!< Bit field size in bits for USB_OBSERVE_DMPD. */
3116 /*! @brief Read current value of the USB_OBSERVE_DMPD field. */
3117 #define BR_USB_OBSERVE_DMPD(x) (BITBAND_ACCESS8(HW_USB_OBSERVE_ADDR(x), BP_USB_OBSERVE_DMPD))
3121 * @name Register USB_OBSERVE, field DPPD[6] (RO)
3123 * Provides observability of the D+ Pulldown enable at the USB transceiver.
3126 * - 0 - D+ pulldown disabled.
3127 * - 1 - D+ pulldown enabled.
3130 #define BP_USB_OBSERVE_DPPD (6U) /*!< Bit position for USB_OBSERVE_DPPD. */
3131 #define BM_USB_OBSERVE_DPPD (0x40U) /*!< Bit mask for USB_OBSERVE_DPPD. */
3132 #define BS_USB_OBSERVE_DPPD (1U) /*!< Bit field size in bits for USB_OBSERVE_DPPD. */
3134 /*! @brief Read current value of the USB_OBSERVE_DPPD field. */
3135 #define BR_USB_OBSERVE_DPPD(x) (BITBAND_ACCESS8(HW_USB_OBSERVE_ADDR(x), BP_USB_OBSERVE_DPPD))
3139 * @name Register USB_OBSERVE, field DPPU[7] (RO)
3141 * Provides observability of the D+ Pullup enable at the USB transceiver.
3144 * - 0 - D+ pullup disabled.
3145 * - 1 - D+ pullup enabled.
3148 #define BP_USB_OBSERVE_DPPU (7U) /*!< Bit position for USB_OBSERVE_DPPU. */
3149 #define BM_USB_OBSERVE_DPPU (0x80U) /*!< Bit mask for USB_OBSERVE_DPPU. */
3150 #define BS_USB_OBSERVE_DPPU (1U) /*!< Bit field size in bits for USB_OBSERVE_DPPU. */
3152 /*! @brief Read current value of the USB_OBSERVE_DPPU field. */
3153 #define BR_USB_OBSERVE_DPPU(x) (BITBAND_ACCESS8(HW_USB_OBSERVE_ADDR(x), BP_USB_OBSERVE_DPPU))
3156 /*******************************************************************************
3157 * HW_USB_CONTROL - USB OTG Control register
3158 ******************************************************************************/
3161 * @brief HW_USB_CONTROL - USB OTG Control register (RW)
3163 * Reset value: 0x00U
3165 typedef union _hw_usb_control
3168 struct _hw_usb_control_bitfields
3170 uint8_t RESERVED0
: 4; /*!< [3:0] */
3171 uint8_t DPPULLUPNONOTG
: 1; /*!< [4] */
3172 uint8_t RESERVED1
: 3; /*!< [7:5] */
3177 * @name Constants and macros for entire USB_CONTROL register
3180 #define HW_USB_CONTROL_ADDR(x) ((x) + 0x108U)
3182 #define HW_USB_CONTROL(x) (*(__IO hw_usb_control_t *) HW_USB_CONTROL_ADDR(x))
3183 #define HW_USB_CONTROL_RD(x) (HW_USB_CONTROL(x).U)
3184 #define HW_USB_CONTROL_WR(x, v) (HW_USB_CONTROL(x).U = (v))
3185 #define HW_USB_CONTROL_SET(x, v) (HW_USB_CONTROL_WR(x, HW_USB_CONTROL_RD(x) | (v)))
3186 #define HW_USB_CONTROL_CLR(x, v) (HW_USB_CONTROL_WR(x, HW_USB_CONTROL_RD(x) & ~(v)))
3187 #define HW_USB_CONTROL_TOG(x, v) (HW_USB_CONTROL_WR(x, HW_USB_CONTROL_RD(x) ^ (v)))
3191 * Constants & macros for individual USB_CONTROL bitfields
3195 * @name Register USB_CONTROL, field DPPULLUPNONOTG[4] (RW)
3197 * Provides control of the DP Pullup in USBOTG, if USB is configured in non-OTG
3201 * - 0 - DP Pullup in non-OTG device mode is not enabled.
3202 * - 1 - DP Pullup in non-OTG device mode is enabled.
3205 #define BP_USB_CONTROL_DPPULLUPNONOTG (4U) /*!< Bit position for USB_CONTROL_DPPULLUPNONOTG. */
3206 #define BM_USB_CONTROL_DPPULLUPNONOTG (0x10U) /*!< Bit mask for USB_CONTROL_DPPULLUPNONOTG. */
3207 #define BS_USB_CONTROL_DPPULLUPNONOTG (1U) /*!< Bit field size in bits for USB_CONTROL_DPPULLUPNONOTG. */
3209 /*! @brief Read current value of the USB_CONTROL_DPPULLUPNONOTG field. */
3210 #define BR_USB_CONTROL_DPPULLUPNONOTG(x) (BITBAND_ACCESS8(HW_USB_CONTROL_ADDR(x), BP_USB_CONTROL_DPPULLUPNONOTG))
3212 /*! @brief Format value for bitfield USB_CONTROL_DPPULLUPNONOTG. */
3213 #define BF_USB_CONTROL_DPPULLUPNONOTG(v) ((uint8_t)((uint8_t)(v) << BP_USB_CONTROL_DPPULLUPNONOTG) & BM_USB_CONTROL_DPPULLUPNONOTG)
3215 /*! @brief Set the DPPULLUPNONOTG field to a new value. */
3216 #define BW_USB_CONTROL_DPPULLUPNONOTG(x, v) (BITBAND_ACCESS8(HW_USB_CONTROL_ADDR(x), BP_USB_CONTROL_DPPULLUPNONOTG) = (v))
3219 /*******************************************************************************
3220 * HW_USB_USBTRC0 - USB Transceiver Control register 0
3221 ******************************************************************************/
3224 * @brief HW_USB_USBTRC0 - USB Transceiver Control register 0 (RW)
3226 * Reset value: 0x00U
3228 * Includes signals for basic operation of the on-chip USB Full Speed
3229 * transceiver and configuration of the USB data connection that are not otherwise included
3230 * in the USB Full Speed controller registers.
3232 typedef union _hw_usb_usbtrc0
3235 struct _hw_usb_usbtrc0_bitfields
3237 uint8_t USB_RESUME_INT
: 1; /*!< [0] USB Asynchronous Interrupt */
3238 uint8_t SYNC_DET
: 1; /*!< [1] Synchronous USB Interrupt Detect */
3239 uint8_t USB_CLK_RECOVERY_INT
: 1; /*!< [2] Combined USB Clock
3240 * Recovery interrupt status */
3241 uint8_t RESERVED0
: 2; /*!< [4:3] */
3242 uint8_t USBRESMEN
: 1; /*!< [5] Asynchronous Resume Interrupt Enable
3244 uint8_t RESERVED1
: 1; /*!< [6] */
3245 uint8_t USBRESET
: 1; /*!< [7] USB Reset */
3250 * @name Constants and macros for entire USB_USBTRC0 register
3253 #define HW_USB_USBTRC0_ADDR(x) ((x) + 0x10CU)
3255 #define HW_USB_USBTRC0(x) (*(__IO hw_usb_usbtrc0_t *) HW_USB_USBTRC0_ADDR(x))
3256 #define HW_USB_USBTRC0_RD(x) (HW_USB_USBTRC0(x).U)
3257 #define HW_USB_USBTRC0_WR(x, v) (HW_USB_USBTRC0(x).U = (v))
3258 #define HW_USB_USBTRC0_SET(x, v) (HW_USB_USBTRC0_WR(x, HW_USB_USBTRC0_RD(x) | (v)))
3259 #define HW_USB_USBTRC0_CLR(x, v) (HW_USB_USBTRC0_WR(x, HW_USB_USBTRC0_RD(x) & ~(v)))
3260 #define HW_USB_USBTRC0_TOG(x, v) (HW_USB_USBTRC0_WR(x, HW_USB_USBTRC0_RD(x) ^ (v)))
3264 * Constants & macros for individual USB_USBTRC0 bitfields
3268 * @name Register USB_USBTRC0, field USB_RESUME_INT[0] (RO)
3271 * - 0 - No interrupt was generated.
3272 * - 1 - Interrupt was generated because of the USB asynchronous interrupt.
3275 #define BP_USB_USBTRC0_USB_RESUME_INT (0U) /*!< Bit position for USB_USBTRC0_USB_RESUME_INT. */
3276 #define BM_USB_USBTRC0_USB_RESUME_INT (0x01U) /*!< Bit mask for USB_USBTRC0_USB_RESUME_INT. */
3277 #define BS_USB_USBTRC0_USB_RESUME_INT (1U) /*!< Bit field size in bits for USB_USBTRC0_USB_RESUME_INT. */
3279 /*! @brief Read current value of the USB_USBTRC0_USB_RESUME_INT field. */
3280 #define BR_USB_USBTRC0_USB_RESUME_INT(x) (BITBAND_ACCESS8(HW_USB_USBTRC0_ADDR(x), BP_USB_USBTRC0_USB_RESUME_INT))
3284 * @name Register USB_USBTRC0, field SYNC_DET[1] (RO)
3287 * - 0 - Synchronous interrupt has not been detected.
3288 * - 1 - Synchronous interrupt has been detected.
3291 #define BP_USB_USBTRC0_SYNC_DET (1U) /*!< Bit position for USB_USBTRC0_SYNC_DET. */
3292 #define BM_USB_USBTRC0_SYNC_DET (0x02U) /*!< Bit mask for USB_USBTRC0_SYNC_DET. */
3293 #define BS_USB_USBTRC0_SYNC_DET (1U) /*!< Bit field size in bits for USB_USBTRC0_SYNC_DET. */
3295 /*! @brief Read current value of the USB_USBTRC0_SYNC_DET field. */
3296 #define BR_USB_USBTRC0_SYNC_DET(x) (BITBAND_ACCESS8(HW_USB_USBTRC0_ADDR(x), BP_USB_USBTRC0_SYNC_DET))
3300 * @name Register USB_USBTRC0, field USB_CLK_RECOVERY_INT[2] (RO)
3302 * This read-only field will be set to value high at 1'b1 when any of USB clock
3303 * recovery interrupt conditions are detected and those interrupts are unmasked.
3304 * For customer use the only unmasked USB clock recovery interrupt condition
3305 * results from an overflow of the frequency trim setting values indicating that the
3306 * frequency trim calculated is out of the adjustment range of the IRC48M output
3307 * clock. To clear this bit after it has been set, Write 0xFF to register
3308 * USB_CLK_RECOVER_INT_STATUS.
3311 #define BP_USB_USBTRC0_USB_CLK_RECOVERY_INT (2U) /*!< Bit position for USB_USBTRC0_USB_CLK_RECOVERY_INT. */
3312 #define BM_USB_USBTRC0_USB_CLK_RECOVERY_INT (0x04U) /*!< Bit mask for USB_USBTRC0_USB_CLK_RECOVERY_INT. */
3313 #define BS_USB_USBTRC0_USB_CLK_RECOVERY_INT (1U) /*!< Bit field size in bits for USB_USBTRC0_USB_CLK_RECOVERY_INT. */
3315 /*! @brief Read current value of the USB_USBTRC0_USB_CLK_RECOVERY_INT field. */
3316 #define BR_USB_USBTRC0_USB_CLK_RECOVERY_INT(x) (BITBAND_ACCESS8(HW_USB_USBTRC0_ADDR(x), BP_USB_USBTRC0_USB_CLK_RECOVERY_INT))
3320 * @name Register USB_USBTRC0, field USBRESMEN[5] (RW)
3322 * This bit, when set, allows the USB module to send an asynchronous wakeup
3323 * event to the MCU upon detection of resume signaling on the USB bus. The MCU then
3324 * re-enables clocks to the USB module. It is used for low-power suspend mode when
3325 * USB module clocks are stopped or the USB transceiver is in Suspend mode.
3326 * Async wakeup only works in device mode.
3329 * - 0 - USB asynchronous wakeup from suspend mode disabled.
3330 * - 1 - USB asynchronous wakeup from suspend mode enabled. The asynchronous
3331 * resume interrupt differs from the synchronous resume interrupt in that it
3332 * asynchronously detects K-state using the unfiltered state of the D+ and D-
3333 * pins. This interrupt should only be enabled when the Transceiver is
3337 #define BP_USB_USBTRC0_USBRESMEN (5U) /*!< Bit position for USB_USBTRC0_USBRESMEN. */
3338 #define BM_USB_USBTRC0_USBRESMEN (0x20U) /*!< Bit mask for USB_USBTRC0_USBRESMEN. */
3339 #define BS_USB_USBTRC0_USBRESMEN (1U) /*!< Bit field size in bits for USB_USBTRC0_USBRESMEN. */
3341 /*! @brief Read current value of the USB_USBTRC0_USBRESMEN field. */
3342 #define BR_USB_USBTRC0_USBRESMEN(x) (BITBAND_ACCESS8(HW_USB_USBTRC0_ADDR(x), BP_USB_USBTRC0_USBRESMEN))
3344 /*! @brief Format value for bitfield USB_USBTRC0_USBRESMEN. */
3345 #define BF_USB_USBTRC0_USBRESMEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_USBTRC0_USBRESMEN) & BM_USB_USBTRC0_USBRESMEN)
3347 /*! @brief Set the USBRESMEN field to a new value. */
3348 #define BW_USB_USBTRC0_USBRESMEN(x, v) (BITBAND_ACCESS8(HW_USB_USBTRC0_ADDR(x), BP_USB_USBTRC0_USBRESMEN) = (v))
3352 * @name Register USB_USBTRC0, field USBRESET[7] (WO)
3354 * Generates a hard reset to USBOTG. After this bit is set and the reset occurs,
3355 * this bit is automatically cleared. This bit is always read as zero. Wait two
3356 * USB clock cycles after setting this bit.
3359 * - 0 - Normal USB module operation.
3360 * - 1 - Returns the USB module to its reset state.
3363 #define BP_USB_USBTRC0_USBRESET (7U) /*!< Bit position for USB_USBTRC0_USBRESET. */
3364 #define BM_USB_USBTRC0_USBRESET (0x80U) /*!< Bit mask for USB_USBTRC0_USBRESET. */
3365 #define BS_USB_USBTRC0_USBRESET (1U) /*!< Bit field size in bits for USB_USBTRC0_USBRESET. */
3367 /*! @brief Format value for bitfield USB_USBTRC0_USBRESET. */
3368 #define BF_USB_USBTRC0_USBRESET(v) ((uint8_t)((uint8_t)(v) << BP_USB_USBTRC0_USBRESET) & BM_USB_USBTRC0_USBRESET)
3371 /*******************************************************************************
3372 * HW_USB_USBFRMADJUST - Frame Adjust Register
3373 ******************************************************************************/
3376 * @brief HW_USB_USBFRMADJUST - Frame Adjust Register (RW)
3378 * Reset value: 0x00U
3380 typedef union _hw_usb_usbfrmadjust
3383 struct _hw_usb_usbfrmadjust_bitfields
3385 uint8_t ADJ
: 8; /*!< [7:0] Frame Adjustment */
3387 } hw_usb_usbfrmadjust_t
;
3390 * @name Constants and macros for entire USB_USBFRMADJUST register
3393 #define HW_USB_USBFRMADJUST_ADDR(x) ((x) + 0x114U)
3395 #define HW_USB_USBFRMADJUST(x) (*(__IO hw_usb_usbfrmadjust_t *) HW_USB_USBFRMADJUST_ADDR(x))
3396 #define HW_USB_USBFRMADJUST_RD(x) (HW_USB_USBFRMADJUST(x).U)
3397 #define HW_USB_USBFRMADJUST_WR(x, v) (HW_USB_USBFRMADJUST(x).U = (v))
3398 #define HW_USB_USBFRMADJUST_SET(x, v) (HW_USB_USBFRMADJUST_WR(x, HW_USB_USBFRMADJUST_RD(x) | (v)))
3399 #define HW_USB_USBFRMADJUST_CLR(x, v) (HW_USB_USBFRMADJUST_WR(x, HW_USB_USBFRMADJUST_RD(x) & ~(v)))
3400 #define HW_USB_USBFRMADJUST_TOG(x, v) (HW_USB_USBFRMADJUST_WR(x, HW_USB_USBFRMADJUST_RD(x) ^ (v)))
3404 * Constants & macros for individual USB_USBFRMADJUST bitfields
3408 * @name Register USB_USBFRMADJUST, field ADJ[7:0] (RW)
3410 * In Host mode, the frame adjustment is a twos complement number that adjusts
3411 * the period of each USB frame in 12-MHz clock periods. A SOF is normally
3412 * generated every 12,000 12-MHz clock cycles. The Frame Adjust Register can adjust this
3413 * by -128 to +127 to compensate for inaccuracies in the USB 48-MHz clock.
3414 * Changes to the ADJ bit take effect at the next start of the next frame.
3417 #define BP_USB_USBFRMADJUST_ADJ (0U) /*!< Bit position for USB_USBFRMADJUST_ADJ. */
3418 #define BM_USB_USBFRMADJUST_ADJ (0xFFU) /*!< Bit mask for USB_USBFRMADJUST_ADJ. */
3419 #define BS_USB_USBFRMADJUST_ADJ (8U) /*!< Bit field size in bits for USB_USBFRMADJUST_ADJ. */
3421 /*! @brief Read current value of the USB_USBFRMADJUST_ADJ field. */
3422 #define BR_USB_USBFRMADJUST_ADJ(x) (HW_USB_USBFRMADJUST(x).U)
3424 /*! @brief Format value for bitfield USB_USBFRMADJUST_ADJ. */
3425 #define BF_USB_USBFRMADJUST_ADJ(v) ((uint8_t)((uint8_t)(v) << BP_USB_USBFRMADJUST_ADJ) & BM_USB_USBFRMADJUST_ADJ)
3427 /*! @brief Set the ADJ field to a new value. */
3428 #define BW_USB_USBFRMADJUST_ADJ(x, v) (HW_USB_USBFRMADJUST_WR(x, v))
3431 /*******************************************************************************
3432 * HW_USB_CLK_RECOVER_CTRL - USB Clock recovery control
3433 ******************************************************************************/
3436 * @brief HW_USB_CLK_RECOVER_CTRL - USB Clock recovery control (RW)
3438 * Reset value: 0x00U
3440 * Signals in this register control the crystal-less USB clock mode in which the
3441 * internal IRC48M oscillator is tuned to match the clock extracted from the
3442 * incoming USB data stream. The IRC48M internal oscillator module must be enabled
3443 * in register USB_CLK_RECOVER_IRC_EN for this mode.
3445 typedef union _hw_usb_clk_recover_ctrl
3448 struct _hw_usb_clk_recover_ctrl_bitfields
3450 uint8_t RESERVED0
: 5; /*!< [4:0] */
3451 uint8_t RESTART_IFRTRIM_EN
: 1; /*!< [5] Restart from IFR trim value
3453 uint8_t RESET_RESUME_ROUGH_EN
: 1; /*!< [6] Reset/resume to rough
3455 uint8_t CLOCK_RECOVER_EN
: 1; /*!< [7] Crystal-less USB enable */
3457 } hw_usb_clk_recover_ctrl_t
;
3460 * @name Constants and macros for entire USB_CLK_RECOVER_CTRL register
3463 #define HW_USB_CLK_RECOVER_CTRL_ADDR(x) ((x) + 0x140U)
3465 #define HW_USB_CLK_RECOVER_CTRL(x) (*(__IO hw_usb_clk_recover_ctrl_t *) HW_USB_CLK_RECOVER_CTRL_ADDR(x))
3466 #define HW_USB_CLK_RECOVER_CTRL_RD(x) (HW_USB_CLK_RECOVER_CTRL(x).U)
3467 #define HW_USB_CLK_RECOVER_CTRL_WR(x, v) (HW_USB_CLK_RECOVER_CTRL(x).U = (v))
3468 #define HW_USB_CLK_RECOVER_CTRL_SET(x, v) (HW_USB_CLK_RECOVER_CTRL_WR(x, HW_USB_CLK_RECOVER_CTRL_RD(x) | (v)))
3469 #define HW_USB_CLK_RECOVER_CTRL_CLR(x, v) (HW_USB_CLK_RECOVER_CTRL_WR(x, HW_USB_CLK_RECOVER_CTRL_RD(x) & ~(v)))
3470 #define HW_USB_CLK_RECOVER_CTRL_TOG(x, v) (HW_USB_CLK_RECOVER_CTRL_WR(x, HW_USB_CLK_RECOVER_CTRL_RD(x) ^ (v)))
3474 * Constants & macros for individual USB_CLK_RECOVER_CTRL bitfields
3478 * @name Register USB_CLK_RECOVER_CTRL, field RESTART_IFRTRIM_EN[5] (RW)
3480 * IRC48 has a default trim fine value whose default value is factory trimmed
3481 * (the IFR trim value). Clock recover block tracks the accuracy of the clock 48Mhz
3482 * and keeps updating the trim fine value accordingly
3485 * - 0 - Trim fine adjustment always works based on the previous updated trim
3486 * fine value (default)
3487 * - 1 - Trim fine restarts from the IFR trim value whenever
3488 * bus_reset/bus_resume is detected or module enable is desasserted
3491 #define BP_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN (5U) /*!< Bit position for USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN. */
3492 #define BM_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN (0x20U) /*!< Bit mask for USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN. */
3493 #define BS_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN (1U) /*!< Bit field size in bits for USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN. */
3495 /*! @brief Read current value of the USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN field. */
3496 #define BR_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_CTRL_ADDR(x), BP_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN))
3498 /*! @brief Format value for bitfield USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN. */
3499 #define BF_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(v) ((uint8_t)((uint8_t)(v) << BP_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN) & BM_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN)
3501 /*! @brief Set the RESTART_IFRTRIM_EN field to a new value. */
3502 #define BW_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x, v) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_CTRL_ADDR(x), BP_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN) = (v))
3506 * @name Register USB_CLK_RECOVER_CTRL, field RESET_RESUME_ROUGH_EN[6] (RW)
3508 * The clock recovery block tracks the IRC48Mhz to get an accurate 48Mhz clock.
3509 * It has two phases after user enables clock_recover_en bit, rough phase and
3510 * tracking phase. The step to fine tune the IRC 48Mhz by adjusting the trim fine
3511 * value is different during these two phases. The step in rough phase is larger
3512 * than that in tracking phase. Switch back to rough stage whenever USB bus reset
3513 * or bus resume occurs.
3516 * - 0 - Always works in tracking phase after the 1st time rough to track
3517 * transition (default)
3518 * - 1 - Go back to rough stage whenever bus reset or bus resume occurs
3521 #define BP_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN (6U) /*!< Bit position for USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN. */
3522 #define BM_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN (0x40U) /*!< Bit mask for USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN. */
3523 #define BS_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN (1U) /*!< Bit field size in bits for USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN. */
3525 /*! @brief Read current value of the USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN field. */
3526 #define BR_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_CTRL_ADDR(x), BP_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN))
3528 /*! @brief Format value for bitfield USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN. */
3529 #define BF_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(v) ((uint8_t)((uint8_t)(v) << BP_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN) & BM_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN)
3531 /*! @brief Set the RESET_RESUME_ROUGH_EN field to a new value. */
3532 #define BW_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x, v) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_CTRL_ADDR(x), BP_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN) = (v))
3536 * @name Register USB_CLK_RECOVER_CTRL, field CLOCK_RECOVER_EN[7] (RW)
3538 * This bit must be enabled if user wants to use the crystal-less USB mode for
3539 * the Full Speed USB controller and transceiver. This bit should not be set for
3540 * USB host mode or OTG.
3543 * - 0 - Disable clock recovery block (default)
3544 * - 1 - Enable clock recovery block
3547 #define BP_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN (7U) /*!< Bit position for USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN. */
3548 #define BM_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN (0x80U) /*!< Bit mask for USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN. */
3549 #define BS_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN (1U) /*!< Bit field size in bits for USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN. */
3551 /*! @brief Read current value of the USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN field. */
3552 #define BR_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_CTRL_ADDR(x), BP_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN))
3554 /*! @brief Format value for bitfield USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN. */
3555 #define BF_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(v) ((uint8_t)((uint8_t)(v) << BP_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN) & BM_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN)
3557 /*! @brief Set the CLOCK_RECOVER_EN field to a new value. */
3558 #define BW_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x, v) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_CTRL_ADDR(x), BP_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN) = (v))
3561 /*******************************************************************************
3562 * HW_USB_CLK_RECOVER_IRC_EN - IRC48M oscillator enable register
3563 ******************************************************************************/
3566 * @brief HW_USB_CLK_RECOVER_IRC_EN - IRC48M oscillator enable register (RW)
3568 * Reset value: 0x01U
3570 * Controls basic operation of the on-chip IRC48M module used to produce nominal
3571 * 48MHz clocks for USB crystal-less operation and other functions. See
3572 * additional information about the IRC48M operation in the Clock Distribution chapter.
3574 typedef union _hw_usb_clk_recover_irc_en
3577 struct _hw_usb_clk_recover_irc_en_bitfields
3579 uint8_t REG_EN
: 1; /*!< [0] IRC48M regulator enable */
3580 uint8_t IRC_EN
: 1; /*!< [1] IRC48M enable */
3581 uint8_t RESERVED0
: 6; /*!< [7:2] */
3583 } hw_usb_clk_recover_irc_en_t
;
3586 * @name Constants and macros for entire USB_CLK_RECOVER_IRC_EN register
3589 #define HW_USB_CLK_RECOVER_IRC_EN_ADDR(x) ((x) + 0x144U)
3591 #define HW_USB_CLK_RECOVER_IRC_EN(x) (*(__IO hw_usb_clk_recover_irc_en_t *) HW_USB_CLK_RECOVER_IRC_EN_ADDR(x))
3592 #define HW_USB_CLK_RECOVER_IRC_EN_RD(x) (HW_USB_CLK_RECOVER_IRC_EN(x).U)
3593 #define HW_USB_CLK_RECOVER_IRC_EN_WR(x, v) (HW_USB_CLK_RECOVER_IRC_EN(x).U = (v))
3594 #define HW_USB_CLK_RECOVER_IRC_EN_SET(x, v) (HW_USB_CLK_RECOVER_IRC_EN_WR(x, HW_USB_CLK_RECOVER_IRC_EN_RD(x) | (v)))
3595 #define HW_USB_CLK_RECOVER_IRC_EN_CLR(x, v) (HW_USB_CLK_RECOVER_IRC_EN_WR(x, HW_USB_CLK_RECOVER_IRC_EN_RD(x) & ~(v)))
3596 #define HW_USB_CLK_RECOVER_IRC_EN_TOG(x, v) (HW_USB_CLK_RECOVER_IRC_EN_WR(x, HW_USB_CLK_RECOVER_IRC_EN_RD(x) ^ (v)))
3600 * Constants & macros for individual USB_CLK_RECOVER_IRC_EN bitfields
3604 * @name Register USB_CLK_RECOVER_IRC_EN, field REG_EN[0] (RW)
3606 * This bit is used to enable the local analog regulator for IRC48Mhz module.
3607 * This bit must be set if user wants to use the crystal-less USB clock
3611 * - 0 - IRC48M local regulator is disabled
3612 * - 1 - IRC48M local regulator is enabled (default)
3615 #define BP_USB_CLK_RECOVER_IRC_EN_REG_EN (0U) /*!< Bit position for USB_CLK_RECOVER_IRC_EN_REG_EN. */
3616 #define BM_USB_CLK_RECOVER_IRC_EN_REG_EN (0x01U) /*!< Bit mask for USB_CLK_RECOVER_IRC_EN_REG_EN. */
3617 #define BS_USB_CLK_RECOVER_IRC_EN_REG_EN (1U) /*!< Bit field size in bits for USB_CLK_RECOVER_IRC_EN_REG_EN. */
3619 /*! @brief Read current value of the USB_CLK_RECOVER_IRC_EN_REG_EN field. */
3620 #define BR_USB_CLK_RECOVER_IRC_EN_REG_EN(x) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_IRC_EN_ADDR(x), BP_USB_CLK_RECOVER_IRC_EN_REG_EN))
3622 /*! @brief Format value for bitfield USB_CLK_RECOVER_IRC_EN_REG_EN. */
3623 #define BF_USB_CLK_RECOVER_IRC_EN_REG_EN(v) ((uint8_t)((uint8_t)(v) << BP_USB_CLK_RECOVER_IRC_EN_REG_EN) & BM_USB_CLK_RECOVER_IRC_EN_REG_EN)
3625 /*! @brief Set the REG_EN field to a new value. */
3626 #define BW_USB_CLK_RECOVER_IRC_EN_REG_EN(x, v) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_IRC_EN_ADDR(x), BP_USB_CLK_RECOVER_IRC_EN_REG_EN) = (v))
3630 * @name Register USB_CLK_RECOVER_IRC_EN, field IRC_EN[1] (RW)
3632 * This bit is used to enable the on-chip IRC48Mhz module to generate clocks for
3633 * crystal-less USB. It can only be used for FS USB device mode operation. This
3634 * bit must be set before using the crystal-less USB clock configuration.
3637 * - 0 - Disable the IRC48M module (default)
3638 * - 1 - Enable the IRC48M module
3641 #define BP_USB_CLK_RECOVER_IRC_EN_IRC_EN (1U) /*!< Bit position for USB_CLK_RECOVER_IRC_EN_IRC_EN. */
3642 #define BM_USB_CLK_RECOVER_IRC_EN_IRC_EN (0x02U) /*!< Bit mask for USB_CLK_RECOVER_IRC_EN_IRC_EN. */
3643 #define BS_USB_CLK_RECOVER_IRC_EN_IRC_EN (1U) /*!< Bit field size in bits for USB_CLK_RECOVER_IRC_EN_IRC_EN. */
3645 /*! @brief Read current value of the USB_CLK_RECOVER_IRC_EN_IRC_EN field. */
3646 #define BR_USB_CLK_RECOVER_IRC_EN_IRC_EN(x) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_IRC_EN_ADDR(x), BP_USB_CLK_RECOVER_IRC_EN_IRC_EN))
3648 /*! @brief Format value for bitfield USB_CLK_RECOVER_IRC_EN_IRC_EN. */
3649 #define BF_USB_CLK_RECOVER_IRC_EN_IRC_EN(v) ((uint8_t)((uint8_t)(v) << BP_USB_CLK_RECOVER_IRC_EN_IRC_EN) & BM_USB_CLK_RECOVER_IRC_EN_IRC_EN)
3651 /*! @brief Set the IRC_EN field to a new value. */
3652 #define BW_USB_CLK_RECOVER_IRC_EN_IRC_EN(x, v) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_IRC_EN_ADDR(x), BP_USB_CLK_RECOVER_IRC_EN_IRC_EN) = (v))
3655 /*******************************************************************************
3656 * HW_USB_CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status
3657 ******************************************************************************/
3660 * @brief HW_USB_CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status (W1C)
3662 * Reset value: 0x00U
3664 * A Write operation with value high at 1'b1 on any combination of individual
3665 * bits will clear those bits.
3667 typedef union _hw_usb_clk_recover_int_status
3670 struct _hw_usb_clk_recover_int_status_bitfields
3672 uint8_t RESERVED0
: 4; /*!< [3:0] */
3673 uint8_t OVF_ERROR
: 1; /*!< [4] */
3674 uint8_t RESERVED1
: 3; /*!< [7:5] */
3676 } hw_usb_clk_recover_int_status_t
;
3679 * @name Constants and macros for entire USB_CLK_RECOVER_INT_STATUS register
3682 #define HW_USB_CLK_RECOVER_INT_STATUS_ADDR(x) ((x) + 0x15CU)
3684 #define HW_USB_CLK_RECOVER_INT_STATUS(x) (*(__IO hw_usb_clk_recover_int_status_t *) HW_USB_CLK_RECOVER_INT_STATUS_ADDR(x))
3685 #define HW_USB_CLK_RECOVER_INT_STATUS_RD(x) (HW_USB_CLK_RECOVER_INT_STATUS(x).U)
3686 #define HW_USB_CLK_RECOVER_INT_STATUS_WR(x, v) (HW_USB_CLK_RECOVER_INT_STATUS(x).U = (v))
3687 #define HW_USB_CLK_RECOVER_INT_STATUS_SET(x, v) (HW_USB_CLK_RECOVER_INT_STATUS_WR(x, HW_USB_CLK_RECOVER_INT_STATUS_RD(x) | (v)))
3688 #define HW_USB_CLK_RECOVER_INT_STATUS_CLR(x, v) (HW_USB_CLK_RECOVER_INT_STATUS_WR(x, HW_USB_CLK_RECOVER_INT_STATUS_RD(x) & ~(v)))
3689 #define HW_USB_CLK_RECOVER_INT_STATUS_TOG(x, v) (HW_USB_CLK_RECOVER_INT_STATUS_WR(x, HW_USB_CLK_RECOVER_INT_STATUS_RD(x) ^ (v)))
3693 * Constants & macros for individual USB_CLK_RECOVER_INT_STATUS bitfields
3697 * @name Register USB_CLK_RECOVER_INT_STATUS, field OVF_ERROR[4] (W1C)
3699 * Indicates that the USB clock recovery algorithm has detected that the
3700 * frequency trim adjustment needed for the IRC48M output clock is outside the available
3701 * TRIM_FINE adjustment range for the IRC48M module.
3704 * - 0 - No interrupt is reported
3705 * - 1 - Unmasked interrupt has been generated
3708 #define BP_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR (4U) /*!< Bit position for USB_CLK_RECOVER_INT_STATUS_OVF_ERROR. */
3709 #define BM_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR (0x10U) /*!< Bit mask for USB_CLK_RECOVER_INT_STATUS_OVF_ERROR. */
3710 #define BS_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR (1U) /*!< Bit field size in bits for USB_CLK_RECOVER_INT_STATUS_OVF_ERROR. */
3712 /*! @brief Read current value of the USB_CLK_RECOVER_INT_STATUS_OVF_ERROR field. */
3713 #define BR_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_INT_STATUS_ADDR(x), BP_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR))
3715 /*! @brief Format value for bitfield USB_CLK_RECOVER_INT_STATUS_OVF_ERROR. */
3716 #define BF_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(v) ((uint8_t)((uint8_t)(v) << BP_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR) & BM_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR)
3718 /*! @brief Set the OVF_ERROR field to a new value. */
3719 #define BW_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x, v) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_INT_STATUS_ADDR(x), BP_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR) = (v))
3722 /*******************************************************************************
3723 * hw_usb_t - module struct
3724 ******************************************************************************/
3726 * @brief All USB module registers.
3729 typedef struct _hw_usb
3731 __I hw_usb_perid_t PERID
; /*!< [0x0] Peripheral ID register */
3732 uint8_t _reserved0
[3];
3733 __I hw_usb_idcomp_t IDCOMP
; /*!< [0x4] Peripheral ID Complement register */
3734 uint8_t _reserved1
[3];
3735 __I hw_usb_rev_t REV
; /*!< [0x8] Peripheral Revision register */
3736 uint8_t _reserved2
[3];
3737 __I hw_usb_addinfo_t ADDINFO
; /*!< [0xC] Peripheral Additional Info register */
3738 uint8_t _reserved3
[3];
3739 __IO hw_usb_otgistat_t OTGISTAT
; /*!< [0x10] OTG Interrupt Status register */
3740 uint8_t _reserved4
[3];
3741 __IO hw_usb_otgicr_t OTGICR
; /*!< [0x14] OTG Interrupt Control register */
3742 uint8_t _reserved5
[3];
3743 __IO hw_usb_otgstat_t OTGSTAT
; /*!< [0x18] OTG Status register */
3744 uint8_t _reserved6
[3];
3745 __IO hw_usb_otgctl_t OTGCTL
; /*!< [0x1C] OTG Control register */
3746 uint8_t _reserved7
[99];
3747 __IO hw_usb_istat_t ISTAT
; /*!< [0x80] Interrupt Status register */
3748 uint8_t _reserved8
[3];
3749 __IO hw_usb_inten_t INTEN
; /*!< [0x84] Interrupt Enable register */
3750 uint8_t _reserved9
[3];
3751 __IO hw_usb_errstat_t ERRSTAT
; /*!< [0x88] Error Interrupt Status register */
3752 uint8_t _reserved10
[3];
3753 __IO hw_usb_erren_t ERREN
; /*!< [0x8C] Error Interrupt Enable register */
3754 uint8_t _reserved11
[3];
3755 __I hw_usb_stat_t STAT
; /*!< [0x90] Status register */
3756 uint8_t _reserved12
[3];
3757 __IO hw_usb_ctl_t CTL
; /*!< [0x94] Control register */
3758 uint8_t _reserved13
[3];
3759 __IO hw_usb_addr_t ADDR
; /*!< [0x98] Address register */
3760 uint8_t _reserved14
[3];
3761 __IO hw_usb_bdtpage1_t BDTPAGE1
; /*!< [0x9C] BDT Page register 1 */
3762 uint8_t _reserved15
[3];
3763 __IO hw_usb_frmnuml_t FRMNUML
; /*!< [0xA0] Frame Number register Low */
3764 uint8_t _reserved16
[3];
3765 __IO hw_usb_frmnumh_t FRMNUMH
; /*!< [0xA4] Frame Number register High */
3766 uint8_t _reserved17
[3];
3767 __IO hw_usb_token_t TOKEN
; /*!< [0xA8] Token register */
3768 uint8_t _reserved18
[3];
3769 __IO hw_usb_softhld_t SOFTHLD
; /*!< [0xAC] SOF Threshold register */
3770 uint8_t _reserved19
[3];
3771 __IO hw_usb_bdtpage2_t BDTPAGE2
; /*!< [0xB0] BDT Page Register 2 */
3772 uint8_t _reserved20
[3];
3773 __IO hw_usb_bdtpage3_t BDTPAGE3
; /*!< [0xB4] BDT Page Register 3 */
3774 uint8_t _reserved21
[11];
3776 __IO hw_usb_endptn_t ENDPTn
; /*!< [0xC0] Endpoint Control register */
3777 uint8_t _reserved0
[3];
3779 __IO hw_usb_usbctrl_t USBCTRL
; /*!< [0x100] USB Control register */
3780 uint8_t _reserved22
[3];
3781 __I hw_usb_observe_t OBSERVE
; /*!< [0x104] USB OTG Observe register */
3782 uint8_t _reserved23
[3];
3783 __IO hw_usb_control_t CONTROL
; /*!< [0x108] USB OTG Control register */
3784 uint8_t _reserved24
[3];
3785 __IO hw_usb_usbtrc0_t USBTRC0
; /*!< [0x10C] USB Transceiver Control register 0 */
3786 uint8_t _reserved25
[7];
3787 __IO hw_usb_usbfrmadjust_t USBFRMADJUST
; /*!< [0x114] Frame Adjust Register */
3788 uint8_t _reserved26
[43];
3789 __IO hw_usb_clk_recover_ctrl_t CLK_RECOVER_CTRL
; /*!< [0x140] USB Clock recovery control */
3790 uint8_t _reserved27
[3];
3791 __IO hw_usb_clk_recover_irc_en_t CLK_RECOVER_IRC_EN
; /*!< [0x144] IRC48M oscillator enable register */
3792 uint8_t _reserved28
[23];
3793 __IO hw_usb_clk_recover_int_status_t CLK_RECOVER_INT_STATUS
; /*!< [0x15C] Clock recovery separated interrupt status */
3797 /*! @brief Macro to access all USB registers. */
3798 /*! @param x USB module instance base address. */
3799 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
3800 * use the '&' operator, like <code>&HW_USB(USB0_BASE)</code>. */
3801 #define HW_USB(x) (*(hw_usb_t *)(x))
3803 #endif /* __HW_USB_REGISTERS_H__ */