tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/fsl_bitaccess.h

   1 /*
   2 ** ###################################################################
   3 **     Version:             rev. 2.5, 2014-05-06
   4 **     Build:               b140604
   5 **
   6 **     Abstract:
   7 **         Register bit field access macros.
   8 **
   9 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
  10 **     All rights reserved.
  11 **
  12 **     Redistribution and use in source and binary forms, with or without modification,
  13 **     are permitted provided that the following conditions are met:
  14 **
  15 **     o Redistributions of source code must retain the above copyright notice, this list
  16 **       of conditions and the following disclaimer.
  17 **
  18 **     o Redistributions in binary form must reproduce the above copyright notice, this
  19 **       list of conditions and the following disclaimer in the documentation and/or
  20 **       other materials provided with the distribution.
  21 **
  22 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  23 **       contributors may be used to endorse or promote products derived from this
  24 **       software without specific prior written permission.
  25 **
  26 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  27 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  28 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  29 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  30 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  31 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  32 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  33 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  35 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36 **
  37 **     http:                 www.freescale.com
  38 **     mail:                 support@freescale.com
  39 **
  40 **     Revisions:
  41 **     - rev. 1.0 (2013-07-23)
  42 **         Initial version.
  43 **     - rev. 1.1 (2013-09-17)
  44 **         RM rev. 0.4 update.
  45 **     - rev. 2.0 (2013-10-29)
  46 **         Register accessor macros added to the memory map.
  47 **         Symbols for Processor Expert memory map compatibility added to the memory map.
  48 **         Startup file for gcc has been updated according to CMSIS 3.2.
  49 **         System initialization updated.
  50 **     - rev. 2.1 (2013-10-30)
  51 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
  52 **     - rev. 2.2 (2013-12-20)
  53 **         Update according to reference manual rev. 0.6,
  54 **     - rev. 2.3 (2014-01-13)
  55 **         Update according to reference manual rev. 0.61,
  56 **     - rev. 2.4 (2014-02-10)
  57 **         The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
  58 **     - rev. 2.5 (2014-05-06)
  59 **         Update according to reference manual rev. 1.0,
  60 **         Update of system and startup files.
  61 **         Module access macro module_BASES replaced by module_BASE_PTRS.
  62 **
  63 ** ###################################################################
  64 */
  65
  66
  67 #ifndef _FSL_BITACCESS_H
  68 #define _FSL_BITACCESS_H  1
  69
  70 #include <stdint.h>
  71 #include <stdlib.h>
  72
  73 /**
  74  * @brief Macro to access a single bit of a 32-bit peripheral register (bit band region
  75  *        0x40000000 to 0x400FFFFF) using the bit-band alias region access.
  76  * @param Reg Register to access.
  77  * @param Bit Bit number to access.
  78  * @return Value of the targeted bit in the bit band region.
  79  */
  80 #define BITBAND_ACCESS32(Reg,Bit) (*((uint32_t volatile*)(0x42000000u + (32u*((uint32_t)(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))))
  81
  82 /**
  83  * @brief Macro to access a single bit of a 16-bit peripheral register (bit band region
  84  *        0x40000000 to 0x400FFFFF) using the bit-band alias region access.
  85  * @param Reg Register to access.
  86  * @param Bit Bit number to access.
  87  * @return Value of the targeted bit in the bit band region.
  88  */
  89 #define BITBAND_ACCESS16(Reg,Bit) (*((uint16_t volatile*)(0x42000000u + (32u*((uint32_t)(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))))
  90
  91 /**
  92  * @brief Macro to access a single bit of an 8-bit peripheral register (bit band region
  93  *        0x40000000 to 0x400FFFFF) using the bit-band alias region access.
  94  * @param Reg Register to access.
  95  * @param Bit Bit number to access.
  96  * @return Value of the targeted bit in the bit band region.
  97  */
  98 #define BITBAND_ACCESS8(Reg,Bit) (*((uint8_t volatile*)(0x42000000u + (32u*((uint32_t)(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))))
  99
 100 /*
 101  * Macros for single instance registers
 102  */
 103
 104 #define BF_SET(reg, field)       HW_##reg##_SET(BM_##reg##_##field)
 105 #define BF_CLR(reg, field)       HW_##reg##_CLR(BM_##reg##_##field)
 106 #define BF_TOG(reg, field)       HW_##reg##_TOG(BM_##reg##_##field)
 107
 108 #define BF_SETV(reg, field, v)   HW_##reg##_SET(BF_##reg##_##field(v))
 109 #define BF_CLRV(reg, field, v)   HW_##reg##_CLR(BF_##reg##_##field(v))
 110 #define BF_TOGV(reg, field, v)   HW_##reg##_TOG(BF_##reg##_##field(v))
 111
 112 #define BV_FLD(reg, field, sym)  BF_##reg##_##field(BV_##reg##_##field##__##sym)
 113 #define BV_VAL(reg, field, sym)  BV_##reg##_##field##__##sym
 114
 115 #define BF_RD(reg, field)        HW_##reg.B.field
 116 #define BF_WR(reg, field, v)     BW_##reg##_##field(v)
 117
 118 #define BF_CS1(reg, f1, v1)  \
 119         (HW_##reg##_CLR(BM_##reg##_##f1),      \
 120          HW_##reg##_SET(BF_##reg##_##f1(v1)))
 121
 122 #define BF_CS2(reg, f1, v1, f2, v2)  \
 123         (HW_##reg##_CLR(BM_##reg##_##f1 |      \
 124                         BM_##reg##_##f2),      \
 125          HW_##reg##_SET(BF_##reg##_##f1(v1) |  \
 126                         BF_##reg##_##f2(v2)))
 127
 128 #define BF_CS3(reg, f1, v1, f2, v2, f3, v3)  \
 129         (HW_##reg##_CLR(BM_##reg##_##f1 |      \
 130                         BM_##reg##_##f2 |      \
 131                         BM_##reg##_##f3),      \
 132          HW_##reg##_SET(BF_##reg##_##f1(v1) |  \
 133                         BF_##reg##_##f2(v2) |  \
 134                         BF_##reg##_##f3(v3)))
 135
 136 #define BF_CS4(reg, f1, v1, f2, v2, f3, v3, f4, v4)  \
 137         (HW_##reg##_CLR(BM_##reg##_##f1 |      \
 138                         BM_##reg##_##f2 |      \
 139                         BM_##reg##_##f3 |      \
 140                         BM_##reg##_##f4),      \
 141          HW_##reg##_SET(BF_##reg##_##f1(v1) |  \
 142                         BF_##reg##_##f2(v2) |  \
 143                         BF_##reg##_##f3(v3) |  \
 144                         BF_##reg##_##f4(v4)))
 145
 146 #define BF_CS5(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5)  \
 147         (HW_##reg##_CLR(BM_##reg##_##f1 |      \
 148                         BM_##reg##_##f2 |      \
 149                         BM_##reg##_##f3 |      \
 150                         BM_##reg##_##f4 |      \
 151                         BM_##reg##_##f5),      \
 152          HW_##reg##_SET(BF_##reg##_##f1(v1) |  \
 153                         BF_##reg##_##f2(v2) |  \
 154                         BF_##reg##_##f3(v3) |  \
 155                         BF_##reg##_##f4(v4) |  \
 156                         BF_##reg##_##f5(v5)))
 157
 158 #define BF_CS6(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6)  \
 159         (HW_##reg##_CLR(BM_##reg##_##f1 |      \
 160                         BM_##reg##_##f2 |      \
 161                         BM_##reg##_##f3 |      \
 162                         BM_##reg##_##f4 |      \
 163                         BM_##reg##_##f5 |      \
 164                         BM_##reg##_##f6),      \
 165          HW_##reg##_SET(BF_##reg##_##f1(v1) |  \
 166                         BF_##reg##_##f2(v2) |  \
 167                         BF_##reg##_##f3(v3) |  \
 168                         BF_##reg##_##f4(v4) |  \
 169                         BF_##reg##_##f5(v5) |  \
 170                         BF_##reg##_##f6(v6)))
 171
 172 #define BF_CS7(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7)  \
 173         (HW_##reg##_CLR(BM_##reg##_##f1 |      \
 174                         BM_##reg##_##f2 |      \
 175                         BM_##reg##_##f3 |      \
 176                         BM_##reg##_##f4 |      \
 177                         BM_##reg##_##f5 |      \
 178                         BM_##reg##_##f6 |      \
 179                         BM_##reg##_##f7),      \
 180          HW_##reg##_SET(BF_##reg##_##f1(v1) |  \
 181                         BF_##reg##_##f2(v2) |  \
 182                         BF_##reg##_##f3(v3) |  \
 183                         BF_##reg##_##f4(v4) |  \
 184                         BF_##reg##_##f5(v5) |  \
 185                         BF_##reg##_##f6(v6) |  \
 186                         BF_##reg##_##f7(v7)))
 187
 188 #define BF_CS8(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8)  \
 189         (HW_##reg##_CLR(BM_##reg##_##f1 |      \
 190                         BM_##reg##_##f2 |      \
 191                         BM_##reg##_##f3 |      \
 192                         BM_##reg##_##f4 |      \
 193                         BM_##reg##_##f5 |      \
 194                         BM_##reg##_##f6 |      \
 195                         BM_##reg##_##f7 |      \
 196                         BM_##reg##_##f8),      \
 197          HW_##reg##_SET(BF_##reg##_##f1(v1) |  \
 198                         BF_##reg##_##f2(v2) |  \
 199                         BF_##reg##_##f3(v3) |  \
 200                         BF_##reg##_##f4(v4) |  \
 201                         BF_##reg##_##f5(v5) |  \
 202                         BF_##reg##_##f6(v6) |  \
 203                         BF_##reg##_##f7(v7) |  \
 204                         BF_##reg##_##f8(v8)))
 205
 206 /*
 207  * Macros for multiple instance registers
 208  */
 209
 210 #define BF_SETn(reg, n, field)       HW_##reg##_SET(n, BM_##reg##_##field)
 211 #define BF_CLRn(reg, n, field)       HW_##reg##_CLR(n, BM_##reg##_##field)
 212 #define BF_TOGn(reg, n, field)       HW_##reg##_TOG(n, BM_##reg##_##field)
 213
 214 #define BF_SETVn(reg, n, field, v)   HW_##reg##_SET(n, BF_##reg##_##field(v))
 215 #define BF_CLRVn(reg, n, field, v)   HW_##reg##_CLR(n, BF_##reg##_##field(v))
 216 #define BF_TOGVn(reg, n, field, v)   HW_##reg##_TOG(n, BF_##reg##_##field(v))
 217
 218 #define BV_FLDn(reg, n, field, sym)  BF_##reg##_##field(BV_##reg##_##field##__##sym)
 219 #define BV_VALn(reg, n, field, sym)  BV_##reg##_##field##__##sym
 220
 221 #define BF_RDn(reg, n, field)        HW_##reg(n).B.field
 222 #define BF_WRn(reg, n, field, v)     BW_##reg##_##field(n, v)
 223
 224 #define BF_CS1n(reg, n, f1, v1)  \
 225         (HW_##reg##_CLR(n, (BM_##reg##_##f1)),      \
 226          HW_##reg##_SET(n, (BF_##reg##_##f1(v1))))
 227
 228 #define BF_CS2n(reg, n, f1, v1, f2, v2)  \
 229         (HW_##reg##_CLR(n, (BM_##reg##_##f1 |       \
 230                             BM_##reg##_##f2)),      \
 231          HW_##reg##_SET(n, (BF_##reg##_##f1(v1) |   \
 232                             BF_##reg##_##f2(v2))))
 233
 234 #define BF_CS3n(reg, n, f1, v1, f2, v2, f3, v3)  \
 235         (HW_##reg##_CLR(n, (BM_##reg##_##f1 |       \
 236                             BM_##reg##_##f2 |       \
 237                             BM_##reg##_##f3)),      \
 238          HW_##reg##_SET(n, (BF_##reg##_##f1(v1) |   \
 239                             BF_##reg##_##f2(v2) |   \
 240                             BF_##reg##_##f3(v3))))
 241
 242 #define BF_CS4n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4)  \
 243         (HW_##reg##_CLR(n, (BM_##reg##_##f1 |       \
 244                             BM_##reg##_##f2 |       \
 245                             BM_##reg##_##f3 |       \
 246                             BM_##reg##_##f4)),      \
 247          HW_##reg##_SET(n, (BF_##reg##_##f1(v1) |   \
 248                             BF_##reg##_##f2(v2) |   \
 249                             BF_##reg##_##f3(v3) |   \
 250                             BF_##reg##_##f4(v4))))
 251
 252 #define BF_CS5n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5)  \
 253         (HW_##reg##_CLR(n, (BM_##reg##_##f1 |       \
 254                             BM_##reg##_##f2 |       \
 255                             BM_##reg##_##f3 |       \
 256                             BM_##reg##_##f4 |       \
 257                             BM_##reg##_##f5)),      \
 258          HW_##reg##_SET(n, (BF_##reg##_##f1(v1) |   \
 259                             BF_##reg##_##f2(v2) |   \
 260                             BF_##reg##_##f3(v3) |   \
 261                             BF_##reg##_##f4(v4) |   \
 262                             BF_##reg##_##f5(v5))))
 263
 264 #define BF_CS6n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6)  \
 265         (HW_##reg##_CLR(n, (BM_##reg##_##f1 |       \
 266                             BM_##reg##_##f2 |       \
 267                             BM_##reg##_##f3 |       \
 268                             BM_##reg##_##f4 |       \
 269                             BM_##reg##_##f5 |       \
 270                             BM_##reg##_##f6)),      \
 271          HW_##reg##_SET(n, (BF_##reg##_##f1(v1) |   \
 272                             BF_##reg##_##f2(v2) |   \
 273                             BF_##reg##_##f3(v3) |   \
 274                             BF_##reg##_##f4(v4) |   \
 275                             BF_##reg##_##f5(v5) |   \
 276                             BF_##reg##_##f6(v6))))
 277
 278 #define BF_CS7n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7)  \
 279         (HW_##reg##_CLR(n, (BM_##reg##_##f1 |       \
 280                             BM_##reg##_##f2 |       \
 281                             BM_##reg##_##f3 |       \
 282                             BM_##reg##_##f4 |       \
 283                             BM_##reg##_##f5 |       \
 284                             BM_##reg##_##f6 |       \
 285                             BM_##reg##_##f7)),      \
 286          HW_##reg##_SET(n, (BF_##reg##_##f1(v1) |   \
 287                             BF_##reg##_##f2(v2) |   \
 288                             BF_##reg##_##f3(v3) |   \
 289                             BF_##reg##_##f4(v4) |   \
 290                             BF_##reg##_##f5(v5) |   \
 291                             BF_##reg##_##f6(v6) |   \
 292                             BF_##reg##_##f7(v7))))
 293
 294 #define BF_CS8n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8)  \
 295         (HW_##reg##_CLR(n, (BM_##reg##_##f1 |       \
 296                             BM_##reg##_##f2 |       \
 297                             BM_##reg##_##f3 |       \
 298                             BM_##reg##_##f4 |       \
 299                             BM_##reg##_##f5 |       \
 300                             BM_##reg##_##f6 |       \
 301                             BM_##reg##_##f7 |       \
 302                             BM_##reg##_##f8)),      \
 303          HW_##reg##_SET(n, (BF_##reg##_##f1(v1) |   \
 304                             BF_##reg##_##f2(v2) |   \
 305                             BF_##reg##_##f3(v3) |   \
 306                             BF_##reg##_##f4(v4) |   \
 307                             BF_##reg##_##f5(v5) |   \
 308                             BF_##reg##_##f6(v6) |   \
 309                             BF_##reg##_##f7(v7) |   \
 310                             BF_##reg##_##f8(v8))))
 311
 312 /*
 313  * Macros for single instance MULTI-BLOCK registers
 314  */
 315
 316 #define BFn_SET(reg, blk, field)       HW_##reg##_SET(blk, BM_##reg##_##field)
 317 #define BFn_CLR(reg, blk, field)       HW_##reg##_CLR(blk, BM_##reg##_##field)
 318 #define BFn_TOG(reg, blk, field)       HW_##reg##_TOG(blk, BM_##reg##_##field)
 319
 320 #define BFn_SETV(reg, blk, field, v)   HW_##reg##_SET(blk, BF_##reg##_##field(v))
 321 #define BFn_CLRV(reg, blk, field, v)   HW_##reg##_CLR(blk, BF_##reg##_##field(v))
 322 #define BFn_TOGV(reg, blk, field, v)   HW_##reg##_TOG(blk, BF_##reg##_##field(v))
 323
 324 #define BVn_FLD(reg, field, sym)  BF_##reg##_##field(BV_##reg##_##field##__##sym)
 325 #define BVn_VAL(reg, field, sym)  BV_##reg##_##field##__##sym
 326
 327 #define BFn_RD(reg, blk, field)        HW_##reg(blk).B.field
 328 #define BFn_WR(reg, blk, field, v)     BW_##reg##_##field(blk, v)
 329
 330 #define BFn_CS1(reg, blk, f1, v1)  \
 331         (HW_##reg##_CLR(blk, BM_##reg##_##f1),      \
 332          HW_##reg##_SET(blk, BF_##reg##_##f1(v1)))
 333
 334 #define BFn_CS2(reg, blk, f1, v1, f2, v2)  \
 335         (HW_##reg##_CLR(blk, BM_##reg##_##f1 |      \
 336                         BM_##reg##_##f2),      \
 337          HW_##reg##_SET(blk, BF_##reg##_##f1(v1) |  \
 338                         BF_##reg##_##f2(v2)))
 339
 340 #define BFn_CS3(reg, blk, f1, v1, f2, v2, f3, v3)  \
 341         (HW_##reg##_CLR(blk, BM_##reg##_##f1 |      \
 342                         BM_##reg##_##f2 |      \
 343                         BM_##reg##_##f3),      \
 344          HW_##reg##_SET(blk, BF_##reg##_##f1(v1) |  \
 345                         BF_##reg##_##f2(v2) |  \
 346                         BF_##reg##_##f3(v3)))
 347
 348 #define BFn_CS4(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4)  \
 349         (HW_##reg##_CLR(blk, BM_##reg##_##f1 |      \
 350                         BM_##reg##_##f2 |      \
 351                         BM_##reg##_##f3 |      \
 352                         BM_##reg##_##f4),      \
 353          HW_##reg##_SET(blk, BF_##reg##_##f1(v1) |  \
 354                         BF_##reg##_##f2(v2) |  \
 355                         BF_##reg##_##f3(v3) |  \
 356                         BF_##reg##_##f4(v4)))
 357
 358 #define BFn_CS5(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5)  \
 359         (HW_##reg##_CLR(blk, BM_##reg##_##f1 |      \
 360                         BM_##reg##_##f2 |      \
 361                         BM_##reg##_##f3 |      \
 362                         BM_##reg##_##f4 |      \
 363                         BM_##reg##_##f5),      \
 364          HW_##reg##_SET(blk, BF_##reg##_##f1(v1) |  \
 365                         BF_##reg##_##f2(v2) |  \
 366                         BF_##reg##_##f3(v3) |  \
 367                         BF_##reg##_##f4(v4) |  \
 368                         BF_##reg##_##f5(v5)))
 369
 370 #define BFn_CS6(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6)  \
 371         (HW_##reg##_CLR(blk, BM_##reg##_##f1 |      \
 372                         BM_##reg##_##f2 |      \
 373                         BM_##reg##_##f3 |      \
 374                         BM_##reg##_##f4 |      \
 375                         BM_##reg##_##f5 |      \
 376                         BM_##reg##_##f6),      \
 377          HW_##reg##_SET(blk, BF_##reg##_##f1(v1) |  \
 378                         BF_##reg##_##f2(v2) |  \
 379                         BF_##reg##_##f3(v3) |  \
 380                         BF_##reg##_##f4(v4) |  \
 381                         BF_##reg##_##f5(v5) |  \
 382                         BF_##reg##_##f6(v6)))
 383
 384 #define BFn_CS7(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7)  \
 385         (HW_##reg##_CLR(blk, BM_##reg##_##f1 |      \
 386                         BM_##reg##_##f2 |      \
 387                         BM_##reg##_##f3 |      \
 388                         BM_##reg##_##f4 |      \
 389                         BM_##reg##_##f5 |      \
 390                         BM_##reg##_##f6 |      \
 391                         BM_##reg##_##f7),      \
 392          HW_##reg##_SET(blk, BF_##reg##_##f1(v1) |  \
 393                         BF_##reg##_##f2(v2) |  \
 394                         BF_##reg##_##f3(v3) |  \
 395                         BF_##reg##_##f4(v4) |  \
 396                         BF_##reg##_##f5(v5) |  \
 397                         BF_##reg##_##f6(v6) |  \
 398                         BF_##reg##_##f7(v7)))
 399
 400 #define BFn_CS8(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8)  \
 401         (HW_##reg##_CLR(blk, BM_##reg##_##f1 |      \
 402                         BM_##reg##_##f2 |      \
 403                         BM_##reg##_##f3 |      \
 404                         BM_##reg##_##f4 |      \
 405                         BM_##reg##_##f5 |      \
 406                         BM_##reg##_##f6 |      \
 407                         BM_##reg##_##f7 |      \
 408                         BM_##reg##_##f8),      \
 409          HW_##reg##_SET(blk, BF_##reg##_##f1(v1) |  \
 410                         BF_##reg##_##f2(v2) |  \
 411                         BF_##reg##_##f3(v3) |  \
 412                         BF_##reg##_##f4(v4) |  \
 413                         BF_##reg##_##f5(v5) |  \
 414                         BF_##reg##_##f6(v6) |  \
 415                         BF_##reg##_##f7(v7) |  \
 416                         BF_##reg##_##f8(v8)))
 417
 418 /*
 419  * Macros for MULTI-BLOCK multiple instance registers
 420  */
 421
 422 #define BFn_SETn(reg, blk, n, field)       HW_##reg##_SET(blk, n, BM_##reg##_##field)
 423 #define BFn_CLRn(reg, blk, n, field)       HW_##reg##_CLR(blk, n, BM_##reg##_##field)
 424 #define BFn_TOGn(reg, blk, n, field)       HW_##reg##_TOG(blk, n, BM_##reg##_##field)
 425
 426 #define BFn_SETVn(reg, blk, n, field, v)   HW_##reg##_SET(blk, n, BF_##reg##_##field(v))
 427 #define BFn_CLRVn(reg, blk, n, field, v)   HW_##reg##_CLR(blk, n, BF_##reg##_##field(v))
 428 #define BFn_TOGVn(reg, blk, n, field, v)   HW_##reg##_TOG(blk, n, BF_##reg##_##field(v))
 429
 430 #define BVn_FLDn(reg, blk, n, field, sym)  BF_##reg##_##field(BV_##reg##_##field##__##sym)
 431 #define BVn_VALn(reg, blk, n, field, sym)  BV_##reg##_##field##__##sym
 432
 433 #define BFn_RDn(reg, blk, n, field)        HW_##reg(n).B.field
 434 #define BFn_WRn(reg, blk, n, field, v)     BW_##reg##_##field(n, v)
 435
 436 #define BFn_CS1n(reg, blk, n, f1, v1)  \
 437         (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1)),      \
 438          HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1))))
 439
 440 #define BFn_CS2n(reg, blk, n, f1, v1, f2, v2)  \
 441         (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 |       \
 442                             BM_##reg##_##f2)),      \
 443          HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) |   \
 444                             BF_##reg##_##f2(v2))))
 445
 446 #define BFn_CS3n(reg, blk, n, f1, v1, f2, v2, f3, v3)  \
 447         (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 |       \
 448                             BM_##reg##_##f2 |       \
 449                             BM_##reg##_##f3)),      \
 450          HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) |   \
 451                             BF_##reg##_##f2(v2) |   \
 452                             BF_##reg##_##f3(v3))))
 453
 454 #define BFn_CS4n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4)  \
 455         (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 |       \
 456                             BM_##reg##_##f2 |       \
 457                             BM_##reg##_##f3 |       \
 458                             BM_##reg##_##f4)),      \
 459          HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) |   \
 460                             BF_##reg##_##f2(v2) |   \
 461                             BF_##reg##_##f3(v3) |   \
 462                             BF_##reg##_##f4(v4))))
 463
 464 #define BFn_CS5n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5)  \
 465         (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 |       \
 466                             BM_##reg##_##f2 |       \
 467                             BM_##reg##_##f3 |       \
 468                             BM_##reg##_##f4 |       \
 469                             BM_##reg##_##f5)),      \
 470          HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) |   \
 471                             BF_##reg##_##f2(v2) |   \
 472                             BF_##reg##_##f3(v3) |   \
 473                             BF_##reg##_##f4(v4) |   \
 474                             BF_##reg##_##f5(v5))))
 475
 476 #define BFn_CS6n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6)  \
 477         (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 |       \
 478                             BM_##reg##_##f2 |       \
 479                             BM_##reg##_##f3 |       \
 480                             BM_##reg##_##f4 |       \
 481                             BM_##reg##_##f5 |       \
 482                             BM_##reg##_##f6)),      \
 483          HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) |   \
 484                             BF_##reg##_##f2(v2) |   \
 485                             BF_##reg##_##f3(v3) |   \
 486                             BF_##reg##_##f4(v4) |   \
 487                             BF_##reg##_##f5(v5) |   \
 488                             BF_##reg##_##f6(v6))))
 489
 490 #define BFn_CS7n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7)  \
 491         (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 |       \
 492                             BM_##reg##_##f2 |       \
 493                             BM_##reg##_##f3 |       \
 494                             BM_##reg##_##f4 |       \
 495                             BM_##reg##_##f5 |       \
 496                             BM_##reg##_##f6 |       \
 497                             BM_##reg##_##f7)),      \
 498          HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) |   \
 499                             BF_##reg##_##f2(v2) |   \
 500                             BF_##reg##_##f3(v3) |   \
 501                             BF_##reg##_##f4(v4) |   \
 502                             BF_##reg##_##f5(v5) |   \
 503                             BF_##reg##_##f6(v6) |   \
 504                             BF_##reg##_##f7(v7))))
 505
 506 #define BFn_CS8n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8)  \
 507         (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 |       \
 508                             BM_##reg##_##f2 |       \
 509                             BM_##reg##_##f3 |       \
 510                             BM_##reg##_##f4 |       \
 511                             BM_##reg##_##f5 |       \
 512                             BM_##reg##_##f6 |       \
 513                             BM_##reg##_##f7 |       \
 514                             BM_##reg##_##f8)),      \
 515          HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) |   \
 516                             BF_##reg##_##f2(v2) |   \
 517                             BF_##reg##_##f3(v3) |   \
 518                             BF_##reg##_##f4(v4) |   \
 519                             BF_##reg##_##f5(v5) |   \
 520                             BF_##reg##_##f6(v6) |   \
 521                             BF_##reg##_##f7(v7) |   \
 522                             BF_##reg##_##f8(v8))))
 523
 524 #endif /* _FSL_BITACCESS_H */
 525
 526 /******************************************************************************/