tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_features.h

   1 /*
   2 ** ###################################################################
   3 **     Version:             rev. 1.0, 2014-05-14
   4 **     Build:               b140515
   5 **
   6 **     Abstract:
   7 **         Chip specific module features.
   8 **
   9 **     Copyright: 2014 Freescale Semiconductor, Inc.
  10 **     All rights reserved.
  11 **
  12 **     Redistribution and use in source and binary forms, with or without modification,
  13 **     are permitted provided that the following conditions are met:
  14 **
  15 **     o Redistributions of source code must retain the above copyright notice, this list
  16 **       of conditions and the following disclaimer.
  17 **
  18 **     o Redistributions in binary form must reproduce the above copyright notice, this
  19 **       list of conditions and the following disclaimer in the documentation and/or
  20 **       other materials provided with the distribution.
  21 **
  22 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  23 **       contributors may be used to endorse or promote products derived from this
  24 **       software without specific prior written permission.
  25 **
  26 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  27 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  28 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  29 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  30 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  31 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  32 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  33 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  35 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36 **
  37 **     http:                 www.freescale.com
  38 **     mail:                 support@freescale.com
  39 **
  40 **     Revisions:
  41 **     - rev. 1.0 (2014-05-14)
  42 **         Customer release.
  43 **
  44 ** ###################################################################
  45 */
  46
  47 #if !defined(__FSL_ADC_FEATURES_H__)
  48 #define __FSL_ADC_FEATURES_H__
  49
  50 #if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \
  51     defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || \
  52     defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || \
  53     defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || \
  54     defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \
  55     defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \
  56     defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \
  57     defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || \
  58     defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || \
  59     defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || \
  60     defined(CPU_MK22FN512VLL12) || defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || \
  61     defined(CPU_MK24FN256VDC12) || defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || \
  62     defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || \
  63     defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK65FN2M0CAC18) || \
  64     defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || \
  65     defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) || defined(CPU_MKL13Z64VFM4) || \
  66     defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || defined(CPU_MKL13Z128VFT4) || \
  67     defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || defined(CPU_MKL13Z256VLH4) || \
  68     defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || defined(CPU_MKL23Z64VFM4) || \
  69     defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || defined(CPU_MKL23Z128VFT4) || \
  70     defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || defined(CPU_MKL23Z256VLH4) || \
  71     defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || defined(CPU_MKL25Z32VFM4) || \
  72     defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || \
  73     defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || \
  74     defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4) || defined(CPU_MKL26Z256VLK4) || \
  75     defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VMC4) || \
  76     defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || \
  77     defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || \
  78     defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || \
  79     defined(CPU_MKL46Z128VLL4) || defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) || \
  80     defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || defined(CPU_MKV30F128VLF10) || defined(CPU_MKV30F64VLF10) || \
  81     defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) || defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10) || \
  82     defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31F512VLH12) || defined(CPU_MKV31F512VLL12)
  83     /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */
  84     #define FSL_FEATURE_ADC_HAS_PGA (0)
  85     /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */
  86     #define FSL_FEATURE_ADC_HAS_DMA (1)
  87     /* @brief Has differential mode (bitfield SC1x[DIFF]). */
  88     #define FSL_FEATURE_ADC_HAS_DIFF_MODE (1)
  89     /* @brief Has FIFO (bit SC4[AFDEP]). */
  90     #define FSL_FEATURE_ADC_HAS_FIFO (0)
  91     /* @brief FIFO size if available (bitfield SC4[AFDEP]). */
  92     #define FSL_FEATURE_ADC_FIFO_SIZE (0)
  93     /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */
  94     #define FSL_FEATURE_ADC_HAS_MUX_SELECT (1)
  95     /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */
  96     #define FSL_FEATURE_ADC_HAS_HW_TRIGGER_MASK (0)
  97     /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */
  98     #define FSL_FEATURE_ADC_HAS_CALIBRATION (1)
  99     /* @brief Has HW averaging (bit SC3[AVGE]). */
 100     #define FSL_FEATURE_ADC_HAS_HW_AVERAGE (1)
 101     /* @brief Has offset correction (register OFS). */
 102     #define FSL_FEATURE_ADC_HAS_OFFSET_CORRECTION (1)
 103     /* @brief Maximum ADC resolution. */
 104     #define FSL_FEATURE_ADC_MAX_RESOLUTION (16)
 105     /* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */
 106     #define FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT (2)
 107 #elif defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \
 108     defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5)
 109     /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */
 110     #define FSL_FEATURE_ADC_HAS_PGA (0)
 111     /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */
 112     #define FSL_FEATURE_ADC_HAS_DMA (1)
 113     /* @brief Has differential mode (bitfield SC1x[DIFF]). */
 114     #define FSL_FEATURE_ADC_HAS_DIFF_MODE (0)
 115     /* @brief Has FIFO (bit SC4[AFDEP]). */
 116     #define FSL_FEATURE_ADC_HAS_FIFO (0)
 117     /* @brief FIFO size if available (bitfield SC4[AFDEP]). */
 118     #define FSL_FEATURE_ADC_FIFO_SIZE (0)
 119     /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */
 120     #define FSL_FEATURE_ADC_HAS_MUX_SELECT (1)
 121     /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */
 122     #define FSL_FEATURE_ADC_HAS_HW_TRIGGER_MASK (0)
 123     /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */
 124     #define FSL_FEATURE_ADC_HAS_CALIBRATION (1)
 125     /* @brief Has HW averaging (bit SC3[AVGE]). */
 126     #define FSL_FEATURE_ADC_HAS_HW_AVERAGE (1)
 127     /* @brief Has offset correction (register OFS). */
 128     #define FSL_FEATURE_ADC_HAS_OFFSET_CORRECTION (1)
 129     /* @brief Maximum ADC resolution. */
 130     #define FSL_FEATURE_ADC_MAX_RESOLUTION (16)
 131     /* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */
 132     #define FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT (2)
 133 #elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \
 134     defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15)
 135     /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */
 136     #define FSL_FEATURE_ADC_HAS_PGA (1)
 137     /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */
 138     #define FSL_FEATURE_ADC_HAS_DMA (1)
 139     /* @brief Has differential mode (bitfield SC1x[DIFF]). */
 140     #define FSL_FEATURE_ADC_HAS_DIFF_MODE (1)
 141     /* @brief Has FIFO (bit SC4[AFDEP]). */
 142     #define FSL_FEATURE_ADC_HAS_FIFO (0)
 143     /* @brief FIFO size if available (bitfield SC4[AFDEP]). */
 144     #define FSL_FEATURE_ADC_FIFO_SIZE (0)
 145     /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */
 146     #define FSL_FEATURE_ADC_HAS_MUX_SELECT (1)
 147     /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */
 148     #define FSL_FEATURE_ADC_HAS_HW_TRIGGER_MASK (0)
 149     /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */
 150     #define FSL_FEATURE_ADC_HAS_CALIBRATION (1)
 151     /* @brief Has HW averaging (bit SC3[AVGE]). */
 152     #define FSL_FEATURE_ADC_HAS_HW_AVERAGE (1)
 153     /* @brief Has offset correction (register OFS). */
 154     #define FSL_FEATURE_ADC_HAS_OFFSET_CORRECTION (1)
 155     /* @brief Maximum ADC resolution. */
 156     #define FSL_FEATURE_ADC_MAX_RESOLUTION (16)
 157     /* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */
 158     #define FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT (2)
 159 #elif defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || defined(CPU_MKL03Z32VFG4) || \
 160     defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || defined(CPU_MKL03Z32VFK4)
 161     /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */
 162     #define FSL_FEATURE_ADC_HAS_PGA (0)
 163     /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */
 164     #define FSL_FEATURE_ADC_HAS_DMA (0)
 165     /* @brief Has differential mode (bitfield SC1x[DIFF]). */
 166     #define FSL_FEATURE_ADC_HAS_DIFF_MODE (0)
 167     /* @brief Has FIFO (bit SC4[AFDEP]). */
 168     #define FSL_FEATURE_ADC_HAS_FIFO (0)
 169     /* @brief FIFO size if available (bitfield SC4[AFDEP]). */
 170     #define FSL_FEATURE_ADC_FIFO_SIZE (0)
 171     /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */
 172     #define FSL_FEATURE_ADC_HAS_MUX_SELECT (1)
 173     /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */
 174     #define FSL_FEATURE_ADC_HAS_HW_TRIGGER_MASK (0)
 175     /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */
 176     #define FSL_FEATURE_ADC_HAS_CALIBRATION (1)
 177     /* @brief Has HW averaging (bit SC3[AVGE]). */
 178     #define FSL_FEATURE_ADC_HAS_HW_AVERAGE (1)
 179     /* @brief Has offset correction (register OFS). */
 180     #define FSL_FEATURE_ADC_HAS_OFFSET_CORRECTION (1)
 181     /* @brief Maximum ADC resolution. */
 182     #define FSL_FEATURE_ADC_MAX_RESOLUTION (12)
 183     /* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */
 184     #define FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT (2)
 185 #elif defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || \
 186     defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || \
 187     defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4)
 188     /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */
 189     #define FSL_FEATURE_ADC_HAS_PGA (0)
 190     /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */
 191     #define FSL_FEATURE_ADC_HAS_DMA (1)
 192     /* @brief Has differential mode (bitfield SC1x[DIFF]). */
 193     #define FSL_FEATURE_ADC_HAS_DIFF_MODE (0)
 194     /* @brief Has FIFO (bit SC4[AFDEP]). */
 195     #define FSL_FEATURE_ADC_HAS_FIFO (0)
 196     /* @brief FIFO size if available (bitfield SC4[AFDEP]). */
 197     #define FSL_FEATURE_ADC_FIFO_SIZE (0)
 198     /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */
 199     #define FSL_FEATURE_ADC_HAS_MUX_SELECT (1)
 200     /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */
 201     #define FSL_FEATURE_ADC_HAS_HW_TRIGGER_MASK (0)
 202     /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */
 203     #define FSL_FEATURE_ADC_HAS_CALIBRATION (1)
 204     /* @brief Has HW averaging (bit SC3[AVGE]). */
 205     #define FSL_FEATURE_ADC_HAS_HW_AVERAGE (1)
 206     /* @brief Has offset correction (register OFS). */
 207     #define FSL_FEATURE_ADC_HAS_OFFSET_CORRECTION (1)
 208     /* @brief Maximum ADC resolution. */
 209     #define FSL_FEATURE_ADC_MAX_RESOLUTION (12)
 210     /* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */
 211     #define FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT (2)
 212 #else
 213     #error "No valid CPU defined!"
 214 #endif
 215
 216 #endif /* __FSL_ADC_FEATURES_H__ */
 217
 218 /*******************************************************************************
 219  * EOF
 220  ******************************************************************************/