tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/enet/fsl_enet_hal.h

   1 /*
   2  * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without modification,
   6  * are permitted provided that the following conditions are met:
   7  *
   8  * o Redistributions of source code must retain the above copyright notice, this list
   9  *   of conditions and the following disclaimer.
  10  *
  11  * o Redistributions in binary form must reproduce the above copyright notice, this
  12  *   list of conditions and the following disclaimer in the documentation and/or
  13  *   other materials provided with the distribution.
  14  *
  15  * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  16  *   contributors may be used to endorse or promote products derived from this
  17  *   software without specific prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  21  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  22  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  23  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  24  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  25  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  26  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  27  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  28  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29  */
  30
  31 #ifndef __FSL_ENET_HAL_H__
  32 #define __FSL_ENET_HAL_H__
  33
  34 #include <stdint.h>
  35 #include <stdbool.h>
  36 #include "fsl_device_registers.h"
  37 #include "fsl_enet_features.h"
  38 #include <assert.h>
  39
  40 #ifndef MBED_NO_ENET
  41
  42 /*!
  43  * @addtogroup enet_hal
  44  * @{
  45  */
  46
  47 /*******************************************************************************
  48  * Definitions
  49  ******************************************************************************/
  50 /*! @brief Defines the system endian type.*/
  51 #define SYSTEM_LITTLE_ENDIAN      (1)
  52
  53 /*! @brief Define macro to do the endianness swap*/
  54 #define BSWAP_16(x)     (uint16_t)((uint16_t)(((uint16_t)(x) & (uint16_t)0xFF00) >> 0x8) | (uint16_t)(((uint16_t)(x) & (uint16_t)0xFF) << 0x8))
  55 #define BSWAP_32(x) (uint32_t)((((uint32_t)(x) & 0x00FFU) << 24) | (((uint32_t)(x) & 0x00FF00U) << 8) | (((uint32_t)(x) & 0xFF0000U) >> 8) | (((uint32_t)(x) & 0xFF000000U) >> 24))
  56 #if SYSTEM_LITTLE_ENDIAN && FSL_FEATURE_ENET_DMA_BIG_ENDIAN_ONLY
  57 #define HTONS(n)                      BSWAP_16(n)
  58 #define HTONL(n)                      BSWAP_32(n)
  59 #define NTOHS(n)                      BSWAP_16(n)
  60 #define NTOHL(n)                      BSWAP_32(n)
  61 #else
  62 #define HTONS(n)                       (n)
  63 #define HTONL(n)                       (n)
  64 #define NTOHS(n)                       (n)
  65 #define NTOHL(n)                       (n)
  66 #endif
  67
  68 /*! @brief Defines the Status return codes.*/
  69 typedef enum _enet_status
  70 {
  71     kStatus_ENET_Success = 0,
  72     kStatus_ENET_InvalidInput,       /*!< Invalid ENET input parameter */
  73     kStatus_ENET_MemoryAllocateFail, /*!< Memory allocate failure*/
  74     kStatus_ENET_GetClockFreqFail,   /*!< Get clock frequency failure*/
  75     kStatus_ENET_Initialized,        /*!< ENET device already initialized*/
  76     kStatus_ENET_Layer2QueueNull,    /*!< NULL L2 PTP buffer queue pointer*/
  77     kStatus_ENET_Layer2OverLarge,    /*!< Layer2 packet length over large*/
  78     kStatus_ENET_Layer2BufferFull,   /*!< Layer2 packet buffer full*/
  79     kStatus_ENET_PtpringBufferFull,  /*!< PTP ring buffer full*/
  80     kStatus_ENET_PtpringBufferEmpty, /*!< PTP ring buffer empty*/
  81     kStatus_ENET_Miiuninitialized,   /*!< MII uninitialized*/
  82     kStatus_ENET_RxbdInvalid,        /*!< Receive buffer descriptor invalid*/
  83     kStatus_ENET_RxbdEmpty,          /*!< Receive buffer descriptor empty*/
  84     kStatus_ENET_RxbdTrunc,          /*!< Receive buffer descriptor truncate*/
  85     kStatus_ENET_RxbdError,          /*!< Receive buffer descriptor error*/
  86     kStatus_ENET_RxBdFull,           /*!< Receive buffer descriptor full*/
  87     kStatus_ENET_SmallBdSize,        /*!< Small receive buffer size*/
  88     kStatus_ENET_LargeBufferFull,    /*!< Receive large buffer full*/
  89     kStatus_ENET_TxbdFull,           /*!< Transmit buffer descriptor full*/
  90     kStatus_ENET_TxbdNull,           /*!< Transmit buffer descriptor Null*/
  91     kStatus_ENET_TxBufferNull,       /*!< Transmit data buffer Null*/
  92     kStatus_ENET_NoRxBufferLeft,       /*!< No more receive buffer left*/
  93     kStatus_ENET_UnknownCommand,     /*!< Invalid ENET PTP IOCTL command*/
  94     kStatus_ENET_TimeOut,            /*!< ENET Timeout*/
  95     kStatus_ENET_MulticastPointerNull, /*!< Null multicast group pointer*/
  96     kStatus_ENET_AlreadyAddedMulticast /*!< Have Already added to multicast group*/
  97 } enet_status_t;
  98
  99
 100 #if FSL_FEATURE_ENET_DMA_BIG_ENDIAN_ONLY && SYSTEM_LITTLE_ENDIAN
 101 /*! @brief Defines the control and status regions of the receive buffer descriptor.*/
 102 typedef enum _enet_rx_bd_control_status
 103 {
 104     kEnetRxBdBroadCast = 0x8000,       /*!< Broadcast */
 105     kEnetRxBdMultiCast = 0x4000,       /*!< Multicast*/
 106     kEnetRxBdLengthViolation = 0x2000, /*!< Receive length violation*/
 107     kEnetRxBdNoOctet = 0x1000,         /*!< Receive non-octet aligned frame*/
 108     kEnetRxBdCrc = 0x0400,             /*!< Receive CRC error*/
 109     kEnetRxBdOverRun = 0x0200,         /*!< Receive FIFO overrun*/
 110     kEnetRxBdTrunc = 0x0100,           /*!< Frame is truncated */
 111     kEnetRxBdEmpty = 0x0080,           /*!< Empty bit*/
 112     kEnetRxBdRxSoftOwner1 = 0x0040,    /*!< Receive software owner*/
 113     kEnetRxBdWrap = 0x0020,            /*!< Update buffer descriptor*/
 114     kEnetRxBdRxSoftOwner2 = 0x0010,    /*!< Receive software owner*/
 115     kEnetRxBdLast = 0x0008,            /*!< Last BD in the frame*/
 116     kEnetRxBdMiss = 0x0001             /*!< Receive for promiscuous mode*/
 117 } enet_rx_bd_control_status_t;
 118
 119 /*! @brief Defines the control extended regions of the receive buffer descriptor.*/
 120 typedef enum _enet_rx_bd_control_extend
 121 {
 122     kEnetRxBdUnicast = 0x0001,              /*!< Unicast frame*/
 123     kEnetRxBdCollision = 0x0002,            /*!< BD collision*/
 124     kEnetRxBdPhyErr = 0x0004,               /*!< PHY error*/
 125     kEnetRxBdMacErr = 0x0080,               /*!< Mac error*/
 126     kEnetRxBdIpv4 = 0x0100,                 /*!< Ipv4 frame*/
 127     kEnetRxBdIpv6 = 0x0200,                 /*!< Ipv6 frame*/
 128     kEnetRxBdVlan = 0x0400,                 /*!< VLAN*/
 129     kEnetRxBdProtocolChecksumErr = 0x1000,  /*!< Protocol checksum error*/
 130     kEnetRxBdIpHeaderChecksumErr = 0x2000,  /*!< IP header checksum error*/
 131     kEnetRxBdIntrrupt = 0x8000              /*!< BD interrupt*/
 132 } enet_rx_bd_control_extend_t;
 133
 134 /*! @brief Defines the control status region of the transmit buffer descriptor.*/
 135 typedef enum _enet_tx_bd_control_status
 136 {
 137     kEnetTxBdReady = 0x0080,         /*!<  Ready bit*/
 138     kEnetTxBdTxSoftOwner1 = 0x0040,  /*!<  Transmit software owner*/
 139     kEnetTxBdWrap = 0x0020,          /*!<  Wrap buffer descriptor*/
 140     kEnetTxBdTxSoftOwner2 = 0x0010,  /*!<  Transmit software owner*/
 141     kEnetTxBdLast = 0x0008,          /*!<  Last BD in the frame*/
 142     kEnetTxBdTransmitCrc = 0x0004    /*!<  Receive for transmit CRC*/
 143 } enet_tx_bd_control_status_t;
 144
 145 /*! @brief Defines the control extended region of the transmit buffer descriptor.*/
 146 typedef enum _enet_tx_bd_control_extend
 147 {
 148     kEnetTxBdTxErr = 0x0080,                 /*!<  Transmit error*/
 149     kEnetTxBdTxUnderFlowErr = 0x0020,        /*!<  Underflow error*/
 150     kEnetTxBdExcessCollisionErr = 0x0010,    /*!<  Excess collision error*/
 151     kEnetTxBdTxFrameErr = 0x0008,            /*!<  Frame error*/
 152     kEnetTxBdLatecollisionErr = 0x0004,      /*!<  Late collision error*/
 153     kEnetTxBdOverFlowErr = 0x0002,           /*!<  Overflow error*/
 154     kEnetTxTimestampErr = 0x0001             /*!<  Timestamp error*/
 155 } enet_tx_bd_control_extend_t;
 156
 157 /*! @brief Defines the control extended2 region of the transmit buffer descriptor.*/
 158 typedef enum _enet_tx_bd_control_extend2
 159 {
 160     kEnetTxBdTxInterrupt = 0x0040, /*!< Transmit interrupt*/
 161     kEnetTxBdTimeStamp = 0x0020    /*!< Transmit timestamp flag */
 162 } enet_tx_bd_control_extend2_t;
 163 #else
 164 /*! @brief Defines the control and status region of the receive buffer descriptor.*/
 165 typedef enum _enet_rx_bd_control_status
 166 {
 167     kEnetRxBdEmpty = 0x8000,           /*!< Empty bit*/
 168     kEnetRxBdRxSoftOwner1 = 0x4000,    /*!< Receive software owner*/
 169     kEnetRxBdWrap = 0x2000,            /*!< Update buffer descriptor*/
 170     kEnetRxBdRxSoftOwner2 = 0x1000,    /*!< Receive software owner*/
 171     kEnetRxBdLast = 0x0800,            /*!< Last BD in the frame*/
 172     kEnetRxBdMiss = 0x0100,            /*!< Receive for promiscuous mode*/
 173     kEnetRxBdBroadCast = 0x0080,       /*!< Broadcast */
 174     kEnetRxBdMultiCast = 0x0040,       /*!< Multicast*/
 175     kEnetRxBdLengthViolation = 0x0020, /*!< Receive length violation*/
 176     kEnetRxBdNoOctet = 0x0010,         /*!< Receive non-octet aligned frame*/
 177     kEnetRxBdCrc = 0x0004,             /*!< Receive CRC error*/
 178     kEnetRxBdOverRun = 0x0002,         /*!< Receive FIFO overrun*/
 179     kEnetRxBdTrunc = 0x0001            /*!< Frame is truncated    */
 180 } enet_rx_bd_control_status_t;
 181
 182 /*! @brief Defines the control extended region of the receive buffer descriptor.*/
 183 typedef enum _enet_rx_bd_control_extend
 184 {
 185     kEnetRxBdIpv4 = 0x0001,                 /*!< Ipv4 frame*/
 186     kEnetRxBdIpv6 = 0x0002,                 /*!< Ipv6 frame*/
 187     kEnetRxBdVlan = 0x0004,                 /*!< VLAN*/
 188     kEnetRxBdProtocolChecksumErr = 0x0010,  /*!< Protocol checksum error*/
 189     kEnetRxBdIpHeaderChecksumErr = 0x0020,  /*!< IP header checksum error*/
 190     kEnetRxBdIntrrupt = 0x0080,             /*!< BD interrupt*/
 191     kEnetRxBdUnicast = 0x0100,              /*!< Unicast frame*/
 192     kEnetRxBdCollision = 0x0200,            /*!< BD collision*/
 193     kEnetRxBdPhyErr = 0x0400,               /*!< PHY error*/
 194     kEnetRxBdMacErr = 0x8000                /*!< Mac error */
 195 } enet_rx_bd_control_extend_t;
 196
 197 /*! @brief Defines the control status of the transmit buffer descriptor.*/
 198 typedef enum _enet_tx_bd_control_status
 199 {
 200     kEnetTxBdReady = 0x8000,         /*!<  Ready bit*/
 201     kEnetTxBdTxSoftOwner1 = 0x4000,  /*!<  Transmit software owner*/
 202     kEnetTxBdWrap = 0x2000,          /*!<  Wrap buffer descriptor*/
 203     kEnetTxBdTxSoftOwner2 = 0x1000,  /*!<  Transmit software owner*/
 204     kEnetTxBdLast = 0x0800,          /*!<  Last BD in the frame*/
 205     kEnetTxBdTransmitCrc = 0x0400    /*!<  Receive for transmit CRC   */
 206 } enet_tx_bd_control_status_t;
 207
 208 /*! @brief Defines the control extended of the transmit buffer descriptor.*/
 209 typedef enum _enet_tx_bd_control_extend
 210 {
 211     kEnetTxBdTxErr = 0x8000,                /*!<  Transmit error*/
 212     kEnetTxBdTxUnderFlowErr = 0x2000,       /*!<  Underflow error*/
 213     kEnetTxBdExcessCollisionErr = 0x1000,   /*!<  Excess collision error*/
 214     kEnetTxBdTxFrameErr = 0x0800,           /*!<  Frame error*/
 215     kEnetTxBdLatecollisionErr = 0x0400,     /*!<  Late collision error*/
 216     kEnetTxBdOverFlowErr = 0x0200,          /*!<  Overflow error*/
 217     kEnetTxTimestampErr = 0x0100            /*!<  Timestamp error*/
 218 } enet_tx_bd_control_extend_t;
 219
 220 /*! @brief Defines the control extended2 of the transmit buffer descriptor.*/
 221 typedef enum _enet_tx_bd_control_extend2
 222 {
 223     kEnetTxBdTxInterrupt = 0x4000, /*!< Transmit interrupt*/
 224     kEnetTxBdTimeStamp = 0x2000    /*!< Transmit timestamp flag */
 225 } enet_tx_bd_control_extend2_t;
 226 #endif
 227
 228 /*! @brief Defines the macro to the different ENET constant value.*/
 229 typedef enum _enet_constant_parameter
 230 {
 231     kEnetMacAddrLen = 6,       /*!< ENET mac address length*/
 232     kEnetHashValMask = 0x1f,   /*!< ENET hash value mask*/
 233     kEnetRxBdCtlJudge1 = 0x0080,/*!< ENET receive buffer descriptor control judge value1*/
 234     kEnetRxBdCtlJudge2 = 0x8000 /*!< ENET receive buffer descriptor control judge value2*/
 235 } enet_constant_parameter_t;
 236
 237 /*! @brief Defines the RMII or MII mode for data interface between the MAC and the PHY.*/
 238 typedef enum _enet_config_rmii
 239 {
 240     kEnetCfgMii = 0,   /*!< MII mode for data interface*/
 241     kEnetCfgRmii = 1   /*!< RMII mode for data interface*/
 242 } enet_config_rmii_t;
 243
 244 /*! @brief Defines the 10 Mbps or 100 Mbps speed mode for the data transfer.*/
 245 typedef enum _enet_config_speed
 246 {
 247     kEnetCfgSpeed100M = 0,  /*!< Speed 100 M mode*/
 248     kEnetCfgSpeed10M = 1    /*!< Speed 10 M mode*/
 249 } enet_config_speed_t;
 250
 251 /*! @brief Defines the half or full duplex mode for the data transfer.*/
 252 typedef enum _enet_config_duplex
 253 {
 254     kEnetCfgHalfDuplex = 0, /*!< Half duplex mode*/
 255     kEnetCfgFullDuplex = 1  /*!< Full duplex mode*/
 256 } enet_config_duplex_t;
 257
 258 /*! @brief Defines the write/read operation for the MII.*/
 259 typedef enum _enet_mii_operation
 260 {
 261     kEnetWriteNoCompliant = 0, /*!< Write frame operation, but not MII compliant.*/
 262     kEnetWriteValidFrame = 1,  /*!< Write frame operation for a valid MII management frame*/
 263     kEnetReadValidFrame = 2,   /*!< Read frame operation for a valid MII management frame.*/
 264     kEnetReadNoCompliant = 3   /*!< Read frame operation, but not MII compliant*/
 265 }enet_mii_operation_t;
 266
 267 /*! @brief Define holdon time on MDIO output*/
 268 typedef enum _enet_mdio_holdon_clkcycle
 269 {
 270     kEnetMdioHoldOneClkCycle = 0, /*!< MDIO output hold on one clock cycle*/
 271     kEnetMdioHoldTwoClkCycle = 1, /*!< MDIO output hold on two clock cycles*/
 272     kEnetMdioHoldThreeClkCycle = 2, /*!< MDIO output hold on three clock cycles*/
 273     kEnetMdioHoldFourClkCycle = 3, /*!< MDIO output hold on four clock cycles*/
 274     kEnetMdioHoldFiveClkCycle = 4, /*!< MDIO output hold on five clock cycles*/
 275     kEnetMdioHoldSixClkCycle = 5, /*!< MDIO output hold on six clock cycles*/
 276     kEnetMdioHoldSevenClkCycle = 6, /*!< MDIO output hold seven two clock cycles*/
 277     kEnetMdioHoldEightClkCycle = 7, /*!< MDIO output hold on eight clock cycles*/
 278 }enet_mdio_holdon_clkcycle_t;
 279
 280 /*! @brief Defines the initialization, enables or disables the operation for a special address filter */
 281 typedef enum _enet_special_address_filter
 282 {
 283     kEnetSpecialAddressInit= 0,     /*!< Initializes the special address filter.*/
 284     kEnetSpecialAddressEnable = 1,  /*!< Enables the special address filter.*/
 285     kEnetSpecialAddressDisable = 2  /*!< Disables the special address filter.*/
 286 } enet_special_address_filter_t;
 287
 288 /*! @brief Defines the capture or compare mode for 1588 timer channels.*/
 289 typedef enum _enet_timer_channel_mode
 290 {
 291     kEnetChannelDisable = 0,         /*!< Disable timer channel*/
 292     kEnetChannelRisingCapture = 1,   /*!< Input capture on rising edge*/
 293     kEnetChannelFallingCapture = 2,  /*!< Input capture on falling edge*/
 294     kEnetChannelBothCapture = 3,     /*!< Input capture on both edges*/
 295     kEnetChannelSoftCompare = 4,     /*!< Output compare software only*/
 296     kEnetChannelToggleCompare = 5,   /*!< Toggle output on compare*/
 297     kEnetChannelClearCompare = 6,    /*!< Clear output on compare*/
 298     kEnetChannelSetCompare = 7,      /*!< Set output on compare*/
 299     kEnetChannelClearCompareSetOverflow = 10, /*!< Clear output on compare, set output on overflow*/
 300     kEnetChannelSetCompareClearOverflow = 11, /*!< Set output on compare, clear output on overflow*/
 301     kEnetChannelPulseLowonCompare = 14, /*!< Pulse output low on compare for one 1588 clock cycle*/
 302     kEnetChannelPulseHighonCompare = 15 /*!< Pulse output high on compare for one 1588 clock cycle*/
 303 } enet_timer_channel_mode_t;
 304
 305 /*! @brief Defines the RXFRAME/RXBYTE/TXFRAME/TXBYTE/MII/TSTIMER/TSAVAIL interrupt source for ENET.*/
 306 typedef enum _enet_interrupt_request
 307 {
 308     kEnetBabrInterrupt = 0x40000000,   /*!< BABR interrupt source*/
 309     kEnetBabtInterrupt = 0x20000000,   /*!< BABT interrupt source*/
 310     kEnetGraInterrupt = 0x10000000,    /*!< GRA interrupt source*/
 311     kEnetTxFrameInterrupt = 0x8000000, /*!< TXFRAME interrupt source */
 312     kEnetTxByteInterrupt = 0x4000000,  /*!< TXBYTE interrupt source*/
 313     kEnetRxFrameInterrupt = 0x2000000, /*!< RXFRAME interrupt source */
 314     kEnetRxByteInterrupt = 0x1000000,  /*!< RXBYTE interrupt source */
 315     kEnetMiiInterrupt = 0x0800000,     /*!< MII interrupt source*/
 316     kEnetEBERInterrupt = 0x0400000,    /*!< EBERR interrupt source*/
 317     kEnetLcInterrupt = 0x0200000,      /*!< LC interrupt source*/
 318     kEnetRlInterrupt = 0x0100000,      /*!< RL interrupt source*/
 319     kEnetUnInterrupt = 0x0080000,      /*!< UN interrupt source*/
 320     kEnetPlrInterrupt = 0x0040000,     /*!< PLR interrupt source*/
 321     kEnetWakeupInterrupt = 0x0020000,  /*!< WAKEUP interrupt source*/
 322     kEnetTsAvailInterrupt = 0x0010000, /*!< TS AVAIL interrupt source*/
 323     kEnetTsTimerInterrupt = 0x0008000, /*!< TS WRAP interrupt source*/
 324     kEnetAllInterrupt = 0x7FFFFFFF     /*!< All interrupt*/
 325 } enet_interrupt_request_t;
 326
 327 /*! @brief Defines the six-byte Mac address type.*/
 328 typedef uint8_t enetMacAddr[kEnetMacAddrLen];
 329
 330 #if (!FSL_FEATURE_ENET_DMA_BIG_ENDIAN_ONLY) && SYSTEM_LITTLE_ENDIAN
 331 /*! @brief Defines the buffer descriptor structure for the little-Endian system and endianness configurable IP.*/
 332 typedef struct ENETBdStruct
 333 {
 334     uint16_t  length;           /*!< Buffer descriptor data length*/
 335     uint16_t  control;          /*!< Buffer descriptor control*/
 336     uint8_t   *buffer;          /*!< Data buffer pointer*/
 337     uint16_t  controlExtend0;   /*!< Extend buffer descriptor control0*/
 338     uint16_t  controlExtend1;   /*!< Extend buffer descriptor control1*/
 339     uint16_t  payloadCheckSum;  /*!< Internal payload checksum*/
 340     uint8_t   headerLength;     /*!< Header length*/
 341     uint8_t   protocalTyte;     /*!< Protocol type*/
 342     uint16_t  reserved0;
 343     uint16_t  controlExtend2;   /*!< Extend buffer descriptor control2*/
 344     uint32_t  timestamp;        /*!< Timestamp */
 345     uint16_t  reserved1;
 346     uint16_t  reserved2;
 347     uint16_t  reserved3;
 348     uint16_t  reserved4;
 349 } enet_bd_struct_t;
 350 #define TX_DESC_UPDATED_MASK  (0x8000)
 351 #else
 352 /*! @brief Defines the buffer descriptors structure for the Big-Endian system.*/
 353 typedef struct ENETBdStruct
 354 {
 355     uint16_t  control;          /*!< Buffer descriptor control   */
 356     uint16_t   length;          /*!< Buffer descriptor data length*/
 357     uint8_t   *buffer;          /*!< Data buffer pointer*/
 358     uint16_t  controlExtend1;   /*!< Extend buffer descriptor control1*/
 359     uint16_t  controlExtend0;   /*!< Extend buffer descriptor control0*/
 360     uint8_t   headerLength;     /*!< Header length*/
 361     uint8_t   protocalTyte;     /*!< Protocol type*/
 362     uint16_t  payloadCheckSum;  /*!< Internal payload checksum*/
 363     uint16_t  controlExtend2;   /*!< Extend buffer descriptor control2*/
 364     uint16_t  reserved0;
 365     uint32_t  timestamp;        /*!< Timestamp pointer*/
 366     uint16_t  reserved1;
 367     uint16_t  reserved2;
 368     uint16_t  reserved3;
 369     uint16_t  reserved4;
 370 } enet_bd_struct_t;
 371 #define TX_DESC_UPDATED_MASK  (0x0080)
 372 #endif
 373
 374 /*! @brief Defines the configuration structure for the 1588 PTP timer.*/
 375 typedef struct ENETConfigPtpTimer
 376 {
 377     bool isSlaveEnabled;        /*!< Master or slave PTP timer*/
 378     uint32_t clockIncease;      /*!< Timer increase value each clock period*/
 379     uint32_t period;            /*!< Timer period for generate interrupt event  */
 380 } enet_config_ptp_timer_t;
 381
 382 /*! @brief Defines the transmit accelerator configuration.*/
 383 typedef struct ENETConfigTxAccelerator
 384 {
 385     bool  isIpCheckEnabled;         /*!< Insert IP header checksum */
 386     bool  isProtocolCheckEnabled;   /*!< Insert protocol checksum*/
 387     bool  isShift16Enabled;         /*!< Tx FIFO shift-16*/
 388 } enet_config_tx_accelerator_t;
 389
 390 /*! @brief Defines the receive accelerator configuration.*/
 391 typedef struct ENETConfigRxAccelerator
 392 {
 393     bool isIpcheckEnabled;        /*!< Discard with wrong IP header checksum */
 394     bool isProtocolCheckEnabled;  /*!< Discard with wrong protocol checksum*/
 395     bool isMacCheckEnabled;       /*!< Discard with Mac layer errors*/
 396     bool isPadRemoveEnabled;      /*!< Padding removal for short IP frames*/
 397     bool isShift16Enabled;        /*!< Rx FIFO shift-16*/
 398 } enet_config_rx_accelerator_t;
 399
 400 /*! @brief Defines the transmit FIFO configuration.*/
 401 typedef struct ENETConfigTxFifo
 402 {
 403     bool isStoreForwardEnabled;   /*!< Transmit FIFO store and forward */
 404     uint8_t txFifoWrite;          /*!< Transmit FIFO write */
 405     uint8_t txEmpty;              /*!< Transmit FIFO section empty threshold*/
 406     uint8_t txAlmostEmpty;        /*!< Transmit FIFO section almost empty threshold*/
 407     uint8_t txAlmostFull;         /*!< Transmit FIFO section almost full threshold*/
 408 } enet_config_tx_fifo_t;
 409
 410 /*! @brief Defines the receive FIFO configuration.*/
 411 typedef struct ENETConfigRxFifo
 412 {
 413     uint8_t rxFull;           /*!< Receive FIFO section full threshold*/
 414     uint8_t rxAlmostFull;     /*!< Receive FIFO section almost full threshold*/
 415     uint8_t rxEmpty;          /*!< Receive FIFO section empty threshold*/
 416     uint8_t rxAlmostEmpty;    /*!< Receive FIFO section almost empty threshold*/
 417 } enet_config_rx_fifo_t;
 418
 419 /*******************************************************************************
 420  * API
 421  ******************************************************************************/
 422
 423 #if defined(__cplusplus)
 424 extern "C" {
 425 #endif
 426
 427 /*!
 428  * @brief Resets the ENET module.
 429  *
 430  * @param instance The ENET instance number
 431  */
 432 static inline void enet_hal_reset_ethernet(uint32_t instance)
 433 {
 434    // assert(instance < HW_ENET_INSTANCE_COUNT);
 435
 436    HW_ENET_ECR_SET(instance, BM_ENET_ECR_RESET);
 437 }
 438
 439 /*!
 440  * @brief Gets the ENET status to check whether the reset has completed.
 441  *
 442  * @param instance The ENET instance number
 443  * @return Current status of the reset operation
 444  *         - true if ENET reset completed.
 445  *         - false if ENET reset has not completed.
 446  */
 447 static inline bool enet_hal_is_reset_completed(uint32_t instance)
 448 {
 449    // assert(instance < HW_ENET_INSTANCE_COUNT);
 450
 451    return (BR_ENET_ECR_RESET(instance) == 0);
 452 }
 453
 454 /*!
 455  * @brief Enable or disable stop mode.
 456  *
 457  * Enable stop mode will control device behavior in doze mode.
 458  * In doze mode, if this filed is set then all clock of the enet assemably are
 459  * disabled, except the RMII/MII clock.
 460  *
 461  * @param instance The ENET instance number.
 462  * @param isEnabled The switch to enable/disable stop mode.
 463  *               - true to enabale the stop mode.
 464  *               - false to disable the stop mode.
 465  */
 466 static inline void enet_hal_enable_stop(uint32_t instance, bool isEnabled)
 467 {
 468     // assert(instance < HW_ENET_INSTANCE_COUNT);
 469     BW_ENET_ECR_STOPEN(instance, isEnabled);
 470 }
 471 /*!
 472  * @brief Enable or disable sleep mode.
 473  *
 474  * Enable sleep mode will disable normal operating mode. When enable the sleep
 475  * mode, the magic packet detection is also enabled so that a remote agent can
 476  * wakeup the node.
 477  *
 478  * @param instance The ENET instance number.
 479  * @param isEnabled The switch to enable/disable the sleep mode.
 480  *               - true to enabale the sleep mode.
 481  *               - false to disable the sleep mode.
 482  */
 483  static inline void enet_hal_enable_sleep(uint32_t instance, bool isEnabled)
 484 {
 485     // assert(instance < HW_ENET_INSTANCE_COUNT);
 486     BW_ENET_ECR_SLEEP(instance, isEnabled);
 487     BW_ENET_ECR_MAGICEN(instance, isEnabled);
 488 }
 489
 490 /*!
 491  * @brief Sets the Mac address.
 492  *
 493  * This interface sets the six-byte Mac address of the ENET interface.
 494  *
 495  * @param instance The ENET instance number
 496  * @param hwAddr The mac address pointer store for six bytes Mac address
 497  */
 498 void enet_hal_set_mac_address(uint32_t instance, enetMacAddr hwAddr);
 499
 500 /*!
 501  * @brief Sets the hardware addressing filtering to a multicast group address.
 502  *
 503  * This interface is used to add the ENET device to a multicast group address.
 504  * After joining the group,  Mac  receives all frames with the group Mac address.
 505  *
 506  * @param instance The ENET instance number
 507  * @param crcValue The CRC value of the special address
 508  * @param mode The operation for init/enable/disable the specified hardware address
 509  */
 510 void enet_hal_set_group_hashtable(uint32_t instance, uint32_t crcValue, enet_special_address_filter_t mode);
 511
 512 /*!
 513  * @brief Sets the hardware addressing filtering to an individual address.
 514  *
 515  * This interface is used to add an individual address to the hardware address
 516  * filter. Mac  receives all frames with the individual address as a destination address.
 517  *
 518  * @param instance The ENET instance number
 519  * @param crcValue The CRC value of the special address
 520  * @param mode The operation for init/enable/disable the specified hardware address
 521  */
 522 void enet_hal_set_individual_hashtable(uint32_t instance, uint32_t crcValue, enet_special_address_filter_t mode);
 523
 524 /*!
 525  * @brief Enable/disable payload length check.
 526  *
 527  * If the length/type is less than 0x600,When enable payload length check
 528  * the core checks the fame's payload length. If the length/type is greater
 529  * than or equal to 0x600. The MAC interprets the field as a type and no
 530  * payload length check is performanced.
 531  *
 532  * @param instance The ENET instance number
 533  * @param isEnabled The switch to enable/disable payload length check
 534  *             - True to enabale payload length check.
 535  *             - False to disable payload legnth check.
 536  */
 537 static inline void enet_hal_enable_payloadcheck(uint32_t instance, bool isEnabled)
 538 {
 539     // assert(instance < HW_ENET_INSTANCE_COUNT);
 540     BW_ENET_RCR_NLC(instance, isEnabled);
 541 }
 542
 543 /*!
 544  * @brief Enable/disable append CRC to transmitted frames.
 545  *
 546  * If transmit CRC forward is enabled, the transmit buffer descriptor controls
 547  * whether the frame has a CRC from the application. If transmit CRC forward is disabled,
 548  * transmitter does not append any CRC to transmitted frames.
 549  *
 550  * @param instance The ENET instance number
 551  * @param isEnabled The switch to enable/disable transmit the receive CRC
 552  *             - True the transmitter control CRC through transmit buffer descriptor.
 553  *             - False the transmitter does not append any CRC to transmitted frames.
 554  */
 555 static inline void enet_hal_enable_txcrcforward(uint32_t instance, bool isEnabled)
 556 {
 557     // assert(instance < HW_ENET_INSTANCE_COUNT);
 558     BW_ENET_TCR_CRCFWD(instance, !isEnabled);
 559 }
 560
 561 /*!
 562  * @brief Enable/disable forward the CRC filed of the received frame.
 563  *
 564  * This is used to deceide whether the CRC field of received frame is transmitted
 565  * or stripped. Enable this feature to strip CRC field from the frame.
 566  * If padding remove is enabled, this feature will be ignored and
 567  * the CRC field is checked and always terminated and removed.
 568  *
 569  * @param instance The ENET instance number
 570  * @param isEnabled The switch to enable/disable transmit the receive CRC
 571  *             - True to  transmit the received CRC.
 572  *             - False to strip the received CRC.
 573  */
 574 static inline void enet_hal_enable_rxcrcforward(uint32_t instance, bool isEnabled)
 575 {
 576     // assert(instance < HW_ENET_INSTANCE_COUNT);
 577     BW_ENET_RCR_CRCFWD(instance, !isEnabled);
 578 }
 579 /*!
 580  * @brief Enable/disable forward PAUSE frames.
 581  *
 582  * This is used to deceide whether PAUSE frames is forwarded or discarded.
 583  *
 584  * @param instance The ENET instance number
 585  * @param isEnabled The switch to enable/disable forward PAUSE frames
 586  *             - True to forward PAUSE frames.
 587  *             - False to terminate and discard PAUSE frames.
 588  */
 589 static inline void enet_hal_enable_pauseforward(uint32_t instance, bool isEnabled)
 590 {
 591     // assert(instance < HW_ENET_INSTANCE_COUNT);
 592     BW_ENET_RCR_PAUFWD(instance, isEnabled);
 593 }
 594
 595 /*!
 596  * @brief Enable/disable frame padding remove on receive.
 597  *
 598  * Enable frame padding remove will remove the padding from the received frames.
 599  *
 600  * @param instance The ENET instance number
 601  * @param isEnabled The switch to enable/disable remove padding
 602  *             - True to remove padding from frames.
 603  *             - False to disable padding remove.
 604  */
 605 static inline void enet_hal_enable_padremove(uint32_t instance, bool isEnabled)
 606 {
 607     // assert(instance < HW_ENET_INSTANCE_COUNT);
 608     BW_ENET_RCR_PADEN(instance, isEnabled);
 609 }
 610
 611 /*!
 612  * @brief Enable/disable flow control.
 613  *
 614  * If flow control is enabled, the receive detects PAUSE frames.
 615  * Upon PAUSE frame detection, the transmitter stops transmitting
 616  * data frames for a given duration.
 617  *
 618  * @param instance The ENET instance number
 619  * @param isEnabled The switch to enable/disable flow control
 620  *             - True to enable the flow control.
 621  *             - False to disable the flow control.
 622  */
 623 static inline void enet_hal_enable_flowcontrol(uint32_t instance, bool isEnabled)
 624 {
 625     // assert(instance < HW_ENET_INSTANCE_COUNT);
 626     BW_ENET_RCR_CFEN(instance, isEnabled);
 627     BW_ENET_RCR_FCE(instance, isEnabled);
 628 }
 629
 630 /*!
 631  * @brief Enable/disable broadcast frame reject.
 632  *
 633  * If broadcast frame reject is enabled, frames with destination address
 634  * equal to 0xffff_ffff_ffff are rejected unless the promiscuous mode is open.
 635  *
 636  * @param instance The ENET instance number
 637  * @param isEnabled The switch to enable/disable reject broadcast frames
 638  *             - True to reject broadcast frames.
 639  *             - False to accept broadcast frames.
 640  */
 641 static inline void enet_hal_enable_broadcastreject(uint32_t instance, bool isEnabled)
 642 {
 643     // assert(instance < HW_ENET_INSTANCE_COUNT);
 644     BW_ENET_RCR_BC_REJ(instance, isEnabled);
 645 }
 646
 647 /*!
 648  * @brief Sets PAUSE duration for a PAUSE frame.
 649  *
 650  * This function is used to set the pause duraion used in transmission
 651  * of a PAUSE frame. When another node detects a PAUSE frame, that node
 652  * pauses transmission for the pause duration.
 653  *
 654  * @param instance The ENET instance number
 655  * @param pauseDuration The PAUSE duration for the transmitted PAUSE frame
 656  *                      the maximum pause duration is 0xFFFF.
 657  */
 658 static inline void enet_hal_set_pauseduration(uint32_t instance, uint32_t pauseDuration)
 659 {
 660     // assert(instance < HW_ENET_INSTANCE_COUNT);
 661     assert(pauseDuration <= BM_ENET_OPD_PAUSE_DUR);
 662     BW_ENET_OPD_PAUSE_DUR(instance, pauseDuration);
 663 }
 664
 665 /*!
 666  * @brief Gets receive PAUSE frame status.
 667  *
 668  * This function is used to get the received PAUSE frame status.
 669  *
 670  * @param instance The ENET instance number
 671  * @return The status of the received flow control frames
 672  *         true if the flow control pause frame is received.
 673  *         false if there is no flow control frame received or the pause duration is complete.
 674  */
 675 static inline bool enet_hal_get_rxpause_status(uint32_t instance)
 676 {
 677     // assert(instance < HW_ENET_INSTANCE_COUNT);
 678     return BR_ENET_TCR_RFC_PAUSE(instance);
 679 }
 680 /*!
 681  * @brief Enables transmit frame control PAUSE.
 682  *
 683  * This function enables pauses frame transmission.
 684  * When this is set, with transmission of data frames stopped, the MAC
 685  * transmits a MAC control PAUSE frame. NEXT, the MAC clear the
 686  * and resumes transmitting data frames.
 687  *
 688  * @param instance The ENET instance number
 689  * @param isEnabled The switch to enable/disable PAUSE control frame transmission
 690  *              - True enable PAUSE control frame transmission.
 691  *              - Flase disable PAUSE control frame transmission.
 692  */
 693 static inline void enet_hal_enable_txpause(uint32_t instance, bool isEnabled)
 694 {
 695     // assert(instance < HW_ENET_INSTANCE_COUNT);
 696     BW_ENET_TCR_TFC_PAUSE(instance, isEnabled);
 697 }
 698
 699 /*!
 700  * @brief Sets transmit PAUSE frame.
 701  *
 702  * This function Sets ENET transmit controller with pause duration.
 703  * And set the transmit control to do PAUSE frame transmission
 704  * This should be called when a PAUSE frame is dynamically wanted.
 705  *
 706  * @param instance The ENET instance number
 707  */
 708 void enet_hal_set_txpause(uint32_t instance, uint32_t pauseDuration);
 709
 710 /*!
 711  * @brief Sets the transmit inter-packet gap.
 712  *
 713  * This function indicates the IPG, in bytes, between transmitted frames.
 714  * Valid values range from 8 to 27. If value is less than 8, the IPG is 8.
 715  * If value is greater than 27, the IPG is 27.
 716  *
 717  * @param instance The ENET instance number
 718  * @param ipgValue The IPG for transmitted frames
 719  *                 The default value is 12, the maximum value set to ipg is 0x1F.
 720  *
 721  */
 722 static inline void enet_hal_set_txipg(uint32_t instance, uint32_t ipgValue)
 723 {
 724     // assert(instance < HW_ENET_INSTANCE_COUNT);
 725     assert(ipgValue <= BM_ENET_TIPG_IPG);
 726     BW_ENET_TIPG_IPG(instance, ipgValue);
 727 }
 728
 729 /*!
 730  * @brief Sets the receive frame truncation length.
 731  *
 732  * This function indicates the value a receive frame is truncated,
 733  * if it is greater than this value. The frame truncation length must be greater
 734  * than or equal to the receive maximum frame length.
 735  *
 736  * @param instance The ENET instance number
 737  * @param length The truncation length. The maximum value is 0x3FFF
 738  *               The default truncation length is 2047(0x7FF).
 739  *
 740  */
 741 static inline void enet_hal_set_truncationlen(uint32_t instance, uint32_t length)
 742 {
 743     // assert(instance < HW_ENET_INSTANCE_COUNT);
 744     assert(length <= BM_ENET_FTRL_TRUNC_FL);
 745     BW_ENET_FTRL_TRUNC_FL(instance, length);
 746 }
 747
 748 /*!
 749  * @brief Sets the maximum receive buffer size and the maximum frame size.
 750  *
 751  * @param instance The ENET instance number
 752  * @param maxBufferSize The maximum receive buffer size, which  should not be smaller than 256
 753  *        It should be evenly divisible by 16 and the maximum receive size should not be larger than 0x3ff0.
 754  * @param maxFrameSize The maximum receive frame size, the reset value is 1518 or 1522 if the VLAN tags are
 755  *        supported. The length is measured starting at DA and including the CRC.
 756  */
 757 static inline void enet_hal_set_rx_max_size(uint32_t instance, uint32_t maxBufferSize, uint32_t maxFrameSize)
 758 {
 759     // assert(instance < HW_ENET_INSTANCE_COUNT);
 760     /* max buffer size must larger than 256 to minimize bus usage*/
 761     assert(maxBufferSize >= 256);
 762     assert(maxFrameSize <= (BM_ENET_RCR_MAX_FL >> BP_ENET_RCR_MAX_FL));
 763
 764     BW_ENET_RCR_MAX_FL(instance, maxFrameSize);
 765     HW_ENET_MRBR_WR(instance, (maxBufferSize & BM_ENET_MRBR_R_BUF_SIZE));
 766 }
 767
 768 /*!
 769  * @brief Configures the ENET transmit FIFO.
 770  *
 771  * @param instance The ENET instance number
 772  * @param thresholdCfg The FIFO threshold configuration
 773  */
 774 void enet_hal_config_tx_fifo(uint32_t instance, enet_config_tx_fifo_t *thresholdCfg);
 775
 776 /*!
 777  * @brief Configures the ENET receive FIFO.
 778  *
 779  * @param instance The ENET instance number
 780  * @param thresholdCfg The FIFO threshold configuration
 781  */
 782 void enet_hal_config_rx_fifo(uint32_t instance, enet_config_rx_fifo_t *thresholdCfg);
 783
 784 /*!
 785  * @brief Sets the start address for ENET receive buffer descriptors.
 786  *
 787  * This interface provides the beginning of the receive
 788  * and receive buffer descriptor queue in the external memory. The
 789  * txbdAddr is recommended to be 128-bit aligned, must be evenly divisible by 16.
 790  *
 791  * @param instance The ENET instance number
 792  * @param rxBdAddr The start address of receive buffer descriptors
 793  */
 794 static inline void enet_hal_set_rxbd_address(uint32_t instance, uint32_t rxBdAddr)
 795 {
 796     // assert(instance < HW_ENET_INSTANCE_COUNT);
 797
 798     HW_ENET_RDSR_WR(instance,rxBdAddr);   /* Initialize receive buffer descriptor start address*/
 799 }
 800 /*!
 801  * @brief Sets the start address for ENET transmit buffer descriptors.
 802  *
 803  * This interface provides the beginning of the receive
 804  * and transmit buffer descriptor queue in the external memory. The
 805  * txbdAddr is recommended to be 128-bit aligned, must be evenly divisible by 16.
 806  *
 807  * @param instance The ENET instance number
 808  * @param txBdAddr The start address of transmit buffer descriptors
 809  */
 810 static inline void enet_hal_set_txbd_address(uint32_t instance, uint32_t txBdAddr)
 811 {
 812     // assert(instance < HW_ENET_INSTANCE_COUNT);
 813
 814     HW_ENET_TDSR_WR(instance,txBdAddr);   /* Initialize transmit buffer descriptor start address*/
 815 }
 816
 817 /*!
 818  * @brief Initializes the receive buffer descriptors.
 819  *
 820  * To make sure the uDMA will do the right data transfer after you activate
 821  * with wrap flag and all the buffer descriptors should be initialized with an empty bit.
 822  *
 823  * @param rxBds The current receive buffer descriptor
 824  * @param buffer The data buffer on buffer descriptor
 825  * @param isLastBd The flag to indicate the last receive buffer descriptor
 826  */
 827 void enet_hal_init_rxbds(void *rxBds, uint8_t *buffer, bool isLastBd);
 828
 829 /*!
 830  * @brief Initializes the  transmit buffer descriptors.
 831  *
 832  * To make sure the uDMA will do the right data transfer after you active
 833  * with wrap flag.
 834  *
 835  * @param txBds The current transmit buffer descriptor.
 836  * @param isLastBd The last transmit buffer descriptor flag.
 837  */
 838 void enet_hal_init_txbds(void *txBds, bool isLastBd);
 839
 840 /*!
 841  * @brief Updates the receive buffer descriptors.
 842  *
 843  * This interface mainly clears the status region and updates the received
 844  * buffer descriptor to ensure that the BD is  correctly used.
 845  *
 846  * @param rxBds The current receive buffer descriptor
 847  * @param data The data buffer address
 848  * @param isbufferUpdate The data buffer update flag. When you want to update
 849  *        the data buffer of the buffer descriptor ensure that this flag
 850  *        is set.
 851  */
 852 void enet_hal_update_rxbds(void *rxBds, uint8_t *data, bool isbufferUpdate);
 853
 854 /*!
 855  * @brief Initializes the transmit buffer descriptors.
 856  *
 857  * Ensures that the uDMA transfer data correctly after the user activates
 858  * with the wrap flag.
 859  *
 860  * @param txBds The current transmit buffer descriptor
 861  * @param isLastBd The last transmit buffer descriptor flag
 862  */
 863 void enet_hal_init_txbds(void *txBds, bool isLastBd);
 864
 865 /*!
 866  * @brief Updates the transmit buffer descriptors.
 867  *
 868  * This interface mainly clears the status region and updates the transmit
 869  * buffer descriptor to ensure tat this BD is  correctly used again.
 870  * You should set the isTxtsCfged when the transmit timestamp feature is required.
 871  *
 872  * @param txBds The current transmit buffer descriptor
 873  * @param buffer The data buffer on buffer descriptor
 874  * @param length The data length on buffer descriptor
 875  * @param isTxtsCfged The timestamp configure flag. The timestamp is
 876  *        added to the transmit buffer descriptor when this flag is set.
 877  */
 878 void enet_hal_update_txbds(void *txBds,uint8_t *buffer, uint16_t length, bool isTxtsCfged);
 879
 880 /*!
 881  * @brief Clears the context in the transmit buffer descriptors.
 882  *
 883  * Clears the data, length, control, and status region of the transmit buffer descriptor.
 884  *
 885  * @param curBd The current buffer descriptor
 886  */
 887 static inline void enet_hal_clear_txbds(void *curBd)
 888 {
 889     assert(curBd);
 890
 891     volatile enet_bd_struct_t *bdPtr = (enet_bd_struct_t *)curBd;
 892     bdPtr->length = 0;                /* Set data length*/
 893     bdPtr->buffer = (uint8_t *)(NULL);/* Set data buffer*/
 894     bdPtr->control &= (kEnetTxBdWrap);/* Set control */
 895 }
 896
 897 /*!
 898  * @brief Gets the control and the status region of the receive buffer descriptors.
 899  *
 900  * This interface can get the whole control and status region of the
 901  * receive buffer descriptor. The enet_rx_bd_control_status_t enum type
 902  * definition should be used if you want to get each status bit of
 903  * the control and status region.
 904  *
 905  * @param curBd The current receive buffer descriptor
 906  * @return The control and status data on buffer descriptors
 907  */
 908 uint16_t enet_hal_get_rxbd_control(void *curBd);
 909
 910 /*!
 911  * @brief Gets the control and the status region of the transmit buffer descriptors.
 912  *
 913  * This interface can get the whole control and status region of the
 914  * transmit buffer descriptor. The enet_tx_bd_control_status_t enum type
 915  * definition should be used if you want to get each status bit of
 916  * the control and status region.
 917  *
 918  * @param curBd The current transmit buffer descriptor
 919  * @return The extended control region of transmit buffer descriptor
 920  */
 921 uint16_t enet_hal_get_txbd_control(void *curBd);
 922
 923 /*!
 924  * @brief Gets the extended control region of the receive buffer descriptors.
 925  *
 926  * This interface can get the whole control and status region of the
 927  * receive buffer descriptor. The enet_rx_bd_control_extend_t enum type
 928  * definition should be used if you want to get each status bit of
 929  * the control and status region.
 930  *
 931  * @param curBd The current receive buffer descriptor
 932  * @param controlRegion The different control region
 933  * @return The extended control region data of receive buffer descriptor
 934  *         - true when the control region is set
 935  *         - false when the control region is not set
 936  */
 937 bool enet_hal_get_rxbd_control_extend(void *curBd,enet_rx_bd_control_extend_t controlRegion);
 938 /*!
 939  * @brief Gets the extended control region of the transmit buffer descriptors.
 940  *
 941  * This interface can get the whole control and status region of the
 942  * transmit buffer descriptor. The enet_tx_bd_control_extend_t enum type
 943  * definition should be used if you want to get each status bit of
 944  * the control and status region.
 945  *
 946  * @param curBd The current transmit buffer descriptor
 947  * @return The extended control data
 948  */
 949 uint16_t enet_hal_get_txbd_control_extend(void *curBd);
 950
 951 /*!
 952  * @brief Gets  the data length of the buffer descriptors.
 953  *
 954  * @param curBd The current buffer descriptor
 955  * @return The data length of the buffer descriptor
 956  */
 957 uint16_t enet_hal_get_bd_length(void *curBd);
 958
 959 /*!
 960  * @brief Gets the buffer address of the buffer descriptors.
 961  *
 962  * @param curBd The current buffer descriptor
 963  * @return The buffer address of the buffer descriptor
 964  */
 965 uint8_t* enet_hal_get_bd_buffer(void *curBd);
 966
 967 /*!
 968  * @brief Gets  the timestamp of the buffer descriptors.
 969  *
 970  * @param curBd The current buffer descriptor
 971  * @return The time stamp of the frame in the buffer descriptor.
 972  *         Notice that the frame timestamp is only set in the last
 973  *         buffer descriptor of the frame.
 974  */
 975 uint32_t enet_hal_get_bd_timestamp(void *curBd);
 976
 977 /*!
 978  * @brief Activates the receive buffer descriptor.
 979  *
 980  * The buffer descriptor activation
 981  * should be done after the ENET module is enabled. Otherwise, the activation  fails.
 982  *
 983  * @param instance The ENET instance number
 984  */
 985  static inline void enet_hal_active_rxbd(uint32_t instance)
 986 {
 987     // assert(instance < HW_ENET_INSTANCE_COUNT);
 988
 989     HW_ENET_RDAR_SET(instance, BM_ENET_RDAR_RDAR);
 990 }
 991
 992 /*!
 993  * @brief Activates the transmit buffer descriptor.
 994  *
 995  * The  buffer descriptor activation should be done after the ENET module is
 996  * enabled. Otherwise, the activation  fails.
 997  *
 998  * @param instance The ENET instance number
 999  */
1000 static inline void enet_hal_active_txbd(uint32_t instance)
1001 {
1002     // assert(instance < HW_ENET_INSTANCE_COUNT);
1003
1004     HW_ENET_TDAR_SET(instance, BM_ENET_TDAR_TDAR);
1005 }
1006
1007 /*!
1008  * @brief Configures the (R)MII of ENET.
1009  *
1010  * @param instance The ENET instance number
1011  * @param mode The RMII or MII mode
1012  * @param speed The speed of RMII
1013  * @param duplex The full or half duplex mode
1014  * @param isRxOnTxDisabled The Receive on transmit disable flag
1015  * @param isLoopEnabled The loop enable flag
1016  */
1017 void enet_hal_config_rmii(uint32_t instance, enet_config_rmii_t mode, enet_config_speed_t speed, enet_config_duplex_t duplex, bool isRxOnTxDisabled,  bool isLoopEnabled);
1018
1019 /*!
1020  * @brief Configures the MII of ENET.
1021  *
1022  * Sets the MII interface between Mac and PHY. The miiSpeed is
1023  * a value that controls the frequency of the MDC, relative to the internal module clock(InterClockSrc).
1024  * A value of zero in this parameter turns the MDC off and leaves it in the low voltage state.
1025  * Any non-zero value results in the MDC frequency MDC = InterClockSrc/((miiSpeed + 1)*2).
1026  * So miiSpeed = InterClockSrc/(2*MDC) - 1.
1027  * The Maximum MDC clock is 2.5MHZ(maximum). We should round up and plus one to simlplify:
1028  *  miiSpeed = InterClockSrc/(2*2.5MHZ).
1029  *
1030  * @param instance The ENET instance number
1031  * @param miiSpeed The MII speed and it is ranged from 0~0x3F
1032  * @param time The holdon clock cycles for MDIO output
1033  * @param isPreambleDisabled The preamble disabled flag
1034  */
1035 static inline void enet_hal_config_mii(uint32_t instance, uint32_t miiSpeed,
1036                               enet_mdio_holdon_clkcycle_t clkCycle, bool isPreambleDisabled)
1037 {
1038     // assert(instance < HW_ENET_INSTANCE_COUNT);
1039
1040     BW_ENET_MSCR_MII_SPEED(instance, miiSpeed);          /* MII speed set*/
1041     BW_ENET_MSCR_DIS_PRE(instance, isPreambleDisabled);  /* Preamble is disabled*/
1042     BW_ENET_MSCR_HOLDTIME(instance, clkCycle);  /* hold on clock cycles for MDIO output*/
1043
1044 }
1045
1046 /*!
1047  * @brief Gets the MII configuration status.
1048  *
1049  * This interface is usually called to check the MII interface before
1050  * the Mac  writes or reads the PHY registers.
1051  *
1052  * @param instance The ENET instance number
1053  * @return The MII configuration status
1054  *         - true if the MII has been configured.
1055  *         - false if the MII has not been configured.
1056  */
1057 static inline bool enet_hal_is_mii_enabled(uint32_t instance)
1058 {
1059     // assert(instance < HW_ENET_INSTANCE_COUNT);
1060
1061     return (HW_ENET_MSCR_RD(instance) & 0x7E)!= 0;
1062 }
1063
1064 /*!
1065  * @brief Reads data from PHY.
1066  *
1067  * @param instance The ENET instance number
1068  * @return The data read from PHY
1069  */
1070 static inline uint32_t enet_hal_get_mii_data(uint32_t instance)
1071 {
1072     // assert(instance < HW_ENET_INSTANCE_COUNT);
1073
1074     return (uint32_t)BR_ENET_MMFR_DATA(instance);
1075 }
1076
1077 /*!
1078  * @brief Sets the MII command.
1079  *
1080  * @param instance The ENET instance number
1081  * @param phyAddr The PHY address
1082  * @param phyReg The PHY register
1083  * @param operation The read or write operation
1084  * @param data The data written to PHY
1085  */
1086 void enet_hal_set_mii_command(uint32_t instance, uint32_t phyAddr, uint32_t phyReg, enet_mii_operation_t operation, uint32_t data);
1087
1088 /*!
1089  * @brief Enables/Disables the ENET module.
1090  *
1091  * @param instance The ENET instance number
1092  * @param isEnhanced The enhanced 1588 feature switch
1093  * @param isEnabled The ENET module enable switch
1094  */
1095 void enet_hal_config_ethernet(uint32_t instance, bool isEnhanced, bool isEnabled);
1096
1097 /*!
1098  * @brief Enables/Disables the ENET interrupt.
1099  *
1100  * @param instance The ENET instance number
1101  * @param source The interrupt sources. enet_interrupt_request_t enum types
1102  *        is recommended as the interrupt source.
1103  * @param isEnabled The interrupt enable switch
1104  */
1105 void enet_hal_config_interrupt(uint32_t instance, uint32_t source, bool isEnabled);
1106
1107 /*!
1108  * @brief Clears  ENET interrupt events.
1109  *
1110  * @param instance The ENET instance number
1111  * @param source The interrupt source to be cleared. enet_interrupt_request_t
1112  *        enum types is recommended as the interrupt source.
1113  */
1114 static inline void enet_hal_clear_interrupt(uint32_t instance, uint32_t source)
1115 {
1116     // assert(instance < HW_ENET_INSTANCE_COUNT);
1117
1118     HW_ENET_EIR_WR(instance,source);
1119 }
1120
1121 /*!
1122  * @brief Gets the ENET interrupt status.
1123  *
1124  * @param instance The ENET instance number
1125  * @param source The interrupt sources. enet_interrupt_request_t
1126  *        enum types is recommended as the interrupt source.
1127  * @return The event status of the interrupt source
1128  *         - true if the interrupt event happened.
1129  *         - false if the interrupt event has not happened.
1130  */
1131 static inline bool enet_hal_get_interrupt_status(uint32_t instance, uint32_t source)
1132 {
1133     // assert(instance < HW_ENET_INSTANCE_COUNT);
1134
1135     return ((HW_ENET_EIR_RD(instance) & source) != 0);
1136 }
1137
1138 /*
1139  * @brief Enables/disables the ENET promiscuous mode.
1140  *
1141  * @param instance The ENET instance number
1142  * @param isEnabled The enable switch
1143  */
1144 static inline void enet_hal_config_promiscuous(uint32_t instance, bool isEnabled)
1145 {
1146     // assert(instance < HW_ENET_INSTANCE_COUNT);
1147
1148     BW_ENET_RCR_PROM(instance,isEnabled);
1149 }
1150
1151 /*!
1152  * @brief Enables/disables the clear MIB counter.
1153  *
1154  * @param instance The ENET instance number
1155  * @param isEnabled The enable switch
1156  */
1157 static inline void enet_hal_clear_mib(uint32_t instance, bool isEnabled)
1158 {
1159     // assert(instance < HW_ENET_INSTANCE_COUNT);
1160
1161     BW_ENET_MIBC_MIB_CLEAR(instance, isEnabled);
1162
1163 }
1164
1165 /*!
1166  * @brief Sets the enable/disable of the MIB block.
1167  *
1168  * @param instance The ENET instance number
1169  * @param isEnabled The enable flag
1170  *             - True to enabale MIB block.
1171  *             - False to disable MIB block.
1172  */
1173 static inline void enet_hal_enable_mib(uint32_t instance, bool isEnabled)
1174 {
1175     // assert(instance < HW_ENET_INSTANCE_COUNT);
1176
1177     BW_ENET_MIBC_MIB_DIS(instance,!isEnabled);
1178
1179 }
1180
1181 /*!
1182  * @brief Gets the MIB idle status.
1183  *
1184  * @param instance The ENET instance number
1185  * @return true if in MIB idle and MIB is not updating else false.
1186  */
1187 static inline bool enet_hal_get_mib_status(uint32_t instance)
1188 {
1189     // assert(instance < HW_ENET_INSTANCE_COUNT);
1190
1191     return BR_ENET_MIBC_MIB_IDLE(instance);
1192 }
1193
1194 /*!
1195  * @brief Sets the transmit accelerator.
1196  *
1197  * @param instance The ENET instance number
1198  * @param txCfgPtr The transmit accelerator configuration
1199  */
1200 void enet_hal_config_tx_accelerator(uint32_t instance, enet_config_tx_accelerator_t *txCfgPtr);
1201
1202 /*!
1203  * @brief Sets the receive accelerator.
1204  *
1205  * @param instance The ENET instance number
1206  * @param rxCfgPtr The receive accelerator configuration
1207  */
1208 void enet_hal_config_rx_accelerator(uint32_t instance, enet_config_rx_accelerator_t *rxCfgPtr);
1209
1210 /*!
1211  * @brief Initializes the 1588 timer.
1212  *
1213  * This interface  initializes the 1588 context structure.
1214  * Initialize 1588 parameters according to the user configuration structure.
1215  *
1216  * @param instance The ENET instance number
1217  * @param ptpCfg The 1588 timer configuration
1218  */
1219 void enet_hal_init_ptp_timer(uint32_t instance, enet_config_ptp_timer_t *ptpCfgPtr);
1220
1221 /*!
1222  * @brief Enables or disables the 1588 timer.
1223  *
1224  * Enable the PTP timer will starts the timer. Disable the timer will stop timer
1225  * at the current value.
1226  *
1227  * @param instance The ENET instance number.
1228  * @param isEnabled The 1588 timer Enable switch
1229  *              - True enbaled the 1588 PTP timer.
1230  *              - False disable or stop the 1588 PTP timer.
1231  */
1232 static inline void enet_hal_enable_ptp_timer(uint32_t instance, uint32_t isEnabled)
1233 {
1234     // assert(instance < HW_ENET_INSTANCE_COUNT);
1235
1236     BW_ENET_ATCR_EN(instance,isEnabled);
1237 }
1238
1239 /*!
1240  * @brief Restarts the 1588 timer.
1241  *
1242  * Restarting the PTP timer  clears all PTP-timer counters to zero.
1243  *
1244  * @param instance The ENET instance number
1245  */
1246 static inline void enet_hal_restart_ptp_timer(uint32_t instance)
1247 {
1248     // assert(instance < HW_ENET_INSTANCE_COUNT);
1249
1250     BW_ENET_ATCR_RESTART(instance,1);
1251 }
1252
1253 /*!
1254  * @brief Adjusts the 1588 timer.
1255  *
1256  * Adjust the 1588 timer according to the increase and correction period of the configured correction.
1257  *
1258  * @param instance The ENET instance number
1259  * @param inceaseCorrection The increase correction for 1588 timer
1260  * @param periodCorrection The period correction for 1588 timer
1261  */
1262 static inline void enet_hal_adjust_ptp_timer(uint32_t instance, uint32_t increaseCorrection, uint32_t periodCorrection)
1263 {
1264     // assert(instance < HW_ENET_INSTANCE_COUNT);
1265
1266     HW_ENET_ATINC_SET(instance,((increaseCorrection << ENET_ATINC_INC_CORR_SHIFT) & ENET_ATINC_INC_CORR_MASK));      /* set correction for ptp timer increase*/
1267     /* set correction for ptp timer period*/
1268     HW_ENET_ATCOR_SET(instance, (BM_ENET_ATCOR_COR & periodCorrection));
1269 }
1270
1271 /*!
1272  * @brief Initializes the 1588 timer channel.
1273  *
1274  * @param instance The ENET instance number
1275  * @Param channel The 1588 timer channel number
1276  * @param mode Compare or capture mode for the 1588 timer channel
1277  */
1278 static inline void enet_hal_init_timer_channel(uint32_t instance, uint32_t channel, enet_timer_channel_mode_t mode)
1279 {
1280     // assert(instance < HW_ENET_INSTANCE_COUNT);
1281     assert(channel < HW_ENET_TCSRn_COUNT);
1282     HW_ENET_TCSRn_SET(instance, channel,
1283         (BM_ENET_TCSRn_TMODE &(mode << BP_ENET_TCSRn_TMODE)));
1284     HW_ENET_TCSRn_SET(instance, channel, BM_ENET_TCSRn_TIE);
1285 }
1286
1287 /*!
1288  * @brief Sets the compare value for the 1588 timer channel.
1289  *
1290  * @param instance The ENET instance number
1291  * @Param channel The 1588 timer channel number
1292  * @param compareValue Compare value for 1588 timer channel
1293  */
1294 static inline void enet_hal_set_timer_channel_compare(uint32_t instance, uint32_t channel, uint32_t compareValue)
1295 {
1296     assert(instance < HW_ENET_INSTANCE_COUNT);
1297     assert(channel < HW_ENET_TCSRn_COUNT);
1298     HW_ENET_TCCRn_WR(instance,channel, compareValue);
1299 }
1300
1301 /*!
1302  * @brief Gets the 1588 timer channel status.
1303  *
1304  * @param instance The ENET instance number
1305  * @param channel The 1588 timer channel number
1306  * @return Compare or capture operation status
1307  *         - True if the compare or capture has occurred.
1308  *         - False if the compare or capture has not occurred.
1309  */
1310 static inline bool enet_hal_get_timer_channel_status(uint32_t instance, uint32_t channel)
1311 {
1312     // assert(instance < HW_ENET_INSTANCE_COUNT);
1313     assert(channel < HW_ENET_TCSRn_COUNT);
1314
1315     return BR_ENET_TCSRn_TF(instance,channel);
1316 }
1317
1318 /*!
1319  * @brief Clears the 1588 timer channel flag.
1320  *
1321  * @param instance The ENET instance number
1322  * @param channel The 1588 timer channel number
1323  */
1324 static inline void enet_hal_clear_timer_channel_flag(uint32_t instance, uint32_t channel)
1325 {
1326     // assert(instance < HW_ENET_INSTANCE_COUNT);
1327     assert(channel < HW_ENET_TCSRn_COUNT);
1328     HW_ENET_TCSRn_SET(instance, channel, BM_ENET_TCSRn_TF);/* clear interrupt flag*/
1329     HW_ENET_TGSR_WR(instance,(1U << channel));            /* clear channel flag*/
1330 }
1331
1332 /*!
1333  * @brief Sets the capture command to the 1588 timer.
1334  *
1335  * This is used before reading the current time register.
1336  * After set timer capture, please wait for about 1us before read
1337  * the captured timer.
1338  *
1339  * @param instance The ENET instance number
1340  */
1341 static inline void enet_hal_set_timer_capture(uint32_t instance)
1342 {
1343     assert(instance < HW_ENET_INSTANCE_COUNT);
1344
1345     HW_ENET_ATCR_SET(instance, BM_ENET_ATCR_CAPTURE);
1346 }
1347
1348 /*!
1349  * @brief Sets the 1588 timer.
1350  *
1351  * @param instance The ENET instance number
1352  * @param nanSecond The nanosecond set to 1588 timer
1353  */
1354 static inline void enet_hal_set_current_time(uint32_t instance, uint32_t nanSecond)
1355 {
1356     // assert(instance < HW_ENET_INSTANCE_COUNT);
1357
1358     HW_ENET_ATVR_WR(instance,nanSecond);
1359 }
1360
1361 /*!
1362  * @brief Gets the time from the 1588 timer.
1363  *
1364  * @param instance The ENET instance number
1365  * @return the current time from 1588 timer
1366  */
1367 static inline uint32_t enet_hal_get_current_time(uint32_t instance)
1368 {
1369     // assert(instance < HW_ENET_INSTANCE_COUNT);
1370
1371     return HW_ENET_ATVR_RD(instance);
1372 }
1373
1374 /*!
1375  * @brief Gets the transmit timestamp.
1376  *
1377  * @param instance The ENET instance number
1378  * @return The timestamp of the last transmitted frame
1379  */
1380 static inline uint32_t enet_hal_get_tx_timestamp(uint32_t instance)
1381 {
1382     // assert(instance < HW_ENET_INSTANCE_COUNT);
1383
1384     return HW_ENET_ATSTMP_RD(instance);
1385 }
1386
1387 /*!
1388  * @brief Gets the transmit buffer descriptor timestamp flag.
1389  *
1390  * @param curBd The ENET transmit buffer descriptor
1391  * @return true if timestamp region is set else false.
1392  */
1393 bool enet_hal_get_txbd_timestamp_flag(void *curBd);
1394
1395 /*!
1396  * @brief Gets the buffer descriptor timestamp.
1397  *
1398  * @param null
1399  * @return The the size of the buffer descriptor
1400  */
1401 static inline uint32_t enet_hal_get_bd_size(void)
1402 {
1403     return sizeof(enet_bd_struct_t);
1404 }
1405
1406 /* @} */
1407
1408 #if defined(__cplusplus)
1409 }
1410 #endif
1411
1412 #endif
1413
1414 /*! @}*/
1415 #endif /*!< __FSL_ENET_HAL_H__*/
1416
1417 /*******************************************************************************
1418  * EOF
1419  ******************************************************************************/
1420