tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/flextimer/fsl_ftm_features.h

   1 /*
   2 ** ###################################################################
   3 **     Version:             rev. 1.0, 2014-05-14
   4 **     Build:               b140515
   5 **
   6 **     Abstract:
   7 **         Chip specific module features.
   8 **
   9 **     Copyright: 2014 Freescale Semiconductor, Inc.
  10 **     All rights reserved.
  11 **
  12 **     Redistribution and use in source and binary forms, with or without modification,
  13 **     are permitted provided that the following conditions are met:
  14 **
  15 **     o Redistributions of source code must retain the above copyright notice, this list
  16 **       of conditions and the following disclaimer.
  17 **
  18 **     o Redistributions in binary form must reproduce the above copyright notice, this
  19 **       list of conditions and the following disclaimer in the documentation and/or
  20 **       other materials provided with the distribution.
  21 **
  22 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  23 **       contributors may be used to endorse or promote products derived from this
  24 **       software without specific prior written permission.
  25 **
  26 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  27 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  28 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  29 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  30 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  31 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  32 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  33 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  35 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36 **
  37 **     http:                 www.freescale.com
  38 **     mail:                 support@freescale.com
  39 **
  40 **     Revisions:
  41 **     - rev. 1.0 (2014-05-14)
  42 **         Customer release.
  43 **
  44 ** ###################################################################
  45 */
  46
  47 #if !defined(__FSL_FTM_FEATURES_H__)
  48 #define __FSL_FTM_FEATURES_H__
  49
  50 #if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \
  51     defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || \
  52     defined(CPU_MKV30F128VLF10) || defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10)
  53     /* @brief Bus clock is the source clock for the module. */
  54     #define FSL_FEATURE_FTM_BUS_CLOCK (1)
  55     /* @brief Number of channels. */
  56     #define FSL_FEATURE_FTM_CHANNEL_COUNT (6)
  57     #define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \
  58         ((x) == 0 ? (6) : \
  59         ((x) == 1 ? (2) : \
  60         ((x) == 2 ? (2) : (-1))))
  61     /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
  62     #define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (1)
  63 #elif defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \
  64     defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \
  65     defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \
  66     defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \
  67     defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \
  68     defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \
  69     defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \
  70     defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5)
  71     /* @brief Bus clock is the source clock for the module. */
  72     #define FSL_FEATURE_FTM_BUS_CLOCK (1)
  73     /* @brief Number of channels. */
  74     #define FSL_FEATURE_FTM_CHANNEL_COUNT (8)
  75     #define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \
  76         ((x) == 0 ? (8) : \
  77         ((x) == 1 ? (2) : (-1)))
  78     /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
  79     #define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0)
  80 #elif defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || \
  81     defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \
  82     defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12)
  83     /* @brief Bus clock is the source clock for the module. */
  84     #define FSL_FEATURE_FTM_BUS_CLOCK (1)
  85     /* @brief Number of channels. */
  86     #define FSL_FEATURE_FTM_CHANNEL_COUNT (8)
  87     #define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \
  88         ((x) == 0 ? (8) : \
  89         ((x) == 1 ? (2) : \
  90         ((x) == 2 ? (2) : (-1))))
  91     /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
  92     #define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (1)
  93 #elif defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MKV31F512VLH12) || \
  94     defined(CPU_MKV31F512VLL12)
  95     /* @brief Bus clock is the source clock for the module. */
  96     #define FSL_FEATURE_FTM_BUS_CLOCK (1)
  97     /* @brief Number of channels. */
  98     #define FSL_FEATURE_FTM_CHANNEL_COUNT (8)
  99     #define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \
 100         ((x) == 0 ? (8) : \
 101         ((x) == 1 ? (2) : \
 102         ((x) == 2 ? (2) : \
 103         ((x) == 3 ? (8) : (-1)))))
 104     /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
 105     #define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (1)
 106 #elif defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK24FN256VDC12) || \
 107     defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || \
 108     defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || \
 109     defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || \
 110     defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || \
 111     defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) || defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || \
 112     defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || \
 113     defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15)
 114     /* @brief Bus clock is the source clock for the module. */
 115     #define FSL_FEATURE_FTM_BUS_CLOCK (1)
 116     /* @brief Number of channels. */
 117     #define FSL_FEATURE_FTM_CHANNEL_COUNT (8)
 118     #define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \
 119         ((x) == 0 ? (8) : \
 120         ((x) == 1 ? (2) : \
 121         ((x) == 2 ? (2) : \
 122         ((x) == 3 ? (8) : (-1)))))
 123     /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
 124     #define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0)
 125 #elif defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F64VLH15) || defined(CPU_MKV45F128VLH15) || \
 126     defined(CPU_MKV45F256VLH15) || defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F256VLH15)
 127     /* @brief Bus clock is the source clock for the module. */
 128     #define FSL_FEATURE_FTM_BUS_CLOCK (1)
 129     /* @brief Number of channels. */
 130     #define FSL_FEATURE_FTM_CHANNEL_COUNT (8)
 131     #define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \
 132         ((x) == 0 ? (8) : \
 133         ((x) == 1 ? (2) : (-1)))
 134     /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
 135     #define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (1)
 136 #elif defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLL15) || defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLL15) || \
 137     defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLL15)
 138     /* @brief Bus clock is the source clock for the module. */
 139     #define FSL_FEATURE_FTM_BUS_CLOCK (1)
 140     /* @brief Number of channels. */
 141     #define FSL_FEATURE_FTM_CHANNEL_COUNT (8)
 142     #define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \
 143         ((x) == 0 ? (8) : \
 144         ((x) == 1 ? (2) : \
 145         ((x) == 2 ? (8) : (-1))))
 146     /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
 147     #define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (1)
 148 #else
 149     #error "No valid CPU defined!"
 150 #endif
 151
 152 #endif /* __FSL_FTM_FEATURES_H__ */
 153
 154 /*******************************************************************************
 155  * EOF
 156  ******************************************************************************/