tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/gpio/fsl_gpio_features.h

   1 /*
   2 ** ###################################################################
   3 **     Version:             rev. 1.0, 2014-05-14
   4 **     Build:               b140515
   5 **
   6 **     Abstract:
   7 **         Chip specific module features.
   8 **
   9 **     Copyright: 2014 Freescale Semiconductor, Inc.
  10 **     All rights reserved.
  11 **
  12 **     Redistribution and use in source and binary forms, with or without modification,
  13 **     are permitted provided that the following conditions are met:
  14 **
  15 **     o Redistributions of source code must retain the above copyright notice, this list
  16 **       of conditions and the following disclaimer.
  17 **
  18 **     o Redistributions in binary form must reproduce the above copyright notice, this
  19 **       list of conditions and the following disclaimer in the documentation and/or
  20 **       other materials provided with the distribution.
  21 **
  22 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  23 **       contributors may be used to endorse or promote products derived from this
  24 **       software without specific prior written permission.
  25 **
  26 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  27 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  28 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  29 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  30 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  31 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  32 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  33 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  35 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36 **
  37 **     http:                 www.freescale.com
  38 **     mail:                 support@freescale.com
  39 **
  40 **     Revisions:
  41 **     - rev. 1.0 (2014-05-14)
  42 **         Customer release.
  43 **
  44 ** ###################################################################
  45 */
  46
  47 #if !defined(__FSL_GPIO_FEATURES_H__)
  48 #define __FSL_GPIO_FEATURES_H__
  49
  50 #if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \
  51     defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || \
  52     defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || \
  53     defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || \
  54     defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || \
  55     defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || \
  56     defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || \
  57     defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || \
  58     defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || \
  59     defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || \
  60     defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \
  61     defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MK24FN1M0VDC12) || \
  62     defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK24FN256VDC12) || defined(CPU_MK63FN1M0VLQ12) || \
  63     defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || \
  64     defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || \
  65     defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || \
  66     defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || \
  67     defined(CPU_MK66FX1M0VMD18) || defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || defined(CPU_MKV30F128VLF10) || \
  68     defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) || defined(CPU_MKV31F128VLH10) || \
  69     defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31F512VLH12) || \
  70     defined(CPU_MKV31F512VLL12)
  71     /* @brief Has fast (single cycle) access capability via a dedicated memory region. */
  72     #define FSL_FEATURE_GPIO_HAS_FAST_GPIO (0)
  73     /* @brief Has port input disable register (PIDR). */
  74     #define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0)
  75     /* @brief Has dedicated interrupt vector. */
  76     #define FSL_FEATURE_GPIO_HAS_INTERRUPT_VECTOR (1)
  77     #define FSL_FEATURE_GPIO_HAS_INTERRUPT_VECTORn(x) \
  78         ((x) == 0 ? (1) : \
  79         ((x) == 1 ? (1) : \
  80         ((x) == 2 ? (1) : \
  81         ((x) == 3 ? (1) : \
  82         ((x) == 4 ? (1) : (-1))))))
  83 #elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \
  84     defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15)
  85     /* @brief Has fast (single cycle) access capability via a dedicated memory region. */
  86     #define FSL_FEATURE_GPIO_HAS_FAST_GPIO (0)
  87     /* @brief Has port input disable register (PIDR). */
  88     #define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0)
  89     /* @brief Has dedicated interrupt vector. */
  90     #define FSL_FEATURE_GPIO_HAS_INTERRUPT_VECTOR (1)
  91     #define FSL_FEATURE_GPIO_HAS_INTERRUPT_VECTORn(x) \
  92         ((x) == 0 ? (1) : \
  93         ((x) == 1 ? (1) : \
  94         ((x) == 2 ? (1) : \
  95         ((x) == 3 ? (1) : \
  96         ((x) == 4 ? (1) : \
  97         ((x) == 5 ? (1) : (-1)))))))
  98 #elif defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || defined(CPU_MKL03Z32VFG4) || \
  99     defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || defined(CPU_MKL03Z32VFK4) || defined(CPU_MKL05Z8VFK4) || \
 100     defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || defined(CPU_MKL05Z16VLC4) || \
 101     defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || defined(CPU_MKL05Z32VFM4) || \
 102     defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4)
 103     /* @brief Has fast (single cycle) access capability via a dedicated memory region. */
 104     #define FSL_FEATURE_GPIO_HAS_FAST_GPIO (1)
 105     /* @brief Has port input disable register (PIDR). */
 106     #define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0)
 107     /* @brief Has dedicated interrupt vector. */
 108     #define FSL_FEATURE_GPIO_HAS_INTERRUPT_VECTOR (1)
 109     #define FSL_FEATURE_GPIO_HAS_INTERRUPT_VECTORn(x) \
 110         ((x) == 0 ? (1) : \
 111         ((x) == 1 ? (1) : (-1)))
 112 #elif defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || \
 113     defined(CPU_MKL13Z128VFT4) || defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || \
 114     defined(CPU_MKL13Z256VLH4) || defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || \
 115     defined(CPU_MKL23Z64VFM4) || defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || \
 116     defined(CPU_MKL23Z128VFT4) || defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || \
 117     defined(CPU_MKL23Z256VLH4) || defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || \
 118     defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || \
 119     defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || \
 120     defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4)
 121     /* @brief Has fast (single cycle) access capability via a dedicated memory region. */
 122     #define FSL_FEATURE_GPIO_HAS_FAST_GPIO (0)
 123     /* @brief Has port input disable register (PIDR). */
 124     #define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0)
 125     /* @brief Has dedicated interrupt vector. */
 126     #define FSL_FEATURE_GPIO_HAS_INTERRUPT_VECTOR (1)
 127     #define FSL_FEATURE_GPIO_HAS_INTERRUPT_VECTORn(x) \
 128         ((x) == 0 ? (1) : \
 129         ((x) == 1 ? (0) : \
 130         ((x) == 2 ? (1) : \
 131         ((x) == 3 ? (1) : \
 132         ((x) == 4 ? (0) : (-1))))))
 133 #elif defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || \
 134     defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || \
 135     defined(CPU_MKL25Z128VLH4) || defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4)
 136     /* @brief Has fast (single cycle) access capability via a dedicated memory region. */
 137     #define FSL_FEATURE_GPIO_HAS_FAST_GPIO (1)
 138     /* @brief Has port input disable register (PIDR). */
 139     #define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0)
 140     /* @brief Has dedicated interrupt vector. */
 141     #define FSL_FEATURE_GPIO_HAS_INTERRUPT_VECTOR (1)
 142     #define FSL_FEATURE_GPIO_HAS_INTERRUPT_VECTORn(x) \
 143         ((x) == 0 ? (1) : \
 144         ((x) == 1 ? (0) : \
 145         ((x) == 2 ? (0) : \
 146         ((x) == 3 ? (1) : \
 147         ((x) == 4 ? (0) : (-1))))))
 148 #elif defined(CPU_MKL26Z256VLK4) || defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || \
 149     defined(CPU_MKL26Z256VMC4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || \
 150     defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4)
 151     /* @brief Has fast (single cycle) access capability via a dedicated memory region. */
 152     #define FSL_FEATURE_GPIO_HAS_FAST_GPIO (1)
 153     /* @brief Has port input disable register (PIDR). */
 154     #define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0)
 155     /* @brief Has dedicated interrupt vector. */
 156     #define FSL_FEATURE_GPIO_HAS_INTERRUPT_VECTOR (1)
 157     #define FSL_FEATURE_GPIO_HAS_INTERRUPT_VECTORn(x) \
 158         ((x) == 0 ? (1) : \
 159         ((x) == 1 ? (0) : \
 160         ((x) == 2 ? (1) : \
 161         ((x) == 3 ? (1) : \
 162         ((x) == 4 ? (0) : (-1))))))
 163 #elif defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F256VLL15) || \
 164     defined(CPU_MKV40F64VLH15) || defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15) || \
 165     defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) || defined(CPU_MKV45F128VLH15) || \
 166     defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || defined(CPU_MKV45F256VLL15) || defined(CPU_MKV46F128VLH15) || \
 167     defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || defined(CPU_MKV46F256VLL15)
 168     /* @brief Has fast (single cycle) access capability via a dedicated memory region. */
 169     #define FSL_FEATURE_GPIO_HAS_FAST_GPIO (0)
 170     /* @brief Has port input disable register (PIDR). */
 171     #define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0)
 172     /* @brief Has dedicated interrupt vector. */
 173     #define FSL_FEATURE_GPIO_HAS_INTERRUPT_VECTOR (1)
 174     #define FSL_FEATURE_GPIO_HAS_INTERRUPT_VECTORn(x) \
 175         ((x) == 0 ? (1) : \
 176         ((x) == 1 ? (1) : \
 177         ((x) == 2 ? (1) : \
 178         ((x) == 3 ? (1) : \
 179         ((x) == 4 ? (1) : (-1))))))
 180 #else
 181     #error "No valid CPU defined!"
 182 #endif
 183
 184 #endif /* __FSL_GPIO_FEATURES_H__ */
 185
 186 /*******************************************************************************
 187  * EOF
 188  ******************************************************************************/