tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/i2c/fsl_i2c_features.h

   1 /*
   2 ** ###################################################################
   3 **     Version:             rev. 1.0, 2014-05-14
   4 **     Build:               b140515
   5 **
   6 **     Abstract:
   7 **         Chip specific module features.
   8 **
   9 **     Copyright: 2014 Freescale Semiconductor, Inc.
  10 **     All rights reserved.
  11 **
  12 **     Redistribution and use in source and binary forms, with or without modification,
  13 **     are permitted provided that the following conditions are met:
  14 **
  15 **     o Redistributions of source code must retain the above copyright notice, this list
  16 **       of conditions and the following disclaimer.
  17 **
  18 **     o Redistributions in binary form must reproduce the above copyright notice, this
  19 **       list of conditions and the following disclaimer in the documentation and/or
  20 **       other materials provided with the distribution.
  21 **
  22 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  23 **       contributors may be used to endorse or promote products derived from this
  24 **       software without specific prior written permission.
  25 **
  26 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  27 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  28 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  29 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  30 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  31 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  32 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  33 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  35 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36 **
  37 **     http:                 www.freescale.com
  38 **     mail:                 support@freescale.com
  39 **
  40 **     Revisions:
  41 **     - rev. 1.0 (2014-05-14)
  42 **         Customer release.
  43 **
  44 ** ###################################################################
  45 */
  46
  47 #if !defined(__FSL_I2C_FEATURES_H__)
  48 #define __FSL_I2C_FEATURES_H__
  49
  50 #if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \
  51     defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || \
  52     defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || \
  53     defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || \
  54     defined(CPU_MK22FN512VLL12) || defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || \
  55     defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || \
  56     defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || \
  57     defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || \
  58     defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || \
  59     defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) || defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || \
  60     defined(CPU_MKV30F128VLF10) || defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) || \
  61     defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || \
  62     defined(CPU_MKV31F512VLH12) || defined(CPU_MKV31F512VLL12)
  63     /* @brief Has I2C bus stop detection (register bit FLT[STOPF]). */
  64     #define FSL_FEATURE_I2C_HAS_STOP_DETECT (1)
  65     /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */
  66     #define FSL_FEATURE_I2C_HAS_SMBUS (1)
  67     /* @brief Maximum supported baud rate in kilobit per second. */
  68     #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400)
  69     /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */
  70     #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0)
  71     /* @brief Has DMA support (register bit C1[DMAEN]). */
  72     #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1)
  73     /* @brief Has I2C bus start detection (register bits FLT[STARTF] and FLT[SSIE]). */
  74     #define FSL_FEATURE_I2C_HAS_START_DETECT (1)
  75     /* @brief Has I2C bus stop detection interrupt (register bit FLT[STOPIE]). */
  76     #define FSL_FEATURE_I2C_HAS_STOP_DETECT_INTERRUPT (0)
  77     /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */
  78     #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1)
  79     /* @brief Maximum width of the glitch filter in number of bus clocks. */
  80     #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15)
  81     /* @brief Has control of the drive capability of the I2C pins. */
  82     #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1)
  83     /* @brief Has double buffering support (register S2). */
  84     #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0)
  85 #elif defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \
  86     defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \
  87     defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \
  88     defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \
  89     defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \
  90     defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \
  91     defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \
  92     defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || \
  93     defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || \
  94     defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15)
  95     /* @brief Has I2C bus stop detection (register bit FLT[STOPF]). */
  96     #define FSL_FEATURE_I2C_HAS_STOP_DETECT (0)
  97     /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */
  98     #define FSL_FEATURE_I2C_HAS_SMBUS (1)
  99     /* @brief Maximum supported baud rate in kilobit per second. */
 100     #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400)
 101     /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */
 102     #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0)
 103     /* @brief Has DMA support (register bit C1[DMAEN]). */
 104     #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1)
 105     /* @brief Has I2C bus start detection (register bits FLT[STARTF] and FLT[SSIE]). */
 106     #define FSL_FEATURE_I2C_HAS_START_DETECT (0)
 107     /* @brief Has I2C bus stop detection interrupt (register bit FLT[STOPIE]). */
 108     #define FSL_FEATURE_I2C_HAS_STOP_DETECT_INTERRUPT (0)
 109     /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */
 110     #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (0)
 111     /* @brief Maximum width of the glitch filter in number of bus clocks. */
 112     #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (31)
 113     /* @brief Has control of the drive capability of the I2C pins. */
 114     #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1)
 115     /* @brief Has double buffering support (register S2). */
 116     #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0)
 117 #elif defined(CPU_MK24FN256VDC12)
 118     /* @brief Has I2C bus stop detection (register bit FLT[STOPF]). */
 119     #define FSL_FEATURE_I2C_HAS_STOP_DETECT (1)
 120     /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */
 121     #define FSL_FEATURE_I2C_HAS_SMBUS (1)
 122     /* @brief Maximum supported baud rate in kilobit per second. */
 123     #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (100)
 124     /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */
 125     #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0)
 126     /* @brief Has DMA support (register bit C1[DMAEN]). */
 127     #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1)
 128     /* @brief Has I2C bus start detection (register bits FLT[STARTF] and FLT[SSIE]). */
 129     #define FSL_FEATURE_I2C_HAS_START_DETECT (1)
 130     /* @brief Has I2C bus stop detection interrupt (register bit FLT[STOPIE]). */
 131     #define FSL_FEATURE_I2C_HAS_STOP_DETECT_INTERRUPT (0)
 132     /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */
 133     #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1)
 134     /* @brief Maximum width of the glitch filter in number of bus clocks. */
 135     #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15)
 136     /* @brief Has control of the drive capability of the I2C pins. */
 137     #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1)
 138     /* @brief Has double buffering support (register S2). */
 139     #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0)
 140 #elif defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || defined(CPU_MKL03Z32VFG4) || \
 141     defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || defined(CPU_MKL03Z32VFK4)
 142     /* @brief Has I2C bus stop detection (register bit FLT[STOPF]). */
 143     #define FSL_FEATURE_I2C_HAS_STOP_DETECT (1)
 144     /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */
 145     #define FSL_FEATURE_I2C_HAS_SMBUS (1)
 146     /* @brief Maximum supported baud rate in kilobit per second. */
 147     #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400)
 148     /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */
 149     #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0)
 150     /* @brief Has DMA support (register bit C1[DMAEN]). */
 151     #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (0)
 152     /* @brief Has I2C bus start detection (register bits FLT[STARTF] and FLT[SSIE]). */
 153     #define FSL_FEATURE_I2C_HAS_START_DETECT (1)
 154     /* @brief Has I2C bus stop detection interrupt (register bit FLT[STOPIE]). */
 155     #define FSL_FEATURE_I2C_HAS_STOP_DETECT_INTERRUPT (0)
 156     /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */
 157     #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1)
 158     /* @brief Maximum width of the glitch filter in number of bus clocks. */
 159     #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15)
 160     /* @brief Has control of the drive capability of the I2C pins. */
 161     #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (0)
 162     /* @brief Has double buffering support (register S2). */
 163     #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (1)
 164 #elif defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || \
 165     defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || \
 166     defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4) || defined(CPU_MKL25Z32VFM4) || \
 167     defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || \
 168     defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || \
 169     defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4)
 170     /* @brief Has I2C bus stop detection (register bit FLT[STOPF]). */
 171     #define FSL_FEATURE_I2C_HAS_STOP_DETECT (1)
 172     /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */
 173     #define FSL_FEATURE_I2C_HAS_SMBUS (1)
 174     /* @brief Maximum supported baud rate in kilobit per second. */
 175     #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400)
 176     /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */
 177     #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (1)
 178     /* @brief Has DMA support (register bit C1[DMAEN]). */
 179     #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1)
 180     /* @brief Has I2C bus start detection (register bits FLT[STARTF] and FLT[SSIE]). */
 181     #define FSL_FEATURE_I2C_HAS_START_DETECT (0)
 182     /* @brief Has I2C bus stop detection interrupt (register bit FLT[STOPIE]). */
 183     #define FSL_FEATURE_I2C_HAS_STOP_DETECT_INTERRUPT (1)
 184     /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */
 185     #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1)
 186     /* @brief Maximum width of the glitch filter in number of bus clocks. */
 187     #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (31)
 188     /* @brief Has control of the drive capability of the I2C pins. */
 189     #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1)
 190     /* @brief Has double buffering support (register S2). */
 191     #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0)
 192 #elif defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || \
 193     defined(CPU_MKL13Z128VFT4) || defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || \
 194     defined(CPU_MKL13Z256VLH4) || defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || \
 195     defined(CPU_MKL23Z64VFM4) || defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || \
 196     defined(CPU_MKL23Z128VFT4) || defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || \
 197     defined(CPU_MKL23Z256VLH4) || defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || \
 198     defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || \
 199     defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || \
 200     defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4)
 201     /* @brief Has I2C bus stop detection (register bit FLT[STOPF]). */
 202     #define FSL_FEATURE_I2C_HAS_STOP_DETECT (1)
 203     /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */
 204     #define FSL_FEATURE_I2C_HAS_SMBUS (1)
 205     /* @brief Maximum supported baud rate in kilobit per second. */
 206     #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400)
 207     /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */
 208     #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (1)
 209     /* @brief Has DMA support (register bit C1[DMAEN]). */
 210     #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1)
 211     /* @brief Has I2C bus start detection (register bits FLT[STARTF] and FLT[SSIE]). */
 212     #define FSL_FEATURE_I2C_HAS_START_DETECT (1)
 213     /* @brief Has I2C bus stop detection interrupt (register bit FLT[STOPIE]). */
 214     #define FSL_FEATURE_I2C_HAS_STOP_DETECT_INTERRUPT (0)
 215     /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */
 216     #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1)
 217     /* @brief Maximum width of the glitch filter in number of bus clocks. */
 218     #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15)
 219     /* @brief Has control of the drive capability of the I2C pins. */
 220     #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1)
 221     /* @brief Has double buffering support (register S2). */
 222     #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (1)
 223 #elif defined(CPU_MKL26Z256VLK4) || defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || \
 224     defined(CPU_MKL26Z256VMC4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || \
 225     defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4)
 226     /* @brief Has I2C bus stop detection (register bit FLT[STOPF]). */
 227     #define FSL_FEATURE_I2C_HAS_STOP_DETECT (1)
 228     /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */
 229     #define FSL_FEATURE_I2C_HAS_SMBUS (1)
 230     /* @brief Maximum supported baud rate in kilobit per second. */
 231     #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (100)
 232     /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */
 233     #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (1)
 234     /* @brief Has DMA support (register bit C1[DMAEN]). */
 235     #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1)
 236     /* @brief Has I2C bus start detection (register bits FLT[STARTF] and FLT[SSIE]). */
 237     #define FSL_FEATURE_I2C_HAS_START_DETECT (0)
 238     /* @brief Has I2C bus stop detection interrupt (register bit FLT[STOPIE]). */
 239     #define FSL_FEATURE_I2C_HAS_STOP_DETECT_INTERRUPT (1)
 240     /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */
 241     #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1)
 242     /* @brief Maximum width of the glitch filter in number of bus clocks. */
 243     #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (31)
 244     /* @brief Has control of the drive capability of the I2C pins. */
 245     #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1)
 246     /* @brief Has double buffering support (register S2). */
 247     #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0)
 248 #elif defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F256VLL15) || \
 249     defined(CPU_MKV40F64VLH15) || defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15) || \
 250     defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) || defined(CPU_MKV45F128VLH15) || \
 251     defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || defined(CPU_MKV45F256VLL15) || defined(CPU_MKV46F128VLH15) || \
 252     defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || defined(CPU_MKV46F256VLL15)
 253     /* @brief Has I2C bus stop detection (register bit FLT[STOPF]). */
 254     #define FSL_FEATURE_I2C_HAS_STOP_DETECT (1)
 255     /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */
 256     #define FSL_FEATURE_I2C_HAS_SMBUS (1)
 257     /* @brief Maximum supported baud rate in kilobit per second. */
 258     #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (100)
 259     /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */
 260     #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0)
 261     /* @brief Has DMA support (register bit C1[DMAEN]). */
 262     #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1)
 263     /* @brief Has I2C bus start detection (register bits FLT[STARTF] and FLT[SSIE]). */
 264     #define FSL_FEATURE_I2C_HAS_START_DETECT (0)
 265     /* @brief Has I2C bus stop detection interrupt (register bit FLT[STOPIE]). */
 266     #define FSL_FEATURE_I2C_HAS_STOP_DETECT_INTERRUPT (1)
 267     /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */
 268     #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1)
 269     /* @brief Maximum width of the glitch filter in number of bus clocks. */
 270     #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (31)
 271     /* @brief Has control of the drive capability of the I2C pins. */
 272     #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1)
 273     /* @brief Has double buffering support (register S2). */
 274     #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0)
 275 #else
 276     #error "No valid CPU defined!"
 277 #endif
 278
 279 #endif /* __FSL_I2C_FEATURES_H__ */
 280
 281 /*******************************************************************************
 282  * EOF
 283  ******************************************************************************/