tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/mcg/fsl_mcg_features.h

   1 /*
   2 ** ###################################################################
   3 **     Version:             rev. 1.0, 2014-05-14
   4 **     Build:               b140515
   5 **
   6 **     Abstract:
   7 **         Chip specific module features.
   8 **
   9 **     Copyright: 2014 Freescale Semiconductor, Inc.
  10 **     All rights reserved.
  11 **
  12 **     Redistribution and use in source and binary forms, with or without modification,
  13 **     are permitted provided that the following conditions are met:
  14 **
  15 **     o Redistributions of source code must retain the above copyright notice, this list
  16 **       of conditions and the following disclaimer.
  17 **
  18 **     o Redistributions in binary form must reproduce the above copyright notice, this
  19 **       list of conditions and the following disclaimer in the documentation and/or
  20 **       other materials provided with the distribution.
  21 **
  22 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  23 **       contributors may be used to endorse or promote products derived from this
  24 **       software without specific prior written permission.
  25 **
  26 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  27 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  28 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  29 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  30 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  31 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  32 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  33 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  35 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36 **
  37 **     http:                 www.freescale.com
  38 **     mail:                 support@freescale.com
  39 **
  40 **     Revisions:
  41 **     - rev. 1.0 (2014-05-14)
  42 **         Customer release.
  43 **
  44 ** ###################################################################
  45 */
  46
  47 #if !defined(__FSL_MCG_FEATURES_H__)
  48 #define __FSL_MCG_FEATURES_H__
  49
  50 #if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \
  51     defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || \
  52     defined(CPU_MKV30F128VLF10) || defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) || \
  53     defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10)
  54     /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV] increased by one). */
  55     #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (0)
  56     /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */
  57     #define FSL_FEATURE_MCG_PLL_VDIV_BASE (0)
  58     /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */
  59     #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0)
  60     /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1] and C8[LOCRE1]). */
  61     #define FSL_FEATURE_MCG_HAS_RTC_32K (0)
  62     /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */
  63     #define FSL_FEATURE_MCG_HAS_PLL1 (0)
  64     /* @brief Has 48MHz internal oscillator. */
  65     #define FSL_FEATURE_MCG_HAS_IRC_48M (1)
  66     /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */
  67     #define FSL_FEATURE_MCG_HAS_OSC1 (0)
  68     /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */
  69     #define FSL_FEATURE_MCG_HAS_FCFTRIM (1)
  70     /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */
  71     #define FSL_FEATURE_MCG_HAS_LOLRE (0)
  72     /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */
  73     #define FSL_FEATURE_MCG_USE_OSCSEL (1)
  74     /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */
  75     #define FSL_FEATURE_MCG_USE_PLLREFSEL (0)
  76     /* @brief TBD */
  77     #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0)
  78     /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */
  79     #define FSL_FEATURE_MCG_HAS_PLL (0)
  80     /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */
  81     #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0)
  82     /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */
  83     #define FSL_FEATURE_MCG_HAS_FLL (1)
  84     /* @brief Has PLL external to MCG (register C9). */
  85     #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0)
  86     /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */
  87     #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1)
  88     /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */
  89     #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (0)
  90     /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */
  91     #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0)
  92     /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */
  93     #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1)
  94     /* @brief Has external clock monitor (register bit C6[CME]). */
  95     #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1)
  96     /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */
  97     #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0)
  98     /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */
  99     #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0)
 100 #elif defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \
 101     defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \
 102     defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \
 103     defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \
 104     defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \
 105     defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \
 106     defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \
 107     defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5)
 108     /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV] increased by one). */
 109     #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (25)
 110     /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */
 111     #define FSL_FEATURE_MCG_PLL_VDIV_BASE (24)
 112     /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */
 113     #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0)
 114     /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1] and C8[LOCRE1]). */
 115     #define FSL_FEATURE_MCG_HAS_RTC_32K (1)
 116     /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */
 117     #define FSL_FEATURE_MCG_HAS_PLL1 (0)
 118     /* @brief Has 48MHz internal oscillator. */
 119     #define FSL_FEATURE_MCG_HAS_IRC_48M (0)
 120     /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */
 121     #define FSL_FEATURE_MCG_HAS_OSC1 (0)
 122     /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */
 123     #define FSL_FEATURE_MCG_HAS_FCFTRIM (0)
 124     /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */
 125     #define FSL_FEATURE_MCG_HAS_LOLRE (1)
 126     /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */
 127     #define FSL_FEATURE_MCG_USE_OSCSEL (1)
 128     /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */
 129     #define FSL_FEATURE_MCG_USE_PLLREFSEL (0)
 130     /* @brief TBD */
 131     #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0)
 132     /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */
 133     #define FSL_FEATURE_MCG_HAS_PLL (1)
 134     /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */
 135     #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (1)
 136     /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */
 137     #define FSL_FEATURE_MCG_HAS_FLL (1)
 138     /* @brief Has PLL external to MCG (register C9). */
 139     #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0)
 140     /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */
 141     #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1)
 142     /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */
 143     #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1)
 144     /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */
 145     #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0)
 146     /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */
 147     #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1)
 148     /* @brief Has external clock monitor (register bit C6[CME]). */
 149     #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1)
 150     /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */
 151     #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0)
 152     /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */
 153     #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0)
 154 #elif defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10)
 155     /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV] increased by one). */
 156     #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (0)
 157     /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */
 158     #define FSL_FEATURE_MCG_PLL_VDIV_BASE (0)
 159     /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */
 160     #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0)
 161     /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1] and C8[LOCRE1]). */
 162     #define FSL_FEATURE_MCG_HAS_RTC_32K (1)
 163     /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */
 164     #define FSL_FEATURE_MCG_HAS_PLL1 (0)
 165     /* @brief Has 48MHz internal oscillator. */
 166     #define FSL_FEATURE_MCG_HAS_IRC_48M (1)
 167     /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */
 168     #define FSL_FEATURE_MCG_HAS_OSC1 (0)
 169     /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */
 170     #define FSL_FEATURE_MCG_HAS_FCFTRIM (1)
 171     /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */
 172     #define FSL_FEATURE_MCG_HAS_LOLRE (0)
 173     /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */
 174     #define FSL_FEATURE_MCG_USE_OSCSEL (1)
 175     /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */
 176     #define FSL_FEATURE_MCG_USE_PLLREFSEL (0)
 177     /* @brief TBD */
 178     #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0)
 179     /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */
 180     #define FSL_FEATURE_MCG_HAS_PLL (0)
 181     /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */
 182     #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0)
 183     /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */
 184     #define FSL_FEATURE_MCG_HAS_FLL (1)
 185     /* @brief Has PLL external to MCG (register C9). */
 186     #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0)
 187     /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */
 188     #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1)
 189     /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */
 190     #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (0)
 191     /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */
 192     #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0)
 193     /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */
 194     #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1)
 195     /* @brief Has external clock monitor (register bit C6[CME]). */
 196     #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1)
 197     /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */
 198     #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0)
 199     /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */
 200     #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0)
 201 #elif defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \
 202     defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MK24FN1M0VDC12) || \
 203     defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK24FN256VDC12) || defined(CPU_MK63FN1M0VLQ12) || \
 204     defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || \
 205     defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || \
 206     defined(CPU_MK64FN1M0VMD12)
 207     /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV] increased by one). */
 208     #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (25)
 209     /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */
 210     #define FSL_FEATURE_MCG_PLL_VDIV_BASE (24)
 211     /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */
 212     #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0)
 213     /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1] and C8[LOCRE1]). */
 214     #define FSL_FEATURE_MCG_HAS_RTC_32K (1)
 215     /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */
 216     #define FSL_FEATURE_MCG_HAS_PLL1 (0)
 217     /* @brief Has 48MHz internal oscillator. */
 218     #define FSL_FEATURE_MCG_HAS_IRC_48M (1)
 219     /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */
 220     #define FSL_FEATURE_MCG_HAS_OSC1 (0)
 221     /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */
 222     #define FSL_FEATURE_MCG_HAS_FCFTRIM (1)
 223     /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */
 224     #define FSL_FEATURE_MCG_HAS_LOLRE (1)
 225     /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */
 226     #define FSL_FEATURE_MCG_USE_OSCSEL (1)
 227     /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */
 228     #define FSL_FEATURE_MCG_USE_PLLREFSEL (0)
 229     /* @brief TBD */
 230     #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0)
 231     /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */
 232     #define FSL_FEATURE_MCG_HAS_PLL (1)
 233     /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */
 234     #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0)
 235     /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */
 236     #define FSL_FEATURE_MCG_HAS_FLL (1)
 237     /* @brief Has PLL external to MCG (register C9). */
 238     #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0)
 239     /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */
 240     #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1)
 241     /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */
 242     #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1)
 243     /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */
 244     #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0)
 245     /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */
 246     #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1)
 247     /* @brief Has external clock monitor (register bit C6[CME]). */
 248     #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1)
 249     /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */
 250     #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0)
 251     /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */
 252     #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0)
 253 #elif defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || \
 254     defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18)
 255     /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV] increased by one). */
 256     #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (8)
 257     /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */
 258     #define FSL_FEATURE_MCG_PLL_VDIV_BASE (24)
 259     /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */
 260     #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0)
 261     /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1] and C8[LOCRE1]). */
 262     #define FSL_FEATURE_MCG_HAS_RTC_32K (1)
 263     /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */
 264     #define FSL_FEATURE_MCG_HAS_PLL1 (0)
 265     /* @brief Has 48MHz internal oscillator. */
 266     #define FSL_FEATURE_MCG_HAS_IRC_48M (1)
 267     /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */
 268     #define FSL_FEATURE_MCG_HAS_OSC1 (0)
 269     /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */
 270     #define FSL_FEATURE_MCG_HAS_FCFTRIM (1)
 271     /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */
 272     #define FSL_FEATURE_MCG_HAS_LOLRE (1)
 273     /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */
 274     #define FSL_FEATURE_MCG_USE_OSCSEL (1)
 275     /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */
 276     #define FSL_FEATURE_MCG_USE_PLLREFSEL (0)
 277     /* @brief TBD */
 278     #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0)
 279     /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */
 280     #define FSL_FEATURE_MCG_HAS_PLL (1)
 281     /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */
 282     #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0)
 283     /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */
 284     #define FSL_FEATURE_MCG_HAS_FLL (1)
 285     /* @brief Has PLL external to MCG (register C9). */
 286     #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (1)
 287     /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */
 288     #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1)
 289     /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */
 290     #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1)
 291     /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */
 292     #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (1)
 293     /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */
 294     #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1)
 295     /* @brief Has external clock monitor (register bit C6[CME]). */
 296     #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1)
 297     /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */
 298     #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0)
 299     /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */
 300     #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0)
 301 #elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \
 302     defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15)
 303     /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV] increased by one). */
 304     #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (8)
 305     /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */
 306     #define FSL_FEATURE_MCG_PLL_VDIV_BASE (16)
 307     /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */
 308     #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0)
 309     /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1] and C8[LOCRE1]). */
 310     #define FSL_FEATURE_MCG_HAS_RTC_32K (1)
 311     /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */
 312     #define FSL_FEATURE_MCG_HAS_PLL1 (1)
 313     /* @brief Has 48MHz internal oscillator. */
 314     #define FSL_FEATURE_MCG_HAS_IRC_48M (0)
 315     /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */
 316     #define FSL_FEATURE_MCG_HAS_OSC1 (1)
 317     /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */
 318     #define FSL_FEATURE_MCG_HAS_FCFTRIM (0)
 319     /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */
 320     #define FSL_FEATURE_MCG_HAS_LOLRE (0)
 321     /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */
 322     #define FSL_FEATURE_MCG_USE_OSCSEL (1)
 323     /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */
 324     #define FSL_FEATURE_MCG_USE_PLLREFSEL (1)
 325     /* @brief TBD */
 326     #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0)
 327     /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */
 328     #define FSL_FEATURE_MCG_HAS_PLL (1)
 329     /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */
 330     #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (1)
 331     /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */
 332     #define FSL_FEATURE_MCG_HAS_FLL (1)
 333     /* @brief Has PLL external to MCG (register C9). */
 334     #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0)
 335     /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */
 336     #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1)
 337     /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */
 338     #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1)
 339     /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */
 340     #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (1)
 341     /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */
 342     #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1)
 343     /* @brief Has external clock monitor (register bit C6[CME]). */
 344     #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1)
 345     /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */
 346     #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0)
 347     /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */
 348     #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0)
 349 #elif defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || defined(CPU_MKL03Z32VFG4) || \
 350     defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || defined(CPU_MKL03Z32VFK4)
 351     /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV] increased by one). */
 352     #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (0)
 353     /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */
 354     #define FSL_FEATURE_MCG_PLL_VDIV_BASE (0)
 355     /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */
 356     #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (1)
 357     /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1] and C8[LOCRE1]). */
 358     #define FSL_FEATURE_MCG_HAS_RTC_32K (0)
 359     /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */
 360     #define FSL_FEATURE_MCG_HAS_PLL1 (0)
 361     /* @brief Has 48MHz internal oscillator. */
 362     #define FSL_FEATURE_MCG_HAS_IRC_48M (0)
 363     /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */
 364     #define FSL_FEATURE_MCG_HAS_OSC1 (0)
 365     /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */
 366     #define FSL_FEATURE_MCG_HAS_FCFTRIM (0)
 367     /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */
 368     #define FSL_FEATURE_MCG_HAS_LOLRE (0)
 369     /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */
 370     #define FSL_FEATURE_MCG_USE_OSCSEL (0)
 371     /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */
 372     #define FSL_FEATURE_MCG_USE_PLLREFSEL (0)
 373     /* @brief TBD */
 374     #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0)
 375     /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */
 376     #define FSL_FEATURE_MCG_HAS_PLL (0)
 377     /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */
 378     #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0)
 379     /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */
 380     #define FSL_FEATURE_MCG_HAS_FLL (0)
 381     /* @brief Has PLL external to MCG (register C9). */
 382     #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0)
 383     /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */
 384     #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (0)
 385     /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */
 386     #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (0)
 387     /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */
 388     #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0)
 389     /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */
 390     #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (0)
 391     /* @brief Has external clock monitor (register bit C6[CME]). */
 392     #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (0)
 393     /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */
 394     #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (1)
 395     /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */
 396     #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (1)
 397 #elif defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || \
 398     defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || \
 399     defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4)
 400     /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV] increased by one). */
 401     #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (0)
 402     /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */
 403     #define FSL_FEATURE_MCG_PLL_VDIV_BASE (0)
 404     /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */
 405     #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (1)
 406     /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1] and C8[LOCRE1]). */
 407     #define FSL_FEATURE_MCG_HAS_RTC_32K (0)
 408     /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */
 409     #define FSL_FEATURE_MCG_HAS_PLL1 (0)
 410     /* @brief Has 48MHz internal oscillator. */
 411     #define FSL_FEATURE_MCG_HAS_IRC_48M (0)
 412     /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */
 413     #define FSL_FEATURE_MCG_HAS_OSC1 (0)
 414     /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */
 415     #define FSL_FEATURE_MCG_HAS_FCFTRIM (0)
 416     /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */
 417     #define FSL_FEATURE_MCG_HAS_LOLRE (0)
 418     /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */
 419     #define FSL_FEATURE_MCG_USE_OSCSEL (0)
 420     /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */
 421     #define FSL_FEATURE_MCG_USE_PLLREFSEL (0)
 422     /* @brief TBD */
 423     #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0)
 424     /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */
 425     #define FSL_FEATURE_MCG_HAS_PLL (0)
 426     /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */
 427     #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (1)
 428     /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */
 429     #define FSL_FEATURE_MCG_HAS_FLL (1)
 430     /* @brief Has PLL external to MCG (register C9). */
 431     #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0)
 432     /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */
 433     #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1)
 434     /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */
 435     #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (0)
 436     /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */
 437     #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0)
 438     /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */
 439     #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1)
 440     /* @brief Has external clock monitor (register bit C6[CME]). */
 441     #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1)
 442     /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */
 443     #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0)
 444     /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */
 445     #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0)
 446 #elif defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || \
 447     defined(CPU_MKL13Z128VFT4) || defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || \
 448     defined(CPU_MKL13Z256VLH4) || defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || \
 449     defined(CPU_MKL23Z64VFM4) || defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || \
 450     defined(CPU_MKL23Z128VFT4) || defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || \
 451     defined(CPU_MKL23Z256VLH4) || defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || \
 452     defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || \
 453     defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || \
 454     defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4)
 455     /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV] increased by one). */
 456     #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (0)
 457     /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */
 458     #define FSL_FEATURE_MCG_PLL_VDIV_BASE (0)
 459     /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */
 460     #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (1)
 461     /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1] and C8[LOCRE1]). */
 462     #define FSL_FEATURE_MCG_HAS_RTC_32K (0)
 463     /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */
 464     #define FSL_FEATURE_MCG_HAS_PLL1 (0)
 465     /* @brief Has 48MHz internal oscillator. */
 466     #define FSL_FEATURE_MCG_HAS_IRC_48M (0)
 467     /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */
 468     #define FSL_FEATURE_MCG_HAS_OSC1 (0)
 469     /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */
 470     #define FSL_FEATURE_MCG_HAS_FCFTRIM (0)
 471     /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */
 472     #define FSL_FEATURE_MCG_HAS_LOLRE (0)
 473     /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */
 474     #define FSL_FEATURE_MCG_USE_OSCSEL (0)
 475     /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */
 476     #define FSL_FEATURE_MCG_USE_PLLREFSEL (0)
 477     /* @brief TBD */
 478     #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0)
 479     /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */
 480     #define FSL_FEATURE_MCG_HAS_PLL (0)
 481     /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */
 482     #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (1)
 483     /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */
 484     #define FSL_FEATURE_MCG_HAS_FLL (0)
 485     /* @brief Has PLL external to MCG (register C9). */
 486     #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0)
 487     /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */
 488     #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1)
 489     /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */
 490     #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (0)
 491     /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */
 492     #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0)
 493     /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */
 494     #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (0)
 495     /* @brief Has external clock monitor (register bit C6[CME]). */
 496     #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (0)
 497     /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */
 498     #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (1)
 499     /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */
 500     #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (1)
 501 #elif defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || \
 502     defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || \
 503     defined(CPU_MKL25Z128VLH4) || defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4)
 504     /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV] increased by one). */
 505     #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (25)
 506     /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */
 507     #define FSL_FEATURE_MCG_PLL_VDIV_BASE (24)
 508     /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */
 509     #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (1)
 510     /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1] and C8[LOCRE1]). */
 511     #define FSL_FEATURE_MCG_HAS_RTC_32K (0)
 512     /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */
 513     #define FSL_FEATURE_MCG_HAS_PLL1 (0)
 514     /* @brief Has 48MHz internal oscillator. */
 515     #define FSL_FEATURE_MCG_HAS_IRC_48M (0)
 516     /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */
 517     #define FSL_FEATURE_MCG_HAS_OSC1 (0)
 518     /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */
 519     #define FSL_FEATURE_MCG_HAS_FCFTRIM (0)
 520     /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */
 521     #define FSL_FEATURE_MCG_HAS_LOLRE (1)
 522     /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */
 523     #define FSL_FEATURE_MCG_USE_OSCSEL (0)
 524     /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */
 525     #define FSL_FEATURE_MCG_USE_PLLREFSEL (0)
 526     /* @brief TBD */
 527     #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0)
 528     /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */
 529     #define FSL_FEATURE_MCG_HAS_PLL (1)
 530     /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */
 531     #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (1)
 532     /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */
 533     #define FSL_FEATURE_MCG_HAS_FLL (1)
 534     /* @brief Has PLL external to MCG (register C9). */
 535     #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (1)
 536     /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */
 537     #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1)
 538     /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */
 539     #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1)
 540     /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */
 541     #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0)
 542     /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */
 543     #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1)
 544     /* @brief Has external clock monitor (register bit C6[CME]). */
 545     #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1)
 546     /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */
 547     #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0)
 548     /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */
 549     #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0)
 550 #elif defined(CPU_MKL26Z256VLK4) || defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || \
 551     defined(CPU_MKL26Z256VMC4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || \
 552     defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4)
 553     /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV] increased by one). */
 554     #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (25)
 555     /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */
 556     #define FSL_FEATURE_MCG_PLL_VDIV_BASE (24)
 557     /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */
 558     #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (1)
 559     /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1] and C8[LOCRE1]). */
 560     #define FSL_FEATURE_MCG_HAS_RTC_32K (0)
 561     /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */
 562     #define FSL_FEATURE_MCG_HAS_PLL1 (0)
 563     /* @brief Has 48MHz internal oscillator. */
 564     #define FSL_FEATURE_MCG_HAS_IRC_48M (0)
 565     /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */
 566     #define FSL_FEATURE_MCG_HAS_OSC1 (0)
 567     /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */
 568     #define FSL_FEATURE_MCG_HAS_FCFTRIM (1)
 569     /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */
 570     #define FSL_FEATURE_MCG_HAS_LOLRE (1)
 571     /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */
 572     #define FSL_FEATURE_MCG_USE_OSCSEL (0)
 573     /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */
 574     #define FSL_FEATURE_MCG_USE_PLLREFSEL (0)
 575     /* @brief TBD */
 576     #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0)
 577     /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */
 578     #define FSL_FEATURE_MCG_HAS_PLL (1)
 579     /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */
 580     #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (1)
 581     /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */
 582     #define FSL_FEATURE_MCG_HAS_FLL (1)
 583     /* @brief Has PLL external to MCG (register C9). */
 584     #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (1)
 585     /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */
 586     #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1)
 587     /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */
 588     #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1)
 589     /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */
 590     #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0)
 591     /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */
 592     #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1)
 593     /* @brief Has external clock monitor (register bit C6[CME]). */
 594     #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1)
 595     /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */
 596     #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0)
 597     /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */
 598     #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0)
 599 #elif defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31F512VLH12) || defined(CPU_MKV31F512VLL12)
 600     /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV] increased by one). */
 601     #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (25)
 602     /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */
 603     #define FSL_FEATURE_MCG_PLL_VDIV_BASE (24)
 604     /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */
 605     #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0)
 606     /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1] and C8[LOCRE1]). */
 607     #define FSL_FEATURE_MCG_HAS_RTC_32K (0)
 608     /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */
 609     #define FSL_FEATURE_MCG_HAS_PLL1 (0)
 610     /* @brief Has 48MHz internal oscillator. */
 611     #define FSL_FEATURE_MCG_HAS_IRC_48M (1)
 612     /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */
 613     #define FSL_FEATURE_MCG_HAS_OSC1 (0)
 614     /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */
 615     #define FSL_FEATURE_MCG_HAS_FCFTRIM (1)
 616     /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */
 617     #define FSL_FEATURE_MCG_HAS_LOLRE (1)
 618     /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */
 619     #define FSL_FEATURE_MCG_USE_OSCSEL (1)
 620     /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */
 621     #define FSL_FEATURE_MCG_USE_PLLREFSEL (0)
 622     /* @brief TBD */
 623     #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0)
 624     /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */
 625     #define FSL_FEATURE_MCG_HAS_PLL (1)
 626     /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */
 627     #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0)
 628     /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */
 629     #define FSL_FEATURE_MCG_HAS_FLL (1)
 630     /* @brief Has PLL external to MCG (register C9). */
 631     #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0)
 632     /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */
 633     #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1)
 634     /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */
 635     #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1)
 636     /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */
 637     #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0)
 638     /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */
 639     #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1)
 640     /* @brief Has external clock monitor (register bit C6[CME]). */
 641     #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1)
 642     /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */
 643     #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0)
 644     /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */
 645     #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0)
 646 #elif defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F256VLL15) || \
 647     defined(CPU_MKV40F64VLH15) || defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15) || \
 648     defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) || defined(CPU_MKV45F128VLH15) || \
 649     defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || defined(CPU_MKV45F256VLL15) || defined(CPU_MKV46F128VLH15) || \
 650     defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || defined(CPU_MKV46F256VLL15)
 651     /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV] increased by one). */
 652     #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (8)
 653     /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */
 654     #define FSL_FEATURE_MCG_PLL_VDIV_BASE (16)
 655     /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */
 656     #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (1)
 657     /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1] and C8[LOCRE1]). */
 658     #define FSL_FEATURE_MCG_HAS_RTC_32K (0)
 659     /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */
 660     #define FSL_FEATURE_MCG_HAS_PLL1 (0)
 661     /* @brief Has 48MHz internal oscillator. */
 662     #define FSL_FEATURE_MCG_HAS_IRC_48M (0)
 663     /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */
 664     #define FSL_FEATURE_MCG_HAS_OSC1 (0)
 665     /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */
 666     #define FSL_FEATURE_MCG_HAS_FCFTRIM (1)
 667     /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */
 668     #define FSL_FEATURE_MCG_HAS_LOLRE (1)
 669     /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */
 670     #define FSL_FEATURE_MCG_USE_OSCSEL (0)
 671     /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */
 672     #define FSL_FEATURE_MCG_USE_PLLREFSEL (0)
 673     /* @brief TBD */
 674     #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0)
 675     /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */
 676     #define FSL_FEATURE_MCG_HAS_PLL (1)
 677     /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */
 678     #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0)
 679     /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */
 680     #define FSL_FEATURE_MCG_HAS_FLL (1)
 681     /* @brief Has PLL external to MCG (register C9). */
 682     #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0)
 683     /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */
 684     #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1)
 685     /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */
 686     #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1)
 687     /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */
 688     #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0)
 689     /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */
 690     #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1)
 691     /* @brief Has external clock monitor (register bit C6[CME]). */
 692     #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1)
 693     /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */
 694     #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0)
 695     /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */
 696     #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0)
 697 #else
 698     #error "No valid CPU defined!"
 699 #endif
 700
 701 #endif /* __FSL_MCG_FEATURES_H__ */
 702
 703 /*******************************************************************************
 704  * EOF
 705  ******************************************************************************/