tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/mpu/fsl_mpu_hal.h

   1 /*
   2  * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without modification,
   6  * are permitted provided that the following conditions are met:
   7  *
   8  * o Redistributions of source code must retain the above copyright notice, this list
   9  *   of conditions and the following disclaimer.
  10  *
  11  * o Redistributions in binary form must reproduce the above copyright notice, this
  12  *   list of conditions and the following disclaimer in the documentation and/or
  13  *   other materials provided with the distribution.
  14  *
  15  * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  16  *   contributors may be used to endorse or promote products derived from this
  17  *   software without specific prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  21  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  22  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  23  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  24  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  25  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  26  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  27  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  28  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29  */
  30 #ifndef __FSL_MPU_HAL_H__
  31 #define __FSL_MPU_HAL_H__
  32
  33 #include <assert.h>
  34 #include <stdint.h>
  35 #include <stdbool.h>
  36 #include "fsl_mpu_features.h"
  37 #include "fsl_device_registers.h"
  38
  39 #ifndef MBED_NO_MPU
  40
  41 #define MPU_REGION_NUMBER 12
  42
  43 /*!
  44  * @addtogroup mpu_hal
  45  * @{
  46  */
  47
  48 /*******************************************************************************
  49  * Definitions
  50  *******************************************************************************/
  51
  52 /*! @brief MPU region number region0~region11. */
  53 typedef enum _mpu_region_num{
  54     kMPURegionNum00 = 0U,  /*!< MPU region number 0*/
  55     kMPURegionNum01 = 1U,  /*!< MPU region number 1*/
  56     kMPURegionNum02 = 2U,  /*!< MPU region number 2*/
  57     kMPURegionNum03 = 3U,  /*!< MPU region number 3*/
  58     kMPURegionNum04 = 4U,  /*!< MPU region number 4*/
  59     kMPURegionNum05 = 5U,  /*!< MPU region number 5*/
  60     kMPURegionNum06 = 6U,  /*!< MPU region number 6*/
  61     kMPURegionNum07 = 7U,  /*!< MPU region number 7*/
  62     kMPURegionNum08 = 8U,  /*!< MPU region number 8*/
  63     kMPURegionNum09 = 9U,  /*!< MPU region number 9*/
  64     kMPURegionNum10 = 10U, /*!< MPU region number 10*/
  65     kMPURegionNum11 = 11U, /*!< MPU region number 11*/
  66 #if defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \
  67     defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15)
  68     kMPURegionNum11 = 12U, /*!< MPU region number 12*/
  69     kMPURegionNum11 = 13U, /*!< MPU region number 13*/
  70     kMPURegionNum11 = 14U, /*!< MPU region number 14*/
  71     kMPURegionNum11 = 15U, /*!< MPU region number 15*/
  72 #endif
  73 }mpu_region_num;
  74
  75 /*! @brief MPU error address register0~4. */
  76 typedef enum _mpu_error_addr_reg{
  77     kMPUErrorAddrReg00 = 0U, /*!< MPU error address register 0*/
  78     kMPUErrorAddrReg01 = 1U, /*!< MPU error address register 1*/
  79     kMPUErrorAddrReg02 = 2U, /*!< MPU error address register 2*/
  80     kMPUErrorAddrReg03 = 3U, /*!< MPU error address register 3*/
  81     kMPUErrorAddrReg04 = 4U  /*!< MPU error address register 4*/
  82 }mpu_error_addr_reg;
  83
  84 /*! @brief MPU error detail register0~4. */
  85 typedef enum _mpu_error_detail_reg{
  86     kMPUErrorDetailReg00 = 0U, /*!< MPU error detail register 0*/
  87     kMPUErrorDetailReg01 = 1U, /*!< MPU error detail register 1*/
  88     kMPUErrorDetailReg02 = 2U, /*!< MPU error detail register 2*/
  89     kMPUErrorDetailReg03 = 3U, /*!< MPU error detail register 3*/
  90     kMPUErrorDetailReg04 = 4U  /*!< MPU error detail register 4*/
  91 }mpu_error_detail_reg;
  92
  93 /*! @brief MPU access error. */
  94 typedef enum _mpu_error_access_type{
  95     kMPUReadErrorType  = 0U, /*!< MPU error type---read*/
  96     kMPUWriteErrorType = 1U  /*!< MPU error type---write*/
  97 }mpu_error_access_type;
  98
  99 /*! @brief MPU access error attributes.*/
 100 typedef enum _mpu_error_attributes{
 101     kMPUUserModeInstructionAccess       = 0U, /*!< access instruction error in user mode*/
 102     kMPUUserModeDataAccess              = 1U, /*!< access data error in user mode*/
 103     kMPUSupervisorModeInstructionAccess = 2U, /*!< access instruction error in supervisor mode*/
 104     kMPUSupervisorModeDataAccess        = 3U  /*!< access data error in supervisor mode*/
 105 }mpu_error_attributes;
 106
 107 /*! @brief access MPU in which mode. */
 108 typedef enum _mpu_access_mode{
 109     kMPUAccessInUserMode       = 0U, /*!< access data or instruction in user mode*/
 110     kMPUAccessInSupervisorMode = 1U  /*!< access data or instruction in supervisor mode*/
 111 }mpu_access_mode;
 112
 113 /*! @brief MPU master number. */
 114 typedef enum _mpu_master_num{
 115     kMPUMaster00 = 0U, /*!< Core.*/
 116     kMPUMaster01 = 1U, /*!< Debugger.*/
 117     kMPUMaster02 = 2U, /*!< DMA.*/
 118     kMPUMaster03 = 3U, /*!< ENET.*/
 119     kMPUMaster04 = 4U, /*!< USB.*/
 120     kMPUMaster05 = 5U, /*!< SDHC.*/
 121     kMPUMaster06 = 6U, /*!< undefined.*/
 122     kMPUMaster07 = 7U  /*!< undefined.*/
 123 }mpu_master_num;
 124
 125 /*! @brief MPU error access control detail. */
 126 typedef enum _mpu_error_access_control{
 127     kMPUNoRegionHitError        = 0U, /*!< no region hit error*/
 128     kMPUNoneOverlappRegionError = 1U, /*!< access single region error*/
 129     kMPUOverlappRegionError     = 2U  /*!< access overlapping region error*/
 130 }mpu_error_access_control;
 131
 132 /*! @brief MPU access rights in supervisor mode for master0~master3. */
 133 typedef enum _mpu_supervisor_access_rights{
 134     kMPUSupervisorReadWriteExecute = 0U, /*!< R W E allowed in supervisor mode*/
 135     kMPUSupervisorReadExecute      = 1U, /*!< R E allowed in supervisor mode*/
 136     kMPUSupervisorReadWrite        = 2U, /*!< R W allowed in supervisor mode*/
 137     kMPUSupervisorEqualToUsermode  = 3U  /*!< access permission equal to user mode*/
 138 }mpu_supervisor_access_rights;
 139
 140 /*! @brief MPU access rights in user mode for master0~master3. */
 141 typedef enum _mpu_user_access_rights{
 142     kMPUUserNoAccessRights   = 0U, /*!< no access allowed in user mode*/
 143     kMPUUserExecute          = 1U, /*!< E allowed in user mode*/
 144     kMPUUserWrite            = 2U, /*!< W allowed in user mode*/
 145     kMPUUserWriteExecute     = 3U, /*!< W E allowed in user mode*/
 146     kMPUUserRead             = 4U, /*!< R allowed in user mode*/
 147     kMPUUserReadExecute      = 5U, /*!< R E allowed in user mode*/
 148     kMPUUserReadWrite        = 6U, /*!< R W allowed in user mode*/
 149     kMPUUserReadWriteExecute = 7U  /*!< R W E allowed in user mode*/
 150 }mpu_user_access_rights;
 151
 152 /*! @brief MPU process identifier. */
 153 typedef enum _mpu_process_identifier_value{
 154     kMPUIdentifierDisable = 0U, /*!< processor identifier disable*/
 155     kMPUIdentifierEnable  = 1U  /*!< processor identifier enable*/
 156 }mpu_process_identifier_value;
 157
 158 /*! @brief MPU access control for master4~master7. */
 159 typedef enum _mpu_access_control{
 160     kMPUAccessDisable = 0U, /*!< Read or Write not allowed*/
 161     kMPUAccessEnable  = 1U  /*!< Read or Write allowed*/
 162 }mpu_access_control;
 163
 164 /*! @brief MPU access type for master4~master7. */
 165 typedef enum _mpu_access_type{
 166     kMPUAccessRead  = 0U, /*!< Access type is read*/
 167     kMPUAccessWrite = 1U  /*!< Access type is write*/
 168 }mpu_access_type;
 169
 170 /*! @brief MPU access region valid. */
 171 typedef enum _mpu_region_valid{
 172     kMPURegionInvalid = 0U, /*!< region invalid*/
 173     kMPURegionValid   = 1U  /*!< region valid*/
 174 }mpu_region_valid;
 175
 176 /*! @brief MPU status return codes.*/
 177 typedef enum _MPU_status {
 178     kStatus_MPU_Success                   = 0x0U, /*!< Succeed. */
 179     kStatus_MPU_NotInitlialized           = 0x1U, /*!< MPU is not initialized yet. */
 180     kStatus_MPU_NullArgument              = 0x2U, /*!< Argument is NULL.*/
 181  } mpu_status_t;
 182
 183 /*******************************************************************************
 184  ** Variables
 185  *******************************************************************************/
 186
 187 /*******************************************************************************
 188  * API
 189  *******************************************************************************/
 190
 191 #if defined(__cplusplus)
 192 extern "C" {
 193 #endif
 194
 195 /*!
 196  * @name MPU HAL.
 197  * @{
 198  */
 199
 200 /*!
 201  * @brief Enables the MPU module operation
 202  *
 203  * @param baseAddr The MPU peripheral base address
 204  */
 205 static inline void MPU_HAL_Enable(uint32_t baseAddr)
 206 {
 207     BW_MPU_CESR_VLD(baseAddr, (uint8_t)true);
 208 }
 209
 210 /*!
 211  * @brief Disables the MPU module operation
 212  *
 213  * @param baseAddr The MPU peripheral base address
 214  */
 215 static inline void MPU_HAL_Disable(uint32_t baseAddr)
 216 {
 217     BW_MPU_CESR_VLD(baseAddr, (uint8_t)false);
 218 }
 219
 220 /*!
 221  * @brief Checks whether the MPU module is enabled
 222  *
 223  * @param baseAddr The MPU peripheral base address
 224  * @retval true MPU module is enabled
 225  * @retval false MPU module is disabled
 226  */
 227 static inline bool MPU_HAL_IsEnabled(uint32_t baseAddr)
 228 {
 229    return BR_MPU_CESR_VLD(baseAddr);
 230 }
 231
 232 /*!
 233  * @brief Returns the total region number
 234  *
 235  * @param baseAddr The MPU peripheral base address
 236  * @retval the number of regions
 237  */
 238 static inline uint32_t MPU_HAL_GetNumberOfRegions(uint32_t baseAddr)
 239 {
 240     return (BR_MPU_CESR_NRGD(baseAddr));
 241 }
 242
 243 /*!
 244  * @brief Returns MPU slave sports
 245  *
 246  * @param baseAddr The MPU peripheral base address
 247  * @retval the number of slaves
 248  */
 249 static inline uint32_t MPU_HAL_GetNumberOfSlaves(uint32_t baseAddr)
 250 {
 251     return (BR_MPU_CESR_NSP(baseAddr));
 252 }
 253
 254 /*!
 255  * @brief Returns hardware level info
 256  *
 257  * @param baseAddr The MPU peripheral base address
 258  * @retval hardware revision level
 259  */
 260 static inline uint32_t MPU_HAL_GetHardwareRevisionLevel(uint32_t baseAddr)
 261 {
 262     return (BR_MPU_CESR_HRL(baseAddr));
 263 }
 264
 265 /*!
 266  * @brief Returns hardware level info
 267  *
 268  * @param baseAddr The MPU peripheral base address
 269  * @param regNum Error address register number
 270  * @retval error access address
 271  */
 272 static inline uint32_t MPU_HAL_GetErrorAccessAddr(uint32_t baseAddr, mpu_error_addr_reg regNum)
 273 {
 274     assert(regNum < HW_MPU_EARn_COUNT);
 275     return (BR_MPU_EARn_EADDR(baseAddr, regNum));
 276 }
 277
 278 /*!
 279  * @brief Returns error access slaves sports
 280  *
 281  * @param baseAddr The MPU peripheral base address
 282  * @retval error slave sports
 283 */
 284 static inline uint8_t MPU_HAL_GetErrorSlaveSports(uint32_t baseAddr)
 285 {
 286     return (BR_MPU_CESR_SPERR(baseAddr));
 287 }
 288
 289 /*!
 290  * @brief Returns error access address
 291  *
 292  * @param baseAddr The MPU peripheral base address
 293  * @param errorDetailRegNum Error detail register number
 294  * @retval error access type
 295 */
 296 static inline mpu_error_access_type MPU_HAL_GetErrorAccessType(uint32_t baseAddr, mpu_error_detail_reg errorDetailRegNum)
 297 {
 298     assert(errorDetailRegNum < HW_MPU_EDRn_COUNT);
 299     return (mpu_error_access_type)(BR_MPU_EDRn_ERW(baseAddr, errorDetailRegNum));
 300 }
 301
 302 /*!
 303  * @brief Returns error access attributes
 304  *
 305  * @param baseAddr The MPU peripheral base address
 306  * @param errorDetailRegNum Detail error register number
 307  * @retval error access attributes
 308  */
 309 static inline mpu_error_attributes MPU_HAL_GetErrorAttributes(uint32_t baseAddr, mpu_error_detail_reg errorDetailRegNum)
 310 {
 311     assert(errorDetailRegNum < HW_MPU_EDRn_COUNT);
 312     return (mpu_error_attributes)(BR_MPU_EDRn_EATTR(baseAddr, errorDetailRegNum));
 313 }
 314
 315 /*!
 316  * @brief Returns error access master number
 317  *
 318  * @param baseAddr The MPU peripheral base address
 319  * @param errorDetailRegNum Error register number
 320  * @retval error master number
 321  */
 322 static inline mpu_master_num MPU_HAL_GetErrorMasterNum(uint32_t baseAddr, mpu_error_detail_reg errorDetailRegNum)
 323 {
 324     assert(errorDetailRegNum < HW_MPU_EDRn_COUNT);
 325     return (mpu_master_num)(BR_MPU_EDRn_EMN(baseAddr, errorDetailRegNum));
 326 }
 327
 328 /*!
 329  * @brief Returns error process identifier
 330  *
 331  * @param baseAddr The MPU peripheral base address
 332  * @param errorDetailRegNum Error register number
 333  * @retval error process identifier
 334  */
 335 static inline uint32_t MPU_HAL_GetErrorProcessIdentifier(uint32_t baseAddr, mpu_error_detail_reg errorDetailRegNum)
 336 {
 337     assert(errorDetailRegNum < HW_MPU_EDRn_COUNT);
 338     return(BR_MPU_EDRn_EPID(baseAddr, errorDetailRegNum));
 339 }
 340
 341 /*!
 342  * @brief Returns error access control
 343  *
 344  * @param baseAddr The MPU peripheral base address
 345  * @param errorDetailRegNum Error register number
 346  * @retval error access control
 347  */
 348 static inline mpu_error_access_control MPU_HAL_GetErrorAccessControl(uint32_t baseAddr, mpu_error_detail_reg errorDetailRegNum)
 349 {
 350     assert(errorDetailRegNum < HW_MPU_EDRn_COUNT);
 351
 352     uint32_t i = BR_MPU_EDRn_EACD(baseAddr, errorDetailRegNum);
 353
 354     if(0 == i)
 355     {
 356         return (kMPUNoRegionHitError);
 357     }
 358     else if(!(i&(i-1)))
 359     {
 360         return (kMPUNoneOverlappRegionError);
 361     }
 362     else
 363     {
 364         return (kMPUOverlappRegionError);
 365     }
 366 }
 367
 368 /*!
 369  * @brief Returns the region start address
 370  *
 371  * @param baseAddr The MPU peripheral base address
 372  * @param regionNum MPU region number
 373  * @retval region start address
 374  */
 375 static inline uint32_t MPU_HAL_GetRegionStartAddr(uint32_t baseAddr, mpu_region_num regionNum)
 376 {
 377     assert(regionNum < HW_MPU_RGDn_WORD0_COUNT);
 378     return (BR_MPU_RGDn_WORD0_SRTADDR(baseAddr, regionNum)<<BP_MPU_RGDn_WORD0_SRTADDR);
 379 }
 380
 381 /*!
 382  * @brief Sets region start address
 383  *
 384  * @param baseAddr The MPU peripheral base address
 385  * @param regionNum MPU region number
 386  * @param startAddr Region start address
 387  */
 388 static inline void MPU_HAL_SetRegionStartAddr(uint32_t baseAddr, mpu_region_num regionNum, uint32_t startAddr)
 389 {
 390     assert(regionNum < HW_MPU_RGDn_WORD0_COUNT);
 391     startAddr >>= BP_MPU_RGDn_WORD0_SRTADDR;
 392     BW_MPU_RGDn_WORD0_SRTADDR(baseAddr, regionNum, startAddr);
 393 }
 394
 395 /*!
 396  * @brief Returns region end address
 397  *
 398  * @param baseAddr The MPU peripheral base address
 399  * @param regionNum MPU region number
 400  * @retval region end address
 401  */
 402 static inline uint32_t MPU_HAL_GetRegionEndAddr(uint32_t baseAddr, mpu_region_num regionNum)
 403 {
 404     assert(regionNum < HW_MPU_RGDn_WORD1_COUNT);
 405     return (BR_MPU_RGDn_WORD1_ENDADDR(baseAddr, regionNum)<<BP_MPU_RGDn_WORD0_SRTADDR);
 406 }
 407
 408 /*!
 409  * @brief Sets region end address
 410  *
 411  * @param baseAddr The MPU peripheral base address
 412  * @param regionNum MPU region number
 413  * @param endAddr Region end address
 414  */
 415 static inline void MPU_HAL_SetRegionEndAddr(uint32_t baseAddr, mpu_region_num regionNum, uint32_t endAddr)
 416 {
 417     assert(regionNum < HW_MPU_RGDn_WORD1_COUNT);
 418     endAddr >>= BP_MPU_RGDn_WORD0_SRTADDR;
 419     BW_MPU_RGDn_WORD1_ENDADDR(baseAddr, regionNum, endAddr);
 420 }
 421
 422 /*!
 423  * @brief Returns all masters access permission for a specific region
 424  *
 425  * @param baseAddr The MPU peripheral base address
 426  * @param regionNum MPU region number
 427  * @retval all masters access permission
 428  */
 429 static inline uint32_t MPU_HAL_GetAllMastersAccessRights(uint32_t baseAddr, mpu_region_num regionNum)
 430 {
 431     assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
 432     return (HW_MPU_RGDn_WORD2_RD(baseAddr, regionNum));
 433 }
 434
 435 /*!
 436  * @brief Sets all masters access permission for a specific region
 437  *
 438  * @param baseAddr The MPU peripheral base address
 439  * @param regionNum MPU region number
 440  * @param accessRights All masters access rights
 441  */
 442 static inline void MPU_HAL_SetAllMastersAccessRights(uint32_t baseAddr, mpu_region_num regionNum, uint32_t accessRights)
 443 {
 444     assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
 445     HW_MPU_RGDn_WORD2_WR(baseAddr, regionNum, accessRights);
 446 }
 447
 448 /*!
 449  * @brief Gets M0 access permission in supervisor mode
 450  *
 451  * @param baseAddr The MPU peripheral base address
 452  * @param regionNum MPU region number
 453  * @retval Master0 access permission
 454  */
 455 static inline mpu_supervisor_access_rights MPU_HAL_GetM0SupervisorAccessRights(uint32_t baseAddr, mpu_region_num regionNum)
 456 {
 457     assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
 458     return (mpu_supervisor_access_rights)(BR_MPU_RGDn_WORD2_M0SM(baseAddr, regionNum));
 459 }
 460
 461 /*!
 462  * @brief Gets M0 access permission in user mode
 463  *
 464  * @param baseAddr The MPU peripheral base address
 465  * @param regionNum MPU region number
 466  * @retval Master0 access permission
 467  */
 468 static inline mpu_user_access_rights MPU_HAL_GetM0UserAccessRights(uint32_t baseAddr, mpu_region_num regionNum)
 469 {
 470     assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
 471     return (mpu_user_access_rights)(BR_MPU_RGDn_WORD2_M0UM(baseAddr, regionNum));
 472 }
 473
 474 /*!
 475  * @brief Sets M0 access permission in supervisor mode
 476  *
 477  * @param baseAddr The MPU peripheral base address
 478  * @param regionNum MPU region number
 479  * @param accessRights Master0 access permission
 480  */
 481 static inline void MPU_HAL_SetM0SupervisorAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_supervisor_access_rights accessRights)
 482 {
 483     assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
 484     BW_MPU_RGDn_WORD2_M0SM(baseAddr, regionNum, accessRights);
 485 }
 486
 487 /*!
 488  * @brief Sets M0 access permission in user mode
 489  *
 490  * @param baseAddr The MPU peripheral base address
 491  * @param regionNum MPU region number
 492  * @param accessRights Master0 access permission
 493  */
 494 static inline void MPU_HAL_SetM0UserAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_user_access_rights accessRights)
 495 {
 496     assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
 497     BW_MPU_RGDn_WORD2_M0UM(baseAddr, regionNum, accessRights);
 498 }
 499
 500 /*!
 501  * @brief Checks whether the M0 process identifier is enabled in region hit evaluation
 502  *
 503  * @param baseAddr The MPU peripheral base address
 504  * @param regionNum MPU region number
 505  * @retval true m0 process identifier is enabled
 506  * @retval false m0 process identifier is disabled
 507  */
 508
 509 static inline bool MPU_HAL_IsM0ProcessIdentifierEnabled(uint32_t baseAddr, mpu_region_num regionNum)
 510 {
 511     assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
 512     return (1 == BR_MPU_RGDn_WORD2_M0PE(baseAddr, regionNum));
 513 }
 514
 515 /*!
 516  * @brief Sets the M0 process identifier value--- 1 enable process identifier in region hit evaluation and 0 disable
 517  *
 518  * @param baseAddr The MPU peripheral base address
 519  * @param regionNum MPU region number
 520  * @param identifierValue Process identifier value
 521  */
 522 static inline void MPU_HAL_SetM0ProcessIdentifierValue(uint32_t baseAddr, mpu_region_num regionNum, mpu_process_identifier_value identifierValue)
 523 {
 524     assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
 525     BW_MPU_RGDn_WORD2_M0PE(baseAddr, regionNum, identifierValue);
 526 }
 527
 528 /*!
 529  * @brief Gets M1 access permission in supervisor mode
 530  *
 531  * @param baseAddr The MPU peripheral base address
 532  * @param regionNum MPU region number
 533  * @retval Master1 access permission
 534  */
 535 static inline mpu_supervisor_access_rights MPU_HAL_GetM1SupervisorAccessRights(uint32_t baseAddr, mpu_region_num regionNum)
 536 {
 537     assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
 538     return (mpu_supervisor_access_rights)(BR_MPU_RGDn_WORD2_M1SM(baseAddr, regionNum));
 539 }
 540
 541 /*!
 542  * @brief Gets M1 access permission in user mode
 543  *
 544  * @param baseAddr The MPU peripheral base address
 545  * @param regionNum MPU region number
 546  * @retval Master1 access permission
 547  */
 548 static inline mpu_user_access_rights MPU_HAL_GetM1UserAccessRights(uint32_t baseAddr, mpu_region_num regionNum)
 549 {
 550     assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
 551     return (mpu_user_access_rights)(BR_MPU_RGDn_WORD2_M1UM(baseAddr, regionNum));
 552 }
 553
 554 /*!
 555  * @brief Sets M1 access permission in supervisor mode
 556  *
 557  * @param baseAddr The MPU peripheral base address
 558  * @param regionNum MPU region number
 559  * @param accessRights Master1 access permission
 560  */
 561 static inline void MPU_HAL_SetM1SupervisorAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_supervisor_access_rights accessRights)
 562 {
 563     assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
 564     BW_MPU_RGDn_WORD2_M1SM(baseAddr, regionNum, accessRights);
 565 }
 566
 567 /*!
 568  * @brief Sets M1 access permission in user mode
 569  *
 570  * @param baseAddr The MPU peripheral base address
 571  * @param regionNum MPU region number
 572  * @param accessRights Master1 access permission
 573  */
 574 static inline void MPU_HAL_SetM1UserAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_user_access_rights accessRights)
 575 {
 576     assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
 577     BW_MPU_RGDn_WORD2_M1UM(baseAddr, regionNum, accessRights);
 578 }
 579
 580 /*!
 581  * @brief Checks whether M1 process identifier enabled in region hit evaluation
 582  *
 583  * @param baseAddr The MPU peripheral base address
 584  * @param regionNum MPU region number
 585  * @retval true m1 process identifier is enabled
 586  * @retval false m1 process identifier is disabled
 587  */
 588 static inline bool MPU_HAL_IsM1ProcessIdentifierEnabled(uint32_t baseAddr, mpu_region_num regionNum)
 589 {
 590     assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
 591     return (1 == BR_MPU_RGDn_WORD2_M1PE(baseAddr, regionNum));
 592 }
 593
 594 /*!
 595  * @brief Sets the M1 process identifier value--- 1 enable process identifier in region hit evaluation and 0 disable
 596  *
 597  * @param baseAddr The MPU peripheral base address
 598  * @param regionNum MPU region number
 599  * @param identifierValue Process identifier value
 600  */
 601 static inline void MPU_HAL_SetM1ProcessIdentifierValue(uint32_t baseAddr, mpu_region_num regionNum, mpu_process_identifier_value identifierValue)
 602 {
 603     assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
 604     BW_MPU_RGDn_WORD2_M1PE(baseAddr, regionNum, identifierValue);
 605 }
 606
 607 /*!
 608  * @brief Gets M2 access permission in supervisor mode
 609  *
 610  * @param baseAddr The MPU peripheral base address
 611  * @param regionNum MPU region number
 612  * @retval Master2 access permission
 613  */
 614 static inline mpu_supervisor_access_rights MPU_HAL_GetM2SupervisorAccessRights(uint32_t baseAddr, mpu_region_num regionNum)
 615 {
 616     assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
 617     return (mpu_supervisor_access_rights)(BR_MPU_RGDn_WORD2_M2SM(baseAddr, regionNum));
 618 }
 619
 620 /*!
 621  * @brief Gets M2 access permission in user mode
 622  *
 623  * @param baseAddr The MPU peripheral base address
 624  * @param regionNum MPU region number
 625  * @retval Master2 access permission
 626  */
 627 static inline mpu_user_access_rights MPU_HAL_GetM2UserAccessRights(uint32_t baseAddr, mpu_region_num regionNum)
 628 {
 629     assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
 630     return (mpu_user_access_rights)(BR_MPU_RGDn_WORD2_M2UM(baseAddr, regionNum));
 631 }
 632
 633 /*!
 634  * @brief Sets M2 access permission in supervisor mode
 635  *
 636  * @param baseAddr The MPU peripheral base address
 637  * @param regionNum MPU region number
 638  * @param accessRights Master2 access permission
 639  */
 640 static inline void MPU_HAL_SetM2SupervisorAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_supervisor_access_rights accessRights)
 641 {
 642     assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
 643     BW_MPU_RGDn_WORD2_M2SM(baseAddr, regionNum, accessRights);
 644 }
 645
 646 /*!
 647  * @brief Sets M2 access permission in user mode
 648  *
 649  * @param baseAddr The MPU peripheral base address
 650  * @param regionNum MPU region number
 651  * @param accessRights Master2 access permission
 652  */
 653 static inline void MPU_HAL_SetM2UserAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_user_access_rights accessRights)
 654 {
 655     assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
 656     BW_MPU_RGDn_WORD2_M2UM(baseAddr, regionNum, accessRights);
 657 }
 658
 659 /*!
 660  * @brief Checks whether the M2 process identifier enabled in region hit evaluation
 661  *
 662  * @param baseAddr The MPU peripheral base address
 663  * @param regionNum MPU region number
 664  * @retval true m2 process identifier is enabled
 665  * @retval false m2 process identifier is disabled
 666  */
 667
 668 static inline bool MPU_HAL_IsM2ProcessIdentifierEnabled(uint32_t baseAddr, mpu_region_num regionNum)
 669 {
 670     assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
 671     return (1 == BR_MPU_RGDn_WORD2_M2PE(baseAddr, regionNum));
 672 }
 673
 674 /*!
 675  * @brief Sets the M2 process identifier value--- 1 enable process identifier in region hit evaluation and 0 disable.
 676  *
 677  * @param baseAddr The MPU peripheral base address.
 678  * @param regionNum MPU region number.
 679  * @param identifierValue Process identifier value.
 680  */
 681 static inline void MPU_HAL_SetM2ProcessIdentifierValue(uint32_t baseAddr, mpu_region_num regionNum, mpu_process_identifier_value identifierValue)
 682 {
 683     assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
 684     BW_MPU_RGDn_WORD2_M2PE(baseAddr, regionNum, identifierValue);
 685 }
 686
 687 /*!
 688  * @brief Gets M3 access permission in supervisor mode
 689  *
 690  * @param baseAddr The MPU peripheral base address
 691  * @param regionNum MPU region number
 692  * @retval Master3 access permission
 693  */
 694 static inline mpu_supervisor_access_rights MPU_HAL_GetM3SupervisorAccessRights(uint32_t baseAddr, mpu_region_num regionNum)
 695 {
 696     assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
 697     return (mpu_supervisor_access_rights)(BR_MPU_RGDn_WORD2_M3SM(baseAddr, regionNum));
 698 }
 699
 700 /*!
 701  * @brief Gets M3 access permission in user mode
 702  *
 703  * @param baseAddr The MPU peripheral base address
 704  * @param regionNum MPU region number
 705  * @retval Master3 access permission
 706  */
 707 static inline mpu_user_access_rights MPU_HAL_GetM3UserAccessRights(uint32_t baseAddr, mpu_region_num regionNum)
 708 {
 709     assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
 710     return (mpu_user_access_rights)(BR_MPU_RGDn_WORD2_M3UM(baseAddr, regionNum));
 711 }
 712
 713 /*!
 714  * @brief Sets M3 access permission in supervisor mode.
 715  *
 716  * @param baseAddr The MPU peripheral base address.
 717  * @param regionNum MPU region number.
 718  * @param accessRights Master3 access permission.
 719  */
 720 static inline void MPU_HAL_SetM3SupervisorAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_supervisor_access_rights accessRights)
 721 {
 722     assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
 723     BW_MPU_RGDn_WORD2_M3SM(baseAddr, regionNum, accessRights);
 724 }
 725
 726 /*!
 727  * @brief Sets M3 access permission in user mode
 728  *
 729  * @param baseAddr The MPU peripheral base address
 730  * @param regionNum MPU region number
 731  * @param accessRights Master3 access permission
 732  */
 733 static inline void MPU_HAL_SetM3UserAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_user_access_rights accessRights)
 734 {
 735     assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
 736     BW_MPU_RGDn_WORD2_M3UM(baseAddr, regionNum, accessRights);
 737 }
 738
 739 /*!
 740  * @brief Checks whether the M3 process identifier enabled in region hit evaluation
 741  *
 742  * @param baseAddr The MPU peripheral base address
 743  * @param regionNum MPU region number
 744  * @retval true m3 process identifier is enabled
 745  * @retval false m3 process identifier is disabled
 746  */
 747
 748 static inline bool MPU_HAL_IsM3ProcessIdentifierEnabled(uint32_t baseAddr, mpu_region_num regionNum)
 749 {
 750     assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
 751     return (1 == BR_MPU_RGDn_WORD2_M3PE(baseAddr, regionNum));
 752 }
 753
 754 /*!
 755  * @brief Sets M3 process identifier value--- 1 enable process identifier in region hit evaluation and 0 disable
 756  *
 757  * @param baseAddr The MPU peripheral base address
 758  * @param regionNum MPU region number
 759  * @param identifierValue Process identifier value
 760  */
 761 static inline void MPU_HAL_SetM3ProcessIdentifierValue(uint32_t baseAddr, mpu_region_num regionNum, mpu_process_identifier_value identifierValue)
 762 {
 763     assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
 764     BW_MPU_RGDn_WORD2_M3PE(baseAddr, regionNum, identifierValue);
 765 }
 766
 767 /*!
 768  * @brief Gets the M4 access permission.
 769  *
 770  * @param baseAddr The MPU peripheral base address
 771  * @param regionNum MPU region number
 772  * @param accessType Access type Read/Write
 773  * @retval read or write permission
 774  */
 775 static inline mpu_access_control MPU_HAL_GetM4AccessControl(uint32_t baseAddr, mpu_region_num regionNum, mpu_access_type accessType)
 776 {
 777     assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
 778     if(kMPUAccessRead == accessType)
 779     {
 780         return (mpu_access_control)(BR_MPU_RGDn_WORD2_M4RE(baseAddr, regionNum));
 781     }
 782     else
 783     {
 784         return (mpu_access_control)(BR_MPU_RGDn_WORD2_M4WE(baseAddr, regionNum));
 785     }
 786 }
 787
 788 /*!
 789  * @brief Sets the M4 access permission
 790  *
 791  * @param baseAddr The MPU peripheral base address
 792  * @param regionNum MPU region number
 793  * @param accessType Access type Read/Write
 794  * @param accessControl Access permission
 795  */
 796 static inline void MPU_HAL_SetM4AccessControl(uint32_t baseAddr, mpu_region_num regionNum, mpu_access_type accessType, mpu_access_control accessControl)
 797 {
 798     assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
 799     if(kMPUAccessRead == accessType)
 800     {
 801        BW_MPU_RGDn_WORD2_M4RE(baseAddr, regionNum, accessControl);
 802     }
 803     else
 804     {
 805         BW_MPU_RGDn_WORD2_M4WE(baseAddr, regionNum, accessControl);
 806     }
 807 }
 808
 809 /*!
 810  * @brief Gets the M5 access permission
 811  *
 812  * @param baseAddr The MPU peripheral base address
 813  * @param regionNum MPU region number
 814  * @param accessType Access type Read/Write
 815  * @retval read or write permission
 816  */
 817 static inline mpu_access_control MPU_HAL_GetM5AccessControl(uint32_t baseAddr, mpu_region_num regionNum, mpu_access_type accessType)
 818 {
 819     assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
 820     if(kMPUAccessRead == accessType)
 821     {
 822         return (mpu_access_control)(BR_MPU_RGDn_WORD2_M5RE(baseAddr, regionNum));
 823     }
 824     else
 825     {
 826         return (mpu_access_control)(BR_MPU_RGDn_WORD2_M5WE(baseAddr, regionNum));
 827     }
 828 }
 829
 830 /*!
 831  * @brief Sets the M5 access permission
 832  *
 833  * @param baseAddr The MPU peripheral base address
 834  * @param regionNum MPU region number
 835  * @param accessType Access type Read/Write
 836  * @param accessControl Access permission
 837  */
 838 static inline void MPU_HAL_SetM5AccessControl(uint32_t baseAddr, mpu_region_num regionNum, mpu_access_type accessType, mpu_access_control accessControl)
 839 {
 840     assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
 841     if(kMPUAccessRead == accessType)
 842     {
 843        BW_MPU_RGDn_WORD2_M5RE(baseAddr, regionNum, accessControl);
 844     }
 845     else
 846     {
 847         BW_MPU_RGDn_WORD2_M5WE(baseAddr, regionNum, accessControl);
 848     }
 849 }
 850
 851 /*!
 852  * @brief Gets the M6 access permission
 853  *
 854  * @param baseAddr The MPU peripheral base address
 855  * @param regionNum MPU region number
 856  * @param accessType access type Read/Write
 857  * @retval read or write permission
 858  */
 859 static inline mpu_access_control MPU_HAL_GetM6AccessControl(uint32_t baseAddr, mpu_region_num regionNum, mpu_access_type accessType)
 860 {
 861     assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
 862     if(kMPUAccessRead == accessType)
 863     {
 864         return (mpu_access_control)(BR_MPU_RGDn_WORD2_M6RE(baseAddr, regionNum));
 865     }
 866     else
 867     {
 868         return (mpu_access_control)(BR_MPU_RGDn_WORD2_M6WE(baseAddr, regionNum));
 869     }
 870 }
 871
 872 /*!
 873  * @brief Sets the M6 access permission
 874  *
 875  * @param baseAddr The MPU peripheral base address
 876  * @param regionNum MPU region number
 877  * @param accessType Access type Read/Write
 878  * @param accessControl Access permission
 879  */
 880 static inline void MPU_HAL_SetM6AccessControl(uint32_t baseAddr, mpu_region_num regionNum, mpu_access_type accessType, mpu_access_control accessControl)
 881 {
 882     assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
 883     if(kMPUAccessRead == accessType)
 884     {
 885        BW_MPU_RGDn_WORD2_M6RE(baseAddr, regionNum, accessControl);
 886     }
 887     else
 888     {
 889         BW_MPU_RGDn_WORD2_M6WE(baseAddr, regionNum, accessControl);
 890     }
 891 }
 892
 893 /*!
 894  * @brief Gets the M7 access permission
 895  *
 896  * @param baseAddr The MPU peripheral base address
 897  * @param regionNum MPU region number
 898  * @param accessType Access type Read/Write
 899  * @retval read or write permission
 900  */
 901 static inline mpu_access_control MPU_HAL_GetM7AccessControl(uint32_t baseAddr, mpu_region_num regionNum, mpu_access_type accessType)
 902 {
 903     assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
 904     if(kMPUAccessRead == accessType)
 905     {
 906         return (mpu_access_control)(BR_MPU_RGDn_WORD2_M7RE(baseAddr, regionNum));
 907     }
 908     else
 909     {
 910         return (mpu_access_control)(BR_MPU_RGDn_WORD2_M7WE(baseAddr, regionNum));
 911     }
 912 }
 913
 914 /*!
 915  * @brief Sets the M7 access permission
 916  *
 917  * @param baseAddr The MPU peripheral base address
 918  * @param regionNum MPU region number
 919  * @param accessType Access type Read/Write
 920  * @param accessControl Access permission
 921  */
 922 static inline void MPU_HAL_SetM7AccessControl(uint32_t baseAddr, mpu_region_num regionNum, mpu_access_type accessType, mpu_access_control accessControl)
 923 {
 924     assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
 925     if(kMPUAccessRead == accessType)
 926     {
 927        BW_MPU_RGDn_WORD2_M7RE(baseAddr, regionNum, accessControl);
 928     }
 929     else
 930     {
 931         BW_MPU_RGDn_WORD2_M7WE(baseAddr, regionNum, accessControl);
 932     }
 933 }
 934
 935 /*!
 936  * @brief Checks whether region is valid
 937  *
 938  * @param baseAddr The MPU peripheral base address
 939  * @param regionNum MPU region number
 940  * @retval true region is valid
 941  * @retval false region is invalid
 942  */
 943 static inline bool MPU_HAL_IsRegionValid(uint32_t baseAddr, mpu_region_num regionNum)
 944 {
 945     assert(regionNum < HW_MPU_RGDn_WORD3_COUNT);
 946     return (1 == BR_MPU_RGDn_WORD3_VLD(baseAddr, regionNum));
 947 }
 948
 949 /*!
 950  * @brief Sets  the region valid value
 951  *
 952  * @param baseAddr The MPU peripheral base address
 953  * @param regionNum MPU region number
 954  * @param validValue Region valid value
 955  */
 956 static inline void MPU_HAL_SetRegionValidValue(uint32_t baseAddr, mpu_region_num regionNum, mpu_region_valid validValue)
 957 {
 958     assert(regionNum < HW_MPU_RGDn_WORD3_COUNT);
 959     BW_MPU_RGDn_WORD3_VLD(baseAddr, regionNum, validValue);
 960 }
 961
 962 /*!
 963  * @brief Gets the process identifier mask
 964  *
 965  * @param baseAddr The MPU peripheral base address
 966  * @param regionNum MPU region number
 967  * @retval region process identifier mask
 968  */
 969 static inline uint8_t MPU_HAL_GetProcessIdentifierMask(uint32_t baseAddr, mpu_region_num regionNum)
 970 {
 971     assert(regionNum < HW_MPU_RGDn_WORD3_COUNT);
 972     return (BR_MPU_RGDn_WORD3_PIDMASK(baseAddr, regionNum));
 973 }
 974
 975 /*!
 976  * @brief Sets the process identifier mask
 977  *
 978  * @param baseAddr The MPU peripheral base address
 979  * @param regionNum MPU region number
 980  * @param processIdentifierMask Process identifier mask value
 981  */
 982 static inline void MPU_HAL_SetPIDMASK(uint32_t baseAddr, mpu_region_num regionNum, uint8_t processIdentifierMask)
 983 {
 984     assert(regionNum < HW_MPU_RGDn_WORD3_COUNT);
 985     BW_MPU_RGDn_WORD3_PIDMASK(baseAddr, regionNum, processIdentifierMask);
 986 }
 987
 988 /*!
 989  * @brief Gets the process identifier
 990  *
 991  * @param baseAddr The MPU peripheral base address
 992  * @param regionNum MPU region number
 993  * @retval process identifier
 994  */
 995 static inline uint8_t MPU_HAL_GetProcessIdentifier(uint32_t baseAddr, mpu_region_num regionNum)
 996 {
 997     assert(regionNum < HW_MPU_RGDn_WORD3_COUNT);
 998     return (BR_MPU_RGDn_WORD3_PID(baseAddr, regionNum));
 999 }
1000
1001 /*!
1002  * @brief Sets the process identifier
1003  *
1004  * @param baseAddr The MPU peripheral base address
1005  * @param regionNum MPU region number
1006  * @param processIdentifier Process identifier
1007  */
1008 static inline void MPU_HAL_SetProcessIdentifier(uint32_t baseAddr, mpu_region_num regionNum, uint8_t processIdentifier)
1009 {
1010     assert(regionNum < HW_MPU_RGDn_WORD3_COUNT);
1011     BW_MPU_RGDn_WORD3_PID(baseAddr, regionNum, processIdentifier);
1012 }
1013
1014 /*!
1015  * @brief Gets all masters access permission from alternative register
1016  *
1017  * @param baseAddr The MPU peripheral base address
1018  * @param regionNum MPU region number
1019  * @retval all masters access permission
1020  */
1021 static inline uint32_t MPU_HAL_GetAllMastersAlternateAcessRights(uint32_t baseAddr, mpu_region_num regionNum)
1022 {
1023     assert(regionNum < HW_MPU_RGDAACn_COUNT);
1024     return (HW_MPU_RGDAACn_RD(baseAddr, regionNum));
1025 }
1026
1027 /*!
1028  * @brief Sets all masters access permission through alternative register
1029  *
1030  * @param baseAddr The MPU peripheral base address
1031  * @param regionNum MPU region number
1032  * @param accessRights All masters access permission
1033  */
1034 static inline void MPU_HAL_SetAllMastersAlternateAccessRights(uint32_t baseAddr, mpu_region_num regionNum, uint32_t accessRights)
1035 {
1036     assert(regionNum < HW_MPU_RGDAACn_COUNT);
1037     HW_MPU_RGDAACn_WR(baseAddr, regionNum, accessRights);
1038 }
1039
1040 /*!
1041  * @brief Gets the M0 access rights in supervisor mode
1042  *
1043  * @param baseAddr The MPU peripheral base address
1044  * @param regionNum MPU region number
1045  * @retval Master0 access permission
1046  */
1047 static inline mpu_supervisor_access_rights MPU_HAL_GetM0AlternateSupervisorAccessRights(uint32_t baseAddr, mpu_region_num regionNum)
1048 {
1049     assert(regionNum < HW_MPU_RGDAACn_COUNT);
1050     return (mpu_supervisor_access_rights)(BR_MPU_RGDAACn_M0SM(baseAddr, regionNum));
1051 }
1052
1053 /*!
1054  * @brief Gets the M0 access rights in user mode
1055  *
1056  * @param baseAddr The MPU peripheral base address
1057  * @param regionNum MPU region number
1058  * @retval Master0 access permission
1059  */
1060 static inline mpu_user_access_rights MPU_HAL_GetM0AlternateUserAccessRights(uint32_t baseAddr, mpu_region_num regionNum)
1061 {
1062     assert(regionNum < HW_MPU_RGDAACn_COUNT);
1063     return (mpu_user_access_rights)(BR_MPU_RGDAACn_M0UM(baseAddr, regionNum));
1064 }
1065
1066 /*!
1067  * @brief Sets the M0 access rights in supervisor mode
1068  *
1069  * @param baseAddr The MPU peripheral base address
1070  * @param regionNum MPU region number
1071  * @param accessRights Master0 access permission
1072  */
1073 static inline void MPU_HAL_SetM0AlternateSupervisorAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_supervisor_access_rights accessRights)
1074 {
1075     assert(regionNum < HW_MPU_RGDAACn_COUNT);
1076     BW_MPU_RGDAACn_M0SM(baseAddr, regionNum, accessRights);
1077 }
1078
1079 /*!
1080  * @brief Sets the M0 access rights in user mode
1081  *
1082  * @param baseAddr The MPU peripheral base address
1083  * @param regionNum MPU region number
1084  * @param accessRights Master0 access permission
1085  */
1086 static inline void MPU_HAL_SetM0AlternateUserAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_user_access_rights accessRights)
1087 {
1088     assert(regionNum < HW_MPU_RGDAACn_COUNT);
1089     BW_MPU_RGDAACn_M0UM(baseAddr, regionNum, accessRights);
1090 }
1091
1092 /*!
1093  * @brief Checks whether the M0 process identifier works in region hit evaluation
1094  *
1095  * @param baseAddr The MPU peripheral base address
1096  * @param regionNum MPU region number
1097  * @retval true m0 process identifier is enabled
1098  * @retval false m0 process identifier is disabled
1099  */
1100 static inline bool MPU_HAL_IsM0AlternateProcessIdentifierEnabled(uint32_t baseAddr, mpu_region_num regionNum)
1101 {
1102     assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
1103     return (1 == BR_MPU_RGDAACn_M0PE(baseAddr, regionNum));
1104 }
1105
1106 /*!
1107  * @brief @brief Sets the M0 process identifier value--- 1 enable process identifier in region hit evaluation and 0 disable
1108  *
1109  * @param baseAddr The MPU peripheral base address
1110  * @param regionNum MPU region number
1111  * @param identifierValue Process identifier value
1112  */
1113 static inline void MPU_HAL_SetM0AlternateProcessIdentifierValue(uint32_t baseAddr, mpu_region_num regionNum, mpu_process_identifier_value identifierValue)
1114 {
1115     assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
1116     BW_MPU_RGDAACn_M0PE(baseAddr, regionNum, identifierValue);
1117 }
1118
1119 /*!
1120  * @brief Gets M1 access rights in supervisor mode
1121  *
1122  * @param baseAddr The MPU peripheral base address
1123  * @param regionNum MPU region number
1124  * @retval Master1 access permission
1125  */
1126 static inline mpu_supervisor_access_rights MPU_HAL_GetM1AlternateSupervisorAccessRights(uint32_t baseAddr, mpu_region_num regionNum)
1127 {
1128     assert(regionNum < HW_MPU_RGDAACn_COUNT);
1129     return (mpu_supervisor_access_rights)(BR_MPU_RGDAACn_M1SM(baseAddr, regionNum));
1130 }
1131
1132 /*!
1133  * @brief Gets M1 access rights in user mode
1134  *
1135  * @param baseAddr The MPU peripheral base address
1136  * @param regionNum MPU region number
1137  * @retval Master1 access permission
1138  */
1139 static inline mpu_user_access_rights MPU_HAL_GetM1AlternateUserAccessRights(uint32_t baseAddr, mpu_region_num regionNum)
1140 {
1141     assert(regionNum < HW_MPU_RGDAACn_COUNT);
1142     return (mpu_user_access_rights)(BR_MPU_RGDAACn_M1UM(baseAddr, regionNum));
1143 }
1144
1145 /*!
1146  * @brief Sets M1 access rights in supervisor mode
1147  *
1148  * @param baseAddr The MPU peripheral base address
1149  * @param regionNum MPU region number
1150  * @param accessRights Master1 access permission
1151  */
1152 static inline void MPU_HAL_SetM1AlternateSupervisorAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_supervisor_access_rights accessRights)
1153 {
1154     assert(regionNum < HW_MPU_RGDAACn_COUNT);
1155     BW_MPU_RGDAACn_M1SM(baseAddr, regionNum, accessRights);
1156 }
1157
1158 /*!
1159  * @brief Sets M1 access rights in user mode
1160  *
1161  * @param baseAddr The MPU peripheral base address
1162  * @param regionNum MPU region number
1163  * @param accessRights Master1 access permission
1164  */
1165 static inline void MPU_HAL_SetM1AlternateUserAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_user_access_rights accessRights)
1166 {
1167     assert(regionNum < HW_MPU_RGDAACn_COUNT);
1168     BW_MPU_RGDAACn_M1UM(baseAddr, regionNum, accessRights);
1169 }
1170
1171 /*!
1172  * @brief Checks whether the M1 process identifier works in region hit evaluation
1173  *
1174  * @param baseAddr The MPU peripheral base address
1175  * @param regionNum MPU region number
1176  * @retval true m1 process identifier is enabled
1177  * @retval false m1 process identifier is disabled
1178  */
1179 static inline bool MPU_HAL_IsM1AlternateProcessIdentifierEnabled(uint32_t baseAddr, mpu_region_num regionNum)
1180 {
1181     assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
1182     return (1 == BR_MPU_RGDAACn_M1PE(baseAddr, regionNum));
1183 }
1184
1185 /*!
1186  * @brief @brief Sets M1 process identifier value--- 1 enable process identifier in region hit evaluation and 0 disable
1187  *
1188  * @param baseAddr The MPU peripheral base address
1189  * @param regionNum MPU region number
1190  * @param identifierValue process identifier value
1191  */
1192 static inline void MPU_HAL_SetM1AlternateProcessIdentifierValue(uint32_t baseAddr, mpu_region_num regionNum, mpu_process_identifier_value identifierValue)
1193 {
1194     assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
1195     BW_MPU_RGDAACn_M1PE(baseAddr, regionNum, identifierValue);
1196 }
1197
1198 /*!
1199  * @brief Gets M2 access rights in supervisor mode
1200  *
1201  * @param baseAddr The MPU peripheral base address
1202  * @param regionNum MPU region number
1203  * @retval M2 access permission
1204  */
1205 static inline mpu_supervisor_access_rights MPU_HAL_GetM2AlternateSupervisorAccessRights(uint32_t baseAddr, mpu_region_num regionNum)
1206 {
1207     assert(regionNum < HW_MPU_RGDAACn_COUNT);
1208     return (mpu_supervisor_access_rights)(BR_MPU_RGDAACn_M2SM(baseAddr, regionNum));
1209 }
1210
1211 /*!
1212  * @brief Gets the M2 access rights in user mode
1213  *
1214  * @param baseAddr The MPU peripheral base address
1215  * @param regionNum MPU region number
1216  * @retval M2 access permission
1217  */
1218 static inline mpu_user_access_rights MPU_HAL_GetM2AlternateUserAccessRights(uint32_t baseAddr, mpu_region_num regionNum)
1219 {
1220     assert(regionNum < HW_MPU_RGDAACn_COUNT);
1221     return (mpu_user_access_rights)(BR_MPU_RGDAACn_M2UM(baseAddr, regionNum));
1222 }
1223
1224 /*!
1225  * @brief Sets  M2 access rights in supervisor mode
1226  *
1227  * @param baseAddr The MPU peripheral base address
1228  * @param regionNum MPU region number
1229  * @param accessRights M2 access permission
1230  */
1231 static inline void MPU_HAL_SetM2AlternateSupervisorAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_supervisor_access_rights accessRights)
1232 {
1233     assert(regionNum < HW_MPU_RGDAACn_COUNT);
1234     BW_MPU_RGDAACn_M2SM(baseAddr, regionNum, accessRights);
1235 }
1236
1237 /*!
1238  * @brief Sets M2 access rights in user mode
1239  *
1240  * @param baseAddr The MPU peripheral base address
1241  * @param regionNum MPU region number
1242  * @param accessRights M2 access permission
1243  */
1244 static inline void MPU_HAL_SetM2AlternateUserAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_user_access_rights accessRights)
1245 {
1246     assert(regionNum < HW_MPU_RGDAACn_COUNT);
1247     BW_MPU_RGDAACn_M2UM(baseAddr, regionNum, accessRights);
1248 }
1249
1250 /*!
1251  * @brief Checks whether the M2 process identifier works in region hit evaluation
1252  *
1253  * @param baseAddr The MPU peripheral base address
1254  * @param regionNum MPU region number
1255  * @retval true m2 process identifier is enabled
1256  * @retval false m2 process identifier is disabled
1257  */
1258 static inline bool MPU_HAL_IsM2AlternateProcessIdentifierEnabled(uint32_t baseAddr, mpu_region_num regionNum)
1259 {
1260     assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
1261     return (1 == BR_MPU_RGDAACn_M2PE(baseAddr, regionNum));
1262 }
1263
1264 /*!
1265  * @brief Sets M2 process identifier value--- 1 enable process identifier in region hit evaluation and 0 disable
1266  *
1267  * @param baseAddr The MPU peripheral base address
1268  * @param regionNum MPU region number
1269  * @param identifierValue process identifier value
1270  */
1271 static inline void MPU_HAL_SetM2AlternateProcessIdentifierValue(uint32_t baseAddr, mpu_region_num regionNum, mpu_process_identifier_value identifierValue)
1272 {
1273     assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
1274     BW_MPU_RGDAACn_M2PE(baseAddr, regionNum, identifierValue);
1275 }
1276
1277 /*!
1278  * @brief Gets  M3 access rights in supervisor mode
1279  *
1280  * @param baseAddr The MPU peripheral base address
1281  * @param regionNum MPU region number
1282  * @retval M3 access permission
1283  */
1284 static inline mpu_supervisor_access_rights MPU_HAL_GetM3AlternateSupervisorAccessRights(uint32_t baseAddr, mpu_region_num regionNum)
1285 {
1286     assert(regionNum < HW_MPU_RGDAACn_COUNT);
1287     return (mpu_supervisor_access_rights)(BR_MPU_RGDAACn_M3SM(baseAddr, regionNum));
1288 }
1289
1290 /*!
1291  * @brief Gets M3 access rights in user mode
1292  *
1293  * @param baseAddr The MPU peripheral base address
1294  * @param regionNum MPU region number
1295  * @retval M3 access permission
1296  */
1297 static inline mpu_user_access_rights MPU_HAL_GetM3AlternateUserAccessRights(uint32_t baseAddr, mpu_region_num regionNum)
1298 {
1299     assert(regionNum < HW_MPU_RGDAACn_COUNT);
1300     return (mpu_user_access_rights)(BR_MPU_RGDAACn_M3UM(baseAddr, regionNum));
1301 }
1302
1303 /*!
1304  * @brief Sets M3 access rights in supervisor mode
1305  *
1306  * @param baseAddr The MPU peripheral base address
1307  * @param regionNum MPU region number
1308  * @param accessRights Master3 access permission
1309  */
1310 static inline void MPU_HAL_SetM3AlternateSupervisorAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_supervisor_access_rights accessRights)
1311 {
1312     assert(regionNum < HW_MPU_RGDAACn_COUNT);
1313     BW_MPU_RGDAACn_M3SM(baseAddr, regionNum, accessRights);
1314 }
1315
1316 /*!
1317  * @brief Sets M3 access rights in user mode
1318  *
1319  * @param baseAddr The MPU peripheral base address
1320  * @param regionNum MPU region number
1321  * @param accessRights Master3 access permission
1322  */
1323 static inline void MPU_HAL_SetM3AlternateUserAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_user_access_rights accessRights)
1324 {
1325     assert(regionNum < HW_MPU_RGDAACn_COUNT);
1326     BW_MPU_RGDAACn_M3UM(baseAddr, regionNum, accessRights);
1327 }
1328
1329 /*!
1330  * @brief Checks whether the  M3 process identifier works in region hit evaluation.
1331  *
1332  * @param baseAddr The MPU peripheral base address.
1333  * @param regionNum MPU region number.
1334  * @retval true m3 process identifier is enabled.
1335  * @retval false m3 process identifier is disabled.
1336  */
1337 static inline bool MPU_HAL_IsM3AlternateProcessIdentifierEnabled(uint32_t baseAddr, mpu_region_num regionNum)
1338 {
1339     assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
1340     return (1 == BR_MPU_RGDAACn_M3PE(baseAddr, regionNum));
1341 }
1342
1343 /*!
1344  * @brief Sets M3 process identifier value--- 1 enable process identifier in region hit evaluation and 0 disable.
1345  *
1346  * @param baseAddr The MPU peripheral base address.
1347  * @param regionNum MPU region number.
1348  * @param identifierValue process identifier value.
1349  */
1350 static inline void MPU_HAL_SetM3AlternateProcessIdentifierValue(uint32_t baseAddr, mpu_region_num regionNum, mpu_process_identifier_value identifierValue)
1351 {
1352     assert(regionNum < HW_MPU_RGDn_WORD2_COUNT);
1353     BW_MPU_RGDAACn_M3PE(baseAddr, regionNum, identifierValue);
1354 }
1355
1356 /*!
1357  * @brief Gets M4 access permission from alternate register.
1358  *
1359  * @param baseAddr The MPU peripheral base address.
1360  * @param regionNum MPU region number.
1361  * @param accessType Access type Read/Write.
1362  * @retval read or write permission.
1363  */
1364 static inline mpu_access_control MPU_HAL_GetM4AlternateAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_access_type accessType)
1365 {
1366     assert(regionNum < HW_MPU_RGDAACn_COUNT);
1367     if(kMPUAccessRead == accessType)
1368     {
1369         return (mpu_access_control)(BR_MPU_RGDAACn_M4RE(baseAddr, regionNum));
1370     }
1371     else
1372     {
1373         return (mpu_access_control)(BR_MPU_RGDAACn_M4WE(baseAddr, regionNum));
1374     }
1375 }
1376
1377 /*!
1378  * @brief Sets M4 access permission through alternate register.
1379  *
1380  * @param baseAddr The MPU peripheral base address.
1381  * @param regionNum MPU region number.
1382  * @param accessType Access type Read/Write.
1383  * @param accessControl Access permission.
1384  */
1385 static inline void MPU_HAL_SetM4AlternateAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_access_type accessType, mpu_access_control accessControl)
1386 {
1387     assert(regionNum < HW_MPU_RGDAACn_COUNT);
1388     if(kMPUAccessRead == accessType)
1389     {
1390         BW_MPU_RGDAACn_M4RE(baseAddr, regionNum, accessControl);
1391     }
1392     else
1393     {
1394         BW_MPU_RGDAACn_M4WE(baseAddr, regionNum, accessControl);
1395     }
1396 }
1397
1398 /*!
1399  * @brief Gets M5 access permission from alternate register.
1400  *
1401  * @param baseAddr The MPU peripheral base address.
1402  * @param regionNum MPU region number.
1403  * @param accessType Access type Read/Write.
1404  * @retval read or write permission.
1405  */
1406 static inline mpu_access_control MPU_HAL_GetM5AlternateAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_access_type accessType)
1407 {
1408     assert(regionNum < HW_MPU_RGDAACn_COUNT);
1409     if(kMPUAccessRead == accessType)
1410     {
1411         return (mpu_access_control)(BR_MPU_RGDAACn_M5RE(baseAddr, regionNum));
1412     }
1413     else
1414     {
1415         return (mpu_access_control)(BR_MPU_RGDAACn_M5WE(baseAddr, regionNum));
1416     }
1417 }
1418
1419 /*!
1420  * @brief Sets M5 access permission through alternate register.
1421  *
1422  * @param baseAddr The MPU peripheral base address.
1423  * @param regionNum MPU region number.
1424  * @param accessType Access type Read/Write.
1425  * @param accessControl Master5 Access permission.
1426  */
1427 static inline void MPU_HAL_SetM5AlternateAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_access_type accessType, mpu_access_control accessControl)
1428 {
1429     assert(regionNum < HW_MPU_RGDAACn_COUNT);
1430     if(kMPUAccessRead == accessType)
1431     {
1432         BW_MPU_RGDAACn_M5RE(baseAddr, regionNum, accessControl);
1433     }
1434     else
1435     {
1436         BW_MPU_RGDAACn_M5WE(baseAddr, regionNum, accessControl);
1437     }
1438 }
1439
1440 /*!
1441  * @brief Gets M6 access permission from alternate register.
1442  *
1443  * @param baseAddr The MPU peripheral base address.
1444  * @param regionNum MPU region number.
1445  * @param accessType Access type Read/Write.
1446  * @retval read or write permission.
1447  */
1448 static inline mpu_access_control MPU_HAL_GetM6AlternateAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_access_type accessType)
1449 {
1450     assert(regionNum < HW_MPU_RGDAACn_COUNT);
1451     if(kMPUAccessRead == accessType)
1452     {
1453         return (mpu_access_control)(BR_MPU_RGDAACn_M6RE(baseAddr, regionNum));
1454     }
1455     else
1456     {
1457         return (mpu_access_control)(BR_MPU_RGDAACn_M6WE(baseAddr, regionNum));
1458     }
1459 }
1460
1461 /*!
1462  * @brief Sets M6 access permission through alternate register.
1463  *
1464  * @param baseAddr The MPU peripheral base address.
1465  * @param regionNum MPU region number.
1466  * @param accessType Access type Read/Write.
1467  * @param accessControl Master6 access permission.
1468  */
1469 static inline void MPU_HAL_SetM6AlternateAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_access_type accessType, mpu_access_control accessControl)
1470 {
1471     assert(regionNum < HW_MPU_RGDAACn_COUNT);
1472     if(kMPUAccessRead == accessType)
1473     {
1474         BW_MPU_RGDAACn_M6RE(baseAddr, regionNum, accessControl);
1475     }
1476     else
1477     {
1478         BW_MPU_RGDAACn_M6WE(baseAddr, regionNum, accessControl);
1479     }
1480 }
1481
1482 /*!
1483  * @brief Gets M7 access permission from alternate register.
1484  *
1485  * @param baseAddr The MPU peripheral base address.
1486  * @param regionNum MPU region number.
1487  * @param accessType Access type Read/Write.
1488  * @retval read or write permission.
1489  */
1490 static inline mpu_access_control MPU_HAL_GetM7AlternateAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_access_type accessType)
1491 {
1492     assert(regionNum < HW_MPU_RGDAACn_COUNT);
1493     if(kMPUAccessRead == accessType)
1494     {
1495         return (mpu_access_control)(BR_MPU_RGDAACn_M7RE(baseAddr, regionNum));
1496     }
1497     else
1498     {
1499         return (mpu_access_control)(BR_MPU_RGDAACn_M7WE(baseAddr, regionNum));
1500     }
1501 }
1502
1503 /*!
1504  * @brief Sets M7 access permission through alternate register.
1505  *
1506  * @param baseAddr The MPU peripheral base address.
1507  * @param regionNum MPU region number.
1508  * @param accessType Access type Read/Write.
1509  * @param accessControl Master7 access permission.
1510  */
1511 static inline void MPU_HAL_SetM7AlternateAccessRights(uint32_t baseAddr, mpu_region_num regionNum, mpu_access_type accessType, mpu_access_control accessControl)
1512 {
1513     assert(regionNum < HW_MPU_RGDAACn_COUNT);
1514     if(kMPUAccessRead == accessType)
1515     {
1516         BW_MPU_RGDAACn_M7RE(baseAddr, regionNum, accessControl);
1517     }
1518     else
1519     {
1520         BW_MPU_RGDAACn_M7WE(baseAddr, regionNum, accessControl);
1521     }
1522 }
1523
1524 /*!
1525  * @brief Initializes the MPU module.
1526  *
1527  * @param baseAddr The MPU peripheral base address.
1528  */
1529 void MPU_HAL_Init(uint32_t baseAddr);
1530
1531 /*@}*/
1532
1533 #if defined(__cplusplus)
1534 }
1535 #endif
1536
1537 /*! @}*/
1538
1539 #endif /* MBED_NO_MPU */
1540
1541 #endif /* __FSL_MPU_HAL_H__*/
1542 /*******************************************************************************
1543  * EOF
1544  *******************************************************************************/
1545