]> git.gir.st - tmk_keyboard.git/blob - tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/pit/fsl_pit_hal.h
Squashed 'tmk_core/' changes from 7967731..b9e0ea0
[tmk_keyboard.git] / tool / mbed / mbed-sdk / libraries / mbed / targets / hal / TARGET_Freescale / TARGET_KPSDK_MCUS / TARGET_KPSDK_CODE / hal / pit / fsl_pit_hal.h
1 /*
2 * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without modification,
6 * are permitted provided that the following conditions are met:
7 *
8 * o Redistributions of source code must retain the above copyright notice, this list
9 * of conditions and the following disclaimer.
10 *
11 * o Redistributions in binary form must reproduce the above copyright notice, this
12 * list of conditions and the following disclaimer in the documentation and/or
13 * other materials provided with the distribution.
14 *
15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
16 * contributors may be used to endorse or promote products derived from this
17 * software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30 #ifndef __FSL_PIT_HAL_H__
31 #define __FSL_PIT_HAL_H__
32
33 #include <assert.h>
34 #include <stdint.h>
35 #include <stdbool.h>
36 #include "fsl_pit_features.h"
37 #include "fsl_device_registers.h"
38
39 /*!
40 * @addtogroup pit_hal
41 * @{
42 */
43
44 /*******************************************************************************
45 * API
46 ******************************************************************************/
47
48 #if defined(__cplusplus)
49 extern "C" {
50 #endif
51
52 /*!
53 * @name Initialization
54 * @{
55 */
56
57 /*!
58 * @brief Enables the PIT module.
59 *
60 * This function enables the PIT timer clock (Note: this function does not un-gate
61 * the system clock gating control). It should be called before any other timer
62 * related setup.
63 *
64 * @param baseAddr Base address for current PIT instance.
65 */
66 static inline void PIT_HAL_Enable(uint32_t baseAddr)
67 {
68 BW_PIT_MCR_MDIS(baseAddr, 0U);
69 }
70
71 /*!
72 * @brief Disables the PIT module.
73 *
74 * This function disables all PIT timer clocks(Note: it does not affect the
75 * SIM clock gating control).
76 *
77 * @param baseAddr Base address for current PIT instance.
78 */
79 static inline void PIT_HAL_Disable(uint32_t baseAddr)
80 {
81 BW_PIT_MCR_MDIS(baseAddr, 1U);
82 }
83
84 /*!
85 * @brief Configures the timers to continue running or to stop in debug mode.
86 *
87 * In debug mode, the timers may or may not be frozen, based on the configuration of
88 * this function. This is intended to aid software development, allowing the developer
89 * to halt the processor, investigate the current state of the system (for example,
90 * the timer values), and continue the operation.
91 *
92 * @param baseAddr Base address for current PIT instance.
93 * @param timerRun Timers run or stop in debug mode.
94 * - true: Timers continue to run in debug mode.
95 * - false: Timers stop in debug mode.
96 */
97 static inline void PIT_HAL_SetTimerRunInDebugCmd(uint32_t baseAddr, bool timerRun)
98 {
99 BW_PIT_MCR_FRZ(baseAddr, !timerRun);
100 }
101
102 #if FSL_FEATURE_PIT_HAS_CHAIN_MODE
103 /*!
104 * @brief Enables or disables the timer chain with the previous timer.
105 *
106 * When a timer has a chain mode enabled, it only counts after the previous
107 * timer has expired. If the timer n-1 has counted down to 0, counter n
108 * decrements the value by one. This allows the developers to chain timers together
109 * and form a longer timer. The first timer (timer 0) cannot be chained to any
110 * other timer.
111 *
112 * @param baseAddr Base address for current PIT instance.
113 * @param channel Timer channel number which is chained with the previous timer.
114 * @param enable Enable or disable chain.
115 * - true: Current timer is chained with the previous timer.
116 * - false: Timer doesn't chain with other timers.
117 */
118 static inline void PIT_HAL_SetTimerChainCmd(uint32_t baseAddr, uint32_t channel, bool enable)
119 {
120 assert(channel < FSL_FEATURE_PIT_TIMER_COUNT);
121 BW_PIT_TCTRLn_CHN(baseAddr, channel, enable);
122 }
123
124 #endif /* FSL_FEATURE_PIT_HAS_CHAIN_MODE*/
125
126 /* @} */
127
128 /*!
129 * @name Timer Start and Stop
130 * @{
131 */
132
133 /*!
134 * @brief Starts the timer counting.
135 *
136 * After calling this function, timers load the start value as specified by the function
137 * PIT_HAL_SetTimerPeriodByCount(uint32_t baseAddr, uint32_t channel, uint32_t count), count down to
138 * 0, and load the respective start value again. Each time a timer reaches 0,
139 * it generates a trigger pulse and sets the time-out interrupt flag.
140 *
141 * @param baseAddr Base address for current PIT instance.
142 * @param channel Timer channel number
143 */
144 static inline void PIT_HAL_StartTimer(uint32_t baseAddr, uint32_t channel)
145 {
146 assert(channel < FSL_FEATURE_PIT_TIMER_COUNT);
147 BW_PIT_TCTRLn_TEN(baseAddr, channel, 1U);
148 }
149
150 /*!
151 * @brief Stops the timer from counting.
152 *
153 * This function stops every timer from counting. Timers reload their periods
154 * respectively after they call the PIT_HAL_StartTimer the next time.
155 *
156 * @param baseAddr Base address for current PIT instance.
157 * @param channel Timer channel number
158 */
159 static inline void PIT_HAL_StopTimer(uint32_t baseAddr, uint32_t channel)
160 {
161 assert(channel < FSL_FEATURE_PIT_TIMER_COUNT);
162 BW_PIT_TCTRLn_TEN(baseAddr, channel, 0U);
163 }
164
165 /*!
166 * @brief Checks to see whether the current timer is started or not.
167 *
168 * @param baseAddr Base address for current PIT instance.
169 * @param channel Timer channel number
170 * @return Current timer running status
171 * -true: Current timer is running.
172 * -false: Current timer has stopped.
173 */
174 static inline bool PIT_HAL_IsTimerRunning(uint32_t baseAddr, uint32_t channel)
175 {
176 assert(channel < FSL_FEATURE_PIT_TIMER_COUNT);
177 return BR_PIT_TCTRLn_TEN(baseAddr, channel);
178 }
179
180 /* @} */
181
182 /*!
183 * @name Timer Period
184 * @{
185 */
186
187 /*!
188 * @brief Sets the timer period in units of count.
189 *
190 * Timers begin counting from the value set by this function.
191 * The counter period of a running timer can be modified by first stopping
192 * the timer, setting a new load value, and starting the timer again. If
193 * timers are not restarted, the new value is loaded after the next trigger
194 * event.
195 *
196 * @param baseAddr Base address for current PIT instance.
197 * @param channel Timer channel number
198 * @param count Timer period in units of count
199 */
200 static inline void PIT_HAL_SetTimerPeriodByCount(uint32_t baseAddr, uint32_t channel, uint32_t count)
201 {
202 assert(channel < FSL_FEATURE_PIT_TIMER_COUNT);
203 HW_PIT_LDVALn_WR(baseAddr, channel, count);
204 }
205
206 /*!
207 * @brief Returns the current timer period in units of count.
208 *
209 * @param baseAddr Base address for current PIT instance.
210 * @param channel Timer channel number
211 * @return Timer period in units of count
212 */
213 static inline uint32_t PIT_HAL_GetTimerPeriodByCount(uint32_t baseAddr, uint32_t channel)
214 {
215 assert(channel < FSL_FEATURE_PIT_TIMER_COUNT);
216 return HW_PIT_LDVALn_RD(baseAddr, channel);
217 }
218
219 /*!
220 * @brief Reads the current timer counting value.
221 *
222 * This function returns the real-time timer counting value, in a range from 0 to a
223 * timer period.
224 *
225 * @param baseAddr Base address for current PIT instance.
226 * @param channel Timer channel number
227 * @return Current timer counting value
228 */
229 static inline uint32_t PIT_HAL_ReadTimerCount(uint32_t baseAddr, uint32_t channel)
230 {
231 assert(channel < FSL_FEATURE_PIT_TIMER_COUNT);
232 return HW_PIT_CVALn_RD(baseAddr, channel);
233 }
234
235 #if FSL_FEATURE_PIT_HAS_LIFETIME_TIMER
236 /*!
237 * @brief Reads the current lifetime counter value.
238 *
239 * The lifetime timer is a 64-bit timer which chains timer 0 and timer 1 together.
240 * Timer 0 and 1 are chained by calling the PIT_HAL_SetTimerChainCmd
241 * before using this timer. The period of lifetime timer is equal to the "period of
242 * timer 0 * period of timer 1". For the 64-bit value, the higher 32-bit has
243 * the value of timer 1, and the lower 32-bit has the value of timer 0.
244 *
245 * @param baseAddr Base address for current PIT instance.
246 * @return Current lifetime timer value
247 */
248 uint64_t PIT_HAL_ReadLifetimeTimerCount(uint32_t baseAddr);
249 #endif /*FSL_FEATURE_PIT_HAS_LIFETIME_TIMER*/
250
251 /* @} */
252
253 /*!
254 * @name Interrupt
255 * @{
256 */
257
258 /*!
259 * @brief Enables or disables the timer interrupt.
260 *
261 * If enabled, an interrupt happens when a timeout event occurs
262 * (Note: NVIC should be called to enable pit interrupt in system level).
263 *
264 * @param baseAddr Base address for current PIT instance.
265 * @param channel Timer channel number
266 * @param enable Enable or disable interrupt.
267 * - true: Generate interrupt when timer counts to 0.
268 * - false: No interrupt is generated.
269 */
270 static inline void PIT_HAL_SetIntCmd(uint32_t baseAddr, uint32_t channel, bool enable)
271 {
272 assert(channel < FSL_FEATURE_PIT_TIMER_COUNT);
273 BW_PIT_TCTRLn_TIE(baseAddr, channel, enable);
274 }
275
276 /*!
277 * @brief Checks whether the timer interrupt is enabled or not.
278 *
279 * @param baseAddr Base address for current PIT instance.
280 * @param channel Timer channel number
281 * @return Status of enabled or disabled interrupt
282 * - true: Interrupt is enabled.
283 * - false: Interrupt is disabled.
284 */
285 static inline bool PIT_HAL_GetIntCmd(uint32_t baseAddr, uint32_t channel)
286 {
287 assert(channel < FSL_FEATURE_PIT_TIMER_COUNT);
288 return BR_PIT_TCTRLn_TIE(baseAddr, channel);
289 }
290
291 /*!
292 * @brief Clears the timer interrupt flag.
293 *
294 * This function clears the timer interrupt flag after a timeout event
295 * occurs.
296 *
297 * @param baseAddr Base address for current PIT instance.
298 * @param channel Timer channel number
299 */
300 static inline void PIT_HAL_ClearIntFlag(uint32_t baseAddr, uint32_t channel)
301 {
302 assert(channel < FSL_FEATURE_PIT_TIMER_COUNT);
303 /* Write 1 will clear the flag. */
304 HW_PIT_TFLGn_WR(baseAddr, channel, 1U);
305 }
306
307 /*!
308 * @brief Reads the current timer timeout flag.
309 *
310 * Every time the timer counts to 0, this flag is set.
311 *
312 * @param baseAddr Base address for current PIT instance.
313 * @param channel Timer channel number
314 * @return Current status of the timeout flag
315 * - true: Timeout has occurred.
316 * - false: Timeout has not yet occurred.
317 */
318 static inline bool PIT_HAL_IsIntPending(uint32_t baseAddr, uint32_t channel)
319 {
320 assert(channel < FSL_FEATURE_PIT_TIMER_COUNT);
321 return HW_PIT_TFLGn_RD(baseAddr, channel);
322 }
323
324 /* @} */
325
326 #if defined(__cplusplus)
327 }
328 #endif
329
330 /*! @}*/
331
332 #endif /* __FSL_PIT_HAL_H__*/
333 /*******************************************************************************
334 * EOF
335 *******************************************************************************/
336
Imprint / Impressum