tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/port/fsl_port_features.h

   1 /*
   2 ** ###################################################################
   3 **     Version:             rev. 1.0, 2014-05-14
   4 **     Build:               b140515
   5 **
   6 **     Abstract:
   7 **         Chip specific module features.
   8 **
   9 **     Copyright: 2014 Freescale Semiconductor, Inc.
  10 **     All rights reserved.
  11 **
  12 **     Redistribution and use in source and binary forms, with or without modification,
  13 **     are permitted provided that the following conditions are met:
  14 **
  15 **     o Redistributions of source code must retain the above copyright notice, this list
  16 **       of conditions and the following disclaimer.
  17 **
  18 **     o Redistributions in binary form must reproduce the above copyright notice, this
  19 **       list of conditions and the following disclaimer in the documentation and/or
  20 **       other materials provided with the distribution.
  21 **
  22 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  23 **       contributors may be used to endorse or promote products derived from this
  24 **       software without specific prior written permission.
  25 **
  26 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  27 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  28 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  29 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  30 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  31 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  32 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  33 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  35 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36 **
  37 **     http:                 www.freescale.com
  38 **     mail:                 support@freescale.com
  39 **
  40 **     Revisions:
  41 **     - rev. 1.0 (2014-05-14)
  42 **         Customer release.
  43 **
  44 ** ###################################################################
  45 */
  46
  47 #if !defined(__FSL_PORT_FEATURES_H__)
  48 #define __FSL_PORT_FEATURES_H__
  49
  50 #if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \
  51     defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || \
  52     defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || \
  53     defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || \
  54     defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || \
  55     defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || \
  56     defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || \
  57     defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || \
  58     defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || \
  59     defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || \
  60     defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \
  61     defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MK24FN1M0VDC12) || \
  62     defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK24FN256VDC12) || defined(CPU_MK63FN1M0VLQ12) || \
  63     defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || \
  64     defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || \
  65     defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || \
  66     defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || \
  67     defined(CPU_MK66FX1M0VMD18) || defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || defined(CPU_MKV30F128VLF10) || \
  68     defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) || defined(CPU_MKV31F128VLH10) || \
  69     defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31F512VLH12) || \
  70     defined(CPU_MKV31F512VLL12) || defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || \
  71     defined(CPU_MKV40F256VLL15) || defined(CPU_MKV40F64VLH15) || defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || \
  72     defined(CPU_MKV43F64VLH15) || defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) || \
  73     defined(CPU_MKV45F128VLH15) || defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || defined(CPU_MKV45F256VLL15) || \
  74     defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || defined(CPU_MKV46F256VLL15)
  75     /* @brief Has control lock (register bit PCR[LK]). */
  76     #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1)
  77     /* @brief Has open drain control (register bit PCR[ODE]). */
  78     #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1)
  79     /* @brief Has digital filter (registers DFER, DFCR and DFWR). */
  80     #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1)
  81     #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTERn(x) \
  82         ((x) == 0 ? (0) : \
  83         ((x) == 1 ? (0) : \
  84         ((x) == 2 ? (0) : \
  85         ((x) == 3 ? (1) : \
  86         ((x) == 4 ? (0) : (-1))))))
  87     /* @brief Has DMA request (register bit field PCR[IRQC] values). */
  88     #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
  89     /* @brief Has pull resistor selection (register bit PCR[PS]). */
  90     #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
  91     /* @brief Has separate pull resistor enable registers (PUEL and PUEH). */
  92     #define FSL_FEATURE_PORT_HAS_PULL_ENABLE_REGISTER (0)
  93     /* @brief Has slew rate control (register bit PCR[SRE]). */
  94     #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
  95     /* @brief Has passive filter (register bit field PCR[PFE]). */
  96     #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
  97     #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTERn(x) \
  98         ((x) == 0 ? (1) : \
  99         ((x) == 1 ? (1) : \
 100         ((x) == 2 ? (1) : \
 101         ((x) == 3 ? (1) : \
 102         ((x) == 4 ? (1) : (-1))))))
 103     /* @brief Has drive strength control (register bit PCR[DSE]). */
 104     #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
 105     /* @brief Has separate drive strength register (HDRVE). */
 106     #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
 107     /* @brief Has glitch filter (register IOFLT). */
 108     #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
 109 #elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \
 110     defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15)
 111     /* @brief Has control lock (register bit PCR[LK]). */
 112     #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1)
 113     /* @brief Has open drain control (register bit PCR[ODE]). */
 114     #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1)
 115     /* @brief Has digital filter (registers DFER, DFCR and DFWR). */
 116     #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1)
 117     #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTERn(x) \
 118         ((x) == 0 ? (1) : \
 119         ((x) == 1 ? (1) : \
 120         ((x) == 2 ? (1) : \
 121         ((x) == 3 ? (1) : \
 122         ((x) == 4 ? (1) : \
 123         ((x) == 5 ? (1) : (-1)))))))
 124     /* @brief Has DMA request (register bit field PCR[IRQC] values). */
 125     #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
 126     /* @brief Has pull resistor selection (register bit PCR[PS]). */
 127     #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
 128     /* @brief Has separate pull resistor enable registers (PUEL and PUEH). */
 129     #define FSL_FEATURE_PORT_HAS_PULL_ENABLE_REGISTER (0)
 130     /* @brief Has slew rate control (register bit PCR[SRE]). */
 131     #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
 132     /* @brief Has passive filter (register bit field PCR[PFE]). */
 133     #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
 134     #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTERn(x) \
 135         ((x) == 0 ? (1) : \
 136         ((x) == 1 ? (1) : \
 137         ((x) == 2 ? (1) : \
 138         ((x) == 3 ? (1) : \
 139         ((x) == 4 ? (1) : \
 140         ((x) == 5 ? (1) : (-1)))))))
 141     /* @brief Has drive strength control (register bit PCR[DSE]). */
 142     #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
 143     /* @brief Has separate drive strength register (HDRVE). */
 144     #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
 145     /* @brief Has glitch filter (register IOFLT). */
 146     #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
 147 #elif defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || defined(CPU_MKL03Z32VFG4) || \
 148     defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || defined(CPU_MKL03Z32VFK4)
 149     /* @brief Has control lock (register bit PCR[LK]). */
 150     #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0)
 151     /* @brief Has open drain control (register bit PCR[ODE]). */
 152     #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0)
 153     /* @brief Has digital filter (registers DFER, DFCR and DFWR). */
 154     #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0)
 155     #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTERn(x) \
 156         ((x) == 0 ? (0) : \
 157         ((x) == 1 ? (0) : (-1)))
 158     /* @brief Has DMA request (register bit field PCR[IRQC] values). */
 159     #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (0)
 160     /* @brief Has pull resistor selection (register bit PCR[PS]). */
 161     #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
 162     /* @brief Has separate pull resistor enable registers (PUEL and PUEH). */
 163     #define FSL_FEATURE_PORT_HAS_PULL_ENABLE_REGISTER (0)
 164     /* @brief Has slew rate control (register bit PCR[SRE]). */
 165     #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
 166     /* @brief Has passive filter (register bit field PCR[PFE]). */
 167     #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
 168     #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTERn(x) \
 169         ((x) == 0 ? (1) : \
 170         ((x) == 1 ? (1) : (-1)))
 171     /* @brief Has drive strength control (register bit PCR[DSE]). */
 172     #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
 173     /* @brief Has separate drive strength register (HDRVE). */
 174     #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
 175     /* @brief Has glitch filter (register IOFLT). */
 176     #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
 177 #elif defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || \
 178     defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || \
 179     defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4)
 180     /* @brief Has control lock (register bit PCR[LK]). */
 181     #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0)
 182     /* @brief Has open drain control (register bit PCR[ODE]). */
 183     #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0)
 184     /* @brief Has digital filter (registers DFER, DFCR and DFWR). */
 185     #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0)
 186     #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTERn(x) \
 187         ((x) == 0 ? (0) : \
 188         ((x) == 1 ? (0) : (-1)))
 189     /* @brief Has DMA request (register bit field PCR[IRQC] values). */
 190     #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
 191     /* @brief Has pull resistor selection (register bit PCR[PS]). */
 192     #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
 193     /* @brief Has separate pull resistor enable registers (PUEL and PUEH). */
 194     #define FSL_FEATURE_PORT_HAS_PULL_ENABLE_REGISTER (0)
 195     /* @brief Has slew rate control (register bit PCR[SRE]). */
 196     #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
 197     /* @brief Has passive filter (register bit field PCR[PFE]). */
 198     #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
 199     #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTERn(x) \
 200         ((x) == 0 ? (1) : \
 201         ((x) == 1 ? (1) : (-1)))
 202     /* @brief Has drive strength control (register bit PCR[DSE]). */
 203     #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
 204     /* @brief Has separate drive strength register (HDRVE). */
 205     #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
 206     /* @brief Has glitch filter (register IOFLT). */
 207     #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
 208 #elif defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || \
 209     defined(CPU_MKL13Z128VFT4) || defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || \
 210     defined(CPU_MKL13Z256VLH4) || defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || \
 211     defined(CPU_MKL23Z64VFM4) || defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || \
 212     defined(CPU_MKL23Z128VFT4) || defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || \
 213     defined(CPU_MKL23Z256VLH4) || defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || \
 214     defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || \
 215     defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || \
 216     defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4)
 217     /* @brief Has control lock (register bit PCR[LK]). */
 218     #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0)
 219     /* @brief Has open drain control (register bit PCR[ODE]). */
 220     #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0)
 221     /* @brief Has digital filter (registers DFER, DFCR and DFWR). */
 222     #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0)
 223     #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTERn(x) \
 224         ((x) == 0 ? (0) : \
 225         ((x) == 1 ? (0) : \
 226         ((x) == 2 ? (0) : \
 227         ((x) == 3 ? (0) : \
 228         ((x) == 4 ? (0) : (-1))))))
 229     /* @brief Has DMA request (register bit field PCR[IRQC] values). */
 230     #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
 231     /* @brief Has pull resistor selection (register bit PCR[PS]). */
 232     #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
 233     /* @brief Has separate pull resistor enable registers (PUEL and PUEH). */
 234     #define FSL_FEATURE_PORT_HAS_PULL_ENABLE_REGISTER (0)
 235     /* @brief Has slew rate control (register bit PCR[SRE]). */
 236     #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
 237     /* @brief Has passive filter (register bit field PCR[PFE]). */
 238     #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
 239     #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTERn(x) \
 240         ((x) == 0 ? (1) : \
 241         ((x) == 1 ? (1) : \
 242         ((x) == 2 ? (1) : \
 243         ((x) == 3 ? (1) : \
 244         ((x) == 4 ? (1) : (-1))))))
 245     /* @brief Has drive strength control (register bit PCR[DSE]). */
 246     #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
 247     /* @brief Has separate drive strength register (HDRVE). */
 248     #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
 249     /* @brief Has glitch filter (register IOFLT). */
 250     #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
 251 #elif defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || \
 252     defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || \
 253     defined(CPU_MKL25Z128VLH4) || defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4)
 254     /* @brief Has control lock (register bit PCR[LK]). */
 255     #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0)
 256     /* @brief Has open drain control (register bit PCR[ODE]). */
 257     #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0)
 258     /* @brief Has digital filter (registers DFER, DFCR and DFWR). */
 259     #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0)
 260     #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTERn(x) \
 261         ((x) == 0 ? (0) : \
 262         ((x) == 1 ? (0) : \
 263         ((x) == 2 ? (0) : \
 264         ((x) == 3 ? (0) : \
 265         ((x) == 4 ? (0) : (-1))))))
 266     /* @brief Has DMA request (register bit field PCR[IRQC] values). */
 267     #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
 268     /* @brief Has pull resistor selection (register bit PCR[PS]). */
 269     #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (0)
 270     /* @brief Has separate pull resistor enable registers (PUEL and PUEH). */
 271     #define FSL_FEATURE_PORT_HAS_PULL_ENABLE_REGISTER (0)
 272     /* @brief Has slew rate control (register bit PCR[SRE]). */
 273     #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
 274     /* @brief Has passive filter (register bit field PCR[PFE]). */
 275     #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
 276     #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTERn(x) \
 277         ((x) == 0 ? (1) : \
 278         ((x) == 1 ? (0) : \
 279         ((x) == 2 ? (0) : \
 280         ((x) == 3 ? (0) : \
 281         ((x) == 4 ? (0) : (-1))))))
 282     /* @brief Has drive strength control (register bit PCR[DSE]). */
 283     #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
 284     /* @brief Has separate drive strength register (HDRVE). */
 285     #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
 286     /* @brief Has glitch filter (register IOFLT). */
 287     #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
 288 #elif defined(CPU_MKL26Z256VLK4) || defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || \
 289     defined(CPU_MKL26Z256VMC4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || \
 290     defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4)
 291     /* @brief Has control lock (register bit PCR[LK]). */
 292     #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0)
 293     /* @brief Has open drain control (register bit PCR[ODE]). */
 294     #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0)
 295     /* @brief Has digital filter (registers DFER, DFCR and DFWR). */
 296     #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0)
 297     #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTERn(x) \
 298         ((x) == 0 ? (0) : \
 299         ((x) == 1 ? (0) : \
 300         ((x) == 2 ? (0) : \
 301         ((x) == 3 ? (0) : \
 302         ((x) == 4 ? (0) : (-1))))))
 303     /* @brief Has DMA request (register bit field PCR[IRQC] values). */
 304     #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
 305     /* @brief Has pull resistor selection (register bit PCR[PS]). */
 306     #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
 307     /* @brief Has separate pull resistor enable registers (PUEL and PUEH). */
 308     #define FSL_FEATURE_PORT_HAS_PULL_ENABLE_REGISTER (0)
 309     /* @brief Has slew rate control (register bit PCR[SRE]). */
 310     #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
 311     /* @brief Has passive filter (register bit field PCR[PFE]). */
 312     #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
 313     #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTERn(x) \
 314         ((x) == 0 ? (1) : \
 315         ((x) == 1 ? (0) : \
 316         ((x) == 2 ? (0) : \
 317         ((x) == 3 ? (0) : \
 318         ((x) == 4 ? (0) : (-1))))))
 319     /* @brief Has drive strength control (register bit PCR[DSE]). */
 320     #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
 321     /* @brief Has separate drive strength register (HDRVE). */
 322     #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
 323     /* @brief Has glitch filter (register IOFLT). */
 324     #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
 325 #else
 326     #error "No valid CPU defined!"
 327 #endif
 328
 329 #endif /* __FSL_PORT_FEATURES_H__ */
 330
 331 /*******************************************************************************
 332  * EOF
 333  ******************************************************************************/